Control system and method for a basic input / output system and an expansion card
By introducing shared memory and processing devices on the motherboard, the problem of time-consuming and laborious modifications to the hardware settings of the basic input/output system is solved, enabling rapid adjustment and efficient development, and ensuring uniform instruction format and accurate data transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GIGA BYTE TECH CO LTD
- Filing Date
- 2024-12-12
- Publication Date
- 2026-06-12
AI Technical Summary
In the existing technology, engineers of basic input/output systems face problems such as large and complex program code, time-consuming and laborious modification, time-consuming and inefficient compilation process, and difficulty in testing and debugging when modifying the hardware settings of the motherboard during the boot stage.
By introducing shared memory and processing devices on the motherboard, the processing devices can judge and convert operation instructions to generate target instructions, which are then directly provided to the basic input/output system, avoiding the need to recompile program code and enabling rapid adjustment of hardware settings and configurations.
It improves the development efficiency of basic input/output systems, ensures unified instruction formats and accurate data transmission, and enables flexible hardware configuration and control operations.
Smart Images
Figure CN122195503A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a control system and method for a basic input / output system, as well as an expansion card. Background Technology
[0002] In current technology, engineers working with Basic Input / Output (PIO) systems face several major challenges when modifying motherboard hardware settings during the boot process. First, the sheer size and complexity of the IPI code necessitates a deep understanding of the architecture and module details to pinpoint the exact changes, a time-consuming and labor-intensive process. Furthermore, hardware-specific code is typically scattered across different modules, requiring significant time to locate the correct modifications. Moreover, the compilation process for IPIs is more time-consuming than for general applications, requiring a complete recompile after each modification, further extending the development cycle and reducing efficiency.
[0003] In addition, testing and debugging are also major challenges. Engineers need to flash the modified basic input / output system onto the test motherboard for verification. The slightest mistake may cause the motherboard to fail to boot or generate unknown errors. Debugging such issues is time-consuming and complex, often requiring multiple corrections and tests to ensure stability. Summary of the Invention
[0004] In view of the above, the present invention provides a control system and method for a basic input / output system and an expansion card for solving the above problems.
[0005] A control method for a basic input / output system according to an embodiment of the present invention includes, performed by a processing device,: acquiring an operation instruction corresponding to the basic input / output system; when it is determined that the operation instruction corresponds to a target parameter among a plurality of accessible parameters of the basic input / output system, converting the operation instruction according to the instruction format of the basic input / output system to generate a target instruction; and providing the target instruction to the basic input / output system.
[0006] A control system for a basic input / output system according to an embodiment of the present invention includes a motherboard, a shared memory, and a processing device. The motherboard includes the basic input / output system. The shared memory is connected to the motherboard and is used to store multiple accessible parameters of the basic input / output system. The processing device is connected to the shared memory and the motherboard, and is used to obtain operation instructions corresponding to the basic input / output system; when determining that the operation instruction corresponds to a target parameter among the multiple accessible parameters, the processing device converts the operation instruction according to the instruction format of the basic input / output system to generate a target instruction, and provides the target instruction to the basic input / output system.
[0007] An expansion card according to an embodiment of the present invention is connected to a basic input / output system (PIS). The expansion card includes an instruction receiving interface and an instruction transmitting interface. The instruction receiving interface is used to receive operation instructions corresponding to the PIS, and when it is determined that the operation instruction corresponds to a target parameter among a plurality of accessible parameters of the PIS, it converts the operation instruction according to the instruction format of the PIS to generate a target instruction. The instruction transmitting interface is connected to the instruction receiving interface and is used to provide the target instruction to the PIS.
[0008] The control system and method of the basic input / output system according to one or more of the above embodiments, as well as the expansion card, allow engineers of the basic input / output system to quickly adjust the settings and / or hardware configuration of the basic input / output system without recompiling the entire basic input / output system's program code, thereby improving development efficiency. Furthermore, by converting operation instructions according to the instruction format of the basic input / output system, the uniformity of instruction format and accurate data transmission can be ensured, thereby enabling the basic input / output system to flexibly perform hardware configuration and control operations.
[0009] The foregoing description of the contents of this disclosure and the following description of the embodiments are intended to demonstrate and explain the spirit and principles of the present invention, and to provide a further explanation of the claims of the present invention. Attached Figure Description
[0010] Figure 1 This is a block diagram of a control system for a basic input / output system according to an embodiment of the present invention.
[0011] Figure 2 This is a flowchart illustrating a control method for a basic input / output system according to an embodiment of the present invention.
[0012] Figure 3 This is a block diagram of a control system for a basic input / output system according to another embodiment of the present invention.
[0013] Figure 4 This is a block diagram of an expansion card according to an embodiment of the present invention.
[0014] Figure 5 This is a block diagram of an expansion card according to another embodiment of the present invention.
[0015] The reference numerals in the attached figures are explained as follows:
[0016] 1, 2: Control System
[0017] 11, 21: Motherboard
[0018] 12, 22, 42: Shared memory
[0019] 13, 23: Processing device
[0020] 111, 211: Basic Input / Output System
[0021] 3, 4: Expansion Cards
[0022] 31, 41: Command receiving interface
[0023] 32, 43: Command transmission interface
[0024] S101, S103, S105, S107: Steps Detailed Implementation
[0025] The following detailed description of the features and advantages of the present invention in the embodiments is sufficient to enable anyone skilled in the art to understand the technical content of the present invention and implement it accordingly. Based on the disclosure, claims, and drawings in this specification, anyone skilled in the art can easily understand the related objectives and advantages of the present invention. The following embodiments are further detailed in illustrating the points of view of the present invention, but are not intended to limit the scope of the present invention in any way.
[0026] Please refer to Figure 1 ,in Figure 1 This is a block diagram of a control system for a basic input / output system according to an embodiment of the present invention. Figure 1 As shown, the control system 1 includes a motherboard 11, a shared memory 12, and a processing device 13. The motherboard 11 is connected to the shared memory 12, and the shared memory 12 is connected to the processing device 13. The processing device 13 can be connected to the motherboard 11 via the shared memory 12. The motherboard 11 includes a basic input / output system 111.
[0027] The motherboard 11 can be used to execute user-inputted operation commands, which can be used to modify the hardware settings of the basic input / output system 111, read data from the basic input / output system 111, etc. Furthermore, the operation commands can be used to modify the hardware settings of the basic input / output system 111 during the power-on phase, but this invention is not limited thereto.
[0028] Shared memory 12 is used to store multiple accessible parameters of the basic input / output system 111. These multiple accessible parameters may be parameters for which users have pre-granted modification or read permissions. Each of the multiple accessible parameters may correspond to multiple identification information, and operation instructions may include the identification information of the accessible parameters. Accessible parameters may include multiple of the following: input / output register setting parameters, other system register setting parameters, inter-integrated circuit (I2C) communication setting parameters, system management bus (SMBus) setting parameters, memory setting parameters, memory-mapped I / O (MMIO) setting parameters, basic input / output system 111 variable setting parameters, CPU model-specific register (MSR) setting parameters, super I / O setting parameters, pulse width modulation setting parameters, general purpose input / output setting parameters, and addresses of readable memory blocks, etc., without limitation by this invention. The shared memory 12 may include one or more memories, which may be non-volatile memory (NVM) and random access memory (RAM), such as read-only memory (ROM), flash memory and / or non-volatile random access memory (NVRAM), static random-access memory (SRAM), dynamic random-access memory (DRAM), etc.
[0029] Processing device 13 is used to acquire operation instructions corresponding to the basic input / output system 111 and to provide target instructions corresponding to the operation instructions to the basic input / output system 111 via shared memory 12. Processing device 13 can execute a real-time operating system (RTOS) to process instructions with extremely low latency, ensuring the immediacy of hardware configuration changes. Processing device 13 can receive operation instructions via a user interface, which may be a web browser or a web application. Processing device 13 may have a web service interface, and operation instructions can be output to the web service interface of processing device 13 via Hypertext Transfer Protocol (HTTP) or Hypertext Transfer Protocol Secure (HTTPS). Operation instructions are transmitted to the basic input / output system 111 via an application programming interface (API). The API may be, for example, a representational state transfer (RESTful) API. The steps performed by processing device 13 as described below can be executed by a real-time operating system. The processing device 13 may include one or more processors, such as a central processing unit, a graphics processor, a microcontroller, a programmable logic controller, or other processors with signal processing capabilities.
[0030] Please refer to this as well. Figure 1 and Figure 2 ,in Figure 2 This is a flowchart illustrating a control method for a basic input / output system according to an embodiment of the present invention. Figure 2 As shown, the control method includes: step S101: obtaining an operation instruction corresponding to the basic input / output system; step S103: determining whether the operation instruction corresponds to a target parameter among multiple accessible parameters of the basic input / output system; when the determination result of step S103 is "no", step S101 is executed again; when the determination result of step S103 is "yes", step S105 is executed: converting the operation instruction according to the instruction format of the basic input / output system to generate a target instruction; and step S107: providing the target instruction to the basic input / output system. It should be noted that the control method may also end when the determination result of step S103 is "no", and this invention is not limiting in this regard.
[0031] In step S101, the processing device 13 obtains operation instructions for the basic input / output system 111. The operation instructions may be transmitted to the processing device 13 by the user through the user interface.
[0032] In step S103, the processing device 13 determines whether the operation instruction indicates any of the multiple accessible parameters. If the processing device 13 determines that the operation instruction does not indicate any of the multiple accessible parameters, the processing device 13 may execute step S101 again.
[0033] When the processing device 13 determines that the operation instruction indicates one of a plurality of accessible parameters (hereinafter referred to as the target parameter), in step S105, the processing device 13 converts the operation instruction according to the instruction format of the basic input / output system 111 to generate the target instruction. Further, the instruction format may be JavaScript object notation (JSON) format. The target instruction may include operation instructions converted to JSON format. Furthermore, the processing device 13 may further convert the target instruction into an instruction format string, which may include identification information of the target parameter, the operation type corresponding to the operation instruction (e.g., read), the address corresponding to the operation type (e.g., the address of the block to be read), the data length corresponding to the operation type (e.g., the length of the data to be read), and the running state corresponding to the operation instruction (e.g., pending processing). The content of the instruction format string here is merely an example and is not intended to limit the invention.
[0034] In step S107, the processing device 13 provides the target instruction to the basic input / output system 111. For example, the processing device 13 can provide the target instruction to the basic input / output system 111 through the shared memory 12, and when the processing device 13 is directly connected to the motherboard 11, the processing device 13 can also directly output the target instruction to the basic input / output system 111.
[0035] The basic input / output system 111 can read the instruction format string mentioned above in the shared memory 12, parse the instruction format string to determine the operation type and its corresponding address, and then perform the read operation.
[0036] The control system and method of the basic input / output system according to one or more of the above embodiments allow engineers of the basic input / output system to quickly read or adjust the settings and / or hardware configuration of the basic input / output system without recompiling the entire basic input / output system's program code, thereby improving development efficiency. Furthermore, by converting operation instructions according to the instruction format of the basic input / output system, the uniformity of instruction format and accurate data transmission can be ensured, thereby enabling the basic input / output system to flexibly perform hardware configuration and control operations.
[0037] In one embodiment of step S107, the processing device 13 may store the target instruction (or the instruction format string described above) into the shared memory 12, and the basic input / output system 111 may read the target instruction from the shared memory 12. After storing the target instruction into the shared memory 12, the processing device 13 may further read the instruction execution result from the basic input / output system 111 from the shared memory 12. In other words, after executing the operation corresponding to the target instruction, the basic input / output system 111 may store the instruction execution result corresponding to the target instruction into the shared memory 12. In this embodiment, the motherboard 11 and the shared memory 12 may be connected via a wired connection. For example, the motherboard 11 and the shared memory 12 may each have a peripheral component interconnect express (PCIe) interface. The basic input / output system 111 may read the target instruction stored in the shared memory 12 via the PCIe interface, and the basic input / output system 111 may store the instruction execution result into the shared memory 12 via the PCIe interface.
[0038] Please refer to Figure 3 ,in Figure 3 This is a block diagram of a control system for a basic input / output system according to another embodiment of the present invention. Figure 3 As shown, the control system 2 includes a motherboard 21, a shared memory 22, and a processing device 23. The motherboard 21 is connected to the shared memory 22 and directly connected to the processing device 23, and the shared memory 22 is connected to the processing device 23. The motherboard 21 includes a basic input / output system 211. The implementation of the motherboard 21, the shared memory 22, and the processing device 23 can be described in different ways. Figure 1 The motherboard 11, shared memory 12, and processing device 13 are the same, and will not be described again here.
[0039] In another embodiment of step S107, the processing device 23 can directly output the target instruction (or the instruction format string described above) to the basic input / output system 211 via an application programming interface (API). After outputting the target instruction to the basic input / output system 211, the processing device 23 can further receive the instruction execution result directly from the basic input / output system 211 via the API. In other words, after executing the operation corresponding to the target instruction, the basic input / output system 211 can directly output the corresponding instruction execution result to the processing device 23. In this embodiment, the motherboard 21 and the processing device 23 can be connected wirelessly or via a wired connection. For example, the motherboard 21 and the processing device 23 can each have a network interface. The processing device 23 can directly output the target instruction to the basic input / output system 211 via the network interface, and the processing device 23 can receive the instruction execution result from the basic input / output system 211 via the network interface. The network interface can include at least one of a physical network cable and a wireless network interface. The network interface may be, for example, a local area network (LAN) channel and / or a wireless network (Wi-Fi) channel, and the network interface of the motherboard 21 and the network interface of the processing device 23 may be connected via an Internet router and / or an Intranet router.
[0040] Furthermore, after receiving the instruction format string from the application programming interface of the real-time operating system, the basic input / output system 211 can parse the instruction format string to determine the operation type and its corresponding address, and then perform a read operation.
[0041] At Figure 3 In this embodiment, the processing device 23 may further store the target instruction into the shared memory 22. Furthermore, the processing device 23 may further store the instruction execution result into the shared memory 22.
[0042] Through the above-described embodiments of peripheral component interconnection interfaces and network interfaces, users can choose appropriate methods to modify and control the settings of the basic input / output system according to application scenarios and needs, so as to adapt to more diverse usage scenarios.
[0043] Furthermore, corresponding to the example of the instruction format string mentioned above, the instruction execution result can also be implemented in the form of an instruction format string. The instruction execution result may include the identification information of the target parameter, the operation type (e.g., read), the address corresponding to the operation type (e.g., the address of the block to be read), the data length corresponding to the operation type (e.g., the length of the data read), the running status of the read data and the operation instruction (e.g., completed).
[0044] Please refer to Figure 4 ,in Figure 4 This is a block diagram illustrating an expansion card according to an embodiment of the present invention. Figure 4 As shown, expansion card 3 includes an instruction receiving interface 31 and an instruction transmitting interface 32. The instruction receiving interface 31 is electrically or communicatively connected to the instruction transmitting interface 32. Expansion card 3 can be used to insert into a motherboard (e.g., Figure 1 The expansion card of the motherboard 11 shown, and the instruction transmission interface 32 can be directly connected to the motherboard.
[0045] The instruction receiving interface 31 is used to receive operation instructions corresponding to the basic input / output system (PIS), and when determining that the operation instruction corresponds to a target parameter among multiple accessible parameters of the PIS, to convert the operation instruction according to the PIS instruction format to generate a target instruction. The instruction receiving interface 31 may include a hardware interface of a network service interface. The instruction transmitting interface 32 is used to provide the target instruction or the aforementioned instruction format string to the PIS. The instruction receiving interface 31 and the instruction transmitting interface 32 may be implemented using the processing apparatus described in one or more of the above embodiments.
[0046] The instruction receiving interface 31 can directly output the target instruction to the basic input / output system via the instruction transmission interface 32. Furthermore, the instruction transmission interface 32 can be further configured to output the instruction execution result from the basic input / output system to the instruction receiving interface 31 after outputting the target instruction to the basic input / output system, so that the instruction execution result can be presented on the user interface via the instruction receiving interface 31. In this embodiment, the instruction transmission interface 32 may include a network interface, i.e., the expansion card 3 is connected to the motherboard via the network interface.
[0047] In addition, in embodiments where the expansion card 3 is connected to the motherboard via a network interface, the expansion card 3 may further include a shared memory as described in one or more of the above embodiments, connected to the instruction receiving interface 31 and the instruction transmitting interface 32. The instruction receiving interface 31 may be further used to store target instructions into the shared memory, and the instruction transmitting interface 32 may be further used to store the execution results of instructions from the basic input / output system into the shared memory.
[0048] Please refer to Figure 5 , Figure 5 This is a block diagram illustrating an expansion card according to another embodiment of the present invention. Figure 5 As shown, expansion card 4 includes an instruction receiving interface 41, shared memory 42, and instruction transmission interface 43. The instruction receiving interface 41 is electrically or communicatively connected to the shared memory 42, and the shared memory 42 is electrically or communicatively connected to the instruction transmission interface 43. Expansion card 4 can be used to insert into a motherboard (e.g., Figure 1 The expansion card of the motherboard 11 shown.
[0049] The instruction receiving interface 41 is used to receive operation instructions corresponding to the basic input / output system (PIS), and when determining that the operation instruction corresponds to a target parameter among multiple accessible parameters of the PIS, to convert the operation instruction according to the PIS instruction format to generate a target instruction. The instruction receiving interface 41 can store the target instruction in the shared memory 42. The instruction transmitting interface 43 is used to connect to the PIS to provide the target instruction or the aforementioned instruction format string to the PIS via the shared memory 42. The instruction receiving interface 41 and the instruction transmitting interface 43 can be implemented using the processing apparatus described in one or more of the above embodiments.
[0050] The Basic Input / Output System (PIOS) can read target instructions from shared memory 42 via instruction transfer interface 43. Furthermore, instruction transfer interface 43 can be further configured to store the execution result of the instructions from the PIOS into shared memory 42 after outputting the target instructions to the PIOS. In this embodiment, instruction transfer interface 43 may include a Peripheral Component Interconnect (PCI) interface, meaning that expansion card 4 is directly connected to the motherboard via the PCI interface.
[0051] In one or more of the above embodiments, after the processing device outputs the target instruction to the shared memory or basic input / output system, the processing device may further power on the motherboard, which can then read / receive the target instruction. Furthermore, if the instruction execution result indicates an abnormal condition, the processing device may further power off the motherboard.
[0052] The control system and method of the basic input / output system according to one or more of the above embodiments, as well as the expansion card, allow engineers of the basic input / output system to quickly adjust the settings and / or hardware configuration of the basic input / output system without recompiling the entire basic input / output system's program code, thereby improving development efficiency. Furthermore, by converting operation instructions according to the instruction format of the basic input / output system, the uniformity of instruction format and accurate data transmission can be ensured, thereby enabling the basic input / output system to flexibly perform hardware configuration and control operations. In addition, through embodiments of peripheral component interconnection interfaces and network interfaces, users can choose appropriate methods to modify and control the settings of the basic input / output system according to application scenarios and needs, adapting to more diverse usage scenarios.
[0053] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Any modifications and refinements made without departing from the spirit and scope of the invention are within the scope of patent protection of the present invention. For a description of the scope of protection defined in the present invention, please refer to the appended claims.
Claims
1. A control method for a basic input / output system, executed by a processing device, characterized in that, Include: Obtain the operation instructions corresponding to a basic input / output system; When it is determined that the operation instruction corresponds to a target parameter among the multiple accessible parameters of the basic input / output system, the operation instruction is converted according to the instruction format of the basic input / output system to generate a target instruction. as well as Provide the target instruction to the basic input / output system.
2. The control method for the basic input / output system as described in claim 1, characterized in that, Providing the target instruction to the basic input / output system includes: Store the target instruction in a shared memory. The basic input / output system reads the target instruction from the shared memory.
3. The control method for the basic input / output system as described in claim 2, characterized in that, It also includes: After storing the target instruction in the shared memory, the instruction execution result from the basic input / output system is read from the shared memory.
4. The control method for the basic input / output system as described in claim 1, characterized in that, Providing the target instruction to the basic input / output system includes: The target instruction is output to the basic input / output system via a network interface.
5. The control method for the basic input / output system as described in claim 4, characterized in that, It also includes: After providing the target instruction to the basic input / output system, the instruction execution result from the basic input / output system is received through the network interface.
6. The control method for the basic input / output system as described in claim 4, characterized in that, It also includes: Store the target instruction in a shared memory.
7. A control system for a basic input / output system, characterized in that, Include: A motherboard containing a basic input / output system; A shared memory, connected to the motherboard, is used to store multiple accessible parameters of the basic input / output system; and A processing device is connected to the shared memory and the motherboard. The processing device is used to obtain an operation instruction corresponding to the basic input / output system. When it is determined that the operation instruction corresponds to a target parameter among the plurality of accessible parameters, the processing device converts the operation instruction according to the instruction format of the basic input / output system to generate a target instruction and provides the target instruction to the basic input / output system.
8. The control system of the basic input / output system as described in claim 7, characterized in that, The processing device is further used to store the target instruction into the shared memory, and the basic input / output system reads the target instruction from the shared memory.
9. The control system of the basic input / output system as described in claim 8, characterized in that, The processing device is further configured to, after storing the target instruction in the shared memory, read the instruction execution result from the basic input / output system from the shared memory.
10. The control system of the basic input / output system as described in claim 7, characterized in that, The processing device is connected to the motherboard via a network interface, and the processing device outputs the target instruction to the basic input / output system via the network interface.
11. The control system of the basic input / output system as described in claim 10, characterized in that, The processing device is further configured to receive the instruction execution result from the basic input / output system via the network interface after outputting the target instruction to the basic input / output system.
12. The control system of the basic input / output system as described in claim 10, characterized in that, The processing device is further used to store the target instruction into the shared memory.
13. An expansion card connected to a basic input / output system, characterized in that, This expansion card includes: An instruction receiving interface is used to receive an operation instruction corresponding to the basic input / output system, and when it is determined that the operation instruction corresponds to a target parameter among a plurality of accessible parameters of the basic input / output system, the operation instruction is converted according to the instruction format of the basic input / output system to generate a target instruction. as well as An instruction transmission interface is connected to the instruction receiving interface, and the instruction transmission interface is used to provide the target instruction to the basic input / output system.
14. The expansion card as described in claim 13, characterized in that, It also includes: A shared memory is connected to the instruction receiving interface and the instruction transmitting interface. The instruction receiving interface stores the target instruction into the shared memory, and the basic input / output system reads the target instruction from the shared memory through the instruction transmitting interface.
15. The expansion card as described in claim 14, characterized in that, The instruction transfer interface is further used to store the execution result of the instruction from the basic input / output system into the shared memory after the target instruction is provided to the basic input / output system.
16. The expansion card as described in claim 15, characterized in that, This command transmission interface is a peripheral component interconnection interface.
17. The expansion card as described in claim 13, characterized in that, The command transmission interface is a network interface.
18. The expansion card as described in claim 17, characterized in that, The instruction transmission interface is further used to output the instruction execution result from the basic input / output system to the instruction receiving interface after the target instruction is provided to the basic input / output system.
19. The expansion card as claimed in claim 17, characterized in that, It also includes: A shared memory is connected to the instruction receiving interface, wherein the instruction receiving interface is further used to store the target instruction into the shared memory.