Storage management apparatus, processor, related apparatus and related method

Abstract

Provided are a storage management apparatus, a processor, related apparatuses and related methods. The storage management apparatus comprises: a first-level storage management unit configured to translate a specified virtual address to a corresponding virtual physical address according to a first-level page table cache table item matching the specified virtual address, the first-level page table cache table item storing a mapping relationship between a virtual address frequently accessed by a process in an operation domain and a virtual physical address; and a second-level storage management unit configured to translate the specified virtual physical address to a physical address according to a second-level page table cache table item matching the specified virtual physical address, thereby realizing translation of the virtual address to the physical address, the second-level page table cache table item storing a mapping relationship between the virtual physical address corresponding to the virtual address frequently accessed by the process in the operation domain and the physical address. The embodiments of the present disclosure improve communication efficiency between processes in different operation domains and reduce a large amount of processor computing resources and bus bandwidth.

Description

Technical Field

[0001] This disclosure relates to the field of chips, and more specifically, to a memory management device, a processor, related devices, and related methods. Background Technology

[0002] Modern computer systems are typically multiprocessor systems, consisting of multiple processors. To improve the security of data processing, computer systems can construct one or more operating domains, such as a host operating domain or at least one client operating domain in addition to the host operating domain. Each operating domain runs independently on physical hardware, providing a runtime environment for the corresponding application and operating system running in that domain. Each operating domain includes at least one processor, and processors in different operating domains have exclusive access to hardware devices, including physical memory. Due to the physical memory isolation between different operating domains, the operating system of one operating domain cannot access the physical memory exclusively used by other operating domains. Therefore, communication (such as data exchange) between processes in different operating domains requires data copying between isolated physical memories. This necessitates a large number of memory copying operations during communication between processes in different operating domains, reducing the efficiency of inter-process communication and wasting significant processor computing resources and bus bandwidth. Summary of the Invention

[0003] In view of this, one objective of this disclosure is to improve the efficiency of inter-process communication between different operating domains and reduce the waste of processor computing resources and bus bandwidth.

[0004] In a first aspect, embodiments of this disclosure provide a storage management device located in an operating domain, wherein different operating domains share physical memory, but provide exclusive access to hardware devices other than physical memory, including:

[0005] The first-level storage management unit is used to translate the specified virtual address to the corresponding virtual physical address according to the first-level page table cache entry that matches the specified virtual address. The first-level page table cache entry stores the mapping relationship between virtual addresses and virtual physical addresses that are frequently accessed by processes in the operation domain.

[0006] The second-level storage management unit is used to translate the specified virtual physical address into a physical address according to the second-level page table cache entry that matches the specified virtual physical address, thereby realizing the translation from virtual address to physical address. The second-level page table cache entry stores the mapping relationship between virtual physical address and physical address corresponding to the virtual address frequently accessed by the process in the operation domain.

[0007] Optionally, the first-level storage management unit includes:

[0008] Translation back buffer is used to cache first-level page table cache entries that are frequently accessed by processes in the operational domain;

[0009] The first address translation unit is used to translate the specified virtual address into a corresponding virtual physical address according to the first-level page table cache entry stored in the translation backup buffer when the specified virtual address is matched.

[0010] Optionally, the first-level storage management unit further includes:

[0011] A first control unit, coupled to the first address translation unit, is configured to retrieve a matching entry to be filled from the first-level page table and write the entry to be filled into the translation backup buffer when the first-level page table cache entry cached in the translation backup buffer does not match the specified virtual address.

[0012] Optionally, the second-level storage management unit includes:

[0013] At least one group translation back buffer, the at least one group translation back buffer corresponding to at least one hardware device group in the operation domain, the hardware device group sharing a set of address fields, the group translation back buffer being used to cache the corresponding second-level page table cache entries frequently accessed by the hardware device group;

[0014] The second address translation unit is used to translate the specified virtual physical address into a corresponding physical address according to the second-level page table cache entry when the specified virtual physical address is matched by the second-level page table cache entry stored in the group translation back buffer.

[0015] Optionally, the second-level storage management unit further includes:

[0016] An operation domain translation back buffer, corresponding to the operation domain, is used to cache second-level page table cache entries frequently accessed by the operation domain;

[0017] The second control unit, coupled to the second address translation unit, is used to retrieve a matching entry to be filled from the operation domain translation backup buffer and write the entry to be filled into the corresponding group translation backup buffer when the second-level page table cache entry cached in the group translation backup buffer does not match the specified virtual physical address.

[0018] Optionally, the second control unit is further configured to, when a second-level page table cache entry stored in the operation domain translation back buffer does not hit the specified virtual physical address, obtain a matching entry to be backfilled from the second-level page table, and write the entry to be backfilled into the operation domain translation back buffer and / or the corresponding group translation back buffer.

[0019] In a second aspect, embodiments of this disclosure provide a processor, including:

[0020] Cache memory;

[0021] The storage management device as described above.

[0022] Thirdly, embodiments of this disclosure provide a computing device, including:

[0023] The processor as described above; and

[0024] A memory, coupled to the processor, is used to store first-level page tables and second-level page tables.

[0025] Fourthly, embodiments of this disclosure provide a system-on-a-chip, including:

[0026] The processor as described above; and

[0027] A memory, coupled to the processor, is used to store first-level page tables and second-level page tables.

[0028] Fifthly, embodiments of this disclosure provide a storage management method, including:

[0029] A first-level storage management unit is provided, which translates the specified virtual address to the corresponding virtual physical address according to the first-level page table cache entry that matches the specified virtual address. The first-level page table cache entry stores the mapping relationship between virtual addresses and virtual physical addresses that are frequently accessed by processes in the operation domain.

[0030] A second-level storage management unit is provided, which is used to translate the specified virtual physical address into a physical address according to the second-level page table cache entry that matches the specified virtual physical address, thereby realizing the translation from virtual address to physical address. The second-level page table cache entry stores the mapping relationship between virtual physical address and physical address corresponding to the virtual address frequently accessed by the process in the operation domain.

[0031] The first-level storage management unit and the second-level storage management unit are located in the operation domain. Different operation domains share physical memory, but have exclusive access to hardware devices other than physical memory.

[0032] Sixthly, embodiments of this disclosure provide a communication method applied between different operating domains, which share physical memory but have exclusive access to hardware devices other than physical memory. The operating domains include the storage management device described above, comprising:

[0033] Using the storage management device, the specified virtual address is translated to the corresponding virtual physical address based on a first-level page table cache entry that matches the virtual address specified by the process in the operation domain;

[0034] Update the physical address stored in the second-level page table cache entry of the operation domain that corresponds to the specified virtual physical address to the physical address corresponding to the virtual address specified by the process in another operation domain;

[0035] Using the storage management device, the specified virtual physical address is translated into an updated physical address based on a second-level page table cache entry that matches the specified virtual physical address, thereby realizing the translation from the virtual address to the updated physical address.

[0036] Optionally, the operation domain includes a first operation domain and a second operation domain. The process in the first operation domain specifies a first virtual address, and the second-level page table cache entry of the first operation domain stores the correspondence between the first virtual address and the first virtual physical address. The process in the second operation domain specifies a second virtual address, and the second-level page table cache entry of the second operation domain stores the correspondence between the second virtual address and the second virtual physical address.

[0037] The physical address corresponding to the specified virtual physical address stored in the second-level page table cache entry of the updated operation domain, which is the physical address corresponding to the virtual address specified by a process in another operation domain, includes:

[0038] The first physical address stored in the second-level page table cache entry of the first operation domain is swapped with the second physical address stored in the second-level page table cache entry of the second operation domain.

[0039] In this embodiment, the storage management device located in different operating domains includes a first-level storage management unit and a second-level storage management unit. The first-level page table cache entries store the mapping relationship between virtual addresses frequently accessed by processes in the operating domain and their corresponding virtual physical addresses. The second-level page table cache entries store the mapping relationship between virtual physical addresses and their corresponding physical addresses for the virtual addresses frequently accessed by processes in the operating domain. Thus, the first-level storage management unit can translate a specified virtual address to a corresponding virtual physical address based on the first-level page table cache entry matching the specified virtual address. Similarly, the second-level storage management unit can translate a specified virtual physical address to a corresponding virtual physical address based on the second-level page table cache entry matching the specified virtual physical address. The virtual address is translated into a physical address. This two-level address translation achieves the translation from virtual address to physical address. In situations where physical memory is shared between operating domains of a computer system but exclusive access is required to hardware devices other than physical memory, communication (e.g., data exchange) between processes in different operating domains can be achieved by modifying (e.g., swapping) the physical address corresponding to the virtual physical address stored in the second-level page table cache entry. This translates the specified virtual physical address into an updated physical address, enabling zero-copy communication between processes in different operating domains. This improves the communication efficiency between processes in different operating domains and reduces a significant amount of processor computing resources and bus bandwidth. Attached Figure Description

[0040] The above and other objects, features, and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0041] Figure 1 This is a structural diagram of a data center used in one embodiment of this disclosure;

[0042] Figure 2 This is an internal structural diagram of a computing device according to an embodiment of the present disclosure;

[0043] Figure 3 This is an internal structure diagram of a processor according to an embodiment of the present disclosure;

[0044] Figure 4 An internal structural diagram of a first-level storage management unit according to an embodiment of the present disclosure is shown;

[0045] Figure 5 An internal structural diagram of a second-level storage management unit according to an embodiment of the present disclosure is shown;

[0046] Figure 6 This illustration shows a schematic diagram of the principle of address translation implemented using a first-level memory management unit and a second-level memory management unit according to an embodiment of the present disclosure;

[0047] Figure 7 A schematic flowchart of a storage management method according to an embodiment of the present disclosure is shown;

[0048] Figure 8 A flowchart illustrating a communication method according to an embodiment of this disclosure is shown. Detailed Implementation

[0049] The present disclosure is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present disclosure below, certain specific details are described in detail. Those skilled in the art will fully understand the present disclosure even without these details. To avoid obscuring the substance of the present disclosure, well-known methods, processes, and procedures are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0050] The following terms are used in this document.

[0051] Computing device: A device with computing or processing capabilities. It can take the form of a terminal, such as an IoT device, mobile terminal, desktop computer, or laptop computer, or it can take the form of a server or a cluster of servers. In the data center environment of this application, the computing device is a server in the data center. The computing device can carry one or more operating domains, for example, a host operating domain, or at least one client operating domain in addition to a host operating domain. Each operating domain runs independently on physical hardware, providing a runtime environment for the corresponding application and operating system running in that operating domain. Each operating domain includes at least one processor. Different operating domains share physical memory, and processors located in different operating domains have exclusive access to hardware devices other than physical memory.

[0052] Processor: The processing and control core of a computing device. Its main functions are to execute computer instructions and process data in computer software.

[0053] Memory: A physical structure located within a computer device used to store information. Depending on its purpose, memory can be divided into main memory (also called internal memory, or simply main memory) and auxiliary memory (also called external memory, or simply secondary storage). Main memory stores instruction information and / or data information represented by data signals. For example, it stores data provided by the processor and can also be used to facilitate information exchange between the processor and secondary storage. Information provided by secondary storage needs to be loaded into main memory before it can be accessed by the processor. Therefore, the memory mentioned in this article generally refers to main memory, and the storage devices mentioned generally refer to secondary storage.

[0054] Physical Address (PA): The address on the address bus. A processor or external device (e.g., an input / output device) can provide a physical address to the address bus to access main memory. The physical address is also called the actual address, real address, or absolute address.

[0055] Virtual address: An abstract address used by software or a program running on a processor or external device (e.g., an input / output device). The virtual address space can be larger than the physical address space, and virtual addresses can be mapped to corresponding physical addresses. For example, the abstract address used by software or a program running on the processor is a first virtual address, and the abstract address used by software or a program running on an external device (e.g., an input / output device) is a second virtual address.

[0056] Virtual physical address: An abstract address used by software or programs running in the operating domain. It is obtained by performing a first-level address translation on the virtual address using the first-level memory management unit. The physical address corresponding to the virtual address is obtained by performing a second-level address translation on the virtual physical address using the second-level memory management unit.

[0057] Paging management mechanism: The virtual address space is divided into multiple parts, each representing a virtual page, and the physical address space is also divided into multiple parts, each representing a physical page. A physical page is also called a physical address block or physical address page frame. The virtual physical address space is divided into multiple parts, each representing a virtual physical page.

[0058] The first-level page table (Level 1) specifies the mapping between first virtual pages and virtual physical pages and is typically stored in main memory. It includes multiple entries, each specifying the mapping from first virtual pages to virtual physical pages, along with management flags. This allows it to translate the first virtual address in a first virtual page to the corresponding virtual physical address. The first-level page table can be a single-level table or a multi-level table, such as a second-level table including a first page directory table and a first page table. The first page directory table, also known as the first outer page table or first top-level page table, specifies the mapping between first virtual pages and the first page table. It includes multiple entries, each specifying the mapping from first virtual pages to the first page table, along with management flags. This allows it to translate the first virtual address in a first virtual page to the corresponding first page table number. The first page table specifies the mapping between the first page table number and the virtual physical page. The first page table includes multiple entries, each of which specifies the mapping relationship between the first page table number and the virtual physical page, as well as some management flags, so that the first page table number can be translated into the virtual physical address in the corresponding virtual physical page.

[0059] Level 2 page tables: These specify the mapping between virtual physical pages and physical pages and are typically stored in main memory. A level 2 page table includes multiple entries, each specifying the mapping from virtual physical pages to physical pages and including management flags. This allows for the translation of virtual physical addresses within virtual physical pages into their corresponding physical addresses. Level 2 page tables can be single-level or multi-level, such as a two-level table including a second page directory table and a second page table. The second page directory table, also known as the second outer page table or second top-level page table, specifies the mapping between virtual physical pages and the second page table and is typically stored in main memory. It includes multiple entries, each specifying the mapping from virtual physical pages to the second page table and including management flags. This allows for the translation of virtual physical addresses within virtual physical pages into their corresponding second page table numbers. The second page table specifies the mapping between the second page table number and the physical page and is typically stored in main memory. The second page table includes multiple entries, each of which specifies the mapping relationship between the second page table number and the physical page, as well as some management flags, so that the second page table number can be translated into the physical address in the corresponding physical page.

[0060] Level 1 Page Table Cache Entries: Some frequently used entries in the Level 1 page table can be cached in the translation lookup buffer for easy access during address translation, thus speeding up the translation process. To distinguish them from entries in the Level 1 page table, entries stored in the translation lookup buffer will be referred to as Level 1 page table cache entries in the following text.

[0061] Second-level page table cache entries: Some frequently used entries in the second-level page table can be cached in the translation lookup buffer for easy access during address translation, thus speeding up the translation process. To distinguish them from entries in the second-level page table, entries stored in the translation lookup buffer will be referred to as second-level page table cache entries in the following text.

[0062] Application Environment of This Disclosure

[0063] This disclosure proposes a storage management scheme. The entire storage management scheme is relatively general and can be used for various hardware devices that share physical memory but are otherwise physically isolated, such as data centers, AI (artificial intelligence) acceleration units, GPUs (graphics processing units), IoT (Internet of Things) devices capable of executing deep learning models, and embedded devices. The storage management scheme is independent of the hardware on which the computing device executing the scheme is ultimately deployed. However, for illustrative purposes, the following description will primarily focus on a data center application scenario. Those skilled in the art should understand that this disclosure can also be applied to other application scenarios.

[0064] Data Center

[0065] Data centers are globally collaborative networks of specific devices used to transmit, accelerate, display, compute, and store data information on the internet infrastructure. In the future, data centers will become a key competitive asset for businesses. With the widespread application of data centers, artificial intelligence and other technologies are increasingly being used in them. Neural networks, as a crucial technology in artificial intelligence, are already being extensively applied to big data analytics and computation within data centers.

[0066] In traditional large data centers, the network architecture is typically as follows: Figure 1 As shown, this is the hierarchical inter-networking model. This model includes the following components:

[0067] Server 140: Each server 140 is a processing and storage entity in the data center. The processing and storage of a large amount of data in the data center are all done by these servers 140.

[0068] Access Switch 130: Access Switch 130 is used to connect Server 140 to the data center. One Access Switch 130 connects multiple Servers 140. Access Switches 130 are typically located at the top of the rack, so they are also called Top of Rack switches, and they physically connect the servers.

[0069] Aggregation Switch 120: Each aggregation switch 120 connects to multiple access switches 130 and provides other services such as firewall, intrusion detection, network analysis, etc.

[0070] Core Switch 110: Core Switch 110 provides high-speed forwarding for packets entering and leaving the data center and provides connectivity for Aggregation Switch 120. The entire data center network is divided into an L3 routing network and an L2 routing network. Core Switch 110 typically provides a flexible L3 routing network for the entire data center network.

[0071] Typically, aggregation switch 120 serves as the boundary between L2 and L3 layer routing networks. Below aggregation switch 120 is the L2 network, and above it is the L3 network. Each aggregation switch group manages one Point of Delivery (POD), and each POD contains an independent VLAN network. Server migration within a POD does not require modification of IP addresses and default gateways, as one POD corresponds to one L2 broadcast domain.

[0072] The aggregation switch 120 and access switch 130 typically use the Spanning Tree Protocol (STP). STP ensures that only one aggregation switch 120 is available for a given VLAN network; other aggregation switches 120 are only used in case of failure (dashed lines in the diagram above). In other words, horizontal scaling is not possible at the aggregation switch 120 level, because even if multiple aggregation switches 120 are added, only one will be operational.

[0073] Computing device

[0074] Since server 140 is the actual processing equipment in the data center. Figure 2 An internal structural diagram of a server 140 (computing device 141 or system-on-a-chip 142) according to one embodiment of the present disclosure is shown. The computing device 141 may include a plurality of processors 22. As an example, such as Figure 2 As shown, computing device 141 may include processor 0, processor 1, processor 2 and processor 3, but it should be understood that the number of processors 22 is not limited thereto.

[0075] like Figure 2As shown, the computing device 141 may further include a memory 29. The memory 29 in the computing device 141 may be a main memory (or simply main memory or RAM) used to store instruction information and / or data information represented by data signals, such as storing data provided by the processor 22 (e.g., calculation results), and may also be used to realize data exchange between the processor 22 and the external storage device 27 (or auxiliary memory or external memory).

[0076] In some situations, the processor 22 may need to access memory 29 to retrieve or modify data in memory 29. Since access to memory 29 is relatively slow, to alleviate the speed difference between the processor 22 and memory 29, the computing device 141 also includes a cache memory 28 coupled to bus 21. The cache memory 28 is used to cache program data or message data that may be repeatedly accessed in memory 29. The cache memory 28 is implemented, for example, by a storage device of the type Static Random Access Memory (SRAM). The cache memory 28 can be a multi-level structure, such as a three-level cache structure with a level 1 cache (L1 cache), a level 2 cache (L2 cache), and a level 3 cache (L3 cache), or a cache structure with more than three levels or other types of cache structures. In some embodiments, a portion of the cache memory 28 (e.g., the level 1 cache, or the level 1 cache and the level 2 cache) can be integrated inside the processor 22 or integrated with the processor 22 on the same on-chip system.

[0077] Information exchange between memory 29 and cache memory 28 is typically organized in blocks. In some embodiments, cache memory 28 and memory 29 may be divided into data blocks of the same spatial size, and a data block may serve as the smallest unit of data exchange between cache memory 28 and memory 29 (including one or more data of a preset length). For clarity, the data blocks in cache memory 28 are referred to as cache blocks (or cache lines), and different cache blocks have different cache block addresses; the data blocks in memory 29 are referred to as memory blocks, and different memory blocks have different memory block addresses. Cache block addresses may include, for example, physical address tags used to locate the data blocks.

[0078] Due to space and resource limitations, cache memory 28 cannot cache all the contents of memory 29; that is, the storage capacity of cache memory 28 is usually smaller than that of memory 29, and the addresses of individual cache blocks provided by cache memory 28 cannot correspond to all the memory block addresses provided by memory 29. When processor 22 needs to access memory, it first accesses cache memory 28 via bus 21 to determine whether the content to be accessed is already stored in cache memory 28. If so, cache memory 28 is hit, and processor 22 directly retrieves the content to be accessed from cache memory 28. If the content to be accessed by processor 22 is not in cache memory 28, processor 22 needs to access memory 29 via bus 21 to find the corresponding information in memory 29. Because the access speed of cache memory 28 is very fast, when cache memory 28 is hit, the efficiency of processor 22 can be significantly improved, thereby improving the performance and efficiency of the entire computing device 141.

[0079] As shown in the figure, processor 22, cache memory 28, and memory 29 are packaged in a system-on-a-chip (SoC) 201. Designers can configure the SoC architecture to ensure secure communication between the various components in computing device 141.

[0080] In addition, the computing device 141 may also include hardware devices such as a storage device 27, a display device (not shown), an audio device (not shown), and an input / output device 25. The input / output device 25 may be, for example, a text, audio, and video input / output device. As an example, Figure 2 Input / output devices 0, 1, 2, and 3 are shown, but it should be understood that the number of input / output devices is not limited thereto. Storage devices include, for example, hard disks, optical disks, and flash memory, which are coupled to bus 21 via corresponding interfaces for information access. Display devices are coupled to bus 21 via corresponding graphics cards for displaying information according to display signals provided by bus 21. Computing device 141 typically also includes communication devices (not shown), thus enabling communication with networks or other devices in various ways. Communication devices may include, for example, one or more communication modules. As an example, a communication device may include a wireless communication module suitable for a specific wireless communication protocol. For example, a communication device may include a WLAN module for implementing Wi-Fi™ communication conforming to the IEEE 802.11 standard; a communication device may also include a WWAN module for implementing wireless wide-area communication conforming to cellular or other wireless wide-area protocols; a communication device may also include a Bluetooth module or other communication modules using other protocols, or other custom-type communication modules; a communication device may also be a port for serial data transmission.

[0081] In this example, the computing device 141 may also include various software components, including a host operating system 202, a guest operating system 203, a security monitor 204, an application program 205, a loader 206, and an operation domain monitor 207, as shown in the figure. This software may be embedded in memory 29 or stored in external memory 27. Typically, the operation domain monitor 207, loader 206, host operating system 202, and security monitor 204 are embedded in memory 29, while the guest operating system 203 and application program 205 may be stored in external memory 27.

[0082] In some embodiments, such as Figure 2 As shown, an operation domain monitor 207 is provided above the underlying hardware (i.e., system-on-a-chip 201). The operation domain monitor 207 can run on the physical hardware as a user program. One or more operation domains 26 can be mounted on the operation domain monitor 207, such as host operation domain 0, client operation domain 1, and client operation domain 2. Each operation domain 26 runs independently on the physical hardware, providing a runtime environment for the corresponding application and operating system. Each operation domain 26 includes at least one processor 22. Different operation domains 26 share physical memory, and the processors 22 located in different operation domains 26 have exclusive access to hardware devices other than physical memory. As an example, such as... Figure 2 As shown, processor 0 of host operating domain 0 has exclusive access to input / output device 0, processor 1 of client operating domain 1 has exclusive access to input / output device 1, and processors 2 and 3 of client operating domain 2 have exclusive access to input / output devices 2 and 3, respectively. The operating domain monitor 207 is the core supporting the computing device 141, providing physical memory management and scheduling for different operating domains 26. When an operating domain 26 starts up (i.e., the processor 22 located in that operating domain starts up), it allocates physical memory space for that operating domain 26. When an operating domain 26 exits operation (i.e., the processor 22 located in that operating domain exits operation), it releases the physical memory space of that operating domain 26, thereby allowing different operating domains 26 to share physical memory in a time-sharing manner. In some embodiments, such as... Figure 2As shown, after the computing device 141 is powered on or restarted, the entire computing device 141 is in host operation domain 0, which enjoys the entire memory space. When client operation domain 1 and / or client operation domain 2 starts, commands can be created to instruct the processor 22 assigned to operation domain 26, as well as hardware devices other than physical memory, and to instruct the physical memory space allocated to operation domain 26. Then, based on security monitor 204, the exclusive access permission data of operation domain 26 to hardware devices other than physical memory can be written to memory 29. Based on operation domain monitor 207, a first-level memory management unit (not shown) and a second-level memory management unit 23 can be allocated to operation domain 26, and address translation data can be written to the registers of the first-level memory management unit and the second-level memory management unit 23. When client operation domain 1 or client operation domain 2 exits operation, the corresponding permission data in memory 29 can be cleared based on security monitor 204, and the corresponding first-level memory management unit and the second-level memory management unit 23 can be reclaimed based on operation domain monitor 207. In addition, operation domain monitor 207 can even simulate certain hardware functions.

[0083] In some embodiments, the host operating system 202 and the guest operating system 203 operate in different operating domains 26. The host operating system 202 resides in the host operating domain, and the guest operating system 203 resides in the guest operating domain. The host operating system 202 manages the guest operating system 203, primarily responsible for its startup and shutdown. The host operating system 202 does not participate in the guest operating system 203's access to physical resources or communication. The host operating system 202 and the guest operating system 203 share system buses such as the address bus, data bus, and control bus. Communication between the host operating system 202 and the guest operating system 203, as well as between different guest operating systems 203, is implemented using internal communication mechanisms (e.g., Virtio, a semi-virtualized device abstraction interface specification).

[0084] In some cases, the loader 206 and the host operating system 202 can be combined into one. For these software programs, the loader 206 can be configured to verify and load various software programs into the cache memory 28. The loader 206 itself can be software loaded in a secure manner. The system-on-chip 201 can be configured to retrieve the loader 206 from memory 29 immediately or quickly after system power-on or reset. Then, based on configuration information, it can determine which software to load, and further load the corresponding software into the cache memory 28 based on the verification results, such as software origin, fingerprint, or certificate. Some applications 205 can be independent of the host operating system 202 and loaded by the loader 206, while other applications 205 can depend on the host operating system 202, and be loaded and controlled by the host operating system 202. For example, the security monitor 204 can exist independently of the host operating system 202. Application 205 may include, but is not limited to, programs for controlling or responding to external devices (e.g., biometric sensors, printers, microphones, speakers, flow valves, or other I / O components, sensors, actuators, or devices), programs for various I / O tasks, security programs, authentication programs, various computing modules, communication programs, communication support protocols, or other programs, or combinations thereof.

[0085] In one implementation, the host operating system 202 may determine when to load and execute the security monitor 204 based on the system environment. In another implementation, during the system power-on initialization phase, the loader 206 loads and executes the security monitor 204 according to configuration information. The security monitor 204 may write permission data to the memory 29 according to the application configuration table. The application configuration table may include information on hardware devices used by each application, excluding physical memory, and also includes exclusive access requirements for hardware devices other than physical memory. The application configuration table may be created based on the application's compilation information and stored in a specific location (e.g., in the memory 29). The permission data includes the exclusive access permissions of each operating domain 26 to hardware devices other than physical memory. In some embodiments, when client operating domain 1 and / or client operating domain 2 starts, the host operating system 202 allocates exclusive hardware devices for client operating domain 1 and / or client operating domain 2 according to the permission data.

[0086] In some embodiments, the computing device 141 further includes a first-level memory management unit (MMU) (not shown). The first-level memory management unit may be located within or outside the processor 22 of a different operating domain 26. The first-level memory management unit is used to translate a first virtual address to a corresponding virtual physical address. In some embodiments, the computing device 141 further includes a second-level memory management unit 23, which may be located outside or within the processor 22 of a different operating domain 26. As an example, such as... Figure 2 As shown, the second-level storage management unit 0 is located outside the processor 22 of the host operating domain 0, the second-level storage management unit 1 is located outside the processor 22 of the client operating domain 1, and the second-level storage management unit 2 is located outside the processor 22 of the client operating domain 2. The second-level storage management unit 23 is used to implement the translation of virtual physical addresses to corresponding physical addresses. Since the process of implementing two-level address translation using the second-level storage management unit 23 and the first-level storage management unit will be described in detail below, it will not be repeated here.

[0087] In some embodiments, the computing device 141 may further include an input / output memory management unit 24, which is packaged together with the processor 22, the cache memory 28 and the memory 29 in a system-on-chip (SoC) 201.

[0088] The input / output storage management unit 24 is used to translate the second virtual address to the physical address. The mapping relationship between each second virtual page in the second virtual address space and each physical page in the physical address space can be stored in a page table in main memory. This page table generally includes many entries, each entry providing a mapping relationship between a second virtual page and a corresponding physical page. Thus, the second virtual address in the second virtual page matching the entry can be translated into the corresponding physical address according to the entry. In some embodiments, during the operation of an application 205 or other entity, it may trigger its running input / output device 25 to send a memory access request. Accordingly, the input / output storage management unit 24 translates the second virtual address of the memory access request to obtain the corresponding physical address, accesses the physical address, and reads or writes data from physical memory.

[0089] Of course, the structure of different computer systems may vary depending on the motherboard, operating system, and instruction set architecture.

[0090] processor

[0091] Figure 3 This is a schematic block diagram of a processor 22 according to an embodiment of the present disclosure.

[0092] In some embodiments, each processor 22 may include one or more processor cores 228 for processing instructions, the processing and execution of which can be controlled by a user (e.g., through an application) and / or the system platform. In some embodiments, each processor core may be used to process a specific instruction set. In some embodiments, the instruction set may support Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation based on Very Long Instruction Word (VLIW). Different processor cores 228 may each process different instruction sets. In some embodiments, processor cores 228 may also include other processing modules, such as Digital Signal Processors (DSPs). As an example, Figure 2 The diagram shows processor cores 1 through m, where m is a non-zero natural number.

[0093] In some embodiments, such as Figure 2 As shown, processor 22 may include cache memory 28, and depending on the architecture, cache memory 28 in processor 22 may be a single or multiple levels of internal cache memory 28 located within and / or outside each processor core 228 (e.g., ...). Figure 2 The illustrated three-level cache (L1 to L3) may also include an instruction-oriented cache and a data-oriented cache. In some embodiments, the various components in processor 22 may share at least a portion of the cache 28, such as... Figure 2 As shown, processor cores 1 to m share a common level 3 cache memory L3. Processor 22 may also include an external cache (not shown), and other cache structures may also serve as external caches for processor 22.

[0094] In some embodiments, such as Figure 2 As shown, processor 22 may include register file 227, which may include multiple registers for storing different types of data and / or instructions. These registers may be of different types. For example, register file 227 may include integer registers, floating-point registers, status registers, instruction registers, and pointer registers. The registers in register file 227 may be implemented using general-purpose registers, or a specific design may be adopted according to the actual needs of processor 22.

[0095] In some embodiments, the processor 22 may include a first-level memory management unit 222. The first-level memory management unit 222 stores multiple first-level page table cache entries for translating a first virtual address in a first virtual page to a corresponding virtual physical address. Each processor core 228 may have one or more first-level memory management units 222. The first-level memory management units 222 in different processor cores 228 may also be synchronized with those in other processors or processor cores, enabling each processor or processor core to share a unified virtual memory system.

[0096] In some embodiments, the internal interconnect structure is used to enable the first-level memory management unit 222 to interact with other processor cores via the system-on-a-chip's internal bus, or to directly connect with other modules within the system-on-a-chip to achieve signal exchange.

[0097] The first-level memory management unit 222 can communicate with the instruction prefetch unit 224 used for prefetching instructions and / or the load / store unit (LSU) 225 used for loading / storing data in the processor 22.

[0098] The instruction prefetching unit 224 accesses the first-level memory management unit 222 using the first virtual address of the prefetched instruction to translate the virtual physical address corresponding to the first virtual address of the prefetched instruction. The first-level memory management unit 222 then accesses the second-level memory management unit 23 using the virtual physical address to translate the physical address. The instruction prefetching unit 224, based on the physical address translated by the second-level memory management unit 23, performs addressing in the physical address space to obtain the corresponding instruction. The execution unit in the processor core 228 can receive the instruction obtained by the instruction prefetching unit 224 and process (e.g., decode) the instruction so that it can be executed.

[0099] Load memory unit 225 is an instruction execution unit oriented towards memory access instructions (load instructions or store instructions). Load memory unit 225 can be used to retrieve data information from cache memory 28 and / or memory 29 according to load instructions, and load this data information into the corresponding registers within processor 22; load memory unit 225 can also store data information from the corresponding registers into cache memory 28 and / or memory 29 according to store instructions. Registers include, for example, the address register, step register, and address mask register in register file 227. Load memory unit 225 accesses the first-level memory management unit 222 according to the first virtual address of the memory access instruction, to translate the virtual physical address corresponding to the first virtual address of the memory access instruction. The first-level memory management unit 222 uses the virtual physical address to access the second-level memory management unit 23, to translate the physical address. Load memory unit 225 receives the physical address of the memory access instruction translated by the second-level memory management unit 23, enabling load memory unit 225 to access the corresponding data in the physical address space according to the physical address.

[0100] It should be noted that the above and Figure 2 This description is merely illustrative of one of the processors in the system and is not intended to limit the specific implementation of processor 22. Processor 22 may also include other components, such as a data processing unit; various parts of processor 22 described above may also be appropriately omitted in practical applications.

[0101] Storage Management Unit

[0102] The storage management unit, also known as the memory management unit in some cases, can be a storage management device implemented in hardware and / or software.

[0103] To better manage the address space occupied by each process, computing device 141 can allocate independent virtual address spaces to some processes and provide a mapping relationship from virtual addresses to physical addresses to map or demap virtual address spaces to physical address spaces. Since data transfer in computing device 141 is usually performed in units of pages, computer systems and / or operating systems running on computer systems typically manage physical address spaces and virtual address spaces in units of pages. The virtual address space can be larger than the physical address space; that is, a virtual page in the virtual address space can be mapped to a physical page in the physical address space, or it can be mapped to a swap file, or it may not be mapped at all.

[0104] Based on the paging management mechanism described above, the mapping relationship between each first virtual page and each virtual physical page in the first virtual address space can be stored in the first-level page table in main memory. The first-level page table typically includes many entries, each entry providing a mapping relationship between a first virtual page and its corresponding virtual physical page. Thus, the first virtual address in the first virtual page matching that entry can be translated into the corresponding virtual physical address. The mapping relationship between virtual physical pages and each physical page in the physical address space can be stored in the second-level page table in main memory. The second-level page table typically includes many entries, each entry providing a mapping relationship between a virtual physical page and its corresponding physical page. Thus, the virtual physical address matching that entry can be translated into the corresponding physical address. Therefore, through the two-level translation process of the first-level and second-level page tables, the first virtual address in the first virtual page is translated into the physical address of the corresponding physical page.

[0105] For a given process, the virtual address range (which can be referred to as the page size of the virtual page) corresponding to each first virtual page should be consistent with the page size of the corresponding virtual physical page and physical page, such as, but not limited to, 4kB (kilobytes), 8kB, 16kB, 64kB, etc. It should be noted that for different processes, the page size of the corresponding first virtual page may or may not be consistent; similarly, for different processes, the page size of the corresponding virtual physical page and physical page may or may not be consistent, and different embodiments may have different choices.

[0106] In order to reduce the number of memory accesses by the storage management unit and speed up the address translation process, at least one translation backup buffer (TLB, also known as a fast table, bypass translation buffer, page table buffer, etc.) may be provided in the first-level storage management unit 222 and the second-level storage management unit 23 of this disclosure embodiment.

[0107] Figure 4 A schematic block diagram of a first-level memory management unit according to an embodiment of this disclosure is shown. Figure 4As shown, the first-level memory management unit 222 includes an address translation unit 41, a control unit 42, and a translation lookup buffer (TLB) 43. In some embodiments, the translation lookup buffer (TLB) 43 is used to copy entries from memory into the first-level page table that may be frequently accessed by processes in the operating domain, and store them as first-level page table cache entries to cache the mapping relationship between frequently used first virtual pages and virtual physical pages. The translation lookup buffer (TLB) 43 can be an instruction TLB and / or a data TLB, or it can be a multi-level TLB. Address translation unit 41 is used to search for the corresponding first-level page table cache entry in the translation backup buffer TLB 43 according to the virtual address translation request, and translate the specified first virtual address into a virtual physical address according to the first-level page table cache entry. When address translation unit 41 does not find a first-level page table cache entry in the translation backup buffer TLB 43 that matches the first virtual address to be translated, it can transmit mismatch information to control unit 42. Control unit 42 obtains a matching entry to be filled from the first-level page table according to the mismatch information, and writes the entry to be filled into the translation backup buffer TLB 43 so that the translation backup buffer TLB 43 can be hit. Subsequently, address translation unit 41 can convert the first virtual address to be translated into a virtual physical address according to the matching first-level page table cache entry. The Level 1 Memory Management Unit 222 will only access the Level 1 page table in memory to obtain the corresponding entry if no matching Level 1 page table cache entry for the specified first virtual address can be found in the Translation Lookahead Buffer (TLB43). When a matching Level 1 page table cache entry exists in the TLB43, the Level 1 Memory Management Unit 222 can complete the translation from the first virtual address to the virtual physical address without accessing the Level 1 page table. Therefore, the number of memory accesses by the Level 1 Memory Management Unit 222 is reduced, thereby saving the time required for address translation and improving processor performance.

[0108] It should be noted that the above and Figure 4 This description is merely illustrative of one of the first-level storage management units and is not intended to limit the specific implementation of the first-level storage management unit.

[0109] Figure 5 A schematic block diagram of a second-level storage management unit according to an embodiment of this disclosure is shown. Figure 5 As shown, the second-level memory management unit 23 includes an address translation unit 51, a control unit 52, at least one group translation back buffer (GTLB) 53, and an operation domain translation back buffer (jTLB) 54. As an example, Figure 5 The table shows GTLB1 to GTLBn, where n is a positive integer.

[0110] In some embodiments, hardware devices accessed exclusively by operation domain 26, excluding physical memory, can be divided into at least one hardware device group (e.g., the hardware device group in operation domain 26 corresponds to processor 22). Each hardware device group shares a set of address fields, and a group translation back buffer (GTLB53) is used to translate the virtual physical address of a hardware device group. As an example, hardware devices accessed exclusively by operation domain 26, excluding physical memory, can be divided into n hardware device groups (i.e., hardware device groups 1 to n), with n hardware device groups corresponding to n group translation back buffers (GTLB53). In some embodiments, the group translation back buffer (GTLB53) is used to copy entries from memory in the second-level page table that may be accessed by the corresponding hardware device group into the group translation back buffer (GTLB53) and store them as second-level page table cache entries to cache the mapping relationship between virtual physical pages and physical pages commonly used by the corresponding hardware device group. In some embodiments, the operation domain translation back buffer jTLB54 is used to copy entries from memory into the second-level page table that may be accessed by the operation domain 26, and store them as second-level page table cache entries to cache the mapping relationship between virtual physical pages and physical pages frequently used by the operation domain 26. In some embodiments, in the second-level storage management unit 23 of each operation domain 26, at least one second-level page table cache entry cached in the group translation back buffer GTLB53 is cached in the operation domain translation back buffer jTLB54, and the operation domain translation back buffer jTLB54 caches more second-level page table cache entries than the second-level page table cache entries cached in the group translation back buffer GTLB53. The group translation back buffer GTLB53 and the operation domain translation back buffer jTLB54 can be instruction TLBs and / or data TLBs, or multi-level TLBs.

[0111] In some embodiments, the address translation unit 51 is configured to search for the corresponding second-level page table cache entry in the corresponding group translation back buffer GTLB 53 according to the virtual physical address translation request corresponding to the hardware device group, and translate the specified virtual physical address into a physical page according to the second-level page table cache entry; for example, the address translation unit 51 searches for the corresponding second-level page table cache entry in the group translation back buffer GTLB 2 according to the virtual physical address translation request corresponding to the hardware device group 2, and translates the specified virtual physical address 2 into a physical page according to the second-level page table cache entry. When the address translation unit 51 does not find a second-level page table cache entry in the group translation back buffer GTLB 53 that matches the virtual physical address to be translated, it can transmit first mismatch information to the control unit 52. The control unit 52 obtains a matching entry to be filled from the operation domain translation back buffer jTLB 54 based on the first mismatch information and writes the entry to be filled into the group translation back buffer GTLB 53, so that the group translation back buffer GTLB 53 can be hit. Subsequently, the address translation unit 51 can convert the virtual physical address to be translated into a physical address based on the matching second page table cache entry. When the control unit 52 fails to obtain a matching entry to be filled from the operation domain translation backup buffer jTLB54 based on the first mismatch information, the address translation unit 51 can transmit the second mismatch information to the control unit 52. The control unit 52 obtains the matching entry to be filled from the second-level page table based on the second mismatch information and writes the entry to be filled into the operation domain translation backup buffer jTLB54 and / or the group translation backup buffer GTLB53, so that the group translation backup buffer GTLB53 can be hit. Subsequently, the address translation unit 51 can convert the virtual physical address to be translated into a physical address based on the matching second-level page table cache entry.

[0112] The Level 2 Memory Management Unit 23 will only access the Level 2 Page Table Cache entries in the Operation Domain Translation Backup Buffer (jTLB54) to obtain the corresponding entry if no matching Level 2 Page Table Cache entry for the specified virtual physical address can be found in the Group Translation Backup Buffer (GTLB53). When a matching Level 2 Page Table Cache entry exists in the GTLB53, the Level 2 Memory Management Unit 23 can complete the virtual-to-physical address translation without accessing the operation domain translation backup Buffer (jTLB54). Compared to the operation domain translation backup Buffer (jTLB54), the GTLB53 stores fewer Level 2 Page Table Cache entries. A GTLB53 hit significantly reduces the number of Level 2 Page Table Cache entries that need to be compared with the specified virtual physical address, thereby reducing the time required to search for Level 2 Page Table Cache entries during address translation. This improves processor efficiency, frequency, and performance while reducing power consumption during address translation.

[0113] The second-level memory management unit 23 will only access the second-level page table in memory to obtain the corresponding entry if no matching entry for the specified virtual physical address can be found in the operation domain translation lookup buffer jTLB54. When a matching entry exists in the operation domain translation lookup buffer jTLB54, the second-level memory management unit 23 can complete the virtual-to-physical address translation without accessing the second-level page table. Therefore, the number of memory accesses by the second-level memory management unit 23 is reduced, thus saving the time required for address translation and improving processor performance.

[0114] In some embodiments, when the group translation back buffer GTLB53 in the second-level storage management unit 23 is not hit and the operation domain translation back buffer jTLB54 is hit, the control unit 52 can also select a cache entry to be replaced based on the frequency of use of each second-level page table cache entry in the group translation back buffer GTLB53. For example, the LRU (Least Recently Used) algorithm can be used to replace a second-level page table cache entry in the group translation back buffer GTLB53 that has not been used for the longest time, and the selected cache entry can be replaced with a cache entry in the hit operation domain translation back buffer jTLB54.

[0115] In some embodiments, when both the group translation back buffer GTLB53 and the operation domain translation back buffer jTLB54 in the second-level storage management unit 23 are missed, the control unit 52 may also select a cache entry to be replaced based on the frequency of use of each second-level page table cache entry in the operation domain translation back buffer jTLB54. For example, the LRU (Least Recently Used) algorithm may be used to replace a cache entry in the operation domain translation back buffer jTLB54 that has not been used for the longest time. The selected cache entry may be replaced with a cache entry that has been hit in the second page table.

[0116] In some embodiments, when both the group translation back buffer (GTLB) 53 and the operation domain translation back buffer (jTLB) 54 in the second-level memory management unit 23 are missed, and the second-level page table stored in memory is also missed, the control unit 52 can notify the host operating system 202 that a page access error has occurred. The host operating system 202 can call the corresponding system operation function to determine whether the first virtual address to be translated is a valid address. If it is a valid address, the physical page corresponding to the virtual page of the first virtual address is read into memory, and the mapping relationship between the virtual page and the virtual physical page of the first virtual address is written into the first-level page table, and the mapping relationship between the virtual physical page and the physical page is written into the second-level page table, so that the processor 22 can restart from the position where the page access error occurred. If it is an invalid address, the host operating system 202 terminates the page access. In some embodiments, when the physical page corresponding to the virtual page at the first virtual address is read into memory, if there is no free physical page in memory, the host operating system 202 calls the corresponding system operation function to select and replace a physical page in memory that has not been used the most recently, least recently, and replaces the selected physical page with the physical page corresponding to the virtual page at the first virtual address. If the replaced physical page has not been modified, it is deleted; if the replaced physical page has been modified, it is written back to secondary storage.

[0117] It should be noted that, in some embodiments, the above and Figure 5 The device structure shown is also applicable to the first-level memory management unit 222 and the I / O memory management unit 24 of the embodiments of this disclosure.

[0118] This embodiment will use the Full Associative method as an example to describe the mapping method between the first virtual address and cache entries (first-level page table cache entries and second-level page table cache entries). However, this embodiment is not limited to this. In some other embodiments, the mapping method between the first virtual address and cache entries can also be: direct mapping method, set associative method, or other mapping methods.

[0119] Figure 6 This diagram illustrates the principle of address translation using a first-level memory management unit (MLM) and a second-level memory management unit (MLM). In some embodiments, both the first-level and second-level page tables are second-level page tables. A specified first virtual address can be translated into the first page table number of the corresponding first page table through a matching first page directory cache entry, and this first page table number can be translated into the corresponding virtual physical address through a matching first page table cache entry. Similarly, a specified virtual physical address can be translated into the second page table number of the corresponding second page table through a matching second page directory cache entry, and this second page table number can be translated into the corresponding physical address through a matching second page table cache entry. In some embodiments, such as... Figure 6 As shown, the data structure of the first page directory cache entry may include: page directory label 1, page table start address 1, and auxiliary information, etc. The data structure of the first page table cache entry may include: page table number 1, physical page label 1, and auxiliary information, etc. The data structure of the second page directory cache entry may include: page directory label 2, page table start address 2, and auxiliary information, etc. The data structure of the second page table cache entry may include: page table number 2, physical page label 2, and auxiliary information, etc. In some embodiments, the auxiliary information includes a size flag bit of the page mapped to the cache entry, a valid bit indicating the status of each cache entry, a reference flag bit indicating usage frequency, a dirty bit, etc.

[0120] In some embodiments, page directory label 1 is used to determine whether a first page directory cache entry matches a first virtual address to be translated. Page directory number 1 can be used to identify a first virtual page, therefore, the page directory label 1 of the first page directory cache entry and the page directory number 1 of the first virtual page mapped by the cache entry can be set to the same binary code. Page table start address 1 is used to identify the starting address in memory used to store the corresponding first page table. Page table start address 1 and page offset 1 are combined to form page table label 1 of the first virtual page mapped by the first page directory cache entry. Page table label 1 is used to determine whether a first page table cache entry matches a first virtual address to be translated. Page table number 1 can be used to identify a first virtual page, therefore, the page table number 1 of the first page table cache entry and the page table label 1 of the first virtual page mapped by the first page directory cache entry can be set to the same binary code. Physical page number 1 is used to identify a virtual physical page, and physical page label 1 is used to determine whether a first page table cache entry matches a virtual physical address, therefore, the physical page label 1 of the first page table cache entry and the physical page number 1 of the virtual physical page can be set to the same binary code. When the page directory number 1 of the first virtual address to be translated matches the page directory label 1 of the first page directory cache entry, and the page table label 1 formed by combining the page table start address 1 and page offset 1 of the first page directory cache entry matches the page table number 1 of the first page table cache entry, and the physical page label 1 of the first page table cache entry matches the physical page number 1 of the virtual physical address, it indicates that both the first page directory cache entry and the first page table cache entry have been hit. In this case, since the first virtual address and its mapped virtual physical address have the same page offset 1, the physical page label 1 provided by the hit first page table cache entry and the page offset 1 of the first virtual address to be translated can be combined to form the virtual physical address mapped by the first virtual address to be translated, thus completing the first-level address translation.

[0121] In some embodiments, after the virtual physical address obtained during the first-level address translation process is re-partitioned, the data structure of the virtual physical address may include page directory number 2, page offset 2, and page offset 2. In some embodiments, page directory label 2 is used to determine whether the second page directory cache entry matches the virtual physical address to be translated. Page directory number 2 can be used to identify the virtual physical page, so the page directory label 2 of the second page directory cache entry can be set to the same binary code as the page directory number 2 of the virtual physical page mapped by the cache entry. Page table start address 2 is used to identify the starting address in memory used to store the corresponding second page table. Page table start address 2 and page offset 2 are combined to form the page table label 2 of the virtual physical page mapped by the second page directory cache entry. Page table label 2 is used to determine whether the second page table cache entry matches the virtual physical address to be translated. Page table number 2 can be used to identify the virtual physical page, so the page table number 2 of the second page table cache entry can be set to the same binary code as the page table label 2 of the virtual physical page mapped by the second page directory cache entry. Physical page number 2 is used to identify the physical page, and physical page tag 2 is used to determine whether the second page table cache entry matches the physical address. Therefore, the physical page tag 2 of the second page table cache entry and the physical page number 2 of the physical page can be set to the same binary code. When the page directory number 2 of the virtual physical address to be translated matches the page directory tag 2 of the second page directory cache entry, and the page table tag 2 composed of the page table start address 2 and page offset 2 of the second page directory cache entry matches the page table number 2 of the second page table cache entry, and the physical page tag 2 of the second page table cache entry matches the physical page number 2 of the physical address, it means that both the second page directory cache entry and the second page table cache entry have been hit. In this case, since the virtual physical address and its mapped physical address have the same page offset 2, the physical page tag 2 provided by the hit second page table cache entry and the page offset 2 of the virtual physical address to be translated can be combined to form the physical address mapped by the virtual physical address to be translated, thus completing the second-level address translation. At this point, the address translation is complete.

[0122] It should be noted that, although in the above text and Figure 6 In the description, the page directory label, page table start address, and auxiliary information of the page directory cache table entry, as well as the page table number, physical page label, and auxiliary information of the page table cache table entry, are arranged in order from high to low byte. However, the embodiments of this disclosure are not limited to this. The data structure of each cache table entry can be arranged in a different order. The page directory number, page offset, and page offset included in the virtual address, the page directory number, page offset, and page offset included in the intermediate physical address, and the high and low position settings and division methods of the physical page number and page offset included in the physical address can be different.

[0123] Storage management method of this disclosure embodiment

[0124] According to one embodiment of this disclosure, a storage management method is provided. This method can be executed by an operation domain monitor 207. Figure 7 As shown, a storage management method according to an embodiment of this disclosure includes: step S710, providing a first-level storage management unit, which translates the specified virtual address to a corresponding virtual physical address according to a first-level page table cache entry that matches the specified virtual address, wherein the first-level page table cache entry stores the mapping relationship between virtual addresses and virtual physical addresses frequently accessed by processes in the operation domain; step S720, providing a second-level storage management unit, which translates the specified virtual physical address to a physical address according to a second-level page table cache entry that matches the specified virtual physical address, thereby realizing the translation from virtual address to physical address, wherein the second-level page table cache entry stores the mapping relationship between virtual physical addresses and physical addresses corresponding to virtual addresses frequently accessed by processes in the operation domain; wherein the first-level storage management unit and the second-level storage management unit are located in the operation domain, and different operation domains share physical memory, but have exclusive access to hardware devices other than physical memory.

[0125] Since the process of translating virtual addresses to physical addresses using the above-mentioned storage management device through two-level address translation has been described in detail in the above device embodiments, it will not be repeated here.

[0126] Communication method of this disclosure embodiment

[0127] According to one embodiment of this disclosure, a communication method is provided. This method can be executed by an operation domain monitor 207. For example... Figure 8 As shown, a communication method according to an embodiment of this disclosure includes: step S810, using the storage management device, translating the specified virtual address to a corresponding virtual physical address based on a first-level page table cache entry that matches the virtual address specified by a process in the operation domain; step S820, updating the physical address corresponding to the specified virtual physical address stored in a second-level page table cache entry of the operation domain to the physical address corresponding to the virtual address specified by a process in another operation domain; step S830, using the storage management device, translating the specified virtual physical address to an updated physical address based on a second-level page table cache entry that matches the specified virtual physical address, thereby realizing the translation from the virtual address to the updated physical address.

[0128] Since the process of translating a specified virtual address into a corresponding virtual physical address to complete the first-level address translation and translating a specified virtual physical address into a corresponding physical address to complete the second-level address translation using the aforementioned storage management device has been described in detail in the above device embodiments, it will not be repeated here. Step S820 will be described in detail below.

[0129] Step S820: Update the physical address stored in the second-level page table cache entry of the operation domain that corresponds to the specified virtual physical address to the physical address corresponding to the virtual address specified by the process in another operation domain.

[0130] As described above, for each operating domain, the second-level page table cache entry of the operating domain stores the correspondence between the virtual physical address and the physical address corresponding to the virtual address specified by the process. In some embodiments, the computing device includes a first operating domain and a second operating domain. The process of the first operating domain specifies virtual address 1, and the second-level page table cache entry of the first operating domain stores the correspondence between virtual physical address 1 and physical address 1 corresponding to virtual address 1. The process of the second operating domain specifies virtual address 2, and the second-level page table cache entry of the second operating domain stores the correspondence between virtual physical address 2 and physical address 2 corresponding to virtual address 2. In some embodiments, if the physical address 1 corresponding to the specified virtual physical address 1 stored in the second-level page table cache entry of the update operation domain 1 is the physical address corresponding to the virtual address specified by a process in another operation domain (e.g., operation domain 2), the second-level storage management unit can be used to translate the specified virtual physical address 1 to the changed physical address (e.g., physical address 2) according to the second-level page table cache entry that matches the virtual physical address 1 specified by the process in operation domain 1. In this way, the virtual address 1 specified by the process in operation domain 1 is translated into a physical address in another operation domain after two levels of translation, realizing process communication between operation domain 1 and other operation domains. In some embodiments, the physical address 1 stored in the second-level page table cache entry of operation domain 1 can be exchanged with the physical address 2 stored in the second-level page table cache entry of operation domain 2. In this way, the virtual address 1 specified by the process in operation domain 1 is translated into the physical address 2 in operation domain 2 after two levels of translation, and the virtual address 2 specified by the process in operation domain 2 is translated into the physical address 1 in operation domain 1 after two levels of translation. This realizes the data exchange between operation domain 1 and operation domain 2, and thus realizes the process communication between operation domain 1 and operation domain 2 in a zero-copy manner.

[0131] The commercial value of the embodiments disclosed herein

[0132] In the computing device provided in this disclosure, when processes in different operating domains communicate (e.g., exchange data), the physical pages corresponding to the virtual physical pages stored in the entries of the second-level page table can be modified (e.g., swapped). This modifies the physical pages corresponding to the virtual addresses frequently accessed by processes in the operating domain, thereby achieving zero-copy communication between processes in different operating domains. This improves the efficiency of inter-process communication between different operating domains of the computing device and reduces a significant amount of processor computing resources and bus bandwidth. In this scenario, by reducing processor computing resources and bus bandwidth, the communication cost between processes in different operating domains of the computing device is reduced, thereby reducing the overall operating cost of the data center. This disclosure reduces the overall operating cost of the data center, thus possessing significant commercial and economic value.

[0133] Those skilled in the art will understand that this disclosure can be implemented as a system, method, and computer program product. Therefore, this disclosure can be implemented as entirely hardware, entirely software (including firmware, resident software, and microcode), or a combination of software and hardware. Furthermore, in some embodiments, this disclosure can also be implemented as a computer program product contained in one or more computer-readable media, the computer-readable media containing computer-readable program code.

[0134] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium is, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium include: an electrical connection of one or more wires, a portable computer disk, hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with a processing unit, apparatus, or device.

[0135] Computer-readable signal media may include data signals propagated in baseband or as part of a chopped signal, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any other suitable combination. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of transmitting, propagating, or transmitting programs for use by or in connection with an instruction system, apparatus, or device.

[0136] The program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical fiber, RF, and any suitable combination thereof.

[0137] Computer program code for executing embodiments of this disclosure can be written in one or more programming languages ​​or combinations thereof. The programming languages ​​include object-oriented programming languages ​​such as JAVA and C++, and may also include conventional procedural programming languages ​​such as C. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAn) or a wide area network (WAn), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0138] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A storage management device, the storage management device being located in an operating domain, wherein different operating domains share physical memory, but have exclusive access to hardware devices other than physical memory, comprising: The first-level storage management unit is used to translate the specified virtual address to the corresponding virtual physical address according to the first-level page table cache entry that matches the specified virtual address. The first-level page table cache entry stores the mapping relationship between virtual addresses and virtual physical addresses that are frequently accessed by processes in the operation domain. The virtual physical address is an abstract address obtained by address translation of the virtual address. The second-level storage management unit is used to translate the specified virtual physical address into a physical address according to a second-level page table cache entry that matches the specified virtual physical address, thereby realizing the translation from virtual address to physical address. The second-level page table cache entry stores the mapping relationship between virtual physical addresses and physical addresses corresponding to virtual addresses frequently accessed by processes in the operation domain. The second-level storage management unit includes: at least one group translation back buffer, which corresponds to at least one hardware device group in the operation domain. The hardware device groups share a set of address fields, and the group translation back buffer is used to cache the corresponding second-level page table cache entries frequently accessed by the corresponding hardware device group; and a second address translation unit, which is used to translate the specified virtual physical address into a corresponding physical address according to the second-level page table cache entry when the second-level page table cache entry stored in the group translation back buffer matches the specified virtual physical address.

2. The storage management device according to claim 1, wherein, The first-level storage management unit includes: Translation back buffer is used to cache first-level page table cache entries that are frequently accessed by processes in the operational domain; The first address translation unit is used to translate the specified virtual address into a corresponding virtual physical address according to the first-level page table cache entry stored in the translation backup buffer when the specified virtual address is matched.

3. The storage management device according to claim 2, wherein, The first-level storage management unit also includes: A first control unit, coupled to the first address translation unit, is configured to retrieve a matching entry to be filled from the first-level page table and write the entry to be filled into the translation backup buffer when the first-level page table cache entry cached in the translation backup buffer does not match the specified virtual address.

4. The storage management device according to claim 1, wherein, The second-level storage management unit also includes: An operation domain translation back buffer, corresponding to the operation domain, is used to cache second-level page table cache entries frequently accessed by the operation domain; The second control unit, coupled to the second address translation unit, is used to retrieve a matching entry to be filled from the operation domain translation backup buffer and write the entry to be filled into the corresponding group translation backup buffer when the second-level page table cache entry cached in the group translation backup buffer does not match the specified virtual physical address.

5. The storage management device according to claim 4, wherein, The second control unit is further configured to, when a second-level page table cache entry stored in the operation domain translation back buffer does not match the specified virtual physical address, retrieve a matching entry to be backfilled from the second-level page table and write the entry to be backfilled into the operation domain translation back buffer and / or the corresponding group translation back buffer.

6. A processor, comprising: Cache memory; The storage management device as described in any one of claims 1 to 5.

7. A computing device, comprising: The processor as described in claim 6; as well as A memory, coupled to the processor, is used to store first-level page tables and second-level page tables.

8. A system-on-a-chip, comprising: The processor as described in claim 6; as well as A memory, coupled to the processor, is used to store first-level page tables and second-level page tables.

9. A storage management method, comprising: A first-level storage management unit is provided, which translates the specified virtual address to the corresponding virtual physical address according to the first-level page table cache entry that matches the specified virtual address. The first-level page table cache entry stores the mapping relationship between virtual addresses and virtual physical addresses that are frequently accessed by processes in the operation domain; wherein, the virtual physical address is an abstract address obtained after address translation of the virtual address. A second-level storage management unit is provided, used to translate the specified virtual physical address into a physical address according to a second-level page table cache entry that matches the specified virtual physical address, thereby realizing the translation from virtual address to physical address. The second-level page table cache entry stores the mapping relationship between virtual physical addresses and physical addresses corresponding to virtual addresses frequently accessed by processes in the operation domain. The second-level storage management unit includes: at least one group translation back buffer, the at least one group translation back buffer corresponding to at least one hardware device group in the operation domain, the hardware device group sharing a set of address fields, the group translation back buffer being used to cache the corresponding second-level page table cache entries frequently accessed by the corresponding hardware device group; and a second address translation unit, used to translate the specified virtual physical address into a corresponding physical address according to the second-level page table cache entry when the second-level page table cache entry stored in the group translation back buffer matches the specified virtual physical address. The first-level storage management unit and the second-level storage management unit are located in the operation domain. Different operation domains share physical memory, but have exclusive access to hardware devices other than physical memory.

10. A communication method applied between different operating domains, the operating domains sharing physical memory but having exclusive access to hardware devices other than physical memory, the operating domains including a storage management device as described in any one of claims 1 to 5, comprising: Using the storage management device, the specified virtual address is translated to the corresponding virtual physical address based on a first-level page table cache entry that matches the virtual address specified by the process in the operation domain; wherein, the virtual physical address is an abstract address obtained by address translation of the virtual address; Update the physical address stored in the second-level page table cache entry of the operation domain that corresponds to the specified virtual physical address to the physical address corresponding to the virtual address specified by the process in another operation domain; Using the storage management device, the specified virtual physical address is translated into an updated physical address based on a second-level page table cache entry that matches the specified virtual physical address, thereby realizing the translation from the virtual address to the updated physical address.

11. The communication method according to claim 10, wherein, The operation domain includes a first operation domain and a second operation domain. The process in the first operation domain specifies a first virtual address, and the second-level page table cache entry of the first operation domain stores the correspondence between the first virtual address and the first virtual physical address. The process in the second operation domain specifies a second virtual address, and the second-level page table cache entry of the second operation domain stores the correspondence between the second virtual address and the second virtual physical address. The physical address corresponding to the specified virtual physical address stored in the second-level page table cache entry of the updated operation domain, which is the physical address corresponding to the virtual address specified by a process in another operation domain, includes: The first physical address stored in the second-level page table cache entry of the first operation domain is swapped with the second physical address stored in the second-level page table cache entry of the second operation domain.

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