Memory device

Abstract

To provide a memory device having a switching element with excellent characteristics. [Solution] The memory device of the embodiment includes a memory cell comprising: a first conductive layer; a second conductive layer; a third conductive layer between the first and second conductive layers; a switching layer between the first and third conductive layers; and a resistive switching layer between the third and second conductive layers. The switching layer comprises an oxide, nitride, or oxynitride of a first element selected from the group consisting of Al, Si, Ge, Zr, Y, Ta, La, Ce, Ti, Hf, and Mg; a second element, different from the first element, selected from the group consisting of Al, Zn, Sn, Ga, and In; and a third element selected from the group consisting of Te, S, Se, and Sb. The switching layer includes a first region and a second region, wherein the sum of the atomic concentrations of the second element and the third element in the first region is greater than the sum of the atomic concentrations of the second element and the third element in the second region.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory device.

Background Art

[0002] As a large-capacity non-volatile memory device, there is a cross-point type two-terminal memory device. The cross-point type two-terminal memory device is easy to miniaturize and highly integrate memory cells.

[0003] The memory cell of the cross-point type two-terminal memory device has, for example, a resistance change element and a switching element. By having a switching element in the memory cell, the current flowing through memory cells other than the selected memory cell is suppressed.

[0004] The switching element is required to have excellent characteristics such as a low leakage current, a high on-current, and high reliability.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] The problem to be solved by the present invention is to provide a memory device having a switching element with excellent characteristics.

Means for Solving the Problems

[0007] The memory device of the embodiment includes a memory cell comprising: a first conductive layer; a second conductive layer; a third conductive layer provided between the first and second conductive layers; a switching layer provided between the first and third conductive layers; and a resistive switching layer provided between the third and second conductive layers. The switching layer comprises an oxide, nitride, or oxynitride of at least one first element selected from the group consisting of aluminum (Al), silicon (Si), germanium (Ge), zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), and magnesium (Mg), and, unlike the at least one first element, from aluminum (Al), zinc (Zn), tin (Sn), gallium (Ga), and indium (In). The switching layer comprises at least one second element selected from the group consisting of, and at least one third element selected from the group consisting of tellurium (Te), sulfur (S), selenium (Se), and antimony (Sb), wherein the switching layer comprises a first region and a second region, the second region being provided between the first region and the first conductive layer or between the first region and the third conductive layer, and the total concentration is the sum of the atomic concentrations of the first element, the second element, the third element, oxygen (O), and nitrogen (N), the first concentration, which is the sum of the atomic concentrations of the second element and the third element in the first region divided by the total concentration, is greater than the second concentration, which is the sum of the atomic concentrations of the second element and the third element in the second region divided by the total concentration. [Brief explanation of the drawing]

[0008] [Figure 1] Block diagram of the storage device according to the first embodiment. [Figure 2] A schematic cross-sectional view of the memory cell of the first embodiment of the storage device. [Figure 3] A figure showing the distribution of normalized additive concentrations in the switching layer of the first embodiment. [Figure 4] A diagram illustrating the problems of the storage device according to the first embodiment. [Figure 5] A diagram illustrating the current-voltage characteristics of the switching element according to the first embodiment. [Figure 6] Schematic cross-sectional view of the memory cell of the comparative example storage device. [Figure 7] A figure showing the distribution of normalized additive concentrations in the switching layer of the comparative example. [Figure 8] A schematic cross-sectional view of a memory cell of a first modified memory device according to the first embodiment. [Figure 9] A schematic cross-sectional view of a memory cell of a second modified memory device according to the first embodiment. [Figure 10] A schematic cross-sectional view of a memory cell of a third modified memory device according to the first embodiment. [Figure 11] A schematic cross-sectional view of a memory cell of a memory device in a fourth modified example of the first embodiment. [Figure 12] A figure showing the distribution of normalized additive concentrations in the switching layer of the fourth modification of the first embodiment. [Figure 13] A schematic cross-sectional view of a memory cell of the second embodiment of the storage device. [Figure 14] A figure showing the distribution of normalized additive concentrations in the switching layer of the second embodiment. [Figure 15] A schematic cross-sectional view of a memory cell of a modified memory device according to the second embodiment. [Figure 16] A figure showing the distribution of normalized additive concentrations in the switching layer of a modified example of the second embodiment. [Figure 17] A schematic cross-sectional view of a memory cell of the third embodiment of the storage device. [Figure 18] A diagram showing the distribution of normalized additive concentrations in the switching layer of the third embodiment. [Figure 19] A schematic cross-sectional view of a memory cell of a modified memory device according to the third embodiment. [Figure 20] A figure showing the distribution of normalized additive concentrations in the switching layer of a modified example of the third embodiment. [Figure 21] A schematic cross-sectional view of the memory cell of the fourth embodiment of the storage device. [Figure 22]Schematic cross-sectional view of a memory cell of the memory device according to the fifth embodiment. [Figure 23] Explanatory diagram of the current-voltage characteristics of the memory element according to the fifth embodiment. [Figure 24] Explanatory diagram of the first operation example of the memory operation of the memory device according to the fifth embodiment. [Figure 25] Explanatory diagram of the second operation example of the memory operation of the memory device according to the fifth embodiment. [Figure 26] Explanatory diagram of the current-voltage characteristics of the memory element according to the first modification of the fifth embodiment. [Figure 27] Explanatory diagram of the third operation example of the memory operation of the memory device according to the first modification of the fifth embodiment. [Figure 28] Explanatory diagram of the fourth operation example of the memory operation of the memory device according to the first modification of the fifth embodiment. [Figure 29] Explanatory diagram of the current-voltage characteristics of the memory element according to the second modification of the fifth embodiment. [Figure 30] Explanatory diagram of the fifth operation example of the memory operation of the memory device according to the second modification of the fifth embodiment. s [Figure 31] Explanatory diagram of the sixth operation example of the memory operation of the memory device according to the second modification of the fifth embodiment. [Figure 32] Explanatory diagram of the current-voltage characteristics of the memory element according to the third modification of the fifth embodiment. [Figure 33] Explanatory diagram of the seventh operation example of the memory operation of the memory device according to the third modification of the fifth embodiment. [Figure 34] Explanatory diagram of the eighth operation example of the memory operation of the memory device according to the third modification of the fifth embodiment.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described will be omitted as appropriate.

[0010] For qualitative and quantitative analysis of the chemical composition constituting the memory device described herein, methods such as Rutherford backscattering spectroscopy (RBS), secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDS), and electron energy loss spectroscopy (EELS) can be used. Furthermore, for measuring the thickness of the components constituting the memory device, the distance between components, etc., a transmission electron microscope (TEM) can be used, for example. Furthermore, for identifying the constituent materials of the components constituting the memory device, measuring the relative abundance of the constituent materials, identifying the bonding state of the constituent materials, identifying the local structure (interatomic distance, coordination number) of the constituent materials, measuring the chemical state of the constituent materials, and comparing the concentrations of the constituent materials, for example, X-ray photoelectron spectroscopy (XPS), X-ray absorption fine structure analysis (XAFS), Raman spectroscopy (Raman), scanning transmission electron microscope (STEM), or EELS can be used.

[0011] (First embodiment) The memory device of the first embodiment includes a memory cell comprising a first conductive layer, a second conductive layer, a third conductive layer provided between the first conductive layer and the second conductive layer, a switching layer provided between the first conductive layer and the third conductive layer, and a resistive switching layer provided between the third conductive layer and the second conductive layer. The switching layer comprises an oxide, nitride, or oxynitride of at least one first element selected from the group consisting of aluminum (Al), silicon (Si), germanium (Ge), zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), and magnesium (Mg); at least one second element, different from the at least one first element, selected from the group consisting of aluminum (Al), zinc (Zn), tin (Sn), gallium (Ga), and indium (In); and at least one third element selected from the group consisting of tellurium (Te), sulfur (S), selenium (Se), and antimony (Sb). The switching layer includes a first region and a second region, the second region being provided either between the first region and the first conductive layer or between the first region and the third conductive layer, and the total concentration is the sum of the atomic concentrations of the first element, the second element, the third element, the oxygen (O) atomic concentration, and the nitrogen (N) atomic concentration. The first concentration, which is the sum of the atomic concentrations of the second element and the third element in the first region divided by the total concentration, is greater than the second concentration, which is the sum of the atomic concentrations of the second element and the third element in the second region divided by the total concentration.

[0012] Furthermore, the storage device of the first embodiment further comprises a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

[0013] Figure 1 is a block diagram of the storage device according to the first embodiment.

[0014] The memory cell array 100 of the first embodiment of the memory device includes, for example, a plurality of word lines 102 and a plurality of bit lines 103 intersecting the word lines 102, separated by an insulating layer on a semiconductor substrate 101. The bit lines 103 are provided, for example, on top of the word lines 102. In addition, peripheral circuits such as a first control circuit 104, a second control circuit 105, and a sense circuit 106 are provided around the memory cell array 100.

[0015] Word line 102 is an example of the first wiring. Bit line 103 is an example of the second wiring.

[0016] Multiple memory cells MC are provided in the region where the word line 102 and the bit line 103 intersect. The memory device of the first embodiment is a two-terminal magnetoresistive memory having a crosspoint structure.

[0017] Multiple word lines 102 are each connected to the first control circuit 104. Multiple bit lines 103 are each connected to the second control circuit 105. The sense circuit 106 is connected to both the first control circuit 104 and the second control circuit 105.

[0018] The first control circuit 104 and the second control circuit 105 have functions such as selecting a desired memory cell MC, writing data to the memory cell MC, reading data from the memory cell MC, and erasing data from the memory cell MC. When reading data, the data from the memory cell MC is read out as the amount of current flowing between the word line 102 and the bit line 103, or as a change in the potential of the bit line 103. The sense circuit 106 has a function to determine the polarity of the data by determining the amount of current. For example, it determines whether the data is "0" or "1".

[0019] The first control circuit 104, the second control circuit 105, and the sense circuit 106 are composed of electronic circuits using semiconductor devices formed on a semiconductor substrate 101, for example.

[0020] Figure 2 is a schematic cross-sectional view of a memory cell of the first embodiment of the storage device. Figure 2 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, for example, indicated by a dotted circle. Figure 2 is a cross-section parallel to a first direction connecting the lower electrode 10 to the upper electrode 20.

[0021] As shown in Figure 2, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, and a resistive switching layer 50. The switching layer 40 includes a high-density region 41 and a medium-density region 42. The high-density region 41 includes a first contact portion 41x. The medium-density region 42 includes a second contact portion 42x.

[0022] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer. The high-concentration region 41 is an example of the first region. The medium-concentration region 42 is an example of the second region. The first contact portion 41x is an example of the first part. The second contact portion 42x is an example of the second part.

[0023] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistive switching layer 50, and the upper electrode 20 constitute the resistive switching element of the memory cell MC.

[0024] The lower electrode 10 is connected to the word wire 102. The lower electrode 10 is, for example, a metal. The lower electrode 10 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride. The lower electrode 10 may also be part of the word wire 102.

[0025] The upper electrode 20 is connected to the bit wire 103. The upper electrode 20 is, for example, a metal. The upper electrode 20 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride. The upper electrode 20 may also be part of the bit wire 103.

[0026] The intermediate electrode 30 is provided between the lower electrode 10 and the upper electrode 20. The intermediate electrode 30 is, for example, a metal. The intermediate electrode 30 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0027] The switching layer 40 is provided between the lower electrode 10 and the intermediate electrode 30. The thickness of the switching layer 40 in the first direction from the lower electrode 10 toward the upper electrode 20 is, for example, 4 nm to 25 nm. The length of the switching layer 40 in the second direction perpendicular to the first direction is, for example, 10 nm to 50 nm.

[0028] The switching layer 40 has a function to suppress the increase in semi-selective leakage current flowing to the semi-selective cell. The switching layer 40 has a nonlinear current-voltage characteristic in which the current rises sharply at a specific threshold voltage.

[0029] The switching layer 40 contains a first oxide, nitride, or oxynitride of the first element. The switching layer 40 contains a second element and a third element. The switching layer 40 contains at least one of oxygen (O) or nitrogen (N). Hereinafter, the second and third elements may be referred to as additives.

[0030] The first element is at least one element selected from the group consisting of aluminum (Al), silicon (Si), germanium (Ge), zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), and magnesium (Mg).

[0031] Oxides of the first element include, for example, aluminum oxide, silicon oxide, germanium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, cerium oxide, titanium oxide, hafnium oxide, or magnesium oxide. Nitrides of the first element include, for example, aluminum nitride, silicon nitride, germanium nitride, zirconium nitride, yttrium nitride, tantalum nitride, lanthanum nitride, cerium nitride, titanium nitride, hafnium nitride, or magnesium nitride. Oxynitrides of the first element include, for example, aluminum oxynitride, silicon oxynitride, germanium oxynitride, zirconium oxynitride, yttrium oxynitride, tantalum oxynitride, lanthanum oxynitride, cerium oxynitride, titanium oxynitride, hafnium oxynitride, or magnesium oxynitride.

[0032] The second element is different from the first element. The second element is at least one element selected from the group consisting of aluminum (Al), zinc (Zn), tin (Sn), gallium (Ga), and indium (In). The third element is at least one element selected from the group consisting of tellurium (Te), sulfur (S), selenium (Se), and antimony (Sb).

[0033] It is also possible to select bismuth (Bi) as the second element.

[0034] The switching layer 40 includes, for example, a compound of a second element and a third element. Examples of compounds of the second and third elements include aluminum telluride, zinc telluride, tin telluride, gallium telluride, indium telluride, aluminum sulfide, zinc sulfide, tin sulfide, gallium sulfide, indium sulfide, aluminum selenide, zinc selenide, tin selenide, gallium selenide, indium selenide, aluminum antimonide, zinc antimonide, tin antimonide, gallium antimonide, or indium antimonide.

[0035] The switching layer 40 may also include, for example, bismuth telluride, bismuth sulfide, bismuth selenide, or bismuth antimonide.

[0036] In the switching layer 40, the sum of the atomic concentrations of the first element, the second element, the third element, the oxygen (O) atom, and the nitrogen (N) atom is called the total concentration. The total concentration in the switching layer 40 is, for example, between 80% and 100%.

[0037] In the switching layer 40, the sum of the atomic concentrations of the second element and the third element is called the additive concentration. The concentration obtained by dividing the additive concentration by the total concentration is called the normalized additive concentration. In the switching layer 40, the normalized additive concentration is, for example, 0.1% to 99%.

[0038] The switching layer 40 includes a high-concentration region 41 and a medium-concentration region 42. The medium-concentration region 42 is provided between the high-concentration region 41 and the intermediate electrode 30.

[0039] The high-concentration region 41 is in contact with, for example, the lower electrode 10. The portion of the high-concentration region 41 that is in contact with the lower electrode 10 is the first contact portion 41x.

[0040] The medium-concentration region 42 is in contact with, for example, the intermediate electrode 30. The portion of the medium-concentration region 42 that is in contact with the intermediate electrode 30 is the second contact portion 42x.

[0041] Figure 3 shows the distribution of the normalization additive concentration in the switching layer of the first embodiment. Figure 3 shows the distribution of the normalization additive concentration in the film thickness direction. The film thickness direction is the first direction.

[0042] For example, in chemical composition analysis using TEM and EDS or EELS, the TEM conditions are set to an electron beam acceleration voltage of 200kV, a beam current of 100pA to 1nA, and a beam diameter that provides a spatial resolution of approximately 1nm. For example, using the above TEM conditions, the chemical composition of the switching layer 40 of the sample is continuously measured at intervals of 1nm or less in the direction of the switching layer 40's film thickness, and the normalized additive concentration is calculated to obtain the normalized additive concentration distribution shown in Figure 3.

[0043] The first concentration, which is the normalized additive concentration in the high-concentration region 41, is greater than the second concentration, which is the normalized additive concentration in the medium-concentration region 42.

[0044] The difference between the first concentration of the first contact portion 41x in the high-concentration region 41 (C1 in Figure 3) and the second concentration of the second contact portion 42x in the medium-concentration region 42 (C2 in Figure 3) is, for example, 10% to 70%.

[0045] The first concentration C1 of the first contact portion 41x in the high-concentration region 41 is, for example, 40% to 99%. The second concentration C2 of the second contact portion 42x in the medium-concentration region 42 is, for example, 30% to 70%.

[0046] The normalized additive concentration in the switching layer 40 decreases monotonically, for example, from the lower electrode 10 to the intermediate electrode 30. The portion of the normalized additive concentration in the switching layer 40 has a distribution such as the solid line A, dotted line B, or dotted line C in Figure 3.

[0047] The resistive change layer 50 is provided between the intermediate electrode 30 and the upper electrode 20. The resistive change layer 50 has a fixed layer 51, a tunnel layer 52, and a free layer 53. The resistive change layer 50 includes a magnetic tunnel junction composed of the fixed layer 51, the tunnel layer 52, and the free layer 53.

[0048] The resistive layer 50 has the function of storing data by changing resistance. The resistive layer 50 has the characteristic that its electrical resistance changes when a predetermined voltage is applied.

[0049] The fixed layer 51 is a ferromagnetic material. In the fixed layer 51, the magnetization direction does not change with respect to a predetermined writing voltage, and the magnetization direction is fixed in a specific direction.

[0050] The tunnel layer 52 is an insulator. Electrons pass through the tunnel layer 52 by the tunneling effect.

[0051] The free layer 53 is a ferromagnetic material. In the free layer 53, the magnetization direction changes in response to a predetermined writing voltage. The magnetization direction of the free layer 53 can be either parallel to the magnetization direction of the fixed layer 51 or antiparallel to the magnetization direction of the fixed layer 51. For example, the magnetization direction of the free layer 53 can be changed by applying a voltage and flowing a current between the intermediate electrode 30 and the upper electrode 20.

[0052] By changing the magnetization direction of the free layer 53, the electrical resistance of the resistance-changing layer 50 changes. When the magnetization direction of the free layer 53 is antiparallel to the magnetization direction of the fixed layer 51, a high-resistance state is achieved where current is difficult to flow. On the other hand, when the magnetization direction of the free layer 53 is parallel to the magnetization direction of the fixed layer 51, a low-resistance state is achieved where current is easy to flow. Note that the arrangement of the fixed layer 51 and the free layer 53 can be reversed. In other words, the layers may be stacked in the order of intermediate electrode 30, free layer 53, tunnel layer 52, fixed layer 51, and upper electrode 20.

[0053] Next, the operation and effects of the storage device according to the first embodiment will be described.

[0054] In the first embodiment of the memory device, as described above, the resistance of the resistance change layer 50 changes by changing the magnetization direction of the free layer 53. When the magnetization direction of the free layer 53 is antiparallel to the magnetization direction of the fixed layer 51, it becomes a high-resistance state in which current is difficult to flow. On the other hand, when the magnetization direction of the free layer 53 is parallel to the magnetization direction of the fixed layer 51, it becomes a low-resistance state in which current is easy to flow.

[0055] For example, the high-resistance state of the resistive change layer 50 is defined as data "1," and the low-resistance state is defined as data "0." The memory cell MC can maintain different resistance states, enabling it to store 1-bit data of "0" and "1." Writing to a single memory cell MC is performed by applying a voltage and current between the bit line 103 and the word line 102 connected to that memory cell MC.

[0056] Figure 4 is an explanatory diagram of the problems of the memory device according to the first embodiment. Figure 4 shows the voltage applied to a memory cell MC when one memory cell MC in the memory cell array is selected for a write operation. The intersections of the word line and the bit line represent each memory cell MC.

[0057] The selected memory cell MC is memory cell A (selected cell). The write voltage Vwrite is applied to the word line connected to memory cell A. Also, 0V is applied to the bit line connected to memory cell A.

[0058] The following explanation will use the example where a voltage half the write voltage (Vwrite / 2) is applied to the word line and bit line that are not connected to memory cell A.

[0059] The voltage applied to memory cell C (unselected cell), which is connected to the word line and bit line not connected to memory cell A, is 0V. In other words, no voltage is applied.

[0060] On the other hand, a voltage half the write voltage Vwrite (Vwrite / 2) is applied to memory cell B (a semi-selective cell) that is connected to the word line or bit line connected to memory cell A. Therefore, a semi-selective leakage current flows through memory cell B (a semi-selective cell).

[0061] In addition, as an alternative application method, a method may be used in which a voltage half the write voltage (Vwrite / 2) is applied to the word line connected to memory cell A, a negative voltage half the write voltage (-Vwrite / 2) is applied to the bit line, and 0V is applied to the word line and bit line not connected to memory cell A.

[0062] Figure 5 is an explanatory diagram of the current-voltage characteristics of the switching element in the first embodiment. The horizontal axis represents the voltage applied to the switching element, and the vertical axis represents the current flowing through the switching element.

[0063] A switching element has a nonlinear current-voltage characteristic in which the current rises sharply at a threshold voltage Vth. The threshold voltage Vth is, for example, between 0.5V and 3V.

[0064] The write voltage Vwrite is set such that the write voltage Vwrite is higher than the threshold voltage Vth, and half the write voltage Vwrite (Vwrite / 2) is lower than the threshold voltage. The current that flows through the switching element when the write voltage Vwrite is applied is the on current (Ion in Figure 5). The current that flows through the switching element when half the write voltage Vwrite (Vwrite / 2) is applied is the semi-selective leakage current (Ihalf in Figure 5).

[0065] Furthermore, the read voltage Vread of the memory cell MC is set to a voltage higher than the threshold voltage Vth and lower than the write voltage Vwrite, for example, as shown in Figure 5. Therefore, the semi-selective leakage current flowing through the semi-selective cell can also be suppressed when reading from the memory cell MC.

[0066] A high semi-selective leakage current can lead to increased power consumption of the chip, for example. Also, an increased voltage drop in the wiring can prevent a sufficiently high voltage from being applied to the selected cell, resulting in unstable writing operations to the memory cell MC. Furthermore, a low on-current can lead to insufficient current flowing to the selected cell, resulting in incomplete writing to the memory cell MC. Therefore, the current-voltage characteristics of a switching element require a balance between low semi-selective leakage current and high on-current.

[0067] Furthermore, high reliability is required for the current-voltage characteristics of switching elements. For example, high reliability is achieved by suppressing characteristic fluctuations such as fluctuations in semi-selective leakage current and on-current when voltage is repeatedly applied to the switching element, thereby achieving high endurance tolerance.

[0068] Figure 6 is a schematic cross-sectional view of the memory cell of the comparative example. Figure 7 is a diagram showing the distribution of the normalization additive concentration in the switching layer of the comparative example. Figures 6 and 7 correspond to Figures 2 and 3 of the first embodiment, respectively.

[0069] The memory cell MC of the comparative example differs from the memory cell MC of the first embodiment in that the normalization additive concentration of the switching layer 40 is constant in the film thickness direction, as shown by the solid line X or dotted line Y in Figure 7.

[0070] The switching element of the comparative example's memory device has a problem, for example, low endurance tolerance. One factor contributing to the low endurance tolerance of the comparative example's switching element is thought to be that when an electric field is applied in the direction of the film thickness of the switching layer 40, movement of the second and third elements due to the electric field occurs. For example, it is thought that the movement of the second and third elements generates defects in the switching layer 40, and these defects cause characteristic changes such as fluctuations in semi-selective leakage current and fluctuations in on-current, resulting in low endurance tolerance.

[0071] Furthermore, the switching element in the comparative example also has the problem that the semi-selective leakage current becomes large, especially when the normalized additive concentration in the switching layer 40 is relatively large, as shown by the solid line X in Figure 7.

[0072] The switching element of the first embodiment has a switching layer 40 that includes a high-concentration region 41 and a medium-concentration region 42. The first concentration, which is the normalized additive concentration in the high-concentration region 41, is greater than the second concentration, which is the normalized additive concentration in the medium-concentration region 42. In other words, a concentration gradient is provided in the additive concentration of the switching layer 40.

[0073] By providing a concentration gradient in the additive concentration of the switching layer 40, the endurance resistance of the switching element in the first embodiment is increased. This is thought to be because, by providing a concentration gradient in the additive concentration of the switching layer 40, when an electric field is applied in the direction of the film thickness of the switching layer 40, movement of the second and third elements due to the electric field is less likely to occur. In particular, by providing a concentration gradient that cancels out the movement of the second and third elements when an electric field is applied, the movement of the second and third elements is suppressed, and high endurance resistance can be achieved.

[0074] From the viewpoint of suppressing the movement of the second and third elements and achieving high endurance resistance of the switching element, the difference between the first concentration of the first contact portion 41x in the high-concentration region 41 (C1 in Figure 3) and the second concentration of the second contact portion 42x in the medium-concentration region 42 (C2 in Figure 3) is preferably 10% or more, more preferably 20% or more, and even more preferably 30% or more.

[0075] According to the first embodiment, the endurance resistance of the switching element is improved, and a switching element with superior characteristics can be realized. Therefore, a memory device having a switching element with superior characteristics can be realized.

[0076] (First variation) The first modified memory device of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer comprises a first portion and a second portion, the first portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0077] Figure 8 is a schematic cross-sectional view of a memory cell of a first modified memory device of the first embodiment. Figure 8 corresponds to Figure 2 of the first embodiment.

[0078] The lower electrode 10 includes a first portion 11 and a second portion 12. The second portion 12 is provided between the first portion 11 and the switching layer 40.

[0079] The first part 11 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first part 11 comprises, for example, borides of the above elements. The first part 11 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0080] Part 212 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0081] In the first modified memory device of the first embodiment, the first portion 11 of the lower electrode 10 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing the degradation of the characteristics of the resistive switching element. Furthermore, since the first portion 11 does not come into contact with the switching layer 40, the desorption of oxygen (O) from the switching layer 40 is suppressed, thereby suppressing the degradation of the characteristics of the switching element.

[0082] As described above, according to the first modification of the first embodiment, a switching element with excellent characteristics can be realized, similar to the first embodiment. Therefore, a memory device having a switching element with excellent characteristics can be realized.

[0083] (Second variation) The second modified memory device of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer comprises a first portion and a second portion, the first portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); the second conductive layer comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); and the third conductive layer comprises a third portion and a fourth portion, the fourth portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0084] Figure 9 is a schematic cross-sectional view of a memory cell of a second modified storage device of the first embodiment. Figure 9 corresponds to Figure 2 of the first embodiment.

[0085] The lower electrode 10 includes a first portion 11 and a second portion 12. The second portion 12 is provided between the first portion 11 and the switching layer 40.

[0086] The first part 11 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first part 11 comprises, for example, borides of the above elements. The first part 11 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0087] Part 212 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0088] The upper electrode 20 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 contains, for example, a boride of the above elements. The upper electrode 20 contains, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0089] The intermediate electrode 30 includes a third portion 31 and a fourth portion 32. The third portion 31 is provided between the fourth portion 32 and the switching layer 40.

[0090] The third part 31 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0091] The fourth part 32 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The fourth part 32 comprises, for example, borides of the above elements. The fourth part 32 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0092] In the second modified memory device of the first embodiment, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 contain at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing the degradation of the characteristics of the resistive switching element. Furthermore, since the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 do not come into contact with the switching layer 40, the desorption of oxygen (O) from the switching layer 40 is suppressed, thereby suppressing the degradation of the characteristics of the switching element.

[0093] As described above, according to the second modification of the first embodiment, a switching element with excellent characteristics can be realized, similar to the first embodiment. Therefore, a memory device having a switching element with excellent characteristics can be realized.

[0094] (Third variation) The third modified memory device of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer comprises a first portion, a second portion, and a fifth portion, the first portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); the second conductive layer comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); and the third conductive layer comprises a third portion and a fourth portion, the fourth portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0095] Figure 10 is a schematic cross-sectional view of a memory cell of a third modified memory device of the first embodiment. Figure 10 corresponds to Figure 2 of the first embodiment.

[0096] The lower electrode 10 includes a first portion 11, a second portion 12, and a fifth portion 13. The second portion 12 is provided between the first portion 11 and the switching layer 40. The first portion 11 is provided between the fifth portion 13 and the second portion 12.

[0097] The first part 11 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first part 11 comprises, for example, borides of the above elements. The first part 11 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0098] Part 2 12 and Part 5 13 include, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0099] The upper electrode 20 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 contains, for example, a boride of the above elements. The upper electrode 20 contains, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0100] The intermediate electrode 30 includes a third portion 31 and a fourth portion 32. The third portion 31 is provided between the fourth portion 32 and the switching layer 40.

[0101] The third part 31 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0102] The fourth part 32 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The fourth part 32 comprises, for example, borides of the above elements. The fourth part 32 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0103] In the third modified memory device of the first embodiment, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 contain at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing the degradation of the characteristics of the resistive switching element. Furthermore, since the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 do not come into contact with the switching layer 40, the desorption of oxygen (O) from the switching layer 40 is suppressed, thereby suppressing the degradation of the characteristics of the switching element.

[0104] As described above, according to the third modification of the first embodiment, a switching element with excellent characteristics can be realized, similar to the first embodiment. Therefore, a memory device having a switching element with excellent characteristics can be realized.

[0105] (Fourth variation) The fourth modified memory device of the first embodiment differs from the memory device of the first embodiment in that the second region is provided between the first region and the first conductive layer.

[0106] Figure 11 is a schematic cross-sectional view of a memory cell of a fourth modified storage device of the first embodiment. Figure 11 corresponds to Figure 2 of the first embodiment.

[0107] The switching layer 40 includes a high-concentration region 41 and a medium-concentration region 42. The medium-concentration region 42 is located between the high-concentration region 41 and the lower electrode 10.

[0108] The high-concentration region 41 is in contact with, for example, the intermediate electrode 30. The portion of the high-concentration region 41 that is in contact with the intermediate electrode 30 is the first contact portion 41x.

[0109] The medium-concentration region 42 is in contact with, for example, the lower electrode 10. The portion of the medium-concentration region 42 that is in contact with the lower electrode 10 is the second contact portion 42x.

[0110] Figure 12 shows the distribution of the normalization additive concentration in the switching layer of the fourth modification of the first embodiment. Figure 12 shows the distribution of the normalization additive concentration in the film thickness direction. The film thickness direction is the first direction. Figure 12 corresponds to Figure 3 of the first embodiment.

[0111] The difference between the first concentration of the first contact portion 41x in the high-concentration region 41 (C1 in Figure 12) and the second concentration of the second contact portion 42x in the medium-concentration region 42 (C2 in Figure 12) is, for example, 10% to 70%.

[0112] The first concentration C1 of the first contact portion 41x in the high-concentration region 41 is, for example, 40% to 99%. The second concentration C2 of the second contact portion 42x in the medium-concentration region 42 is, for example, 30% to 70%.

[0113] The normalization additive concentration in the switching layer 40 increases monotonically, for example, from the lower electrode 10 towards the intermediate electrode 30. The portion of the normalization additive concentration in the switching layer 40 has a distribution such as the solid line A, dotted line B, or dotted line C in Figure 12.

[0114] As described above, according to the fourth modification of the first embodiment, a switching element with excellent characteristics can be realized. Therefore, a memory device having a switching element with excellent characteristics can be realized.

[0115] According to the first embodiment and its modifications, the endurance resistance of the switching element is improved, and a switching element with superior characteristics can be realized. Therefore, according to the first embodiment and its modifications, a memory device having a switching element with superior characteristics can be realized.

[0116] (Second embodiment) The storage device of the second embodiment differs from the storage device of the first embodiment in that the first portion of the first region is in contact with the third conductive layer, the second portion of the second region is in contact with the first conductive layer, the first density of the first portion is 20% or more, and the second density of the second portion is less than 30%. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0117] Figure 13 is a schematic cross-sectional view of a memory cell of the second embodiment of the storage device. Figure 13 corresponds to Figure 2 of the first embodiment.

[0118] As shown in Figure 13, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, and a resistive switching layer 50. The switching layer 40 includes a high-density region 41 and a low-density region 43. The high-density region 41 includes a first contact portion 41x. The low-density region 43 includes a third contact portion 43x.

[0119] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer. The high-concentration region 41 is an example of the first region. The low-concentration region 43 is an example of the second region. The first contact portion 41x is an example of the first part. The third contact portion 43x is an example of the second part.

[0120] The switching layer 40 includes a high-concentration region 41 and a low-concentration region 43. The low-concentration region 43 is provided between the high-concentration region 41 and the lower electrode 10.

[0121] The high-concentration region 41 is in contact with, for example, the intermediate electrode 30. The portion of the high-concentration region 41 that is in contact with the intermediate electrode 30 is the first contact portion 41x.

[0122] The low-concentration region 43 is in contact with, for example, the lower electrode 10. The portion of the low-concentration region 43 that is in contact with the lower electrode 10 is the third contact portion 43x.

[0123] Figure 14 shows the distribution of the normalization additive concentration in the switching layer of the second embodiment. Figure 14 shows the distribution of the normalization additive concentration in the film thickness direction. The film thickness direction is the first direction.

[0124] The first concentration, which is the normalized additive concentration in the high-concentration region 41, is greater than the second concentration, which is the normalized additive concentration in the low-concentration region 43.

[0125] The first concentration C1 of the first contact portion 41x in the high-concentration region 41 is, for example, 20% or more and 99% or less. Preferably, the first concentration C1 is 30% or more. The second concentration C2 of the third contact portion 43x in the low-concentration region 43 is, for example, 0.5% or more and less than 30%.

[0126] The difference between the first concentration of the first contact portion 41x in the high-concentration region 41 (C1 in Figure 14) and the second concentration of the third contact portion 43x in the low-concentration region 43 (C2 in Figure 14) is, for example, 20% to 70%.

[0127] The distance in the first direction (d1 in Figure 14) from the lower electrode 10 to the first position (P1 in Figure 14) where the normalized additive concentration is 30% is, for example, 0.1 nm or more and 4 nm or less. Also, the distance in the first direction (d2 in Figure 14) from the intermediate electrode 30 to the first position P1 is, for example, 4 nm or more and 24 nm or less.

[0128] The normalized additive concentration in the switching layer 40 increases monotonically from the lower electrode 10 to the intermediate electrode 30, for example, as shown by the solid line in Figure 14.

[0129] Next, the operation and effects of the storage device according to the second embodiment will be described.

[0130] Figure 6 is a schematic cross-sectional view of the memory cell of the comparative example. Figure 7 is a diagram showing the distribution of the normalization additive concentration in the switching layer of the comparative example. Figures 6 and 7 correspond to Figures 13 and 14 of the second embodiment, respectively.

[0131] The memory cell MC of the comparative example differs from the memory cell MC of the second embodiment in that the normalization additive concentration of the switching layer 40 is constant in the film thickness direction, as shown by the solid line X or dotted line Y in Figure 7.

[0132] Furthermore, the switching element of the comparative example memory device has a problem in that, in particular, when the normalization additive concentration of the switching layer 40 is relatively large, as shown by the solid line X in Figure 7, the semi-selective leakage current becomes large.

[0133] The memory device of the second embodiment has a switching layer 40 that includes a high-concentration region 41 and a low-concentration region 43. The first concentration, which is the normalized additive concentration of the high-concentration region 41, is greater than the second concentration, which is the normalized additive concentration of the low-concentration region 43. In other words, a concentration gradient is provided in the additive concentration of the switching layer 40. Furthermore, the second concentration C2 of the third contact portion 43x of the low-concentration region 43 is less than 30%.

[0134] By providing a concentration gradient in the additive concentration of the switching layer 40 and setting the second concentration C2 of the third contact portion 43x in the low-concentration region 43 to less than 30%, the semi-selective leakage current of the switching element in the second embodiment is reduced. This is thought to be because the current flowing through the switching layer 40 is suppressed by providing a low-concentration region 43 with a low additive concentration and high electrical resistance.

[0135] From the viewpoint of reducing the semi-selective leakage current of the switching element, the distance d1 in the first direction from the lower electrode 10 to the first position P1 where the normalized additive concentration is 30% is preferably 0.5 nm or more, more preferably 1 nm or more, and even more preferably 2 nm or more.

[0136] From the viewpoint of achieving a high on-current of the switching element, it is preferable that the distance d1 in the first direction from the lower electrode 10 to the first position P1 where the normalized additive concentration is 30% is 4 nm or less.

[0137] From the viewpoint of achieving a high on-current of the switching element, the difference between the first concentration C1 of the first contact portion 41x in the high-concentration region 41 and the second concentration C2 of the third contact portion 43x in the low-concentration region 43 is preferably 20% or more, and more preferably 30% or more.

[0138] From the viewpoint of achieving a high on-current of the switching element, the first concentration C1 of the first contact portion 41x in the high-concentration region 41 is preferably 50% or more, more preferably 60% or more, and even more preferably 70% or more.

[0139] According to the second embodiment, the semi-selective leakage current of the switching element is reduced, enabling the realization of a switching element with superior characteristics. Therefore, a memory device having a switching element with superior characteristics can be realized.

[0140] (modified version) The modified storage device of the second embodiment differs from the storage device of the second embodiment in that the second region is provided between the first region and the third conductive layer.

[0141] Figure 15 is a schematic cross-sectional view of a memory cell of a modified memory device according to the second embodiment. Figure 15 corresponds to Figure 13 of the second embodiment.

[0142] The switching layer 40 includes a high-concentration region 41 and a low-concentration region 43. The low-concentration region 43 is located between the high-concentration region 41 and the intermediate electrode 30.

[0143] The high-concentration region 41 is in contact with, for example, the lower electrode 10. The portion of the high-concentration region 41 that is in contact with the lower electrode 10 is the first contact portion 41x.

[0144] The low-concentration region 43 is in contact with, for example, the intermediate electrode 30. The portion of the low-concentration region 43 that is in contact with the intermediate electrode 30 is the third contact portion 43x.

[0145] Figure 16 shows the distribution of the normalization additive concentration in the switching layer of a modified version of the second embodiment. Figure 16 shows the distribution of the normalization additive concentration in the film thickness direction. The film thickness direction is the first direction. Figure 16 corresponds to Figure 14 of the second embodiment.

[0146] The first concentration, which is the normalized additive concentration in the high-concentration region 41, is greater than the second concentration, which is the normalized additive concentration in the low-concentration region 43.

[0147] The first concentration C1 of the first contact portion 41x in the high-concentration region 41 is, for example, 20% or more and 99% or less. Preferably, the first concentration C1 is 30% or more. The second concentration C2 of the third contact portion 43x in the low-concentration region 43 is, for example, 0.5% or more and less than 30%.

[0148] The difference between the first concentration of the first contact portion 41x in the high-concentration region 41 (C1 in Figure 16) and the second concentration of the third contact portion 43x in the low-concentration region 43 (C2 in Figure 16) is, for example, 20% to 70%.

[0149] The distance in the first direction (d3 in Figure 16) from the intermediate electrode 30 to the second position (P2 in Figure 16) where the normalized additive concentration is 30% is, for example, 0.1 nm or more and 4 nm or less. Also, the distance in the first direction from the lower electrode 10 to the second position P2 (d4 in Figure 16) is, for example, 4 nm or more and 24 nm or less.

[0150] The normalized additive concentration in the switching layer 40 decreases monotonically from the lower electrode 10 to the intermediate electrode 30, as shown by the solid line in Figure 16.

[0151] From the viewpoint of reducing the semi-selective leakage current of the switching element, the distance d3 in the first direction from the intermediate electrode 30 to the second position P2 where the normalized additive concentration is 30% is preferably 0.5 nm or more, more preferably 1 nm or more, and even more preferably 2 nm or more.

[0152] From the viewpoint of achieving a high on-current of the switching element, it is preferable that the distance d3 in the first direction from the intermediate electrode 30 to the second position P2 where the normalized additive concentration is 30% is 4 nm or less.

[0153] From the viewpoint of achieving a high on-current of the switching element, the difference between the first concentration C1 of the first contact portion 41x in the high-concentration region 41 and the second concentration C2 of the third contact portion 43x in the low-concentration region 43 is preferably 20% or more, and more preferably 30% or more.

[0154] From the viewpoint of achieving a high on-current of the switching element, the first concentration C1 of the first contact portion 41x in the high-concentration region 41 is preferably 50% or more, more preferably 60% or more, and even more preferably 70% or more.

[0155] As described above, according to the modified version of the second embodiment, a switching element with excellent characteristics can be realized, similar to the second embodiment. Therefore, a storage device having a switching element with excellent characteristics can be realized.

[0156] According to the second embodiment and its modifications, the semi-selective leakage current of the switching element is reduced, enabling the realization of a switching element with superior characteristics. Therefore, according to the second embodiment and its modifications, a memory device having a switching element with superior characteristics can be realized.

[0157] (Third embodiment) The memory device of the third embodiment differs from the memory device of the first embodiment in that the switching layer further includes a third region, a first region is provided between the third region and the second region, and the third concentration, which is the sum of the atomic concentrations of the second element in the third region and the third atomic concentration divided by the total concentration, is smaller than the second concentration. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0158] Figure 17 is a schematic cross-sectional view of the memory cell of the third embodiment of the storage device. Figure 17 corresponds to Figure 2 of the first embodiment.

[0159] As shown in Figure 17, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, and a resistive switching layer 50. The switching layer 40 includes a high-density region 41, a medium-density region 42, and a low-density region 43. The medium-density region 42 includes a second contact portion 42x. The low-density region 43 includes a third contact portion 43x.

[0160] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer. The high-concentration region 41 is an example of the first region. The medium-concentration region 42 is an example of the second region. The low-concentration region 43 is an example of the third region. The second contact portion 42x is an example of the fourth portion. The third contact portion 43x is an example of the third portion.

[0161] The switching layer 40 includes a high-concentration region 41, a medium-concentration region 42, and a low-concentration region 43. The high-concentration region 41 is located between the low-concentration region 43 and the medium-concentration region 42. The low-concentration region 43 is located between the high-concentration region 41 and the lower electrode 10. The medium-concentration region 42 is located between the high-concentration region 41 and the intermediate electrode 30.

[0162] The medium-concentration region 42 is in contact with, for example, the intermediate electrode 30. The portion of the medium-concentration region 42 that is in contact with the intermediate electrode 30 is the second contact portion 42x.

[0163] The low-concentration region 43 is in contact with, for example, the lower electrode 10. The portion of the low-concentration region 43 that is in contact with the lower electrode 10 is the third contact portion 43x.

[0164] Figure 18 shows the distribution of the normalization additive concentration in the switching layer of the third embodiment. Figure 18 shows the distribution of the normalization additive concentration in the film thickness direction. The film thickness direction is the first direction.

[0165] The first normalized additive concentration in the high-concentration region 41 is greater than the second normalized additive concentration in the medium-concentration region 42. The third normalized additive concentration in the low-concentration region 43 is less than both the second normalized additive concentration in the medium-concentration region 42 and the first normalized additive concentration in the high-concentration region 41.

[0166] As shown in Figure 18, the distribution of normalized additive concentration in the first direction in the switching layer 40 reaches a maximum value (Cm in Figure 18) at position Pm in the high-concentration region 41. The distance from the lower electrode 10 to position Pm (d5 in Figure 18) is smaller than, for example, the distance from the intermediate electrode 30 to position Pm (d6 in Figure 18).

[0167] The distance d6 from the intermediate electrode 30 to position Pm is, for example, greater than one-fifth of the distance dx between the lower electrode 10 and the intermediate electrode 30.

[0168] The maximum value Cm in the high-concentration region 41 is, for example, 40% to 99%. The second concentration C2 of the second contact portion 42x in the medium-concentration region 42 is, for example, 30% to 70%. The third concentration C3 of the third contact portion 43x in the low-concentration region 43 is, for example, 0.5% to less than 30%.

[0169] The difference between the maximum value Cm in the high-concentration region 41 and the second concentration C2 in the second contact portion 42x of the medium-concentration region 42 is, for example, 10% to 70%.

[0170] The distance in the first direction (d7 in Figure 18) from the lower electrode 10 to the third position (P3 in Figure 18) where the normalized additive concentration is 30% is, for example, 0.1 nm or more and 4 nm or less. Also, the distance in the first direction from the intermediate electrode 30 to the third position P3 (d8 in Figure 18) is, for example, 4 nm or more and 24 nm or less.

[0171] Next, the operation and effects of the storage device according to the third embodiment will be described.

[0172] Figure 6 is a schematic cross-sectional view of the memory cell of the comparative example. Figure 7 is a diagram showing the distribution of the normalization additive concentration in the switching layer of the comparative example. Figures 6 and 7 correspond to Figures 17 and 18 of the third embodiment, respectively.

[0173] The memory cell MC of the comparative example differs from the memory cell MC of the third embodiment in that the normalization additive concentration of the switching layer 40 is constant in the film thickness direction, as shown by the solid line X or dotted line Y in Figure 7.

[0174] The comparative example's memory device has a problem, for example, the low endurance tolerance of the switching elements. In addition, the comparative example's memory device has a problem in that the semi-selective leakage current of the switching elements becomes large, especially when the normalization additive concentration of the switching layer 40 is relatively large, as shown by the solid line X in Figure 7.

[0175] The memory device of the third embodiment has a switching layer 40 that includes a high-concentration region 41, a medium-concentration region 42, and a low-concentration region 43. The first concentration, which is the normalized additive concentration of the high-concentration region 41, is greater than the second concentration, which is the normalized additive concentration of the medium-concentration region 42. In other words, a concentration gradient is provided in the additive concentration of the switching layer 40. Furthermore, the third concentration C3 of the third contact portion 43x in the low-concentration region 43 is less than 30%.

[0176] By providing a concentration gradient in the additive concentration of the switching layer 40, the endurance resistance of the switching element is increased, similar to the first embodiment. Furthermore, by providing a low-concentration region 43 in the switching layer 40 and setting the third concentration C3 of the third contact portion 43x in the low-concentration region 43 to less than 30%, the semi-selective leakage current of the switching element is reduced, similar to the second embodiment.

[0177] From the viewpoint of suppressing the movement of the second and third elements and achieving high endurance resistance, the difference between the maximum value Cm in the high-concentration region 41 and the second concentration C2 in the second contact portion 42x of the medium-concentration region 42 is preferably 10% or more, more preferably 20% or more, and even more preferably 30% or more.

[0178] From the viewpoint of reducing the semi-selective leakage current of the switching element, the distance d7 in the first direction from the lower electrode 10 to the third position P3 where the normalized additive concentration is 30% is preferably 0.5 nm or more, more preferably 1 nm or more, and even more preferably 2 nm or more.

[0179] From the viewpoint of achieving a high on-current of the switching element and reducing the semi-selective leakage current of the switching element, it is preferable that the distance d5 from the lower electrode 10 to the position Pm where the maximum value Cm occurs is smaller than the distance d6 from the intermediate electrode 30 to position Pm.

[0180] From the viewpoint of achieving a high on-current of the switching element, it is preferable that the distance d7 in the first direction from the lower electrode 10 to the third position P3 where the normalized additive concentration is 30% is 4 nm or less.

[0181] From the viewpoint of achieving a high on-current of the switching element, the maximum value Cm in the high-concentration region 41 is preferably 50% or more, more preferably 60% or more, and even more preferably 70% or more.

[0182] According to the third embodiment, a switching element with excellent characteristics, such as high endurance tolerance and low semi-selective leakage current, can be realized. Therefore, a memory device having a switching element with excellent characteristics can be realized.

[0183] (modified version) The modified storage device of the third embodiment differs from the storage device of the third embodiment in that the third region is provided between the first region and the third conductive layer.

[0184] Figure 19 is a schematic cross-sectional view of a memory cell of a modified memory device according to the third embodiment. Figure 19 corresponds to Figure 17 of the third embodiment.

[0185] The switching layer 40 includes a high-concentration region 41, a medium-concentration region 42, and a low-concentration region 43. The medium-concentration region 42 includes a second contact portion 42x. The low-concentration region 43 includes a third contact portion 43x.

[0186] The high-concentration region 41 is an example of the first region. The medium-concentration region 42 is an example of the second region. The low-concentration region 43 is an example of the third region. The second contact portion 42x is an example of the fourth portion. The third contact portion 43x is an example of the third portion.

[0187] The switching layer 40 includes a high-concentration region 41, a medium-concentration region 42, and a low-concentration region 43. The high-concentration region 41 is located between the low-concentration region 43 and the medium-concentration region 42. The low-concentration region 43 is located between the high-concentration region 41 and the intermediate electrode 30. The medium-concentration region 42 is located between the high-concentration region 41 and the lower electrode 10.

[0188] The medium-concentration region 42 is in contact with, for example, the lower electrode 10. The portion of the medium-concentration region 42 that is in contact with the intermediate electrode 30 is the second contact portion 42x.

[0189] The low-concentration region 43 is in contact with, for example, the intermediate electrode 30. The portion of the low-concentration region 43 that is in contact with the intermediate electrode 30 is the third contact portion 43x.

[0190] Figure 20 shows the distribution of the normalization additive concentration in the switching layer of a modified example of the third embodiment. Figure 20 shows the distribution of the normalization additive concentration in the film thickness direction. The film thickness direction is the first direction. Figure 20 corresponds to Figure 18 of the third embodiment.

[0191] The first normalized additive concentration in the high-concentration region 41 is greater than the second normalized additive concentration in the medium-concentration region 42. The third normalized additive concentration in the low-concentration region 43 is less than both the second normalized additive concentration in the medium-concentration region 42 and the first normalized additive concentration in the high-concentration region 41.

[0192] As shown in Figure 20, the distribution of normalized additive concentration in the first direction in the switching layer 40 reaches a maximum value (Cm in Figure 20) at position Pm in the high-concentration region 41. The distance from the intermediate electrode 30 to position Pm (d9 in Figure 20) is smaller than, for example, the distance from the lower electrode 10 to position Pm (d10 in Figure 20).

[0193] The distance d9 from the intermediate electrode 30 to position Pm is greater than, for example, one-fifth of the distance between the lower electrode 10 and the intermediate electrode 30 (dx in Figure 20). The distance d10 from the lower electrode 10 to position Pm is greater than, for example, one-fifth of the distance dx between the lower electrode 10 and the intermediate electrode 30.

[0194] The maximum value Cm in the high-concentration region 41 is, for example, 40% to 99%. The second concentration C2 of the second contact portion 42x in the medium-concentration region 42 is, for example, 30% to 70%. The third concentration C3 of the third contact portion 43x in the low-concentration region 43 is, for example, 0.5% to less than 30%.

[0195] The difference between the maximum value Cm in the high-concentration region 41 and the second concentration C2 in the second contact portion 42x of the medium-concentration region 42 is, for example, 10% to 70%.

[0196] The distance in the first direction (d11 in Figure 20) from the intermediate electrode 30 to the fourth position (P4 in Figure 20) where the normalized additive concentration is 30% is, for example, 0.1 nm or more and 4 nm or less. Also, the distance in the first direction from the lower electrode 10 to the fourth position P4 (d12 in Figure 20) is, for example, 4 nm or more and 24 nm or less.

[0197] From the viewpoint of suppressing the movement of the second and third elements and achieving high endurance resistance of the switching element, the difference between the maximum value Cm in the high-concentration region 41 and the second concentration C2 in the second contact portion 42x of the medium-concentration region 42 is preferably 10% or more, more preferably 20% or more, and even more preferably 30% or more.

[0198] From the viewpoint of reducing the semi-selective leakage current of the switching element, the distance d11 in the first direction from the intermediate electrode 30 to the fourth position P4 where the normalized additive concentration is 30% is preferably 0.5 nm or more, more preferably 1 nm or more, and even more preferably 2 nm or more.

[0199] From the viewpoint of reducing the semi-selective leakage current of the switching element, it is preferable that the distance d9 from the intermediate electrode 30 to the position Pm where the maximum value Cm occurs is smaller than the distance d10 from the lower electrode 10 to position Pm.

[0200] From the viewpoint of achieving a high on-current of the switching element, the distance d11 in the first direction from the intermediate electrode 30 to the fourth position P4 where the normalized additive concentration is 30% is preferably 4 nm or less.

[0201] From the viewpoint of achieving a high on-current of the switching element, the maximum value Cm in the high-concentration region 41 is preferably 50% or more, more preferably 60% or more, and even more preferably 70% or more.

[0202] As described above, according to the modification of the third embodiment, a switching element with excellent characteristics can be realized, similar to the third embodiment. Therefore, a storage device having a switching element with excellent characteristics can be realized.

[0203] According to the third embodiment and its modifications, a switching element with excellent characteristics, such as high endurance tolerance and low semi-selective leakage current, can be realized. Therefore, according to the third embodiment and its modifications, a memory device having a switching element with excellent characteristics can be realized.

[0204] (Fourth embodiment) The storage device of the fourth embodiment differs from the storage device of the first embodiment in that it is a resistive random-access memory (ReRAM). Some of the content that overlaps with the first embodiment will be omitted below.

[0205] Figure 21 is a schematic cross-sectional view of a memory cell of a storage device according to the fourth embodiment. Figure 21 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, indicated, for example, by a dotted circle.

[0206] As shown in Figure 21, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, and a resistive switching layer 50. The switching layer 40 includes a high-density region 41 and a medium-density region 42. The high-density region 41 includes a first contact portion 41x. The medium-density region 42 includes a second contact portion 42x.

[0207] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer. The high-concentration region 41 is an example of the first region. The medium-concentration region 42 is an example of the second region. The first contact portion 41x is an example of the first part. The second contact portion 42x is an example of the second part.

[0208] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistive switching layer 50, and the upper electrode 20 constitute the resistive switching element of the memory cell MC.

[0209] The configuration of the switching layer 40 is the same as that of the storage device in the first embodiment.

[0210] The resistance-changing layer 50 includes a high-resistance layer 50x and a low-resistance layer 50y.

[0211] The high-resistance layer 50x is, for example, a metal oxide. The high-resistance layer 50x is, for example, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, or niobium oxide.

[0212] The low-resistance layer 50y is, for example, a metal oxide. The low-resistance layer 50y is, for example, titanium oxide, niobium oxide, tantalum oxide, or tungsten oxide.

[0213] The resistive layer 50 has the function of storing data by changing resistance. The resistive layer 50 has the characteristic that its electrical resistance changes when a predetermined voltage is applied.

[0214] By applying a voltage to the resistance-changing layer 50, the resistance-changing layer 50 changes from a high-resistance state to a low-resistance state, or from a low-resistance state to a high-resistance state. The application of voltage to the resistance-changing layer 50 causes oxygen ions to move between the high-resistance layer 50x and the low-resistance layer 50y, changing the amount of oxygen vacancies in the low-resistance layer 50y. The conductivity of the resistance-changing layer 50 changes in accordance with the amount of oxygen vacancies in the low-resistance layer 50y. The low-resistance layer 50y is a so-called vacancy-modulated conductive oxide.

[0215] For example, a high-resistance state is defined as data "1," and a low-resistance state as data "0." The memory cell MC can then store 1-bit data, either "0" or "1."

[0216] As described above, the storage device of the fourth embodiment can realize a switching element with excellent characteristics, similar to the first embodiment. Therefore, the fourth embodiment can realize a storage device having a switching element with excellent characteristics.

[0217] (Fifth embodiment) The fifth embodiment of the memory device includes a memory cell comprising a first conductive layer, a second conductive layer, and a memory layer provided between the first conductive layer and the second conductive layer. The memory layer comprises an oxide, nitride, or oxynitride of at least one first element selected from the group consisting of aluminum (Al), silicon (Si), germanium (Ge), zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), and magnesium (Mg); at least one second element, different from the at least one first element, selected from the group consisting of aluminum (Al), zinc (Zn), tin (Sn), gallium (Ga), and indium (In); and at least one third element selected from the group consisting of tellurium (Te), sulfur (S), selenium (Se), and antimony (Sb). The memory layer includes a first region and a second region, the second region being located either between the first region and the first conductive layer or between the first region and the second conductive layer, and the total concentration is the sum of the atomic concentrations of a first element, a second element, a third element, oxygen (O), and nitrogen (N). The first concentration, which is the sum of the atomic concentrations of the second and third elements in the first region divided by the total concentration, is greater than the second concentration, which is the sum of the atomic concentrations of the second and third elements in the second region divided by the total concentration.

[0218] Furthermore, the storage device of the fifth embodiment further comprises a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

[0219] The memory device of the fifth embodiment differs from the memory device of the first embodiment in that the memory cell does not include a third conductive layer and a resistive switching layer, and instead includes a memory layer with a configuration similar to that of the switching layer of the first embodiment. The following description will omit some parts that overlap with the first embodiment.

[0220] Figure 22 is a schematic cross-sectional view of a memory cell of the fifth embodiment of the storage device. Figure 22 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, indicated, for example, by a dotted circle.

[0221] As shown in Figure 22, the memory cell MC comprises a lower electrode 10, an upper electrode 20, and a memory layer 60. The memory layer 60 includes a high-density region 61 and a medium-density region 62. The high-density region 61 includes a first contact portion 61x. The medium-density region 62 includes a second contact portion 62x.

[0222] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The high-concentration region 61 is an example of the first region. The medium-concentration region 62 is an example of the second region. The first contact portion 61x is an example of the first part. The second contact portion 62x is an example of the second part.

[0223] The lower electrode 10, the memory layer 60, and the upper electrode 20 constitute the memory element of the memory cell MC. The memory element of the memory cell MC has a switching function and a function to store information.

[0224] The memory layer 60 has the same configuration as the switching layer 40 of the first embodiment. The high-density region 61 and the medium-density region 62 of the memory layer 60 have the same configuration as the high-density region 41 and the medium-density region 42 of the switching layer 40 of the first embodiment, respectively.

[0225] The memory layer 60 is provided between the lower electrode 10 and the upper electrode 20. The memory layer 60 is in contact with, for example, the lower electrode 10 and the upper electrode 20. The intermediate electrode 30 in the first embodiment corresponds to the upper electrode 20 in the fifth embodiment. The intermediate electrode 30 in the first embodiment performs the same function as the upper electrode 20 in the fifth embodiment. Therefore, in the fifth embodiment, the third conductive layer in the first embodiment can be read as the second conductive layer.

[0226] The memory layer 60 has a nonlinear current-voltage characteristic in which the current rises sharply at a specific threshold voltage. Furthermore, the memory layer 60 has a characteristic in which the threshold voltage changes when a predetermined voltage is applied. The memory layer 60 also has a characteristic in which its electrical resistance changes when a predetermined voltage is applied. In the fifth embodiment, the high-resistance state is a state in which the resistance of the memory layer 60 is relatively high at the read voltage. Also, in the fifth embodiment, the low-resistance state is a state in which the resistance of the memory layer 60 is relatively low at the read voltage.

[0227] The memory layer 60 has the function of suppressing the increase in semi-selective leakage current flowing to the semi-selective cells. The memory layer 60 also has the function of storing data by resistance changes. The memory layer 60 is a single layer and realizes the functions of the switching layer 40 and the resistance change layer 50 of the first embodiment.

[0228] Figure 23 is an explanatory diagram of the current-voltage characteristics of the memory element in the fifth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 23, the horizontal axis shows the voltage applied to the upper electrode 20 with reference to the potential of the lower electrode 10. Figure 23 shows the current-voltage characteristics of the memory layer 60 in the fifth embodiment. Figure 23 shows the current-voltage characteristics of the memory cell MC in the fifth embodiment.

[0229] The memory element of the fifth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 23, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0230] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0231] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0232] The first positive voltage threshold voltage Vtpp is higher than the second positive voltage threshold voltage Vtnp. Also, the first negative voltage threshold voltage Vtpn is lower than the second negative voltage threshold voltage Vtnn.

[0233] The memory element of the fifth embodiment can take on both a high-resistance state and a low-resistance state under both positive and negative voltage conditions. When a predetermined positive voltage is applied to the upper electrode 20, it enters a high-resistance state under both positive and negative voltage conditions. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it enters a low-resistance state under both positive and negative voltage conditions. Hereinafter, the high-resistance state is defined as data "1" and the low-resistance state as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0234] Figure 24 is an explanatory diagram of a first example of the memory operation of the storage device according to the fifth embodiment. Figure 24 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing memory operation.

[0235] In the first operational example, the high-resistance and low-resistance states on the negative voltage side are used for memory operation. In the first operational example, the negative side read voltage Vrn is used as the read voltage.

[0236] When writing the data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and the data "1" is written to the selected cell.

[0237] When writing the data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is achieved on the negative voltage side, and the data "0" is written to the selected cell.

[0238] In the first example of operation, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0239] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the second negative voltage threshold voltage Vtnn.

[0240] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0241] When reading data from a selected cell, a negative readout voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0242] In the first example of operation, data corruption does not occur by applying the negative read voltage Vrn, regardless of whether the data in the selected cell is "1" or "0". In other words, in the first example of operation, non-destructive reading is possible regardless of whether the data in the selected cell is "1" or "0".

[0243] Figure 25 is an explanatory diagram of a second example of memory operation of the storage device according to the fifth embodiment. Figure 25 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing memory operation.

[0244] In the second operating example, the high-resistance and low-resistance states on the positive voltage side are used for memory operation. In the second operating example, the positive side read voltage Vrp is used as the read voltage.

[0245] When writing the data "1" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a high-resistance state is achieved on the positive voltage side, and the data "1" is written to the selected cell.

[0246] When writing the data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0247] In the second example of operation, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0248] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the second negative voltage threshold voltage Vtnn.

[0249] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0250] When reading data from a selected cell, a positive readout voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0251] In the second example of operation, if the data in the selected cell is "1", no data corruption occurs when the positive read voltage Vrp is applied. In other words, in the second example of operation, if the data in the selected cell is "1", non-destructive reading is possible.

[0252] On the other hand, if the data in the selected cell is "0", applying a positive read voltage Vrp higher than the second positive voltage threshold voltage Vtnp may cause current to flow, potentially changing the data in the selected cell to "1". In other words, in the second example of operation, if the data in the selected cell is "0", a destructive read may occur. Therefore, if the data in the selected cell is "0", it may be necessary to rewrite the data to "0" after reading the data in the selected cell in order to maintain the data in the selected cell.

[0253] (First variation) The first modified memory device of the fifth embodiment differs from the memory device of the fifth embodiment in that the current-voltage characteristics of the memory elements are different.

[0254] Figure 26 is an explanatory diagram of the current-voltage characteristics of the memory element of the first modified example of the fifth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 26, the horizontal axis shows the voltage applied to the upper electrode 20 with reference to the potential of the lower electrode 10. Figure 26 shows the current-voltage characteristics of the memory layer 60 of the first modified example of the fifth embodiment. Figure 26 shows the current-voltage characteristics of the memory cell MC of the first modified example of the fifth embodiment.

[0255] The memory element of the first modified example of the fifth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 26, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0256] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0257] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0258] The first positive voltage threshold voltage Vtpp is lower than the second positive voltage threshold voltage Vtnp. Also, the first negative voltage threshold voltage Vtpn is higher than the second negative voltage threshold voltage Vtnn.

[0259] The memory element of the first modification of the fifth embodiment can take on both a high-resistance state and a low-resistance state on both the positive and negative voltage sides. When a predetermined positive voltage is applied to the upper electrode 20, it enters a low-resistance state on both the positive and negative voltage sides. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it enters a high-resistance state on both the positive and negative voltage sides. Hereinafter, the high-resistance state is defined as data "1" and the low-resistance state as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0260] Figure 27 is an explanatory diagram of a third example of the memory operation of the storage device of the first modified example of the fifth embodiment. Figure 27 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing memory operation.

[0261] In the third operational example, the high-resistance and low-resistance states on the negative voltage side are used for memory operation. In the third operational example, the negative side read voltage Vrn is used as the read voltage.

[0262] When writing the data "1" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and the data "1" is written to the selected cell.

[0263] When writing data “0” to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the second positive-voltage-side threshold voltage Vtnp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a low-resistance state is realized on the negative-voltage side, and data “0” is written to the selected cell.

[0264] In the third operation example, when writing data “1” to the selected cell, if the data stored in the selected cell is data “0”, even if the negative-side writing voltage Vwn is higher than the second negative-voltage-side threshold voltage Vtnn, but lower than the first negative-voltage-side threshold voltage Vtpn, a current will flow. Therefore, there is a possibility that data “1” can be written. Thus, for example, by setting the negative-side writing voltage Vwn to a voltage between the second negative-voltage-side threshold voltage Vtnn and the first negative-voltage-side threshold voltage Vtpn, low power consumption or high reliability of the memory device can be achieved.

[0265] When a positive-side writing voltage Vwp is applied to the selected cell, a voltage Vwp / 2 is applied to the semi-selected cell. Also, when a negative-side writing voltage Vwn is applied to the selected cell, a voltage Vwn / 2 is applied to the semi-selected cell. The voltage Vwp / 2 is lower than the first positive-voltage-side threshold voltage Vtpp. Also, the voltage Vwn / 2 is higher than the first negative-voltage-side threshold voltage Vtpn.

[0266] Therefore, even when the semi-selected cell is in a low-resistance state, the semi-selected leakage current flowing through the semi-selected cell can be suppressed. Thus, the memory element also functions as a switching element.

[0267] When reading the data of the selected cell, a negative-side reading voltage Vrn is applied to the selected cell. The data of the selected cell can be determined by detecting a current change or a potential change caused by the difference in the flowing current between the case of data “1” and the case of data “0”.

[0268] In the case of the third operation example, when the data in the selected cell is data "1", data destruction due to the application of the negative-side read voltage Vrn does not occur. In other words, in the case of the third operation example, if the data in the selected cell is data "1", non-destructive readout is possible.

[0269] On the other hand, when the data in the selected cell is data "0", by applying a negative-side read voltage Vrn lower than the first negative-voltage-side threshold voltage Vtpn, a current may flow and the data in the selected cell may change to data "1". In other words, in the case of the third operation example, when the data in the selected cell is data "0", there is a possibility of destructive readout. Therefore, when the data in the selected cell is data "0", after reading the data in the selected cell, in order to maintain the data in the selected cell, it may be necessary to rewrite the data "0".

[0270] FIG. 28 is an explanatory diagram of a fourth operation example of the memory operation of the memory device according to the first modification of the fifth embodiment. FIG. 28 shows the positive-side write voltage Vwp, a voltage (Vwp / 2) that is half of the positive-side write voltage Vwp, the negative-side write voltage Vwn, a voltage (Vwn / 2) that is half of the negative-side write voltage Vwn, and the positive-side read voltage Vrp when performing the memory operation.

[0271] In the fourth operation example, the high-resistance state and the low-resistance state on the positive voltage side are used for the memory operation. In the fourth operation example, the positive-side read voltage Vrp is used as the read voltage.

[0272] When writing data "1" into the selected cell, a negative-side write voltage Vwn is applied to the upper electrode 20. The negative-side write voltage Vwn is a voltage lower than the second negative-voltage-side threshold voltage Vtnn. By applying the negative-side write voltage Vwn to the upper electrode 20, a high-resistance state is realized on the positive voltage side, and data "1" is written into the selected cell.

[0273] When writing the data "0" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a low-resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0274] In the fourth example of operation, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", current will flow even if the negative write voltage Vwn is higher than the second negative voltage threshold voltage Vtnn, as long as it is lower than the first negative voltage threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage threshold voltage Vtnn and the first negative voltage threshold voltage Vtpn, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0275] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the first positive voltage threshold voltage Vtpp. Voltage Vwn / 2 is higher than the first negative voltage threshold voltage Vtpn.

[0276] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0277] When reading data from a selected cell, a positive readout voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0278] In the fourth example of operation, data corruption does not occur by applying the positive read voltage Vrp, regardless of whether the data in the selected cell is "1" or "0". In other words, in the fourth example of operation, non-destructive reading is possible regardless of whether the data in the selected cell is "1" or "0".

[0279] (Second variation) The second modified memory device of the fifth embodiment differs from the memory device of the fifth embodiment in that the current-voltage characteristics of the memory elements are different.

[0280] Figure 29 is an explanatory diagram of the current-voltage characteristics of a memory element in a second modified example of the fifth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 29, the horizontal axis shows the voltage applied to the upper electrode 20 with reference to the potential of the lower electrode 10. Figure 29 shows the current-voltage characteristics of the memory layer 60 in a second modified example of the fifth embodiment. Figure 29 shows the current-voltage characteristics of the memory cell MC in a second modified example of the fifth embodiment.

[0281] The memory element of the second modified example of the fifth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 29, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0282] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0283] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0284] The first positive voltage threshold voltage Vtpp is lower than the second positive voltage threshold voltage Vtnp. Also, the first negative voltage threshold voltage Vtpn is lower than the second negative voltage threshold voltage Vtnn.

[0285] The memory element of the second modification of the fifth embodiment can take on both a high-resistance state and a low-resistance state on both the positive and negative voltage sides. When a predetermined positive voltage is applied to the upper electrode 20, it takes on a low-resistance state on the positive voltage side and a high-resistance state on the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it takes on a high-resistance state on the positive voltage side and a low-resistance state on the negative voltage side. Hereinafter, the high-resistance state is defined as data "1" and the low-resistance state as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0286] Figure 30 is an explanatory diagram of a fifth example of the memory operation of a storage device in the second modification of the fifth embodiment. Figure 30 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing memory operation.

[0287] In the fifth operating example, the high-resistance and low-resistance states on the negative voltage side are used for memory operation. In the fifth operating example, the negative side read voltage Vrn is used as the read voltage.

[0288] When writing the data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is higher than the second positive voltage threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and the data "1" is written to the selected cell.

[0289] When writing data “0” into the selected cell, a negative-side writing voltage Vwn is applied to the upper electrode 20. The negative-side writing voltage Vwn is a voltage lower than the first negative-voltage-side threshold voltage Vtpn. By applying the negative-side writing voltage Vwn to the upper electrode 20, a low-resistance state is realized on the negative-voltage side, and data “0” is written into the selected cell.

[0290] When a positive-side writing voltage Vwp is applied to the selected cell, a voltage Vwp / 2 is applied to the half-selected cell. Also, when a negative-side writing voltage Vwn is applied to the selected cell, a voltage Vwn / 2 is applied to the half-selected cell. The voltage Vwp / 2 is lower than the first positive-voltage-side threshold voltage Vtpp. Also, the voltage Vwn / 2 is higher than the second negative-voltage-side threshold voltage Vtnn.

[0291] Therefore, even when the half-selected cell is in a low-resistance state, the half-selected leakage current flowing through the half-selected cell can be suppressed. Thus, the memory element also functions as a switching element.

[0292] When reading the data of the selected cell, a negative-side reading voltage Vrn is applied to the selected cell. The data of the selected cell can be determined by detecting a current change or a potential change caused by the difference in the flowing current between the case of data “1” and the case of data “0”. <XXX

[0293] In the case of the fifth operation example, data destruction does not occur by applying the negative-side reading voltage Vrn whether the data of the selected cell is data “1” or data “0”. In other words, in the case of the fifth operation example, non-destructive reading is possible whether the data of the selected cell is data “1” or data “0”.

[0294] FIG. 31 is an explanatory diagram of a sixth operation example of the memory operation of the memory device according to the second modification of the fifth embodiment. FIG. 31 shows the positive-side writing voltage Vwp, the voltage (Vwp / 2) which is half of the positive-side writing voltage Vwp, the negative-side writing voltage Vwn, the voltage (Vwn / 2) which is half of the negative-side writing voltage Vwn, and the positive-side reading voltage Vrp when performing the memory operation.

[0295] In the sixth operating example, the high-resistance and low-resistance states on the positive voltage side are used for memory operation. In the sixth operating example, the positive side read voltage Vrp is used as the read voltage.

[0296] When writing the data "1" to the selected cell, a negative writing voltage Vwn is applied to the upper electrode 20. The negative writing voltage Vwn is lower than the first negative voltage threshold voltage Vtpn. By applying the negative writing voltage Vwn to the upper electrode 20, a high resistance state is achieved on the positive voltage side, and the data "1" is written to the selected cell.

[0297] When writing the data "0" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a low-resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0298] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the first positive voltage threshold voltage Vtpp. Voltage Vwn / 2 is higher than the second negative voltage threshold voltage Vtnn.

[0299] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0300] When reading data from a selected cell, a positive readout voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0301] In the sixth example of operation, data corruption does not occur by applying the positive read voltage Vrp, regardless of whether the data in the selected cell is "1" or "0". In other words, in the sixth example of operation, non-destructive reading is possible regardless of whether the data in the selected cell is "1" or "0".

[0302] (Third variation) The third modified memory device of the fifth embodiment differs from the memory device of the fifth embodiment in that the current-voltage characteristics of the memory elements are different.

[0303] Figure 32 is an explanatory diagram of the current-voltage characteristics of a memory element in the third modified example of the fifth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 32, the horizontal axis shows the voltage applied to the upper electrode 20 with reference to the potential of the lower electrode 10. Figure 32 shows the current-voltage characteristics of the memory layer 60 in the third modified example of the fifth embodiment. Figure 32 shows the current-voltage characteristics of the memory cell MC in the third modified example of the fifth embodiment.

[0304] The memory element of the third modified example of the fifth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 32, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0305] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0306] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0307] The first positive voltage threshold voltage Vtpp is higher than the second positive voltage threshold voltage Vtnp. Also, the first negative voltage threshold voltage Vtpn is higher than the second negative voltage threshold voltage Vtnn.

[0308] The memory element of the third modification of the fifth embodiment can take on both a high-resistance state and a low-resistance state on both the positive and negative voltage sides. When a predetermined positive voltage is applied to the upper electrode 20, it takes on a high-resistance state on the positive voltage side and a low-resistance state on the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it takes on a low-resistance state on the positive voltage side and a high-resistance state on the negative voltage side. Hereinafter, the high-resistance state is defined as data "1" and the low-resistance state as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0309] Figure 33 is an explanatory diagram of a seventh example of memory operation of a storage device in the third modification of the fifth embodiment. Figure 33 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing memory operation.

[0310] In the seventh operating example, the high-resistance and low-resistance states on the negative voltage side are used for memory operation. In the seventh operating example, the negative side read voltage Vrn is used as the read voltage.

[0311] When writing the data "1" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and the data "1" is written to the selected cell.

[0312] When writing the data "0" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the first positive-side threshold voltage Vtpp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a low-resistance state is achieved on the negative voltage side, and the data "0" is written to the selected cell.

[0313] In the seventh example of operation, when writing data "1" to the selected cell, if the data stored in the selected cell is data "0", current will flow even if the negative write voltage Vwn is higher than the second negative voltage threshold voltage Vtnn, as long as it is lower than the first negative voltage threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage threshold voltage Vtnn and the first negative voltage threshold voltage Vtpn, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0314] Furthermore, in the seventh example of operation, when writing data "0" to the selected cell, if the data stored in the selected cell is data "1", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "0" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0315] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the first negative voltage threshold voltage Vtpn.

[0316] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0317] When reading data from a selected cell, a negative readout voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0318] In the case of the seventh operating example, if the data in the selected cell is "1", no data corruption will occur due to the application of the negative read voltage Vrn. In other words, in the case of the seventh operating example, if the data in the selected cell is "1", non-destructive readout is possible.

[0319] On the other hand, if the data of the selected cell is "0", applying a negative read voltage Vrn lower than the first negative voltage threshold voltage Vtpn may cause current to flow, potentially changing the data of the selected cell to "1". In other words, in the seventh example of operation, if the data of the selected cell is "0", a destructive read may occur. Therefore, if the data of the selected cell is "0", it may be necessary to rewrite the data to "0" after reading the data of the selected cell in order to maintain the data.

[0320] Figure 34 is an explanatory diagram of the eighth example of memory operation of the storage device in the third modification of the fifth embodiment. Figure 34 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing memory operation.

[0321] In the eighth operating example, the high-resistance and low-resistance states on the positive voltage side are used for memory operation. In the eighth operating example, the positive side read voltage Vrp is used as the read voltage.

[0322] When writing the data "1" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a high-resistance state is achieved on the positive voltage side, and the data "1" is written to the selected cell.

[0323] When writing the data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0324] In the eighth example of operation, when writing data "1" to the selected cell, if the data stored in the selected cell is data "0", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0325] Furthermore, in the eighth example of operation, when writing data "0" to the selected cell, if the data stored in the selected cell is data "1", current will flow even if the negative write voltage Vwn is higher than the second negative voltage threshold voltage Vtnn, as long as it is lower than the first negative voltage threshold voltage Vtpn. Therefore, there is a possibility that data "0" can be written. Accordingly, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage threshold voltage Vtnn and the first negative voltage threshold voltage Vtpn, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0326] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the first negative voltage threshold voltage Vtpn.

[0327] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0328] When reading data from a selected cell, a positive readout voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0329] In the case of the eighth operating example, if the data in the selected cell is "1", no data corruption will occur by applying the positive side read voltage Vrp. In other words, in the case of the eighth operating example, if the data in the selected cell is "1", non-destructive readout is possible.

[0330] On the other hand, if the data of the selected cell is "0", applying a positive read voltage Vrp that is higher than the second positive voltage threshold voltage Vtnp may cause current to flow, potentially changing the data of the selected cell to "1". In other words, in the case of the eighth example of operation, if the data of the selected cell is "0", a destructive read may occur. Therefore, if the data of the selected cell is "0", it may be necessary to rewrite the data to "0" after reading the data of the selected cell in order to maintain the data of the selected cell.

[0331] In the fifth embodiment and its modified versions, the memory elements of the memory cell MC have a switching function and a function for storing information. The memory layer 60 is a single layer and implements the functions of the switching layer 40 and the resistive switching layer 50 of the first and second embodiments. By having the memory layer 60 of the fifth embodiment be a single layer and possessing both switching and memory functions, the structure of the memory cell MC can be made extremely simple.

[0332] Furthermore, the memory layer 60 of the storage device in the fifth embodiment and its modified form has the same configuration as the switching layer 40 of the first embodiment. Therefore, according to the fifth embodiment and its modified form, a storage device with excellent switching characteristics can be realized, similar to the first embodiment.

[0333] Furthermore, the multiple current-voltage characteristics of the memory element shown in the fifth embodiment and its modified form can be achieved, for example, by employing a memory layer 60 having an appropriate chemical composition.

[0334] In the first to third embodiments, magnetoresistive memory was described as an example of a two-terminal storage device, and in the fourth embodiment, resistive random-access memory was described as an example of a storage device. However, the present invention can be applied to other two-terminal storage devices. For example, the present invention can be applied to phase-change memory (PCM) or ferroelectric random-access memory (FeRAM).

[0335] In the fourth embodiment, the case in which the switching layer of the first embodiment is applied to the switching layer of a resistive random-access memory was described as an example. However, it is also possible to apply a modified version of the first embodiment, the second embodiment or its modified version, or the third embodiment or its modified version to the switching layer.

[0336] In the fifth embodiment, the case in which the switching layer of the first embodiment is applied to the memory layer was described as an example, but it is also possible to apply a modified version of the first embodiment, the second embodiment or modified version, or the third embodiment or modified version of the switching layer to the memory layer.

[0337] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0338] 10 Lower electrode (first conductive layer) 20 Upper electrode (second conductive layer) 30 Intermediate electrode (third conductive layer) 40 Switching Layer 41. High concentration region (first region) 41x First contact area (first part) 42. Medium concentration range (second range) 42x Second contact area (second part, fourth part) 43. Low concentration region (second region, third region) 43x Third contact point (third part) 50 Resistivity change layer 60 memory layers 61. High-concentration region (first region) 61x First contact area (first part) 62. Medium concentration range (second range) 62x Second contact point (second part) 102 Word line (first wiring) 103-bit line (second wiring) MC memory cell

Claims

1. A first conductive layer and A second conductive layer, A third conductive layer is provided between the first conductive layer and the second conductive layer, A switching layer provided between the first conductive layer and the third conductive layer, A memory cell comprising a resistive change layer provided between the third conductive layer and the second conductive layer, The aforementioned switching layer is An oxide, nitride, or oxynitride of at least one first element selected from the group consisting of aluminum (Al), silicon (Si), germanium (Ge), zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), and magnesium (Mg), Unlike the aforementioned at least one first element, at least one second element selected from the group consisting of aluminum (Al), zinc (Zn), tin (Sn), gallium (Ga), and indium (In), It comprises at least one third element selected from the group consisting of tellurium (Te), sulfur (S), selenium (Se), and antimony (Sb), The switching layer includes a first region and a second region, the second region being provided between the first region and the first conductive layer or between the first region and the third conductive layer. When the sum of the atomic concentrations of the first element, the second element, the third element, oxygen (O), and nitrogen (N) is taken as the total concentration, A memory device wherein the first concentration, which is the concentration obtained by dividing the sum of the atomic concentrations of the second element and the third element in the first region by the total concentration, is greater than the second concentration, which is the concentration obtained by dividing the sum of the atomic concentrations of the second element and the third element in the second region by the total concentration.

2. The memory device according to claim 1, wherein the thickness of the switching layer in the first direction from the first conductive layer toward the second conductive layer is 4 nm or more and 25 nm or less.

3. The first portion of the first region is in contact with either the first conductive layer or the third conductive layer, and the second portion of the second region is in contact with the other conductive layer of the first or third conductive layer. The storage device according to claim 1, wherein the difference between the first concentration of the first portion and the second concentration of the second portion is 10% or more.

4. The storage device according to claim 3, wherein the first concentration of the first portion is 99% or less, and the second concentration of the second portion is 30% or more.

5. The first portion of the first region is in contact with either the first conductive layer or the third conductive layer, and the second portion of the second region is in contact with the other conductive layer of the first or third conductive layer. The storage device according to claim 1, wherein the first concentration of the first portion is 20% or more, and the second concentration of the second portion is less than 30%.

6. The storage device according to claim 5, wherein the difference between the first concentration of the first portion and the second concentration of the second portion is 20% or more.

7. In the distribution of the concentration obtained by dividing the sum of the atomic concentration of the second element and the atomic concentration of the third element by the total concentration, in the first direction from the first conductive layer toward the second conductive layer in the switching layer, When the second region is in contact with the first conductive layer, the distance in the first direction from the first conductive layer to the first position where the concentration is 30% is 0.1 nm or more and 4 nm or less, and the distance in the first direction from the third conductive layer to the first position is 4 nm or more. The storage device according to claim 5, wherein when the second region is in contact with the third conductive layer, the distance in the first direction from the third conductive layer to the second position where the concentration is 30% is 0.1 nm or more and 4 nm or less, and the distance in the first direction from the first conductive layer to the second position is 4 nm or more.

8. The switching layer further includes a third region, and the first region is provided between the third region and the second region. The storage device according to claim 1, wherein the third concentration, which is the sum of the atomic concentrations of the second element and the third element in the third region divided by the total concentration, is smaller than the second concentration.

9. In the distribution of the concentration in the switching layer in the first direction toward the second conductive layer, where the concentration is obtained by dividing the sum of the atomic concentration of the second element and the atomic concentration of the third element by the total concentration, When the third region is in contact with the first conductive layer, the distance in the first direction from the first conductive layer to the position where the distribution is maximized is smaller than the distance in the first direction from the third conductive layer to the position. The storage device according to claim 8, wherein when the third region is in contact with the third conductive layer, the distance from the third conductive layer to the position in the first direction is smaller than the distance from the first conductive layer to the position in the first direction.

10. The third region, the third portion thereof, is in contact with either the first conductive layer or the third conductive layer. The storage device according to claim 8, wherein the third concentration of the third portion is less than 30%.

11. The fourth portion of the second region is in contact with the other conductive layer of the first conductive layer or the third conductive layer. In the distribution of the concentration in the switching layer in the first direction toward the second conductive layer, where the concentration is obtained by dividing the sum of the atomic concentration of the second element and the atomic concentration of the third element by the total concentration, The storage device according to claim 10, wherein the difference between the concentration at the position where the distribution reaches a maximum value and the second concentration in the fourth portion is 10% or more.

12. When the third region is in contact with the first conductive layer, the distance in the first direction from the first conductive layer to the third position where the concentration of the distribution is 30% is 0.1 nm or more and 4 nm or less, and the distance in the first direction from the third conductive layer to the third position is 4 nm or more. When the third region is in contact with the third conductive layer, the distance in the first direction from the third conductive layer to the fourth position where the concentration of the distribution is 30% is 0.1 nm or more and 4 nm or less, and the distance in the first direction from the first conductive layer to the fourth position is 4 nm or more, the storage device according to claim 9.

13. The storage device according to claim 1, wherein the switching layer comprises a compound of the second element and the third element.

14. The storage device according to claim 1, wherein the concentration obtained by dividing the sum of the atomic concentration of the second element and the atomic concentration of the third element by the total concentration increases or decreases monotonically from the first conductive layer to the third conductive layer.

15. The memory device according to claim 1, wherein the first conductive layer, the second conductive layer, or the third conductive layer comprises at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

16. The storage device according to claim 1, wherein the first conductive layer, the second conductive layer, or the third conductive layer comprises at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

17. The storage device according to claim 1, wherein the resistance change layer includes a magnetic tunnel junction.

18. The resistance-changing layer changes in electrical resistance when a predetermined voltage is applied. The storage device according to claim 1, wherein the switching layer has a nonlinear current-voltage characteristic in which the current rises at a specific threshold voltage.

19. Multiple first wires and The system further comprises a plurality of second wirings that intersect with the plurality of first wirings, The memory device according to claim 1, wherein the memory cell is provided in a region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

20. A first conductive layer and A second conductive layer, A memory cell comprising a memory layer provided between the first conductive layer and the second conductive layer, The aforementioned memory layer is An oxide, nitride, or oxynitride of at least one first element selected from the group consisting of aluminum (Al), silicon (Si), germanium (Ge), zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), and magnesium (Mg), Unlike the aforementioned at least one first element, at least one second element selected from the group consisting of aluminum (Al), zinc (Zn), tin (Sn), gallium (Ga), and indium (In), It comprises at least one third element selected from the group consisting of tellurium (Te), sulfur (S), selenium (Se), and antimony (Sb), The memory layer includes a first region and a second region, the second region being provided between the first region and the first conductive layer or between the first region and the second conductive layer. When the sum of the atomic concentrations of the first element, the second element, the third element, oxygen (O), and nitrogen (N) is taken as the total concentration, A memory device wherein the first concentration, which is the concentration obtained by dividing the sum of the atomic concentrations of the second element and the third element in the first region by the total concentration, is greater than the second concentration, which is the concentration obtained by dividing the sum of the atomic concentrations of the second element and the third element in the second region by the total concentration.

21. The memory device according to claim 20, wherein the thickness of the memory layer in the first direction from the first conductive layer toward the second conductive layer is 4 nm or more and 25 nm or less.

22. The first portion of the first region is in contact with either the first conductive layer or the second conductive layer, and the second portion of the second region is in contact with the other conductive layer of the first or second conductive layer. The storage device according to claim 20, wherein the difference between the first concentration of the first portion and the second concentration of the second portion is 10% or more.

23. The storage device according to claim 22, wherein the first concentration of the first portion is 99% or less, and the second concentration of the second portion is 30% or more.

24. The first portion of the first region is in contact with either the first conductive layer or the second conductive layer, and the second portion of the second region is in contact with the other conductive layer of the first or second conductive layer. The storage device according to claim 20, wherein the first concentration of the first portion is 20% or more, and the second concentration of the second portion is less than 30%.

25. The storage device according to claim 24, wherein the difference between the first concentration of the first portion and the second concentration of the second portion is 20% or more.

26. In the first direction toward the second conductive layer in the memory layer, the distribution of the concentration obtained by dividing the sum of the atomic concentration of the second element and the atomic concentration of the third element by the total concentration, When the second region is in contact with the first conductive layer, the distance in the first direction from the first conductive layer to the first position where the concentration is 30% is 0.1 nm or more and 4 nm or less, and the distance in the first direction from the second conductive layer to the first position is 4 nm or more. The storage device according to claim 24, wherein when the second region is in contact with the second conductive layer, the distance in the first direction from the second conductive layer to the second position where the concentration is 30% is 0.1 nm or more and 4 nm or less, and the distance in the first direction from the first conductive layer to the second position is 4 nm or more.

27. The memory layer further includes a third region, and the first region is provided between the third region and the second region. The storage device according to claim 20, wherein the third concentration, which is the sum of the atomic concentrations of the second element and the third element in the third region divided by the total concentration, is smaller than the second concentration.

28. In the first direction distribution of the concentration in the memory layer from the first conductive layer toward the second conductive layer, where the concentration is obtained by dividing the sum of the atomic concentration of the second element and the atomic concentration of the third element by the total concentration, When the third region is in contact with the first conductive layer, the distance in the first direction from the first conductive layer to the position where the distribution is maximized is smaller than the distance in the first direction from the second conductive layer to the position. The storage device according to claim 27, wherein when the third region is in contact with the second conductive layer, the distance from the second conductive layer to the position in the first direction is smaller than the distance from the first conductive layer to the position in the first direction.

29. The third region, the third portion thereof, is in contact with either the first conductive layer or the second conductive layer. The storage device according to claim 27, wherein the third concentration of the third portion is less than 30%.

30. The fourth portion of the second region is in contact with the first conductive layer or the other conductive layer of the second conductive layer. In the first direction distribution of the concentration in the memory layer from the first conductive layer toward the second conductive layer, where the concentration is obtained by dividing the sum of the atomic concentration of the second element and the atomic concentration of the third element by the total concentration, The storage device according to claim 29, wherein the difference between the concentration at the position where the distribution reaches a maximum value and the second concentration in the fourth portion is 10% or more.

31. When the third region is in contact with the first conductive layer, the distance in the first direction from the first conductive layer to the third position where the concentration of the distribution is 30% is 0.1 nm or more and 4 nm or less, and the distance in the first direction from the second conductive layer to the third position is 4 nm or more. The storage device according to claim 28, wherein when the third region is in contact with the second conductive layer, the distance in the first direction from the second conductive layer to the fourth position where the concentration of the distribution is 30% is 0.1 nm or more and 4 nm or less, and the distance in the first direction from the first conductive layer to the fourth position is 4 nm or more.

32. The memory device according to claim 20, wherein the memory layer comprises a compound of the second element and the third element.

33. The storage device according to claim 20, wherein the concentration obtained by dividing the sum of the atomic concentration of the second element and the atomic concentration of the third element by the total concentration increases or decreases monotonically from the first conductive layer toward the second conductive layer.

34. The memory layer has a nonlinear current-voltage characteristic in which the current rises at a specific threshold voltage, and the threshold voltage changes when a predetermined voltage is applied, as described in claim 20.

35. Multiple first wires and The system further comprises a plurality of second wirings that intersect with the plurality of first wirings, The storage device according to claim 20, wherein the memory cell is provided in a region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

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