Semiconductor memory
By arranging memory cell arrays horizontally and vertically overlapping sense amplifier units with switch circuits, the semiconductor memory device achieves increased storage capacity with a simplified structure, addressing the complexity of existing wiring designs.
JP2026109221APending Publication Date: 2026-07-01KIOXIA CORP
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2024-12-19
- Publication Date
- 2026-07-01
AI Technical Summary
Technical Problem
The increasing complexity of wiring structures and the need for more sense amplifier units in semiconductor memory devices complicates the design and limits the storage capacity.
Method used
The semiconductor memory device is designed with a first memory cell array and a second memory cell array arranged horizontally offset to each other, with a first sense amplifier unit and a switch circuit positioned vertically to simplify the connection between these arrays, allowing for increased storage capacity with a simpler structure.
Benefits of technology
This configuration enhances storage capacity by optimizing the arrangement of memory cells and sense amplifier units, reducing complexity in wiring and improving operational efficiency.
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Smart Images
Figure 2026109221000001_ABST
Abstract
To increase memory capacity with a simple structure. [Solution] The semiconductor memory device of the embodiment comprises a first memory cell array including a plurality of first memory cells, a second memory cell array including a plurality of second memory cells, a first sense amplifier unit from which data from the plurality of first and second memory cells is read, and a first switch circuit for switching the connections between the plurality of first and second memory cells and the first sense amplifier unit, wherein the first memory cell array and the first sense amplifier unit are arranged to overlap in the vertical direction, the second memory cell array is arranged in a position shifted horizontally relative to the first memory cell array and the first sense amplifier unit, and the first switch circuit is arranged in a position that overlaps in the vertical direction with the region between the first and second memory cell arrays, or in a region that overlaps in the vertical direction with the first memory cell array.
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