Monitoring error correction operations performed in memory

Abstract

The present disclosure includes apparatuses and methods for monitoring error correction operations performed in memory. Several embodiments include a memory and a circuit configured to determine a quantity of error data corrected during an error correction operation performed on soft data associated with sensed data states of several memory cells of the memory, determine a quality of soft information associated with the error data corrected during the error correction operation performed on the soft data, and determine whether to take a corrective action on the sensed data based on the quantity of error data corrected during the error correction operation and the quality of soft information associated with the error data corrected during the error correction operation.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of the invention patent application filed on March 17, 2017, with application number "201780029836.6" and invention title "Monitoring Error Correction Operations Performed in Memory". Technical Field

[0003] The present invention generally relates to semiconductor memories and methods, and more specifically to monitoring error correction operations performed in a memory. Background Technology

[0004] Memory devices are typically provided as internal semiconductor integrated circuits and / or external removable devices in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and may include random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can retain stored data when no power is supplied and may include NAND flash memory, NOR flash memory, phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), etc.

[0005] Memory devices can be combined to form solid-state drives (SSDs). SSDs may include non-volatile memory (e.g., NAND flash memory and / or NOR flash memory) and / or volatile memory (e.g., DRAM and / or SRAM), as well as various other types of non-volatile and volatile memory. Flash memory devices may include, for example, memory cells that store data in charge storage structures (e.g., floating gates) and can be used as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use single-transistor memory cells that allow for high memory density, high reliability, and low power consumption.

[0006] Memory cells in an array architecture can be programmed to a target (e.g., desired) state. For example, charge can be placed on or removed from the charge storage structure of a memory cell to program the memory cell to a specific data state. The stored charge on the charge storage structure of the memory cell can indicate the threshold voltage (Vt) of the cell.

[0007] For example, a single-level cell (SLC) can be programmed to two different target states, which can be represented by binary units 1 or 0. Some flash memory cells can be programmed to more than two target states (e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110). Such cells can be called multi-state memory cells, multi-cell cells, or multi-level cells (MLCs). MLCs can provide higher memory density without increasing the number of memory cells because each cell can represent more than one number (e.g., more than one bit).

[0008] The state of a flash memory cell can be determined by sensing the stored charge (e.g., Vt) on its charge storage structure. However, several mechanisms, such as read interference, programming interference, cell-to-cell interference, and / or charge loss (e.g., charge leakage), can cause a change in the Vt of the memory cell. Due to this change in Vt, errors can occur when sensing the state of the cell. For example, the cell may be sensed as being in a state other than the target state (e.g., a state different from the state the cell is programmed into). Such errors may or may not be corrected by error correction code (ECC) schemes, such as low-density parity-check (LDPC) ECC schemes, which can use soft data associated with the data state of the cell to correct the error. However, soft data values ​​(e.g., bits) can also be erroneous, and these errors may or may not be corrected by ECC schemes. Summary of the Invention

[0009] This application provides an apparatus including a memory and circuitry configured to: determine a bit error rate associated with an error correction operation; perform the error correction operation on sensed data states of a plurality of memory cells of the memory and soft data associated with the sensed data states; determine a high reliability error rate associated with the error correction operation; and determine whether to take corrective action on the sensed data states by plotting the bit error rate and the high reliability error rate in a two-dimensional bit error rate versus high reliability error rate space.

[0010] This application provides a method for operating a memory, the method comprising: determining a bit error rate associated with an error correction operation; performing an error correction operation on a sensed data state of a plurality of memory cells and soft data associated with the sensed data state; determining a high reliability error rate associated with the error correction operation; and determining whether to take a correction action on the sensed data state based on the position of a data point corresponding to the bit error rate and the high reliability error rate in a two-dimensional bit error rate to high reliability error rate space.

[0011] This application provides an apparatus including a memory and circuitry. The circuitry is configured to: sense data states of a plurality of memory cells in the memory and soft data associated with the sensed data states; perform an error correction operation on the sensed data states and the soft data; determine a bit error rate associated with the error correction operation; determine a high reliability error rate associated with the error correction operation; and determine whether to take corrective action on the sensed data states by plotting the bit error rate and the high reliability error rate in a two-dimensional bit error rate versus high reliability error rate space. Attached Figure Description

[0012] Figure 1 A schematic diagram illustrating a portion of a memory array according to several embodiments of the present invention.

[0013] Figure 2 The diagram illustrates several threshold voltage distributions, sensing voltages, and data assignments associated with sensing operations according to several embodiments of the present invention.

[0014] Figure 3 This is a functional block diagram of a computing system including a device in the form of a memory device according to several embodiments of the present invention.

[0015] Figure 4 Examples of two-dimensional bit error rates in a high reliability error rate space according to several embodiments of the present invention are described.

[0016] Figure 5 A method for operating a memory according to several embodiments of the present invention is described. Detailed Implementation

[0017] The present invention includes an apparatus and method for monitoring error correction operations performed in a memory. Several embodiments include a memory and circuitry configured to: determine the amount of erroneous data corrected during an error correction operation performed on soft data associated with sensed data states of a plurality of memory cells of the memory; determine the quality of soft information associated with the erroneous data corrected during the error correction operation on the soft data; and determine whether to take a correction action on the sensed data based on the amount of erroneous data corrected during the error correction operation and the quality of the soft information associated with the erroneous data corrected during the error correction operation.

[0018] For example, hard data can refer to binary data values ​​stored in one or more memory cells and provided to the host in response to a sensing operation. In various examples, soft data can also be determined that is associated with the sensed data state of a memory cell (e.g., with hard data). Soft data can, for example, indicate the quality and / or reliability of the hard data, including, for example, information about the probability that a cell stores read hard data or that a cell stores different data. This quality and / or reliability information may be referred to herein as soft information. Therefore, soft data can provide benefits such as increased error correction capability for error correction codes (which can be translated into increased memory lifetime) and other benefits.

[0019] Error correction operations (such as those utilizing low-density parity-check (LDPC) error correction codes (ECC) schemes) can be used in conjunction with both hard and soft data to detect and correct errors. However, such error correction operations may have limited correction capabilities. For example, such operations may only be able to correct a specific (e.g., a maximum) number of errors that might occur in the data. If this correction limit is reached (e.g., if the data has more errors than the error correction operation can correct), then the error correction operation may fail, and other actions may be required to recover the data.

[0020] Error correction operations can be monitored to determine if they are approaching their correction limits, and if so, appropriate corrective actions can be taken to prevent failure of the error correction operation. For example, in the case of hard data, the performance of the error correction operation may depend solely on the amount of erroneous data corrected during the operation. For example, in the case of hard data, whether error correction fails may depend solely on whether the bit error rate associated with the error correction operation meets or exceeds a certain threshold. Therefore, error correction operations performed on hard data can be effectively monitored based solely on the amount of erroneous data associated with them (e.g., the bit error rate).

[0021] However, in the case of soft data, the performance of error correction operations depends on more than just the amount of erroneous data. For example, in some cases, a certain amount of erroneous soft data can cause error correction operations to fail, while in others, that amount of erroneous data may not. Therefore, it is not necessary to rely solely on the amount of erroneous data (e.g., not just the bit error rate) to effectively monitor error correction operations performed on soft data and determine whether corrective action is needed on the sensed data.

[0022] Embodiments of the present invention may monitor such error correction operations and determine whether to take corrective action not only using the amount of erroneous data corrected during error correction operations performed on soft data. For example, embodiments of the present invention may use the quality of the soft data in conjunction with the amount of erroneous data corrected during error correction operations performed on soft data to monitor error correction operations and determine whether to take corrective action. For example, embodiments of the present invention may use a high reliability error rate (which will be further defined and described herein) in conjunction with a bit error rate associated with error correction operations performed on soft data to monitor operations and determine whether to take corrective action on data that has been sensed (e.g., read) from memory. Therefore, embodiments of the present invention can effectively monitor error correction operations performed on both soft and hard data.

[0023] As used herein, "several" can refer to one or more such things. For example, "several memory cells" can refer to one or more memory cells. Additionally, as used herein, particularly with respect to the designations "N" and "M" in the drawings, indicate that certain embodiments of the invention may include certain specific features as thus specified.

[0024] The figures in this article follow a numbering convention, where the first digit or the first few digits correspond to the figure number and the remaining digits identify the elements or components in the figure. Similar elements or components between different figures can be identified by using similar numbers.

[0025] Figure 1 A schematic diagram illustrating a portion of a memory array 100 according to several embodiments of the present invention. Figure 1 The embodiments described herein illustrate a NAND architecture non-volatile memory array. However, the embodiments described herein are not limited to this example. Figure 1 As shown, memory array 100 includes access lines (e.g., word lines 105-1, ..., 105-N) and data lines (e.g., bit lines) 107-1, 107-2, 107-3, ..., 107-M. To facilitate addressing in a digital environment, the number of word lines 105-1, ..., 105-N and the number of bit lines 107-1, 107-2, 107-3, ..., 107-M can be powers of 2 (e.g., 256 word lines multiplied by 4,096 bit lines).

[0026] Memory array 100 includes NAND strings 109-1, 109-2, 109-3, ..., 109-M. Each NAND string includes non-volatile memory cells 111-1, ..., 111-N, each communicatively coupled to a corresponding word line 105-1, ..., 105-N. Each NAND string (and its constituent memory cells) is also associated with bit lines 107-1, 107-2, 107-3, ..., 107-M. The non-volatile memory cells 111-1, ..., 111-N of each NAND string 109-1, 109-2, 109-3, ..., 109-M are connected in series between a source-select gate (SGS) (e.g., a field-effect transistor (FET)) 113 and a drain-select gate (SGD) (e.g., a FET) 119. Each source select gate 113 is configured to selectively couple a corresponding NAND string to a common source 123 in response to a signal on the source select line 117, and each drain select gate 119 is configured to selectively couple a corresponding NAND string to a corresponding bit line in response to a signal on the drain select line 115.

[0027] like Figure 1 In the illustrated embodiment, the source of source select gate 113 is connected to a common source 123. The drain of source select gate 113 is connected to memory cell 111-1 of the corresponding NAND string 109-1. The drain of drain select gate 119 is connected at drain contact 121-1 to bit line 107-1 of the corresponding NAND string 109-1. The source of drain select gate 119 is connected to memory cell 111-N of the corresponding NAND string 109-1 (e.g., a floating gate transistor).

[0028] In several embodiments, the non-volatile memory cells 111-1, ..., 111-N are constructed including charge storage structures, such as floating gates and control gates. The control gates of the non-volatile memory cells 111-1, ..., 111-N are coupled to word lines 105-1, ..., 105-N, respectively. The “columns” of the non-volatile memory cells 111-1, ..., 111-N constitute NAND strings 109-1, 109-2, 109-3, ..., 109-M, and are coupled to given positioning lines 107-1, 107-2, 107-3, ..., 107-M, respectively. The “rows” of the non-volatile memory cells are the memory cells that are commonly coupled to a given word line 105-1, ..., 105-N. The use of the terms “column” and “row” is not intended to imply a specific linear (e.g., vertical and / or horizontal) orientation of the non-volatile memory cells. The NOR array architecture will be arranged similarly, except that the series of memory cells will be coupled in parallel between the select gates.

[0029] A subset of cells coupled to a selected word line (e.g., 105-1, ..., 105-N) may be programmed and / or sensed (e.g., read) together (e.g., simultaneously). A programming operation (e.g., a write operation) may involve applying a number of programming pulses (e.g., 16V to 20V) to the selected word line to increase the threshold voltage (Vt) of the selected memory cell coupled to the selected access line to a desired programming voltage level corresponding to a target (e.g., desired) data state.

[0030] Sensing operations (e.g., read or program verification operations) may include sensing voltage and / or current changes coupled to a bit line of a selected cell to determine the data state of the selected cell (e.g., hard data value). Sensing operations may also be used to determine soft data associated with the data state of the selected cell, as will be further described herein. Sensing operations may include providing (e.g., biasing) a voltage to (e.g., bit line 107-1) associated with the selected memory cell, said voltage being higher than a voltage (e.g., bias voltage) provided to the source (e.g., source 123) associated with said selected memory cell. Sensing operations may alternatively include pre-charging the bit line, then discharging it when the selected cell begins to conduct, and sensing said discharge.

[0031] Sensing the state of a selected cell may involve providing a plurality of step sensing signals (e.g., step sensing signals including different read voltage levels) to a selected word line, while simultaneously providing a plurality of pass signals (e.g., read pass voltages) to word lines of unselected cells coupled to the string, the plurality of pass signals being sufficient to place the unselected cell in a conductive state independently of the Vt of the unselected cell. Bit lines corresponding to read and / or verified selected cells may be sensed to determine whether the selected cell conducts in response to a specific sense voltage applied to the selected word line. For example, the data state of a selected cell may be determined based on the current corresponding to the bit line of the selected cell.

[0032] When the selected cell is in a conductive state, current flows between the source contact at one end of the string and the bit line contact at the other end of the string. Therefore, the current associated with sensing the selected cell is carried through the other cells in the string and each of the selection transistors.

[0033] Figure 2 Schematic 201 illustrates several threshold voltage (Vt) distributions, sensed voltages, and data (e.g., hard and soft data) assignments associated with sensing operations according to several embodiments of the present invention. Figure 2 The two Vt distributions 225-1 and 225-2 shown can correspond to two-bit (e.g., four-state) multilevel memory cells. Therefore, although in Figure 2Not shown, but a two-bit memory cell will contain two additional Vt distributions (e.g., one Vt distribution corresponding to each of the four data states). In this example, only the Vt distributions corresponding to data states L1 and L2 are shown. Furthermore, embodiments of the invention are not limited to two-bit multilevel memory cells. For example, embodiments of the invention may include single-level cells and / or other multilevel cells, such as three-level cells (TLC) or four-level cells (QLC).

[0034] like Figure 2 As shown, Vt distributions 225-1 and 225-2 represent two target data states that a memory cell can be programmed to (e.g., L1 and L2 of a four-level system, where R3 corresponds to a hard read position of the lower page and R1, R2, R4, and R5 correspond to soft read positions of the lower page). In this example, data state L1 corresponds to data "01" and data state L2 corresponds to data "00". However, embodiments of the present invention are not limited to these specific data assignments. Furthermore, although for simplicity... Figure 2 As shown in the figure, but diagram 201 may also include two additional Vt distributions corresponding to the other two data states (e.g., L0 and L3), and data corresponding to the data states (e.g., "11" and "10").

[0035] Vt distributions 225-1 and 225-2 can represent the number of memory cells programmed to corresponding target states (e.g., L1 and L2, respectively), wherein the height of the Vt distribution curve indicates the number of memory cells programmed to a specific voltage within the Vt distribution (e.g., average). The width of the Vt distribution curve indicates the voltage range representing a specific target state (e.g., the width of Vt distribution curve 225-2 for L2 represents the voltage range corresponding to the hard data value 00).

[0036] During a sensing (e.g., read) operation, a sensing (e.g., read) voltage positioned between Vt distributions 225-1 and 225-2 can be used to distinguish between states L1 and L2. In a read operation performed on selected memory cells in a NAND string, unselected memory cells in the string can be biased by a voltage to be in a conducting state. When all cells in the string are in a conducting state, current can flow between the source contact at one end of the string and the drain line contact at the other end. Thus, when a selected cell begins to conduct (e.g., in response to a specific read voltage applied to the control gate of the cell via the selected word line), the data state of the selected cell can be determined based on the current sensed on the bit line corresponding to a particular string.

[0037] Each data state (e.g., L1 and L2) of a memory cell may have soft data associated with it. For example, the Vt distribution associated with each data state (e.g., 225-1 or 225-2) may have a soft data value (e.g., a bit) assigned to it. Figure 2 In the example described, two bits are used to provide soft data associated with the data state. Multiple sensed voltages (e.g.) can be used. Figure 2 The reference voltages R1 to R5 described in the document are used to sense soft data.

[0038] Soft data (e.g., soft data values) associated with the data state of a memory cell can indicate the quality and / or reliability of the data state, and may be referred to herein as soft information (e.g., soft information may refer to quality and / or reliability information indicated by soft data). For example, soft data associated with the data state of a memory cell can indicate the position of Vt associated with the memory cell within the Vt distribution associated with the data state of the memory cell. For example, in Figure 2 In the embodiment described, soft data 00 associated with data state L2 indicates that the Vt of the memory cell is located at a voltage greater than the reference voltage R5 within the Vt distribution 225-2 (e.g., the Vt of the memory cell is positioned toward the middle of the Vt distribution 225-2), and soft data 00 associated with data state L1 indicates that the Vt of the memory cell is located at a voltage less than the reference voltage R1 within the Vt distribution 225-1 (e.g., the Vt of the memory cell is positioned toward the middle of the Vt distribution 225-1).

[0039] Additionally, soft data 10 associated with data state L2 indicates that the Vt of the memory cell is located at the voltage between reference voltages R4 and R5 within the Vt distribution 225-2, and soft data 10 associated with data state L1 indicates that the Vt of the memory cell is located at the voltage between reference voltages R1 and R2 (e.g., soft data 10 indicates that the Vt of the memory cell is located closer to the edge of the Vt distribution than soft data 00). Furthermore, soft data 11 associated with data state L2 indicates that the Vt of the memory cell is located at the voltage between reference voltages R3 and R4, and soft data 11 associated with data state L1 indicates that the Vt of the memory cell is located at the voltage between reference voltages R2 and R3. Therefore, soft data 11 can indicate a lower confidence level of the target state originally programmed to the hard data matching unit.

[0040] Soft data (e.g., soft data values) associated with the data state of a memory cell can also indicate the probability that Vt associated with the memory cell corresponds to the data state of the memory cell. For example, in Figure 2In the embodiments described, soft data 00 associated with data state L2 indicates that the Vt of the memory cell corresponds to a strong probability of data state L2, soft data 10 associated with data state L2 indicates that the Vt of the memory cell corresponds to a moderate probability of data state L2 (e.g., a probability less than the strong probability), and soft data 11 associated with data state L2 indicates that the Vt of the memory cell corresponds to a weak probability of data state L2 (e.g., a probability less than the moderate probability). Similarly, soft data 00 associated with data state L1 indicates that the Vt of the memory cell corresponds to a strong probability of data state L1, soft data 10 associated with data state L1 indicates that the Vt of the memory cell corresponds to a moderate probability of data state L1, and soft data 11 associated with data state L1 indicates that the Vt of the memory cell corresponds to a weak probability of data state L1.

[0041] The embodiments of the present invention are not limited to Figure 2 The reference voltage and / or soft data assignments shown are illustrated. For example, a larger number of soft data assignments can be used to indicate a more precise Vt location within the Vt distribution and / or a more precise probability that Vt corresponds to a data state. However, for the sake of brevity and to avoid obscuring the embodiments of the invention, in... Figure 2 The description indicates five reference voltages and six soft data values ​​representing six different hard data quality and / or confidence levels (e.g., six different soft data probabilities - three for data state L1 and three for data state L2).

[0042] Figure 3 This is a functional block diagram of a computing system 302 including a device in the form of a memory device 334 according to several embodiments of the present invention. As used herein, "device" may refer to (but is not limited to) any of a variety of structures or combinations thereof, such as circuits or circuits, dies or dies, modules or modules, apparatus or apparatuses or systems or systems.

[0043] The memory device 334 may be, for example, a solid-state drive (SSD). Figure 3 In the embodiments described herein, the memory device 334 includes a physical host interface 336, a plurality of memories 340-1, 340-2, ..., 340-N (e.g., solid-state memory devices), and a controller 338 (e.g., an SSD controller) coupled to the physical host interface 336 and the memories 340-1, 340-2, ..., 340-N.

[0044] Memory arrays 340-1, 340-2, ..., 340-N may include, for example, several non-volatile memory arrays (e.g., non-volatile memory cell arrays). For instance, memory arrays 340-1, 340-2, ..., 340-N may contain arrays similar to those previously combined. Figure 1The memory array 100 described includes several memory arrays.

[0045] The physical host interface 336 can be used to transfer information between the memory device 334 and another device, such as host 332. Host 332 may include memory access devices (e.g., processors). Those skilled in the art will understand that "processor" can mean several processors, such as parallel processing systems, several coprocessors, etc. Example hosts may include personal laptop computers, desktop computers, digital cameras, digital recording and playback devices, mobile phones (e.g., smartphones), PDAs, memory card readers, interface hubs, and the like.

[0046] The physical host interface 336 may take the form of a standardized physical interface. For example, when the memory device 334 is used for information storage in the computing system 302, the physical host interface 336 may be a Serial Advanced Technology Attachment (SATA) physical interface, a Peripheral Component Interconnect High Speed ​​(PCIe) physical interface, or a Universal Serial Bus (USB) physical interface, as well as other physical connectors and / or interfaces. Generally, however, the physical host interface 336 provides an interface for transmitting control, address, information (e.g., data), and other signals between the memory device 334 and a host (e.g., host 332) having a compatible receiver for the physical host interface 336.

[0047] Controller 338 may include, for example, control circuitry and / or logic (e.g., hardware and firmware). For instance, controller 338 may include error correction component 342, such as... Figure 3 The error correction component 342 can perform error correction operations to correct errors that may occur when sensing the data state of memory cells in the memories 340-1, 340-2, ..., 340-N, including, for example, errors in the sensed data state and / or errors in the soft data associated with the sensed data state. For example, the error correction component 342 may be a low-density parity-check (LDPC) ECC component, which can utilize an LDPC ECC scheme to correct errors. The controller 338 can also communicate with the memories 340-1, 340-2, ..., 340-N to sense (e.g., read), program (e.g., write), and / or erase information, and perform other operations. The controller 338 may have circuitry that can be a plurality of integrated circuits and / or discrete components.

[0048] Controller 338 may be contained on the same physical device (e.g., the same die) as the memories 340-1, 340-2, ..., 340-N. For example, controller 338 may be an application-specific integrated circuit (ASIC) coupled to a printed circuit board containing physical host interface 336 and memories 340-1, 340-2, ..., 340-N. Alternatively, controller 338 may be contained on a separate physical device communicatively coupled to the physical devices containing memories 340-1, 340-2, ..., 340-N. In some embodiments, components of controller 338 may be distributed across multiple physical devices as a distributed controller (e.g., some components on the same die as the memories, and some components on different dies, modules, or boards).

[0049] The controller 338 can monitor error correction operations performed by the error correction component 342. For example, the controller 338 can monitor the performance of error correction operations performed by the error correction component 342 on soft data to determine whether the operation is approaching its correction limit, and if so, take appropriate corrective action to prevent future error correction operations from failing.

[0050] For example, controller 338 may determine the number of erroneous soft data points corrected during an error correction operation performed by error correction component 342 on soft data associated with the sensed data state of memory cells 340-1, 340-2, ..., 340-N. The number of erroneous soft data points may correspond to, for example, the number of erroneous soft data bits corrected (e.g., flipped) during the error correction operation, which may be used by controller 338 to determine the bit error rate associated with the error correction operation. For example, as used herein, the bit error rate may refer to the number of erroneous bits corresponding to the amount of erroneous data sensed from memory during the sensing operation divided by the total amount of data sensed during the sensing operation (e.g., the total amount of hard data) (e.g., the sample size). Thus, controller 338 may determine the bit error rate associated with the error correction operation by dividing the number of erroneous bits corrected during the error correction operation performed on the soft data by the total amount of soft data. As an example, in an embodiment where the error correction component 342 is an LDPC ECC component that utilizes the LDPC ECC scheme to perform error correction operations, if the error correction component 342 flips 100 bits in a 10,000-bit codeword, then the bit error rate associated with the error correction operation will be 0.01.

[0051] However, the performance of error correction operations performed on soft data depends not only on the amount of erroneous soft data corrected during the error correction operation, as previously described herein. For example, the performance of error correction operations performed on soft data (e.g., whether the operation might fail) can also depend on the quality of the soft information associated with the erroneous soft data (e.g., indicated by the erroneous soft data). Thus, controller 338 can also determine the quality of the soft information associated with the erroneous soft data corrected during the error correction operation performed on the soft data by error correction component 342.

[0052] The quality of the soft information associated with the corrected error soft data can correspond to, for example, the high reliability error rate associated with the error correction operation. The high reliability error rate associated with the error correction operation can refer to the number of high reliability soft data errors (e.g., error bits) corrected during the error correction operation divided by the total amount of soft data sensed during the sensing operation (e.g., sample size). For example, refer to... Figure 2 High reliability errors can correspond to the left tail portion of Vt distribution 225-2 (e.g., data state L2) less than the reference voltage R1, and the right tail portion of Vt distribution 225-1 (e.g., data state L1) greater than the reference voltage R5. Both cases in this example result in error bits assigned to soft data 00 (which indicates high reliability). Therefore, controller 338 can determine the high reliability error rate by determining the number of erroneous soft data bits that are corrected as high reliability errors during the error correction operation and dividing that number by the total number of soft data bits. Continuing with the previous example, if controller 338 determines that 20 of the 100 error bits toggled by error correction component 342 are high reliability errors, then the high reliability error rate associated with the error correction operation will be 0.002.

[0053] Whether a soft data error is a high-reliability error and therefore the quality of the soft information associated with the erroneous soft data can correspond to the quality and / or reliability information (e.g., level) associated with the sensed data state of the memory cell indicated by the soft data. For example, whether a soft data error is a high-reliability error and therefore the quality of the soft information associated with the erroneous soft data can correspond to the threshold voltage position indicated by the soft data. For example, if the soft data indicates that the threshold voltage associated with the memory cell is located at a level greater than the highest sense voltage that can be used to sense soft data (e.g., greater than...), then... Figure 2 At the voltage of the reference voltage R5 for data state L1 as described in the document, or if the threshold voltage associated with the memory cell for the soft data indication is located below the minimum sensing voltage that can be used to sense the soft data (e.g., less than...). Figure 2 If the reference voltage R1 of data state L2 is specified in the data description, then the soft data error can be classified as a high-reliability error. Therefore, the reference voltage... Figure 2 In the examples described, an error with soft data 00 associated with data state L1 or L2 would be a high-reliability error, while an error with soft data 10 or 11 associated with data state L1 or L2 would not be a high-reliability error. As an additional example, a high-reliability error can be defined as an error that has a voltage that is far removed from the data state used to sense the memory cell (e.g., ...). Figure 2 The reference voltage R3 described herein is a specific voltage amount (e.g., millivolts) of Vt.

[0054] As an additional example, whether a soft data error is a high-reliability error and therefore the quality of the soft data associated with the erroneous soft data can correspond to the probability indicated by the soft data. For instance, if the soft data indicates that the threshold voltage associated with the memory cell has the strongest probability corresponding to the data state of the cell, then the soft data error can be classified as a high-reliability error. Therefore, refer again... Figure 2 In the example described, an error with soft data 00 associated with data state L1 or L2 will again be a high-reliability error because the soft data indicates that the threshold voltage corresponds to the strongest probability of the data state (e.g., stronger than the probability indicated by soft data 10 and 11).

[0055] The controller 338 can then determine whether to take corrective action on the sensed data based on both the quantity and quality of the erroneous soft data corrected during the error correction operation (e.g., whether the operation is approaching its correction limit and may fail). For example, the controller 338 can determine whether to take corrective action based on both the bit error rate and the high reliability error rate associated with the error correction operation. The corrective action can be, for example, the relocation of sensed (e.g., read) data to different locations in memories 340-1, 340-2, ..., 340-N. For example, the data can be programmed into and / or stored in different pages, blocks, or dies of memories 340-1, 340-2, ..., 340-N.

[0056] As an example, controller 338 can plot data points corresponding to the bit error rate and high reliability error rate in a two-dimensional bit error rate versus high reliability error rate space, and determine whether to take a correction action based on the position of the data points in the space. For example, the two-dimensional bit error rate versus high reliability error rate space may contain a curve corresponding to correction constraints (e.g., limitations on the correction capability of error correction component 342) performed on the soft data, and controller 338 can determine whether to take a correction action based on the position of the data point in the space relative to the curve (e.g., based on which side of the curve the data point is on). For example, if the data point is located on the first side of the curve, then controller 338 may take a correction action, and if the data point is located on the second side of the curve, then no correction action may be taken. The curve may be a pre-generated curve provided to controller 338, or the curve may be generated by controller 338 during operation of memory device 334 (e.g., in real time) based on the result of a previous error correction operation performed on the soft data by error correction component 342.

[0057] As an additional example, the two-dimensional bit error rate space for high-reliability error rates may also include several additional curves, each corresponding to a different margin associated with a curve (which corresponds to a correction constraint for error correction operations), and the controller 338 may also determine whether to take a correction action based on the position of the data point relative to the several additional curves. This will be discussed herein (e.g., in conjunction with...) Figure 4 This section further describes an example of this two-dimensional bit error rate space with such curves that can be used to determine whether to take corrective action.

[0058] Figure 3 The embodiments described herein may include additional circuitry, logic, and / or components not described to avoid obscuring the embodiments of the invention. For example, memory device 334 may include address circuitry to latch address signals provided via I / O circuitry through I / O connectors. The address signals may be received and decoded by row decoders and column decoders to access memories 340-1, 340-2, ..., 340-N.

[0059] Figure 4 Examples of two-dimensional bit error rates relative to a high-reliability error rate space 450 according to several embodiments of the present invention are described. For example, in Figure 4 In the example illustrated, the two-dimensional space 450 includes a log-log scale plot, where the bit error rate is on the x-axis and the high reliability error rate is on the y-axis. Therefore, the x-coordinate of a data point plotted in the two-dimensional space 450 will correspond to the bit error rate, and the y-coordinate of a data point plotted in the two-dimensional space 450 will correspond to the high reliability error rate. For example, line 456 illustrates the position where the bit error rate (e.g., x-coordinate) and the high reliability error rate (e.g., y-coordinate) are equal in the two-dimensional space 450.

[0060] Two-dimensional space 450 can (for example) be composed of... Figure 3 The previously described controller 338 is used to monitor the performance of error correction operations performed on soft data, including determining whether the operation is approaching its correction limits and whether correction action should be taken. For example, the controller 338 may plot data points in a two-dimensional space 450 corresponding to determined bit error rates and high reliability error rates associated with error correction operations performed on soft data (e.g., the x-coordinate of the data point would be the bit error rate, and the y-coordinate of the data point would be the high reliability error rate), and may determine whether to take correction action on the sensed data based on the position of the data points in space.

[0061] For example, such as Figure 4 As shown, the two-dimensional space 450 includes a curve 452 extending downward from line 456. Curve 452 may correspond to correction constraints of error correction operations performed on soft data and may be pre-generated or generated in real-time, as previously described herein (e.g., in conjunction with...). Figure 3 In several embodiments, controller 338 may determine whether to take corrective action on the sensed data based on which side of curve 452 the plotted bit error rate-high reliability error rate data point lies on. For example, if the data point is on the right side of curve 452 in two-dimensional space 450, then controller 338 may take corrective action, and if the data point is on the left side of curve 452 in two-dimensional space 450, then no corrective action may be taken. For example, continuing with the previous instance where the bit error rate is determined to be 0.01 and the high reliability error rate is determined to be 0.002, the data point (e.g., 0.01, 0.002) will be on the right side of curve 452, which will cause controller 338 to take corrective action.

[0062] In several embodiments, the two-dimensional space 450 may also include several additional curves extending downward from line 456. For example, in Figure 4 In the embodiment described, the two-dimensional space 450 includes three additional curves 454-1, 454-2, and 454-3. However, embodiments of the invention are not limited to a specific number of additional curves. Each corresponding additional curve may correspond to a different margin associated with curve 452 (e.g., distance from curve 452). For example, in Figure 4 In the embodiments described, curve 454-1 may correspond to a 10% margin from curve 452; curve 454-2 may correspond to a 25% margin from curve 452; and curve 454-3 may correspond to a 50% margin from curve 452. However, embodiments of the invention are not limited to specific margin measures. These margin measures may, for example, increase the protection against unidentified noise sources.

[0063] A curve in a two-dimensional space of 450 can divide the space into several regions. For example, in... Figure 4 In the embodiment described, the two-dimensional space 450 includes region 458-1 to the left of curve 454-3, region 458-2 between curves 454-2 and 454-3, region 458-3 between curves 454-1 and 454-2, region 458-4 between curves 452 and 454-1, and region 458-5 to the right of curve 452. Each region (e.g., a portion of the two-dimensional space 450 contained within each corresponding region) may correspond to a different probability that an error correction operation performed on the soft data will fail (e.g., the error correction operation will be unable to correctly decode errors in the soft data). For example, an error correction operation whose bit error rate - high reliability error rate data point falls in region 458-1 may have a very low probability of failure; an error correction operation whose bit error rate - high reliability error rate data point falls in region 458-2 may have a low probability of failure (e.g., greater than a very low probability); an error correction operation whose bit error rate - high reliability error rate data point falls in region 458-3 may have a moderate probability of failure (e.g., greater than a low probability); an error correction operation whose bit error rate - high reliability error rate data point falls in region 458-4 may have a strong probability of failure (e.g., greater than a moderate probability); and an error correction operation whose bit error rate - high reliability error rate data point falls in region 458-5 may have a very strong probability of failure (e.g., greater than a strong probability).

[0064] In several embodiments, controller 338 may determine whether to take corrective action on the sensed data based on which region the plotted bit error rate - high reliability error rate data point falls into. For example, if the data point falls into region 458-5, controller 338 may take corrective action; if the data point falls into regions 458-4, 458-3, 458-2, or 458-1, controller 338 may not take corrective action. As an additional example, if the data point falls into region 458-5 or 458-4, controller 338 may take corrective action; if the data point falls into regions 458-3, 458-2, or 458-1, controller 338 may not take corrective action. As an additional example, if the data point falls into regions 458-5, 458-4, or 458-3, controller 338 may take corrective action; if the data point falls into regions 458-2 or 458-1, controller 338 may not take corrective action. The controller 338 may determine, for example, which regions the data point needs to fall into, based on the current operating and / or performance level of the memory, so that it can determine to take corrective action. For instance, a higher operating and / or performance level of the memory will result in more regions where corrective action will be taken.

[0065] Figure 5 This describes several embodiments of the invention for operating a memory (e.g., in conjunction with...). Figure 3 Method 560 of the previously described memory (340-1, 340-2, ..., 340-N). Method 560 may be combined with (for example) Figure 3 The previously described controller 338 is executed. Method 560 can be used, for example, to monitor the performance of error correction operations performed on hard and soft data, including determining whether the operation is approaching its correction limit and whether a correction action should be taken.

[0066] At block 562, method 560 includes performing a sensing operation to sense a data state of a memory cell and soft data associated with the sensed data state. In several embodiments, the data state of each corresponding cell and the soft data associated with the data state of each corresponding memory cell may be sensed during the same sensing operation. Multiple sensing voltages may be used to sense the data state and the associated soft data, as previously described herein. For example, multiple sensing voltages may be used. Figure 2 The reference voltages R1 to R5 are used to sense soft data as described in the text.

[0067] At block 564, method 560 includes performing an error correction operation on the sensed data state and / or associated soft data to correct errors therein. Performing error correction on the soft data may include performing an LDPC operation on the soft data, as previously described herein. However, embodiments of the invention are not limited to a particular type of ECC scheme (e.g., other types of ECC schemes may be used to perform the error correction operation).

[0068] At box 556, method 560 includes determining whether the error correction operation was successful (e.g., whether the error correction operation was able to correctly decode errors in the sensed data state and / or soft data). If the error correction operation is determined to be unsuccessful, then at box 568, several recovery schemes (e.g., read-retry recovery scheme, corrected read recovery scheme, and / or independent redundant NAND (RAIN) array recovery scheme) may be performed to attempt to recover the data. If the error correction is determined to be successful, then at box 570, it may be determined whether to perform an error correction operation on the soft data.

[0069] If it is determined that an error correction operation is performed on the soft data, then the bit error rate associated with the error correction operation can be determined at box 572, and the high reliability error rate associated with the error correction operation can be determined at box 574. The bit error rate associated with the error correction operation can be determined, for example, using the number of erroneous soft data bits corrected during the error correction operation (e.g., via an ECC scheme), and the high reliability error rate can be determined, for example, based on the number of soft data errors that are high reliability errors corrected during the error correction operation, as previously described herein.

[0070] At box 576, method 560 includes determining whether to take a correction action on the sensed data. This determination may be based on the bit error rate and high reliability error rate associated with the error correction operation, as previously described herein. For example, this determination may be made by plotting the bit error rate and high reliability error rate in a two-dimensional space 450 having curves 452 and / or 454-1, 454-2, and 454-3, as in conjunction with... Figure 4 As previously described. As an additional example, this determination may be based on a lookup table. For example, this determination may be made by looking up the bit error rate and the high reliability error rate in the lookup table. If it is determined that no corrective action should be taken on the soft data, then no corrective action is taken, and method 560 ends at box 580. If it is determined that corrective action should be taken, then corrective action is taken at box 578. The corrective action may include, for example, repositioning of the sensed data, as previously described herein.

[0071] If it is determined at box 570 that no error correction operation is performed on the soft data (e.g., an error correction operation is performed on the sensed data state), then the bit error rate associated with the error correction operation performed on the sensed data state can be determined at box 582. The bit error rate can refer to the number of erroneous bits corresponding to the amount of erroneous hard data sensed during the sensing operation performed at box 562, divided by the total amount of hard data sensed during the sensing operation (e.g., the sample size). Therefore, the bit error rate associated with the error correction operation is determined by dividing the number of erroneous bits corrected during the error correction operation performed on the sensed data state by the total amount of hard data.

[0072] At block 584, method 560 includes determining whether to take a correction action on the sensed data state (e.g., hard data). This determination may be based on the bit error rate associated with the error correction operation performed at block 564. For example, this determination may be based on whether the bit error rate associated with the error correction operation meets or exceeds a threshold bit error rate. The threshold bit error rate may correspond to a correction limit of the error correction operation (e.g., the amount of error the operation can correct).

[0073] If it is determined that no correction action should be taken based on the sensed data state, then no correction action is taken, and method 560 ends at block 588. If it is determined that a correction action should be taken, then the correction action is taken at block 586. The correction action may include, for example, relocation of data to different locations in memory. For example, data may be programmed into different pages, blocks, or dies of memory and / or stored in said different pages, blocks, or dies.

[0074] While specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This invention is intended to cover adaptations or variations of several embodiments of the invention. It should be understood that the above description has been made in an illustrative rather than restrictive manner. Those skilled in the art will understand, upon reviewing the above description, combinations of the above embodiments not specifically described herein, and other embodiments. The scope of several embodiments of the invention includes other applications in which the above structures and methods are used. Therefore, the scope of several embodiments of the invention should be determined with reference to the appended claims and the full scope of their authorized equivalents.

[0075] In the foregoing embodiments, for the purpose of simplifying the invention, some features are concentrated in a single embodiment. This approach of the invention should not be construed as reflecting an intention that the disclosed embodiments of the invention must use more features than expressly stated in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in all features of fewer than a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the embodiments, wherein each claim is independently considered a separate embodiment.

Claims

1. An apparatus (334) comprising: Memory (340-1, 340-2, ..., 340-N); and The circuit is configured as follows: Determine the bit error rate associated with the error correction operation, and perform the error correction operation on the sensed data state of a plurality of memory cells (111-1, ..., 111-N) of the memory (340-1, 340-2, ..., 340-N) and the soft data associated with the sensed data state; Determine the high reliability error rate associated with the error correction operation; as well as The following methods are used to determine whether to take corrective action on the state of the sensed data: Data points corresponding to the bit error rate and the high reliability error rate are plotted in a two-dimensional bit error rate to high reliability error rate space (450), wherein the two-dimensional bit error rate to high reliability error rate space (450) includes a curve (452) corresponding to the correction constraint of the error correction operation; and Determine the position of the data point relative to the curve (452) in the two-dimensional bit error rate to high reliability error rate space (450).

2. The device of claim 1, wherein the two-dimensional bit error rate to high reliability error rate space includes a plurality of additional curves (454-1, 454-2, 454-3), wherein each corresponding additional curve (454-1, 454-2, 454-3) corresponds to a different margin associated with the curve corresponding to the correction limit of the error correction operation.

3. The device according to claim 2, wherein the plurality of additional curves includes three additional curves.

4. The device according to claim 1, wherein the error correction operation is a successful error correction operation.

5. A method for operating a memory (340-1, 340-2, ..., 340-N), comprising: Determine the bit error rate associated with the error correction operation, and perform the error correction operation on the sensed data state of a plurality of memory cells (111-1, ..., 111-N) and the soft data associated with the sensed data state; Determine the high reliability error rate associated with the error correction operation; as well as The following methods are used to determine whether to take corrective action on the state of the sensed data: Data points corresponding to the bit error rate and the high reliability error rate are plotted in a two-dimensional bit error rate to high reliability error rate space (450), wherein the two-dimensional bit error rate to high reliability error rate space (450) includes a curve (452) corresponding to the correction constraint of the error correction operation; and Determine the position of the data point relative to the curve (452) in the two-dimensional bit error rate to high reliability error rate space (450).

6. The method of claim 5, wherein the method comprises determining whether to take the correction action based on whether the position of the data point in the two-dimensional bit error rate to high reliability error rate space is on the first side of the curve or on the second side of the curve.

7. The method according to claim 5, wherein: The two-dimensional bit error rate includes several additional curves (454-1, 454-2, 454-3) in the high-reliability error rate space, wherein each corresponding additional curve (454-1, 454-2, 454-3) corresponds to a different margin associated with the curve corresponding to the correction limit of the error correction operation; and The method includes determining whether to take the correction action based on the position of the data point in the two-dimensional bit error rate to high reliability error rate space relative to the additional curves (454-1, 454-2, 454-3).

8. The method according to claim 7, wherein: The curve and the additional curves divide the two-dimensional bit error rate into several regions (458-1, 458-2, 458-3, 458-4, 458-5) in the high-reliability error rate space; and The method includes determining whether to take the correction action based on which of the several regions (458-1, 458-2, 458-3, 458-4, 458-5) the location of the data point falls in.

9. The method of claim 8, wherein each corresponding region corresponds to a different probability that the error correction operation performed on the soft data will fail.

10. The method of claim 5, wherein the method comprises: The bit error rate is determined using the controller (338); The controller (338) is used to determine the high reliability error rate; and The controller (338) is used to determine whether to take the corrective action.

11. The method of claim 10, wherein the error correction operation is performed by the error correction component (342) of the controller.

12. An apparatus (334) comprising: Memory (340-1, 340-2, ..., 340-N); and The circuit is configured as follows: The data state of a plurality of memory cells (111-1, ..., 111-N) of the memory (340-1, 340-2, ..., 340-N) and soft data associated with the sensed data state are sensed; Perform error correction operations on the sensed data state and soft data; Determine the bit error rate associated with the error correction operation; Determine the high reliability error rate associated with the error correction operation; and The following methods are used to determine whether to take corrective action on the state of the sensed data: Data points corresponding to the bit error rate and the high reliability error rate are plotted in a two-dimensional bit error rate to high reliability error rate space (450), wherein the two-dimensional bit error rate to high reliability error rate space (450) includes a curve (452) corresponding to the correction constraint of the error correction operation; and Determine the position of the data point relative to the curve (452) in the two-dimensional bit error rate to high reliability error rate space (450).

13. The device of claim 12, wherein the circuitry is configured to: If the position of the data point is on the first side of the curve (452) in the two-dimensional bit error rate versus high reliability error rate space, the correction action is taken; and If the position of the data point is on the second side of the curve (452) in the two-dimensional bit error rate versus high reliability error rate space, no correction action is taken.

14. The device of claim 12, wherein the circuitry is configured to generate the curve based on a previous error correction operation performed on previously sensed data states of the plurality of memory cells and soft data associated with the previously sensed data states.

15. The device according to claim 12, wherein the curve is a pre-generated curve.

16. The device of claim 12, wherein the curve extends downward from the line (456) in the two-dimensional bit error rate versus high reliability error rate space, wherein the bit error rate and the high reliability error rate are equal.

17. The device of claim 12, wherein the two-dimensional bit error rate to high reliability error rate space comprises a log-log scale graph, wherein the log-log scale graph has a bit error rate on the x-axis of the graph and a high reliability error rate on the y-axis of the graph.

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