Semiconductor device and method of manufacturing the same

Abstract

This application relates to semiconductor devices and methods for manufacturing the same. A semiconductor device comprising highly integrated memory cells and a method for manufacturing the same are provided. The semiconductor device includes vertically and horizontally arranged nanosheets; horizontal conductive lines surrounding the horizontally arranged nanosheets; pads coupled to edge portions of the horizontal conductive lines; an inter-pad dielectric layer disposed between the pads; contact plugs, each contact plug coupled to a different pad; and contact spacers, each contact spacer comprising a first low-k material and each contact spacer formed on the sidewall of each contact plug.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0200999, filed on December 30, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure relate to a semiconductor device, and more specifically, to a semiconductor device including a three-dimensional (3D) memory cell and a method of manufacturing the same. Background Technology

[0004] In recent years, there has been a growing demand for larger capacity and smaller size of storage devices. To meet these demands, three-dimensional (3D) storage devices, which include stacked memory cells, have been proposed. Summary of the Invention

[0005] Embodiments of this disclosure relate to semiconductor devices including highly integrated memory cells, and methods of manufacturing such semiconductor devices.

[0006] According to one embodiment of the present disclosure, a semiconductor device may include: vertically and horizontally arranged nanosheets; horizontal wires surrounding the horizontally arranged nanosheets; pads coupled to edge portions of the horizontal wires; an inter-pad dielectric layer disposed between the pads; contact plugs all coupled to different pads; and contact spacers, each contact spacer comprising a first low-k material and each contact spacer formed on the sidewall of each contact plug.

[0007] According to one embodiment of this disclosure, a semiconductor device may include: vertically and horizontally arranged nanosheets; horizontal conductors surrounding the horizontally arranged nanosheets; a stepless structure including horizontally oriented pads coupled to edge portions of the horizontal conductors and a low-k inter-pad dielectric layer formed between the horizontally oriented pads; vertically oriented contact plugs, each contact plug coupled to a different horizontally oriented pad; and low-k spacers surrounding the outer walls of each contact plug.

[0008] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device may include: forming an alternating stack of sacrificial wafers and inter-pad dielectric layers on a substrate; forming a contact hole, the height of which gradually decreases in the stacking direction of the alternating stacked sacrificial wafers and inter-pad dielectric layers; forming a low-k spacer on the sidewall of the contact hole; forming sacrificial plugs, each sacrificial plug filling a different contact hole on the low-k spacer; removing the alternating stacked sacrificial wafers and forming a pad-shaped opening; forming a pad that fills the pad-shaped opening; removing the sacrificial plugs and forming a plug opening; cutting a portion of the low-k spacer through the plug opening and exposing the pad; and forming a contact plug that fills the plug opening and is coupled to the pad.

[0009] According to one embodiment of the present disclosure, a semiconductor device may include: a substrate; a cell array region including a plurality of horizontal wires stacked vertically on the substrate in a first direction; a connection region including pads and a low-k pad dielectric layer alternately stacked in the first direction; each contact plug coupled to a different pad; and a low-k spacer formed on the sidewall of each contact plug. Attached Figure Description

[0010] Figure 1A This is a schematic perspective view showing a storage unit according to an embodiment of the present disclosure.

[0011] Figure 1B yes Figure 1A A schematic cross-sectional view of the storage cell shown.

[0012] Figure 2A This is a schematic perspective view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 2B This is a partial perspective view showing the first spacer.

[0014] Figure 2C This is a partial perspective view showing the second spacer.

[0015] Figure 3 This is a schematic perspective view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 4A This is a schematic perspective view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 4B yes Figure 4A A schematic plan view of the semiconductor device shown.

[0018] Figure 4C It is the edge of semiconductor devices Figure 4B The diagram shows a schematic cross-section taken by line A-A'.

[0019] Figure 4D It is the edge of semiconductor devices Figure 4B The diagram shows a schematic cross-section taken by line B-B'.

[0020] Figure 4E It is the edge of semiconductor devices Figure 4B The cross-sectional view taken by line B1-B1' is shown.

[0021] Figures 5A to 34B Various views of a semiconductor device formed using a method for manufacturing a semiconductor device according to an embodiment of the present disclosure are shown.

[0022] Figure 35 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0023] Figure 36 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0024] Figure 37 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0025] Figure 38 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0026] Figure 39A and Figure 39B This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0027] Figure 40A and Figure 40B Various views of a stacked component according to one embodiment of the present disclosure are shown. Detailed Implementation

[0028] The embodiments of this disclosure can be described with reference to cross-sectional views, plan views, and block diagrams, which are ideal schematic diagrams of semiconductor devices. It should be noted that the structures in the drawings may be modified due to manufacturing processes and / or tolerances. The embodiments of this disclosure are not limited to the specific structures shown in the described embodiments and drawings, but may include other embodiments or modifications to the described embodiments, including any structural changes resulting from manufacturing process requirements. Therefore, the areas shown in the drawings are schematic, and the shapes of the areas shown in the drawings are intended to illustrate specific structures of element regions and are not intended to limit the scope of this disclosure.

[0029] The following embodiments relate to three-dimensional storage cells, wherein the storage cells are vertically stacked to increase storage cell density and reduce parasitic capacitance.

[0030] Figure 1A This is a schematic perspective view showing a storage unit MC according to an embodiment of the present disclosure. Figure 1B yes Figure 1A The diagram shows a schematic cross-sectional view of the storage cell MC.

[0031] refer to Figure 1A and Figure 1B The storage unit MC may include a first wire BL, a switching element TR, and a data storage element CAP.

[0032] The first conductor BL may be oriented perpendicularly to a first direction D1. The first conductor BL may include a bit line. The first conductor BL may be referred to as a "vertical conductor," "vertically oriented bit line," "vertically extended bit line," or "pillar bit line." The first conductor BL may contain a conductive material. The first conductor BL may contain a silicon-based material, a metal-based material, or a combination thereof. The first conductor BL may contain polycrystalline silicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first conductor BL may contain polycrystalline silicon, titanium nitride, tungsten, or a combination thereof. For example, the first conductor BL may contain a titanium nitride / tungsten (TiN / W) stack in which titanium nitride and tungsten are stacked sequentially.

[0033] A switching element TR has the function of controlling the voltage or current supplied to a data storage element CAP during data write and read operations. The switching element TR may include a nanosheet HL, a nanosheet dielectric layer GD, and a second conductor WL. The second conductor WL may include a horizontal conductor (e.g., horizontally oriented) or a horizontal word line, and the nanosheet HL may include an active layer. The switching element TR may include a transistor, in which case the second conductor WL may serve as a gate or gate electrode. The switching element TR may also be referred to as a "nanosheet transistor," an "access element," or a "select element." The second conductor WL may be referred to as a "horizontal gate electrode" or a "horizontal word line."

[0034] The nanosheet HL may extend along a second direction D2 intersecting the first direction D1. The second conductor WL may extend horizontally along a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 may be a vertical direction, the second direction D2 may be a first horizontal direction, and the third direction D3 may be a second horizontal direction (e.g., perpendicular to the first horizontal direction). The nanosheet HL may extend along the first horizontal direction (i.e., the second direction D2), and the second conductor WL may extend along the second horizontal direction (i.e., the third direction D3). The nanosheet HL may be referred to as a "horizontal layer" or a "channel body".

[0035] The nanosheet HL may include a channel CH, a first doped region SR between the channel CH and a first conductive line BL, and a second doped region DR between the channel CH and a data storage element CAP. The first doped region SR may be electrically coupled to the first conductive line BL, and the second doped region DR may be electrically coupled to the data storage element CAP. The height of the second doped region DR in the first direction D1 may be greater than the height of the channel CH in the first direction D1. The length of the second doped region DR in the second direction D2 may be less than the length of the channel CH in the second direction D2. The lengths of the first doped region SR, the channel CH, and the second doped region DR in the third direction D3 may be equal to each other.

[0036] The nanosheet HL may include a first region NS and a second region WS horizontally disposed along a second direction D2. The second region WS may extend from the first region NS. The second region WS may have a thickness that gradually increases from the first region NS to the data storage element CAP along the second direction D2. The average vertical height or thickness of the second region WS in the first direction D1 may be greater than the average vertical height or thickness of the first region NS. Hereinafter, the first region NS will be referred to as a "narrow wafer", and the second region WS will be referred to as a "wide wafer".

[0037] Narrow sheet (NS) can have a flat plate shape. Wide sheet (WS) can have a fan-shaped shape. Wide sheet (WS) can have a thickness that gradually increases along the second direction D2. Narrow sheet (NS) can be called a "flat plate", and wide sheet (WS) can be called a "fan-shaped (or fan-shaped, conical, etc.) plate". Both the upper and lower surfaces of wide sheet (WS) can have curvature.

[0038] The first doped region SR and the channel CH can be disposed in a narrow wafer NS, while the second doped region DR can be disposed in a wide wafer WS. The channel CH formed in the narrow wafer NS can be referred to as a "narrow channel" or a "flat channel". A portion of the second doped region DR can extend to be disposed in the narrow wafer NS. The second doped region DR may include a thick portion disposed in the wide wafer WS and a thin portion disposed in the narrow wafer NS. One side of the wide wafer WS and one side of the second doped region DR (in contact with the data storage element CAP) can both have a flat side profile.

[0039] The horizontal length of the wide slice WS in the second direction D2 can be less than the horizontal length of the narrow slice NS. The narrow slice NS can be called the "long slice", and the wide slice WS can be called the "short slice".

[0040] The nanosheet HL may comprise a semiconductor material. For example, the nanosheet HL may comprise polycrystalline silicon, monocrystalline silicon, germanium, or silicon-germanium. In some embodiments, the nanosheet HL may comprise an oxide semiconductor material. For example, the oxide semiconductor material may comprise indium gallium zinc oxide (IGZO), InSnZnO (commonly referred to as indium tin zinc oxide (ITZO)), zinc stannate (ZnSnO), or combinations thereof. In some embodiments, the nanosheet HL may comprise a conductive metal oxide.

[0041] In some embodiments, the nanosheet HL may comprise a two-dimensional material or a two-dimensional semiconductor material. A two-dimensional semiconductor material can refer to a semiconductor material with a layered structure, whose constituent atoms are bonded in a two-dimensional manner. Two-dimensional materials exhibit excellent electrical properties; even when the thickness of the two-dimensional material is reduced to the nanometer scale, the two-dimensional semiconductor material can maintain high mobility without significantly altering its properties. For example, the nanosheet HL may comprise molybdenum disulfide (MoS2), tungsten disulfide (WS2), or molybdenum diselenide (MoSe2).

[0042] When the nanosheet HL is formed from an oxide semiconductor material, the channel CH can also be formed from an oxide semiconductor material, and the first doped region SR and the second doped region DR can be omitted. The nanosheet HL can also be called an "active layer" or a "thin body".

[0043] The first doped region SR and the second doped region DR can be doped with impurities of the same conductivity type. Both the first doped region SR and the second doped region DR can be doped with either N-type or P-type conductive impurities. For example, conductive impurities may include arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doped region SR can be electrically coupled to the first conductive line BL, and the second doped region DR can be electrically coupled to the data storage element CAP. The first doped region SR and the second doped region DR can be referred to as the "first source / drain region and the second source / drain region".

[0044] The nanosheet HL can be horizontally oriented from the first conductor BL along the second direction D2.

[0045] The second conductor WL may have a gate-all-around (GAA) structure. For example, the second conductor WL may surround the nanosheet HL and extend along a third direction D3. A nanosheet dielectric layer GD may be formed between the nanosheet HL and the second conductor WL. The nanosheet dielectric layer GD may surround the nanosheet HL. The second conductor WL may surround the nanosheet HL on the nanosheet dielectric layer GD.

[0046] The second conductive line WL may comprise a metallic material, a metal-based material, a semiconductor material, or a combination thereof. The second conductive line WL may comprise molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polycrystalline silicon, or a combination thereof. For example, the second conductive line WL may comprise a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The second conductive line WL may comprise an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or lower, while the P-type work function material may have a high work function of about 4.5 eV or higher. The second conductive line WL may comprise a stack of low work function materials and high work function materials.

[0047] A nanosheet dielectric layer (GD) can be disposed between the nanosheet HL and the second conductive line WL. The nanosheet dielectric layer GD can be referred to as a "gate dielectric layer" or a "channel-side dielectric layer." The nanosheet dielectric layer GD can comprise silicon oxide, silicon nitride, metal oxides, metal oxynitrides, metal silicates, high-k materials, ferroelectric materials, antiferroelectric materials, or combinations thereof. Specifically, the nanosheet dielectric layer GD can comprise silicon oxide (SiO2), silicon nitride (Si3N4), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), aluminum oxynitride (AlON), hafnium oxynitride (HfON), hafnium silicate (HfSiO), hafnium oxysilane (HfSiON), hafnium zirconium oxide (HfZrO), or combinations thereof. The nanosheet dielectric layer GD can be formed through thermal oxidation of semiconductor materials. Alternatively, it can be formed through a combination of deposition of nanosheet dielectric materials and oxidation of semiconductor materials.

[0048] The data storage element CAP may include a storage element such as a capacitor. The data storage element CAP may be horizontally disposed from the switching element TR along a second direction D2. The data storage element CAP may include a first electrode SN, a second electrode PN on the first electrode SN, and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN may extend horizontally from the nanosheet HL along the second direction D2. The first electrode SN, the dielectric layer DE, and the second electrode PN may be horizontally disposed along the second direction D2. The first electrode SN may include an internal space and multiple outer surfaces, and the internal space of the first electrode SN may include multiple inner surfaces. The outer surfaces of the first electrode SN may include a vertical outer surface and multiple horizontal outer surfaces. The vertical outer surface of the first electrode SN may extend vertically along a first direction D1, and the horizontal outer surfaces of the first electrode SN may extend horizontally along a second direction D2 or a third direction D3. The internal space of the first electrode SN may be three-dimensional. The dielectric layer DE may conformally cover the inner surface of the first electrode SN. The second electrode PN may be disposed in the internal space of the first electrode SN, on the dielectric layer DE. Some outer surfaces of the first electrode SN may be electrically coupled to a second doped region DR of the nanosheet HL. The second electrode PN of the data storage element CAP can be coupled to the common electrode PL.

[0049] The data storage element CAP can have a three-dimensional structure. The first electrode SN can also have a three-dimensional structure, which may be a horizontal three-dimensional structure oriented along a second direction D2. In an example of a three-dimensional structure, the first electrode SN can be cylindrical. The cylindrical shape of the first electrode SN may include an inner cylindrical surface and an outer cylindrical surface. Some of the outer cylindrical surfaces of the first electrode SN can be electrically coupled to a second doped region DR of the nanosheet HL. A dielectric layer DE and a second electrode PN can be disposed on the inner and outer cylindrical surfaces of the first electrode SN.

[0050] In some embodiments, the first electrode SN may be columnar or cylindrical. Cylindrical may refer to a structure combining columnar and cylindrical shapes.

[0051] The first electrode SN and the second electrode PN may comprise metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the first electrode SN and the second electrode PN may comprise titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum nitride (MoN), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, titanium nitride / silicon titanium nitride (TiN / TiSiN) stacks, titanium silicon nitride / titanium nitride / tungsten (TiSiN / TiN / W) stacks, or combinations thereof. The second electrode PN may also comprise a combination of metal-based materials and silicon-based materials. For example, the second electrode PN can be a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack. In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium can be an interstitial filling material that fills the interior of the first electrode SN, titanium nitride (TiN) can be used as the second electrode PN of the data storage element CAP, and tungsten nitride can be a low-resistance material.

[0052] The dielectric layer DE can be referred to as a "capacitor dielectric layer" or a "storage layer". The dielectric layer DE may comprise silicon oxide, silicon nitride, high-k materials, perovskite materials, or combinations thereof. High-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or titanium strontium oxide (SrTiO3). In some embodiments, the dielectric layer DE may be formed from a composite layer comprising two or more layers of the aforementioned high-k materials.

[0053] The dielectric layer (DE) can be formed from (Zr)-based oxides. The dielectric layer (DE) can have a stacked structure containing zirconium oxide (ZrO2). The dielectric layer (DE) can contain a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can have a structure where alumina (Al2O3) is stacked on top of zirconium oxide (ZrO2). The ZAZ stack can have a structure where zirconium oxide (ZrO2), alumina (Al2O3), and zirconium oxide (ZrO2) are stacked sequentially. Both ZA and ZAZ stacks can be referred to as a "zirconia (ZrO2) base layer".

[0054] In some embodiments, the dielectric layer DE may be formed of a hafnium (Hf)-based oxide. The dielectric layer DE may have a stacked structure comprising hafnium oxide (HfO2). The dielectric layer DE may comprise an HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack may have a structure in which alumina (Al2O3) is stacked on top of hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), alumina (Al2O3), and hafnium oxide (HfO2) are stacked sequentially. Both the HA stack and the HAH stack can be referred to as a "hafnium oxide (HfO2) base layer". In the ZA stack, ZAZ stack, HA stack, and HAH stack, the band gap energy of alumina (Al2O3) may be greater than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). The dielectric constant of alumina (Al₂O₃) can be lower than that of zirconium oxide (ZrO₂) and hafnium oxide (HfO₂). Therefore, the dielectric layer DE can consist of a stack of high-k materials and high-bandgap materials with bandgap energies greater than those of the high-k materials. The dielectric layer DE can also include silicon oxide (SiO₂) as a high-bandgap material other than alumina (Al₂O₃). Because the dielectric layer DE contains high-bandgap materials, leakage current can be suppressed. The high-bandgap materials can be thinner than the high-k materials.

[0055] In some embodiments, the dielectric layer DE may comprise a stacked structure of alternating high-k materials and high-bandgap materials. For example, the dielectric layer DE may comprise ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stacks, ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stacks, HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stacks, HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stacks, HZAZH (HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2) stacks, and ZHZAZHZ (ZrO2 / HfO2 / ZrO2 / Al2O3) stacks. The stacked structures can be 3 / ZrO2 / HfO2 / ZrO2), HZHZ (HfO2 / ZrO2 / HfO2 / ZrO2), AHZAZHA (Al2O3 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / Al2O3), AHZAHZA (Al2O3 / HfO2 / ZrO2 / Al2O3 / HfO2 / ZrO2 / Al2O3), or ZHZAZHZAT (ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2). In these stacked structures, alumina (Al2O3) can be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0056] In some embodiments, the dielectric layer DE may comprise a high-k material and a high-bandgap material. The dielectric layer DE may have a laminated structure composed of multiple high-k materials and multiple high-bandgap materials stacked together, or a hybrid structure composed of a mixture of high-k materials and high-bandgap materials.

[0057] In some embodiments, the dielectric layer DE may comprise a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may comprise HfZrO.

[0058] In some embodiments, the dielectric layer DE may comprise a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, or a combination of a high-k material or a ferroelectric material and an antiferroelectric material.

[0059] In some embodiments, the data storage element CAP may further include multiple interface control layers to mitigate leakage current. Each interface control layer may comprise titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), niobium oxynitride (NbON), or a combination thereof. The data storage element CAP may include a first interface control layer, a second interface control layer, or a combination thereof. The first and second interface control layers may be conductive or dielectric. The first interface control layer may be formed between the first electrode SN and the dielectric layer DE, and the second interface control layer may be formed between the dielectric layer DE and the second electrode PN. The first and second interface control layers may be made of the same material or different materials. For example, the structure of the data storage element CAP, in which the first interface control layer, the dielectric layer DE, and the second interface control layer are stacked sequentially, may comprise an NZHZAZHZATN (Nb2O5 / ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2 / Nb2O5) stack.

[0060] Data storage element CAP may include a three-dimensional capacitor. Data storage element CAP may include a metal-insulator-metal (MIM) capacitor. Data storage element CAP may be replaced with other data storage materials. For example, data storage materials may be thyristors, phase change materials, magnetic tunnel junctions (MTJs), or variable resistance materials.

[0061] The memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may be disposed between the first conductor BL and the nanosheet HL. The first contact node BLC may contain a metal-based material or a semiconductor material. For example, the first contact node BLC may contain titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the first contact node BLC may contain doped polycrystalline silicon, and the first doped region SR may contain impurities diffused from the first contact node BLC. The second contact node SNC may be disposed between the nanosheet HL and the first electrode SN. The second contact node SNC may contain a metal-based material or a semiconductor material. For example, the second contact node SNC may contain titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the second contact node SNC may contain doped silicon, and the second doped region DR may contain impurities diffused from the second contact node SNC. The height of the first contact node BLC in the first direction D1 may be less than the height of the second contact node SNC in the first direction D1. The height of the first contact node BLC in the first direction D1 may be greater than the height of the channel CH in the first direction D1. Both the first contact node (BLC) and the second contact node (SNC) can contain phosphorus-doped polysilicon or arsenic-doped polysilicon.

[0062] In some embodiments, the second contact node SNC can be selectively grown from a wide sheet WS of the nanosheet HL. The second contact node SNC can be formed by selective epitaxial growth (SEG). For example, the second contact node SNC can be a silicon epitaxial layer formed by SEG. The second contact node SNC can be a doped silicon epitaxial layer.

[0063] In some embodiments, the first contact node BLC may also be selectively grown from the narrow NS of the nanosheet HL. The first contact node BLC can be formed by selective epitaxial growth (SEG). For example, the first contact node BLC can be a silicon epitaxial layer formed by SEG. The first contact node BLC can be a doped silicon epitaxial layer.

[0064] The first contact node BLC can be a narrow-side contact node, while the second contact node SNC can be a wide-side contact node.

[0065] The nanosheet HL may include a first edge and a second edge. The first edge may refer to the portion of the first doped region SR that is electrically coupled to the first wire BL, while the second edge may refer to the portion of the second doped region DR that is electrically coupled to the first electrode SN of the data storage element CAP.

[0066] The memory cell MC may also include an ohmic contact layer BLO between the first contact node BLC and the first conductor BL. The ohmic contact layer BLO may contain a metal silicide such as titanium silicide or molybdenum silicide.

[0067] The memory cell MC may further include a first spacer SP1 and a second spacer SP2. The first spacer SP1 may be disposed between the second conductor WL and the second doped region DR. The second spacer SP2 may be disposed between the first conductor BL and the second conductor WL. Both the first spacer SP1 and the second spacer SP2 may contain a dielectric material. Both the first spacer SP1 and the second spacer SP2 may contain silicon oxide, silicon nitride, or a combination thereof. The first spacer SP1 may contain silicon nitride. The second spacer SP2 may be a stack of silicon nitride and silicon oxide. The first spacer SP1 and the second spacer SP2 may be disposed on two sidewalls of the second conductor WL. That is, the first spacer SP1 and the second spacer SP2 may extend along a third direction D3. The first spacer SP1 may surround the second doped region DR of the nanosheet HL, and the second spacer SP2 may surround the first doped region SR of the nanosheet HL. The second spacer SP2 may include a stack of a first pad L1 and a second pad L2. The first pad L1 of the second spacer SP2 may be silicon nitride, and the second pad L2 may be silicon oxide. The second pad L2 can partially fill the internal space of the first pad L1.

[0068] The first conductor BL may include multiple horizontal extensions BLE1, BLE2, and BLE3. The horizontal extensions BLE1, BLE2, and BLE3 may extend along a second direction D2. The horizontal extensions may include an inner horizontal extension BLE2 and outer horizontal extensions BLE1 and BLE3. The inner horizontal extension BLE2 of the first conductor BL may extend to be disposed in the gap between first pads L1 that are adjacent to each other in the vertical direction. Therefore, the inner horizontal extension BLE2 of the first conductor BL may be electrically coupled to the ohmic contact layer BLO.

[0069] The outer horizontal extensions BLE1 and BLE3 of the first conductor BL can extend to be disposed within one side of the second spacer SP2. Therefore, the outer horizontal extensions BLE1 and BLE3 of the first conductor BL can contact the second pad L2 of the second spacer SP2.

[0070] Figure 2A This is a schematic diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 2B This is a partial perspective view showing the first spacer SP1. Figure 2C This is a partial perspective view showing the second spacer SP2.

[0071] Figure 2A A horizontal array HMCA is shown, which has multiple references therein. Figure 1A and Figure 1B The storage unit MC is arranged along the third direction D3.

[0072] refer to Figure 1A , Figure 1Band Figure 2A A horizontal array HMCA may include horizontally arranged memory cells MC. The memory cells MC of the horizontal array HMCA may be horizontally spaced along the third direction D3. Each memory cell MC of the horizontal array HMCA may be coupled to a different first conductor BL. The memory cells MC of the horizontal array HMCA may share a second conductor WL. Each memory cell MC may include a first conductor BL, a nanosheet HL, and a data storage element CAP. The nanosheet HL may include a first doped region SR, a channel CH, and a second doped region DR. A first contact node BLC and an ohmic contact layer BLO may be formed between the first doped region SR and the first conductor BL of the nanosheet HL. A second contact node SNC may be formed between the second doped region DR of the nanosheet HL and the data storage element CAP. The nanosheet HL may be surrounded by a nanosheet dielectric layer GD. The second conductor WL may extend along the third direction D3 and surround the channel CH of the nanosheet HL on the nanosheet dielectric layer GD.

[0073] The horizontal array HMCA may also include the references mentioned above. Figure 1B The first spacer SP1 and the second spacer SP2.

[0074] Refer again Figure 2B The first spacer SP1 may have an integral structure extending along a first direction D1. The first spacer SP1 may surround a portion of the nanosheet HL, i.e., the second doped region DR of the nanosheet HL disposed at the same horizontal level. A portion of the first spacer SP1 may be disposed between the nanosheets HL, thus the first spacer SP1 may extend perpendicularly along the first direction D1. The cross-section of the first spacer SP1 may have a cup shape.

[0075] Refer again Figure 2C The second spacer SP2 may extend on the third direction D3 and surround a portion of the nanosheet HL, namely the first doped region SR of the nanosheet HL set at the same horizontal level.

[0076] Figure 3 This is a schematic perspective view of a semiconductor device 100V according to an embodiment of the present disclosure. Figure 3 The semiconductor device 100V shown may include Figure 2A The diagram shows a horizontal array of HMCA arrays stacked vertically along the first direction D1. (See above for reference.) Figures 1A to 2C Overlapping components (e.g., those previously discussed) are described in detail.

[0077] refer to Figure 3Semiconductor device 100V may include a vertically stacked horizontal array HMCA. Semiconductor device 100V may include a plurality of horizontally arranged first conductors BL and a plurality of vertically arranged second conductors WL. Vertically arranged memory cells MC stacked along a first direction D1 may share a single first conductor BL. Horizontally arranged memory cells MC arranged along a third direction D1 may be coupled to different first conductors BL.

[0078] Horizontally arranged memory cells MC along the third direction D3 can share a single second conductor WL. Vertically arranged memory cells MC stacked along the first direction D1 can be coupled to different second conductors WL.

[0079] Figure 4A This is a schematic perspective view showing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 4B yes Figure 4A A schematic plan view of the semiconductor device 100 shown. Figure 4C It is the edge of semiconductor device 100 Figure 4B The diagram shows a schematic cross-section taken by line A-A'. Figure 4D It is the edge of semiconductor device 100 Figure 4B The schematic cross-sectional view shown is taken by line B-B'. Figure 4E It is the edge of semiconductor device 100 Figure 4B The cross-sectional view shown is taken along line B1-B1'. (As mentioned above...) Figures 1A to 3 The overlapping components are described in detail.

[0080] refer to Figures 4A to 4E The semiconductor device 100 may include a memory cell array (MCA). The memory cell array (MCA) may include a three-dimensional array of memory cells (MC). (See above for reference.) Figure 1A and Figure 1B The memory cell MC is described in detail. The memory cell array MCA can be mounted on the lower structure LS.

[0081] The memory cell array (MCA) may include a first region R1 and a second region R2. The first region R1 may be a region forming a three-dimensional array of memory cells (MCs), and the second region R2 may be a region forming pads WP and contact plugs CT that are coupled to second conductors WL of the memory cells (MCs). The first region R1 may be referred to as the "array region," and the second region R2 may be referred to as the "pad region" or "connection region." The first region R1 may include a vertical stack of memory cells (MCs), and the second region R2 may include a vertical stack of pads WP. The second region R2 may be referred to as a "shared connection region," "shared contact region," or "common contact region."

[0082] The lower structure (LS) can be positioned at a level lower than the memory cell array (MCA). The lower structure (LS) can be made of materials suitable for semiconductor fabrication. The lower structure (LS) may include a semiconductor substrate, a conductive material, a dielectric material, a semiconductor material, or a combination thereof. The lower structure (LS) may contain silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, epitaxial silicon, combinations thereof, or multiple layers thereof. The lower structure (LS) may also contain other semiconductor materials, such as germanium. The lower structure (LS) may also contain a III-V group semiconductor substrate, such as a compound semiconductor substrate like GaAs.

[0083] In some embodiments, the lower structure LS may include a metal wiring structure, a dielectric structure, a conductive structure, a bonding pad structure, and another memory or peripheral circuit portion. For example, the lower structure LS may include a structure in which peripheral circuit portions, metal wiring structures, and bonding pad structures are stacked sequentially. The memory cell array MCA and the peripheral circuit portion of the lower structure LS may be bonded by wafer bonding. Wafer bonding may include pad bonding, hybrid bonding, oxide-oxide bonding, metal-metal bonding, or combinations thereof.

[0084] Each memory cell MC may include a first conductor BL, a switching element TR, and a data storage element CAP. The switching element TR may include a second conductor WL, a nanosheet dielectric layer GD, and a nanosheet HL.

[0085] Semiconductor device 100 may include a column array AR1 of memory cells MC and a row array AR2 of memory cells MC. Column array AR1 may include a plurality of memory cells MC vertically stacked along a first direction D1. The memory cells MC in column array AR1 may share a first conductor BL. Row array AR2 may include a plurality of memory cells MC horizontally arranged along a third direction D3. The memory cells MC in row array AR2 may share a second conductor WL. The first direction D1 may be vertical, and the third direction D3 may be horizontal.

[0086] Semiconductor device 100 may include a plurality of horizontally arranged first conductors BL and a plurality of vertically arranged second conductors WL. Vertically arranged memory cells MC stacked along a first direction D1 may share a single first conductor BL. Horizontally arranged memory cells MC arranged along a third direction D3 may share a single first conductor BL. Horizontally arranged memory cells MC arranged along a third direction D3 may share a single second conductor WL. Vertically arranged memory cells MC stacked along the first direction D1 may be coupled to different second conductors WL.

[0087] Semiconductor device 100 may include a first sub-cell array MCA1 and a second sub-cell array MCA2. Both the first sub-cell array MCA1 and the second sub-cell array MCA2 may include a three-dimensional array of memory cells MC. The first sub-cell array MCA1 and the second sub-cell array MCA2 may share a first conductor BL. The first conductor BL may include a first vertical conductor BLA and a second vertical conductor BLB. The bottom of the first vertical conductor BLA and the bottom of the second vertical conductor BLB may be merged together. The first conductor BL may have a U-shape formed by merging the first vertical conductor BLA and the second vertical conductor BLB. The memory cells MC of the first sub-cell array MCA1 may share the first vertical conductor BLA, and the memory cells MC of the second sub-cell array MCA2 may share the second vertical conductor BLB. Thus, the first sub-cell array MCA1 and the second sub-cell array MCA2, which are adjacent to each other in the second direction D2, may have a mirror structure sharing the first conductor BL. From a top view, both the first vertical conductor BLA and the second vertical conductor BLB may have a rectangular shape.

[0088] The first inter-cell dielectric layer IL1 can be disposed between adjacent data storage elements CAP on the third direction D3. The second inter-cell dielectric layer IL2 can be disposed between second conductors WL stacked vertically on the first direction D1. The third inter-cell dielectric layer IL3 can be disposed between the first electrodes SN of the data storage elements CAP stacked vertically on the first direction D1. The first to third inter-cell dielectric layers IL1, IL2 and IL3 can all contain silicon oxide, silicon oxycarbide (SiCO), silicon nitride or a combination thereof. The first inter-cell dielectric layer IL1 can be referred to as a "device isolation layer".

[0089] The memory cell array (MCA) may further include a first contact node (BLC) and a second contact node (SNC). The first contact node (BLC) may be disposed between the first vertical conductor (BLA) and the second vertical conductor (BLB) and the nanosheet (HL). The first contact node (BLC) may contain a metal-based material or a semiconductor material. For example, the first contact node (BLC) may contain titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the first contact node (BLC) may contain doped polysilicon, and the first doped region (SR) may contain impurities diffused from the first contact node (BLC). The second contact node (SNC) may be disposed between the nanosheet (HL) and the first electrode (SN). The second contact node (SNC) may contain a metal-based material or a semiconductor material. For example, the second contact node (SNC) may contain titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the second contact node (SNC) may contain doped polysilicon, and the second doped region (DR) may contain impurities diffused from the second contact node (SNC). The height of the first contact node (BLC) in the first direction (D1) may be less than the height of the second contact node (SNC) in the first direction (D1). The height of the first contact node (BLC) in the first direction (D1) may be greater than the height of the channel (CH) in the first direction (D1). Both the first contact node (BLC) and the second contact node (SNC) can contain doped polysilicon, such as phosphorus-doped polysilicon or arsenic-doped polysilicon.

[0090] The memory cell array MCA may also include an ohmic contact layer between the first contact node BLC and the first conductor BL (see reference). Figure 1A and Figure 1B (Referring to the reference numeral "BLO" in the attached diagram). The ohmic contact layer may contain metal silicides, such as titanium silicide or molybdenum silicide.

[0091] The memory cell array (MCA) may further include a first spacer SP1 and a second spacer SP2. The first spacer SP1 may be disposed between the second conductor WL and the second doped region DR. The second spacer SP2 may be disposed between the first conductor BL and the second conductor WL. Both the first spacer SP1 and the second spacer SP2 may contain a dielectric material. Both the first spacer SP1 and the second spacer SP2 may contain silicon oxide, silicon nitride, or a combination thereof. (See above reference) Figure 2B and Figure 2C The first spacer SP1 and the second spacer SP2 may extend along a third direction D3 on the two sidewalls of the second conductor WL. The first spacer SP1 and the second spacer SP2 may surround the horizontally arranged nanosheets HL along the third direction D3. In addition, the first spacer SP1 may extend perpendicularly along a first direction D1.

[0092] The memory cell array MCA may include a plurality of second conductors WL stacked vertically along a first direction D1. The memory cell array MCA may include a plurality of nanosheets HL stacked vertically along the first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP stacked vertically along the first direction D1. The memory cell array MCA may include a plurality of first conductors BL spaced apart along a third direction D3. The memory cell array MCA may include dummy second conductors WLU disposed at a level above the uppermost second conductor WL and dummy second conductors WLL disposed at a level below the lowermost second conductor WL. Both the dummy second conductors WLU and WLL may have a horizontally extending linear shape.

[0093] The memory cell array (MCA) may include a stack of multiple hard mask layers HM1, HM2, HM3, and HM4 disposed at a level above the topmost dummy second conductor WLU.

[0094] The memory cell array (MCA) may include multiple first bottom protective layers BT1 and second bottom protective layers BT2. The first bottom protective layer BT1 prevents the first conductor BL from making electrical contact with the underlying structure LS. The second bottom protective layer BT2 prevents the data storage element CAP from making electrical contact with the underlying structure LS. Both the first bottom protective layer BT1 and the second bottom protective layer BT2 may contain dielectric material.

[0095] An array isolation layer BLF may be disposed between the first vertical conductor BLA and the second vertical conductor BLB of the first conductor BL. The array isolation layer BLF may contain a dielectric material. For example, the array isolation layer BLF may contain silicon oxide, silicon nitride, gap-intercalated silicon oxide, or a combination thereof.

[0096] Nanosheets HL of a switching element TR arranged horizontally along the third direction D3 can share a second conductor WL. Nanosheets HL of a switching element TR arranged horizontally along the third direction D3 can be coupled to different first conductors BL. Switching elements TR stacked along the first direction D1 can share a first conductor BL. Switching elements TR arranged horizontally along the third direction D3 can share a second conductor WL.

[0097] The second electrode PN of the data storage element CAP can be coupled to the common plate PL. The second electrodes PN of the data storage element CAP can be merged together to form the common plate PL.

[0098] Refer again Figure 4A , 4BThe second conductors WL of the memory cell array MCA (4D and 4E) can be coupled to pads WP1 to WP4, respectively. Pads WP1 to WP4 can all be horizontally oriented. Each second conductor WL may include a different edge portion WE, each edge portion WE having a concave shape. Pads WP1 to WP4 can all include a different inner edge PE. The inner edge PE of pads WP1 to WP4 can all have a convex shape. The inner edge PE of pads WP1 to WP4 can be disposed within the internal space of the edge portion WE of the second conductor WL. The inner edge PE of pads WP1 to WP4 can be electrically coupled to the edge portion WE of the second conductor WL. The inner edge PE of pads WP1 to WP4 and the edge portion WE of the second conductor WL can contact the first spacer SP1.

[0099] The second region R2 may include alternating stacks of pads WP1 to WP4 and inter-pad dielectric layers P1L, and contact plugs CT1 to CT4 with different heights. Contact plugs CT1 to CT4 may be disposed in the alternating stacks of pads WP1 to WP4 and inter-pad dielectric layers P1L, and are laterally spaced from each other in a first horizontal direction (i.e., third direction D3). Contact plugs CT1 to CT4 may have different heights in the first direction D1. The top surfaces of contact plugs CT1 to CT4 may be disposed on the same horizontal plane, and the bottom surfaces of contact plugs CT1 to CT4 may be adjacent to one of the pads WP1 to WP4.

[0100] Return to reference Figure 4D The first contact plug CT1 is electrically coupled to the first pad WP1 at the first level LV1, and is electrically coupled to the second conductor WL at the first level LV1 via the first pad WP1. The second contact plug CT2 is electrically coupled to the second pad WP2 at the second level L2, and is electrically coupled to the second conductor WL at the second level LV2 via the second pad WP2. The third contact plug CT3 is electrically coupled to the third pad WP3 at the third level LV3, and is electrically coupled to the second conductor WL at the third level LV3 via the third pad WP3. The fourth contact plug CT4 is electrically coupled to the fourth pad WP4 at the fourth level LV4, and is electrically coupled to the second conductor WL at the fourth level LV4 via the fourth pad WP4.

[0101] The first contact spacer CTS1 can be disposed on the side wall of the first contact plug CT1, and the second contact spacer CTS2 can be disposed on the side wall of the second contact plug CT2. The third contact spacer CTS3 can be disposed on the side wall of the third contact plug CT3, and the fourth contact spacer CTS4 can be disposed on the side wall of the fourth contact plug CT4. The vertical height of the fourth contact plug CT4 can be greater than the vertical height of the third contact plug CT3, and the vertical height of the third contact plug CT3 can be greater than the vertical height of the second contact plug CT2. The vertical height of the second contact plug CT2 can be greater than the vertical height of the first contact plug CT1. The vertical height can refer to the height in the first direction D1.

[0102] The fourth contact plug CT4 and the fourth contact spacer CTS4 can penetrate the pads WP1, WP2, and WP3 located in the first level LV1, the second level LV2, and the third level LV3. The fourth contact plug CT4 can be electrically isolated from the pads WP1, WP2, and WP3 located in the first level LV1, the second level LV2, and the third level LV3 through the fourth contact spacer CTS4.

[0103] The third contact plug CT3 and the third contact spacer CTS3 can penetrate the pads WP1 and WP2 located in the first level LV1 and the second level LV2. The third contact plug CT3 can be electrically isolated from the pads WP1 and WP2 located in the first level LV1 and the second level LV2 by the third contact spacer CTS3.

[0104] The second contact plug CT2 and the second contact spacer CTS2 can penetrate the pad WP1 in the first level LV1. The second contact plug CT2 can be electrically isolated from the pad WP1 in the first level LV1 by the second contact spacer CTS2.

[0105] The first pad WP1 may surround the sides of the second to fourth contact plugs CT2, CT3, and CT4. The second pad WP2 may surround the sides of the third contact plug CT3 and the fourth contact plug CT4. The third pad WP3 may surround the side of the fourth contact plug CT4.

[0106] The first pad WP1 can directly contact the bottom surface of the first contact plug CT1. The second pad WP2 can directly contact the bottom surface of the second contact plug CT2. The third pad WP3 can directly contact the bottom surface of the third contact plug CT3. The fourth pad WP4 can directly contact the bottom surface of the fourth contact plug CT4.

[0107] At the same horizontal level, the second conductor WL of the first subcell array MCA1 and the second conductor WL of the second subcell array MCA2 can share pads WP1 to WP4 at the corresponding level. For example, the second pad WP2 can be coupled to the second conductor WL of the first subcell array MCA1 and the second conductor WL of the second subcell array MCA2.

[0108] As described above, the pads WP1 to WP4 of the second region R2 can have a stepless structure. Since the pads WP1 to WP4 are formed with a stepless structure, the area or volume occupied by the pads WP1 to WP4 in the second region R2 can be reduced. In the comparative example, when the pads WP1 to WP4 are formed with a stepped structure, the second region R2 can include the stepped pads WP1 to WP4, thus increasing the area occupied by the second region R2.

[0109] Contact spacers CTS1 to CTS4 may all comprise a dielectric material. Contact spacers CTS1 to CTS4 may all comprise silicon oxide, silicon nitride, or a combination thereof. In some embodiments, contact spacers CTS1 to CTS4 may all comprise a low-k material with a dielectric constant of 4 or less (e.g., 2.0 to 3.5). Contact spacers CTS1 to CTS4 may all comprise SiCOH (a carbon-doped dielectric material comprising silicon (Si), carbon (C), oxygen (O), and hydrogen (H) (or a carbon-doped oxide dielectric material), silicon oxyfluoride (SiOF), or a combination thereof. The dielectric constant of SiCOH may be about 3, lower than that of SiCO. The dielectric constant of SiCO may be about 4. Contact spacers CTS1 to CTS4 may all have a lower dielectric constant than silicon oxide (SiO2) and SiCO.

[0110] An inter-pad dielectric layer (PIL) may be disposed between pads WP1 to WP4. Each PIL may contain a dielectric material. Each PIL may contain silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the PIL may contain a low-k material with a dielectric constant of 4 or less (e.g., 2.0 to 3.5). Each PIL may contain SiCOH, SiOF, or a combination thereof. The dielectric constant of SiCOH may be approximately 3, lower than that of SiCO. The dielectric constant of SiCO may be approximately 4. Each PIL may have a lower dielectric constant than silicon oxide (SiO2) and SiCO.

[0111] Refer again Figure 4EThe outer edges of pads WP1 to WP4 can contact the pad isolation layer WSL. The pad isolation layer WSL may comprise a stack of a first pad isolation layer WSL1, a second pad isolation layer WSL2, and a third pad isolation layer WSL3. The stack of the first pad isolation layer WSL1 and the second pad isolation layer WSL2 can be a lower pad isolation layer. A dummy piece DP may be disposed between the first pad isolation layer WSL1 and the inter-pad dielectric layer PIL. The dummy piece DP may be made of the same material as the nanosheet HL.

[0112] As described above, the semiconductor device 100 may include vertically and horizontally arranged nanosheets HL, a second conductive line WL horizontally oriented and surrounding the horizontally arranged nanosheets HL, pads WP1 to WP4 coupled to the edge portions of the second conductive line WL, an inter-pad dielectric layer PIL disposed between the pads WP1 to WP4, contact plugs CT1 to CT4 each coupled to a different pad among WP1 to WP4, and contact spacers CTS1 to CTS4 respectively formed on the sidewalls of the contact plugs CT1 to CT4. The contact spacers CTS1 to CTS4 may all contain a low-k material. The inter-pad dielectric layer PIL may all contain a low-k material.

[0113] Since the contact spacers CTS1 to CTS4 all contain low-k material, the parasitic capacitance with the pads WP1 to WP3 surrounding the contact plugs CT2 to CT4 can be reduced. Therefore, since the contact spacers CTS1 to CTS4 all contain low-k material, the speed of the semiconductor device 100 can be increased and the power consumption can be reduced.

[0114] Figure 5A Figure 34B Various views of a semiconductor device formed using a method for manufacturing a semiconductor device according to an embodiment of the present disclosure are shown.

[0115] Figure 5A A plan view illustrating the hierarchical structure of the second module layer is provided to describe the method for forming the module stack SB. Figure 5B For along Figure 5A The cross-sectional view of the structure intercepted by line A-A' in the diagram. Figure 5C For along Figure 5A A cross-sectional view of the structure intercepted by line B-B' in the diagram.

[0116] refer to Figures 5A to 5CA module stack SB may be formed on the substrate 11. The module stack SB may include an alternating stack of a first module layer 12 and a second module layer 13. The module stack SB may be formed in each of a first region R1 and a second region R2. The first region R1 may be a region forming a three-dimensional array of memory cells, and the second region R2 may be a region forming pads and contact plugs coupled to the memory cells. The first region R1 may be referred to as an "array region," and the second region R2 may be referred to as a "pad region" or a "connection region." The second region R2 may also be referred to as a "shared connection region," a "shared contact region," or a "common contact region."

[0117] Substrate 11 may be a material suitable for semiconductor processing. Substrate 11 may comprise a semiconductor substrate, a conductive material, a dielectric material, a semiconductor material, or a combination thereof. Substrate 11 may comprise silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, epitaxial silicon, combinations thereof, or multiple layers thereof. Substrate 11 may also comprise other semiconductor materials, such as germanium. Substrate 11 may also comprise a III-V group semiconductor substrate, such as a compound semiconductor substrate (e.g., GaAs). The mode stack SB may comprise an alternating stack of a first mode layer 12 and a second mode layer 13.

[0118] In order to form a module stack SB, the first module layer 12 can be stacked alternately with the second module layer 13, and the first module layer 12 and the second module layer 13 can be epitaxially grown multiple times.

[0119] The first layer 12 and the second layer 13 can be made of different semiconductor materials. The first layer 12 can contain either silicon-germanium or single-crystal silicon-germanium. The second layer 13 can contain single-crystal silicon. The first layer 12 and the second layer 13 can be formed by an epitaxial growth process. The bottommost first layer 12 can be used as a seed layer during the epitaxial growth process. The thickness of each first layer 12 can be less than the thickness of each second layer 13. The first layer 12 may include a first epitaxial growth layer, and the second layer 13 may include a second epitaxial growth layer.

[0120] In one embodiment, in the mode stack SB, multiple monocrystalline silicon-germanium layers may be stacked alternately with multiple monocrystalline silicon layers. For example, the first mode layer 12 may be a monocrystalline silicon-germanium layer, and the second mode layer 13 may be a monocrystalline silicon layer. The stacking of the monocrystalline silicon-germanium layer (first mode layer 12) and the monocrystalline silicon layer (second mode layer 13) (SiGe / Si stacking) may be stacked multiple times (e.g., alternating layers). The first mode layer 12 may be referred to as a "sacrificial layer," and the second mode layer 13 may be referred to as a "nanosheet target layer" or a "recessed target layer."

[0121] Modular stacking (SB) can be referred to as "vertical stacking". Modular stacking SB is formed by alternately stacking multiple sacrificial layers and multiple nanosheet target layers. The sacrificial layer can be a single-crystal silicon-germanium layer, and the nanosheet target layer can be a single-crystal silicon layer.

[0122] The thickness ratio of the first module layer 12 and the thickness ratio of the second module layer 13 in the module stack SB can be modified in various ways. For example, the thickness of the first module layer 12 can be 5 to 20 nm, and the thickness of the second module layer 13 can be 50 to 80 nm. The number of first module layers 12 and the number of second module layers 13 in the module stack SB can be modified in various ways. In some embodiments, a three-layer stack including the first module layer 12, the second module layer 13, and the first module layer 12 can be defined at the bottom and top of the module stack SB. The thickness of the second module layer 13 in the three-layer stack can be less than the thickness of the second module layer 13 in the module stack SB.

[0123] A first hard mask layer 14 may be formed on the die stack SB. The first hard mask layer 14 may contain a dielectric material, such as an oxide-based material, a nitride-based material, a carbon-based material, or a combination thereof. For example, the first hard mask layer 14 may contain SiO2, Si3N4, amorphous carbon, or a combination thereof.

[0124] Subsequently, a first hard mask layer 14 can be used as a barrier layer to etch portions of the die stack SB, forming a plurality of sacrificial isolation openings 15. The sacrificial isolation openings 15 can be initial openings for cell isolation. From a top view, the cross-sectional shape of the sacrificial isolation openings 15 can all be rectangular. In some embodiments, the cross-section of the sacrificial isolation openings 15 can all have a circular or elliptical shape. In some embodiments, the sacrificial isolation openings 15 can be referred to as "sacrificial isolation trenches". The sacrificial isolation openings 15 can extend vertically along a first direction D1 and longitudinally along a second direction D2. The sacrificial isolation openings 15 can be arranged at predetermined intervals in a third direction D3. The bottom surface of each sacrificial isolation opening 15 can extend into the interior of the substrate 11.

[0125] Sacrificial isolation opening 15 may be formed in the first region R1. Simultaneously with forming the sacrificial isolation opening 15, edge sacrificial isolation opening 15E may also be formed. The edge sacrificial isolation opening 15E may be formed at the boundary between the first region R1 and the second region R2. The length of each edge sacrificial isolation opening 15E in the second direction D2 may be greater than the length of each sacrificial isolation opening 15.

[0126] Figure 6A A plan view of the second module layer hierarchy is shown to describe the method of forming the sacrificial isolation layer 16. Figure 6B For along Figure 6A A cross-sectional view of the structure intercepted by line B-B' in the diagram.

[0127] refer to Figure 6A and Figure 6BA sacrificial isolation layer 16 may be formed to fill the sacrificial isolation opening 15. The sacrificial isolation layer 16 may contain the same material. All sacrificial isolation layers 16 may be formed of a dielectric material. The sacrificial isolation layer 16 may have etch selectivity relative to the mold stack SB. For example, all sacrificial isolation layers 16 may contain silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or combinations thereof. Forming the sacrificial isolation layer 16 may include forming a sacrificial isolation material on the mold stack SB to fill the sacrificial isolation opening 15 and planarizing the sacrificial isolation material so that the surface of the first hard mask layer 14 is exposed.

[0128] The sacrificial isolation layer 16 may extend vertically along a first direction D1 and longitudinally along a second direction D2. The sacrificial isolation layers 16 may be disposed at predetermined intervals along a third direction D3. Each sacrificial isolation layer 16 may include a stack of a first sacrificial pad layer and a first sacrificial gap fill layer. The first sacrificial pad layer may be silicon nitride, and the first sacrificial gap fill layer may be silicon oxide. The sacrificial isolation layers 16 may penetrate the mold stack SB along the first direction D1.

[0129] A sacrificial isolation layer 16 may be formed in the first region R1. Simultaneously with the formation of the sacrificial isolation layer 16, an edge sacrificial isolation layer 16E may be formed. The edge sacrificial isolation layer 16E may be formed at the boundary between the first region R1 and the second region R2. The length of each edge sacrificial isolation layer 16E in the second direction D2 may be greater than the length of each sacrificial isolation layer 16.

[0130] Figure 7A A plan view of the second module layer hierarchy is shown to describe the method of forming sacrificial linear openings 18 and 19. Figure 7B For along Figure 7A The cross-sectional view of the structure intercepted by line A-A' in the diagram.

[0131] refer to Figure 7A and Figure 7B A second hard mask layer 17 may be formed on the die stack SB and the sacrificial isolation layer 16. The second hard mask layer 17 may include silicon nitride. The second hard mask layer 17 may be formed by etching a second hard mask material using a mask layer such as photoresist. A plurality of linear openings may be defined in the second hard mask layer 17.

[0132] A second hard mask layer 17 can be used as an etch barrier layer to etch portions of the mold stack SB. Therefore, a plurality of sacrificial linear openings 18 and 19 can be formed between the sacrificial isolation layers 16. The sacrificial linear openings may include a first sacrificial linear opening 18 and a second sacrificial linear opening 19. From a top view perspective, the first sacrificial linear opening 18 and the second sacrificial linear opening 19 may be linear openings extending along a third direction D3. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 may extend vertically in a first direction D1. The sacrificial isolation layer 16 may be disposed between the first sacrificial linear opening 18 and the second sacrificial linear opening 19 along a second direction D2. From a top view perspective, the cross-sections of both the first sacrificial linear opening 18 and the second sacrificial linear opening 19 may have a rectangular shape. In some embodiments, the cross-sections of both the first sacrificial linear opening 18 and the second sacrificial linear opening 19 may have a circular or elliptical shape. The widths of both the first sacrificial linear opening 18 and the second sacrificial linear opening 19 in the second direction D2 may be smaller than their widths in the third third direction D3. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 may be referred to as "sacrificial linear trenches". The sacrificial isolation layer 16 may not contact the first sacrificial linear opening 18 and the second sacrificial linear opening 19. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 may have different horizontal lengths in the third direction D3.

[0133] A first sacrificial linear opening 18 and a second sacrificial linear opening 19 may be formed in the first region R1. One end of the first sacrificial linear opening 18 may extend to be positioned between the edge sacrificial isolation layers 16E.

[0134] In the following description, the thicknesses of the first mold layer 12 and the second mold layer 13 are shown in the cross-sectional view of the structure taken along line A-A'. The thickness of the first mold layer 12 in the cross-sectional view of the structure taken along line A-A' may be equal to the thickness of the first mold layer 12 in the cross-sectional view of the structure taken along line B-B'. The thickness of the second mold layer 13 in the cross-sectional view of the structure taken along line A-A' may be equal to the thickness of the second mold layer 13 in the cross-sectional view of the structure taken along line B-B'.

[0135] Figure 8A A plan view of the second module layer hierarchy is shown to describe the method of forming linear sacrificial layers 18L and 19L. Figure 8B For along Figure 8A The cross-sectional view of the structure intercepted by line A-A' in the diagram.

[0136] refer to Figure 8A and Figure 8BLinear sacrificial layers 18L and 19L can be formed to fill the first linear sacrificial opening 18 and the second linear sacrificial opening 19. The linear sacrificial layers may include the first linear sacrificial layer 18L and the second linear sacrificial layer 19L. From a top view, the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may have a linear shape extending along a third direction D3. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L may extend perpendicularly along a first direction D1. A sacrificial isolation layer 16 may be disposed between the first linear sacrificial layer 18L and the second linear sacrificial layer 19L along a second direction D2. From a top view, the cross-section of both the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may have a rectangular shape. In some embodiments, the cross-section of both the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may have a circular shape or an elliptical shape. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L may contain the same material. Both the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may be formed of a dielectric material. For example, both the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may comprise silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or a combination thereof. The sacrificial isolation layer 16 may not contact the first linear sacrificial layer 18L and the second linear sacrificial layer 19L.

[0137] A first linear sacrificial layer 18L and a second linear sacrificial layer 19L may be formed in a first region R1. One end of the first linear sacrificial layer 18L may extend to be disposed between the edge sacrificial isolation layers 16E.

[0138] Figure 9A A plan view illustrating the hierarchical structure of the second module layer is provided to describe the recesses of the first module layer 12. Figure 9B For along Figure 9A The cross-sectional view of the structure intercepted by line A-A' in the diagram. Figure 9C For along Figure 9A A cross-sectional view of the structure intercepted by line B-B' in the diagram.

[0139] refer to Figures 9A to 9C In the first linear sacrificial layer 18L and the second linear sacrificial layer 19L, the first linear sacrificial layer 18L can be selectively removed. Therefore, a first linear opening 20 can be formed. From a top view, the first linear opening 20 can be configured to be horizontally spaced from the second linear sacrificial layer 19L in the second direction D2.

[0140] The first mold layer 12 can be selectively recessed through the first linear opening 20.

[0141] The first mold layer 12 can be selectively recessed by utilizing the difference in etching selectivity between the first mold layer 12 and the second mold layer 13. The first mold layer 12 can be removed using a wet etching process or a dry etching process. For example, when the first mold layer 12 contains a silicon-germanium layer and the second mold layer 13 contains a monocrystalline silicon layer, an etchant or etching gas selective relative to the monocrystalline silicon layer can be used to etch the silicon-germanium layer. Each first mold layer with its original thickness can be retained, as indicated by reference numeral "12A". The first mold layer 12A can be retained in the first region R1, while the pad-side first mold layer 12B can be retained in the second region R2.

[0142] Figure 10A A plan view showing the hierarchical structure of the second module layer is provided to illustrate the recesses of the second module layer 13. Figure 10B For along Figure 10A The cross-sectional view of the structure intercepted by line A-A' in the diagram. Figure 10C For along Figure 10A A cross-sectional view of the structure intercepted by line B-B' in the diagram.

[0143] refer to Figures 10A to 10C A portion (first portion) of each second mold layer 13 can be recessed to form a narrow wafer 13N. The second mold layer 13 can be recessed using either wet or dry etching processes. By partially recessing each second mold layer 13, an original body portion 13A and a narrow wafer 13N can be formed. The original body portion 13A can maintain its original thickness, while the thickness of the narrow wafer 13N can be less than its original thickness. The horizontal length of the original body portion 13A in the second direction D2 can be equal to or different from the horizontal length of the narrow wafer 13N in the second direction D2. The combination of the original body portion 13A and the narrow wafer 13N can be referred to as a "preliminary active layer." The narrow wafer 13N can be referred to as a "flat wafer" or a "protruding narrow wafer."

[0144] The recessed process used to form the narrow wafer 13N can be referred to as a "thinning process" or "trimming process" for the second module layer 13. To form the narrow wafer 13N, the upper surface, lower surface, and side surfaces of the second module layer 13 can be recessed. The narrow wafer 13N can be referred to as a "thin active layer." The narrow wafer 13N may include a monocrystalline silicon layer. The recessed process used to form the narrow wafer 13N can employ, for example, Hot SC-1 (HSC1). HSC1 may include a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) mixed in a 1:4:20 ratio. Using HSC1, the second module layer 13 can be selectively etched.

[0145] Narrow sheets 13N can be formed by a partial recessing process of the second template layer 13 as described above. Inter-nanosheet recesses 21 can be formed between vertically arranged narrow sheets 13N. The upper and lower surfaces of each narrow sheet 13N can both contain flat surfaces. The boundary between the original body portion 13A and the narrow sheet 13N can be vertical or curved. Each first template layer 12A can be disposed between vertically stacked original body portions 13A.

[0146] A narrow strip 13N can be formed in the first region R1, and a pad-side narrow strip 13P can be formed in the second region R2 at the same time as the narrow strip 13N is formed.

[0147] The original body portion 13A can be retained in the first region R1, and the second mold layer 13B on the pad side can be retained in the second region R2.

[0148] Figure 11A A plan view of the narrow-layer structure is shown to describe the method of forming the sacrificial isolation layer layer opening 22. Figure 11B For along Figure 11A The cross-sectional view of the structure intercepted by line A-A' in the diagram. Figure 11C For along Figure 11A A cross-sectional view of the structure intercepted by line B-B' in the diagram. Figure 11D For along Figure 11A A cross-sectional view of the structure intercepted by line C-C' in the diagram.

[0149] refer to Figures 11A to 11D The sacrificial isolation layer 16 can be selectively peeled off through the recesses 21 between the nanosheets. Thus, each hierarchical opening 22 of the sacrificial isolation layer can be formed on the third direction D3 between the original body portions 13A.

[0150] The sides of the first module layer 12A, the sides of the original body part 13A, and the sides of the narrow strip 13N can be exposed on the third direction D3 through the sacrificial isolation layer hierarchical opening 22.

[0151] When the sacrificial isolation layer hierarchical opening 22 is formed, a portion of the first hard mask layer 14 (see...) Figure 11B The reference numeral "14A" in the attached drawing can be recessed. Therefore, the space of the recessed portion 21 of the uppermost nanosheet can be expanded.

[0152] When forming the sacrificial isolation layer hierarchical opening 22, the edge sacrificial isolation layer 16E can be removed. Therefore, the edge sacrificial isolation layer hierarchical opening 22E can be formed.

[0153] The sacrificial isolation layer hierarchical opening 22 can be formed in the first region R1.

[0154] Figure 12A A plan view of the narrow-layer structure is shown to describe the method of forming the first inter-unit dielectric layer 23. Figure 12B For along Figure 12A The cross-sectional view of the structure intercepted by line A-A' in the diagram. Figure 12C For along Figure 12A A cross-sectional view of the structure intercepted by line B-B' in the diagram. Figure 12D For along Figure 12A A cross-sectional view of the structure intercepted by line C-C' in the diagram.

[0155] refer to Figures 12A to 12D A first inter-cell dielectric layer 23 may be formed in the sacrificial isolation layer level opening 22. The first inter-cell dielectric layer 23 may contain a dielectric material. The first inter-cell dielectric layer 23 may contain silicon oxide, silicon nitride, silicon carbide, or a combination thereof. Forming the first inter-cell dielectric layer 23 may include: forming a dielectric material filling the sacrificial isolation layer level opening 22, and performing an etch-back process on the dielectric material. Simultaneously with forming the first inter-cell dielectric layer 23, an edge inter-cell dielectric layer 23E may be formed to fill the edge sacrificial isolation layer level opening 22E.

[0156] The first inter-cell dielectric layer 23 may fill a portion of the sacrificial isolation layer hierarchy opening 22. The sides of the first module layer 12A and the sides of the original body portion 13A may be covered by the first inter-cell dielectric layer 23 in the third direction D3. The first inter-cell dielectric layer 23 may expose the sides of the narrow segments 13N. The remaining portion of the sacrificial isolation layer hierarchy opening 22, i.e., the non-gap fill portion 23G, may expose the sides of the narrow segments 13N. The non-gap fill portion 23G may be defined between the narrow segments 13N in the third direction D3. The first inter-cell dielectric layer 23 may be formed in the first region R1.

[0157] After forming the first inter-unit dielectric layer 23, a fully open nanosheet recess 24 can be formed, which exposes all the narrow sheets 13N. The fully open nanosheet recess 24 can refer to the combination of the inter-nanosheet recess 21 and the non-gap filling portion 23G of the sacrificial isolation layer hierarchical opening 22. The fully open nanosheet recess 24 can expose all the narrow sheets 13N on the third direction D3.

[0158] Figure 13A To illustrate the plan view of the narrow strip hierarchical structure, a method for forming the first spacer 26A is described. Figure 13B For along Figure 13A The cross-sectional view of the structure intercepted by line A-A' in the diagram. Figure 13C For along Figure 13A A cross-sectional view of the structure intercepted by line B-B' in the diagram.

[0159] refer to Figures 13A to 13C The nanosheet dielectric layer 25 can be formed on the exposed portion of the narrow strip 13N. The nanosheet dielectric layer 25 can be referred to as the "gate dielectric layer".

[0160] The nanosheet dielectric layer 25 can be formed by oxidizing the surface of the narrow sheet 13N. In some embodiments, the nanosheet dielectric layer 25 can be formed by a silicon oxide deposition and oxidation process. The nanosheet dielectric layer 25 may comprise silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The nanosheet dielectric layer 25 may comprise SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or a combination thereof. The nanosheet dielectric layer 25 can be formed on all surfaces of the narrow sheet 13N.

[0161] A first spacer 26A may be formed on the nanosheet dielectric layer 25. The first spacer 26A may comprise silicon nitride. The first spacer 26A may surround and cover the narrow strip 13N on the nanosheet dielectric layer 25. The first spacer 26A may be thicker than the nanosheet dielectric layer 25.

[0162] The second inter-unit dielectric layer 27A may be formed on the first spacer 26A. The second inter-unit dielectric layer 27A may contain silicon oxide.

[0163] The nanosheet dielectric layer 25 and the first spacer 26A may also be formed on the surface of the substrate 11.

[0164] As described above, the first spacer 26A can be disposed on the third direction D3 between the narrow strips 13N.

[0165] Figure 14A A plan view of the narrow-plate hierarchical structure is shown to describe the method of forming the first spacer 26. Figure 14B For along Figure 14A The cross-sectional view of the structure intercepted by line A-A' in the diagram. Figure 14C For along Figure 14A A cross-sectional view of the structure intercepted by line B-B' in the diagram.

[0166] refer to Figures 14A to 14C The second inter-cell dielectric layer 27A can be cut through the first linear opening 20. Subsequently, the first spacer layer 26A can be selectively recessed. The retained first spacer layer can become the first spacer 26, and the second inter-cell dielectric layer can be retained, as indicated by reference numeral "27".

[0167] With the formation of the first spacer 26, a linear surrounding recess 28 can be formed around the narrow strip 13N on the nanosheet dielectric layer 25. Each second inter-unit dielectric layer 27 can be disposed between the vertically arranged linear surrounding recesses 28.

[0168] Figure 15A A plan view of the narrow-slice hierarchical structure is shown to describe the method of forming the horizontal conductor 29. Figure 15B For along Figure 15AThe cross-sectional view of the structure intercepted by line A-A' in the diagram. Figure 15C For along Figure 15A A cross-sectional view of the structure intercepted by line B-B' in the diagram.

[0169] refer to Figures 15A to 15C The horizontal guide 29 can be formed to fill the linear surrounding recess 28. The horizontal guide 29 can extend horizontally along the third direction D3.

[0170] Forming the horizontal conductors 29 may include depositing a conductive material linearly surrounding the recess 28 on the nanosheet dielectric layer 25, and performing a horizontal etch-back process on the conductive material. Each horizontal conductor 29 may simultaneously surround a narrow strip 13N at the same level. The horizontal conductors 29 may each comprise a metal-based material, a semiconductor material, or a combination thereof. The horizontal conductors 29 may each comprise molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the horizontal conductors 29 may each comprise a titanium nitride and tungsten (TiN / W) stack, wherein the titanium nitride and tungsten are stacked sequentially. The horizontal conductors 29 may each comprise an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or lower, while the P-type work function material may have a high work function of about 4.5 eV or higher. Each second inter-unit dielectric layer 27 may be disposed between the plurality of horizontal conductors 29 along a first direction D1. The horizontal conductors 29 surrounding the narrow strip 13N may be referred to as “gate all-around (GAA) electrodes.” Narrow-slice 13N can be referred to as "nanosheet channel", "nanowire" or "nanowire channel".

[0171] A lower-level dummy horizontal electrode 29L can be formed on the surface of the substrate 11. An upper-level dummy horizontal electrode 29U can be formed above the uppermost horizontal conductor 29. Both the dummy horizontal electrodes 29L and 29U can have a non-surrounding shape.

[0172] Figure 16A A plan view of the narrow-plate hierarchical structure is shown to describe the method of forming the second spacer 30. Figure 16B For along Figure 16A The cross-sectional view of the structure intercepted by line A-A' in the diagram.

[0173] refer to Figure 16A and Figure 16B Each second spacer 30 may be formed on one side of each horizontal conductor 29. The second spacer 30 may comprise silicon oxide, silicon nitride, silicon carbide, embedded air gaps, or a combination thereof. A deposition and etch-back process of spacer material may be performed to form the second spacer 30. The second spacer 30 may comprise a stack of silicon oxide pads and silicon nitride pads.

[0174] After the second spacer 30 is formed, a portion of the nanosheet dielectric layer 25 can be cut to expose one side of each narrow strip 13N.

[0175] The second spacer 30 may surround the narrow strip 13N of the same level on one side of the horizontal conductor 29 on the third direction D3.

[0176] Subsequently, a first bottom protective layer 31 may be formed on the surface of the substrate 11. The first bottom protective layer 31 may contain a material that is etch-selective relative to the substrate 11. The first bottom protective layer 31 may contain a dielectric material. The first bottom protective layer 31 may contain silicon oxide, silicon nitride, silicon carbide, or a combination thereof.

[0177] Figure 17A A plan view of the narrow strip hierarchy is shown to describe the method of forming the narrow strip cutout 32. Figure 17B For along Figure 17A The cross-sectional view of the structure intercepted by line A-A' in the diagram.

[0178] refer to Figure 17A and Figure 17B One side of the narrow strip 13N and one side of the nanosheet dielectric layer 25 can be cut. This forms a narrow strip cutout 32 that is horizontally recessed from the edge of the second spacer 30. While forming the narrow strip cutout 32, the surface of the substrate 11 can be protected by the first bottom protective layer 31. The narrow strip cutout 32 can be referred to as a "narrow strip layer recess".

[0179] Figure 18A A plan view of the narrow-slice hierarchical structure is shown to describe the method of forming the first contact node 33. Figure 18B For along Figure 18A The cross-sectional view of the structure intercepted by line A-A' in the diagram.

[0180] refer to Figure 18A and Figure 18B The first contact node 33 can be selectively formed from the edge of the narrow wafer 13N. The first contact node 33 can be formed by selective epitaxial growth (SEG). The first contact node 33 can be an epitaxial layer of silicon. The first contact node 33 can be a doped silicon epitaxial layer.

[0181] The first doped region 34 may be formed within one side of the narrow strip 13N. A thermal processing step may be performed to form the first doped region 34, and thus the dopant may diffuse from the first contact node 33.

[0182] Figure 19A To illustrate the plan view of the narrow-layer structure, a method for forming the first vertical conductor 35A and the second vertical conductor 35B is described. Figure 19B For along Figure 19A The cross-sectional view of the structure intercepted by line A-A' in the diagram.

[0183] refer to Figure 19A and Figure 19BA vertical conductor 35 may be formed on the first contact node 33. Before the vertical conductor 35 is formed, an ohmic contact layer may be formed on the first contact node 33. The ohmic contact layer may contain a metal silicide, such as titanium silicide or molybdenum silicide. The vertical conductor 35 may include a first vertical conductor 35A and a second vertical conductor 35B.

[0184] Forming the first vertical conductor 35A and the second vertical conductor 35B may include depositing a metallic material and etching the metallic material. The bottoms 35C of the first vertical conductor 35A and the second vertical conductor 35B that are adjacent to each other may be merged.

[0185] The first vertical conductor 35A and the second vertical conductor 35B may be oriented perpendicularly along a first direction D1. The first vertical conductor 35A and the second vertical conductor 35B may include bit lines. Both the first vertical conductor 35A and the second vertical conductor 35B may contain a metal, a metal-based material, or a combination thereof. Both the first vertical conductor 35A and the second vertical conductor 35B may contain a metal, a metal nitride, a metal silicide, or a combination thereof. Both the first vertical conductor 35A and the second vertical conductor 35B may contain titanium nitride, tungsten, or a combination thereof. For example, the first vertical conductor 35A and the second vertical conductor 35B may contain a titanium nitride / tungsten (TiN / W) stack, wherein titanium nitride and tungsten are stacked sequentially.

[0186] The tops of the first vertical conductor 35A and the second vertical conductor 35B may extend to a portion of the surface of the second hard mask layer 17.

[0187] The first vertical conductor 35A and the second vertical conductor 35B can be coupled together to the narrow strip 13N disposed along the first direction D1.

[0188] Figure 20A A planar view of the nanosheet hierarchical structure is shown to describe the method of forming the pad isolation opening 37. Figure 20B For along Figure 20A A cross-sectional view of the structure intercepted by line B-B' in the diagram. Figure 20C For along Figure 20A The cross-sectional view of the structure intercepted by line B1-B1'.

[0189] refer to Figures 20A to 20C An array isolation layer 36 may be formed to fill the first linear opening 20 on the first vertical conductor 35A and the second vertical conductor 35B. The array isolation layer 36 may extend vertically along a first direction D1 and horizontally along a third direction D3. The array isolation layer 36 may be formed between the first vertical conductor 35A and the second vertical conductor 35B along the third direction D3. The array isolation layer 36 may include a dielectric material. The array isolation layer 36 may comprise silicon oxide, silicon nitride, an air gap, or a combination thereof.

[0190] Subsequently, the first stencil layer 12B on the pad side and the second stencil layer 13B on the pad side can be etched in the second region R2, and a plurality of pad isolation openings 37 can be formed. The pad isolation openings 37 can extend horizontally along the third direction D3 and vertically along the first direction D1.

[0191] Refer again Figure 20B and Figure 20C The edge portion 29E of the horizontal conductor 29 can cover the edge of the second mold layer 13B on the pad side, and the nanosheet dielectric layer 25 is located between the edge portion 29E of the horizontal conductor 29 and the second mold layer 13B on the pad side.

[0192] Figure 21A This is a planar diagram showing the nanosheet hierarchical structure, used to describe the method of forming the pad side sheet 13PS. Figure 21B It is along Figure 21A A cross-sectional view of the structure intercepted by line B-B' in the diagram. Figure 21C It is along Figure 21A The cross-sectional view of the structure intercepted by line B1-B1'.

[0193] refer to Figures 21A to 21C The first mold layer 12B on the pad side and the second mold layer 13B on the pad side can be recessed sequentially to form a pad side sheet 13PS. The first mold layer 12B on the pad side can be completely removed, and the upper and lower surfaces of the second mold layer 13B on the pad side can be recessed.

[0194] Each pad recess 38 can be formed between the pad side sheets 13PS. The upper and lower surfaces of the narrow sheet 13N can both contain flat surfaces.

[0195] In the pad side sheet 13PS, the bottommost pad side sheet can be called "dummy pad 13DP".

[0196] The pad side pieces 13PS can be sacrificial pieces, replaced by pad pieces in subsequent processes. The horizontal lengths of the pad side pieces 13PS can be equal to each other. The pad side pieces 13PS can have a stepless structure.

[0197] Figure 22A A planar view of the nanosheet hierarchical structure is shown to describe the method for forming the inter-pad dielectric layer 39. Figure 22B For along Figure 22A A cross-sectional view of the structure intercepted by line B-B' in the diagram. Figure 22C For along Figure 22A The cross-sectional view of the structure intercepted by line B1-B1'.

[0198] refer to Figures 22A to 22C An inter-pad dielectric layer 39 can be formed to fill the inter-pad recess 38. The inter-pad dielectric layer 39 can be selective relative to the pad sidesheet 13PS. The inter-pad dielectric layer 39 can contain silicon oxide, silicon nitride, or a combination thereof.

[0199] A sacrificial material deposition and etch-back process can be performed to form the inter-pad dielectric layer 39. After the inter-pad dielectric layer 39 is formed, the outer edges of the pad sidesheets 13PS and dummy pads 13DP can be exposed.

[0200] In some embodiments, the inter-pad dielectric layer 39 may comprise a low-k material with a dielectric constant of 4 or less (e.g., 2.0 to 3.5). The inter-pad dielectric layer 39 may comprise SiCOH, SiOF, or a combination thereof. The dielectric constant of SiCOH may be approximately 3, lower than that of SiCO. The dielectric constant of SiCO may be approximately 4.

[0201] Figure 23A A planar view of the nanosheet hierarchical structure is shown to describe the method for forming contact holes 41A, 41B, 41C and 41D. Figure 23B For along Figure 23A A cross-sectional view of the structure intercepted by line B-B' in the diagram. Figure 23C For along Figure 23A The cross-sectional view of the structure intercepted by line B1-B1'.

[0202] refer to Figures 23A to 23C A first pad isolation layer 40A and a second pad isolation layer 40B can be formed to fill the bottom of the pad isolation opening 37.

[0203] Subsequently, multiple contact holes 41A, 41B, 41C and 41D can be formed sequentially in the second region R2.

[0204] The first to third hard mask layers 14, 17 and 17T, as well as the uppermost inter-pad dielectric layer 39, can be etched to form a first contact hole 41A. The first contact hole 41A can expose the upper surface of the pad side 13PS in the first layer L1.

[0205] After masking the first contact hole 41A, the first to third hard mask layers 14, 17, and 17T, as well as the pad sidewall 13PS in the first layer L1, can be etched to form the second contact hole 41B. Furthermore, the uppermost inter-pad dielectric layer 39 and the inter-pad dielectric layer 39 between the first layer L1 and the second layer L2 can be etched to form the second contact hole 41B. The second contact hole 41B exposes the upper surface of the pad sidewall 13PS in the second layer L2.

[0206] After the first contact hole 41A and the second contact hole 41B are masked, the first to third hard mask layers 14, 17, and 17T, as well as the pad sidewalls 13PS located in the first layer L1 and the second layer L2, can be etched to form the third contact hole 41C. Furthermore, the uppermost inter-pad dielectric layer 39, the inter-pad dielectric layer 39 located between the first layer L1 and the second layer L2, and the inter-pad dielectric layer 39 located between the second layer L2 and the third layer L3 can be etched to form the third contact hole 41C. The third contact hole 41C exposes the upper surface of the pad sidewalls 13PS located in the third layer L3.

[0207] After the first, second, and third contact holes 41A, 41B, and 41C are masked, the first to third hard mask layers 14, 17, and 17T, the pad sideplates 13PS at the first layer L1, the pad sideplates 13PS at the second layer L2, and the pad sideplates 13PS at the third layer L3 can be etched to form the fourth contact hole 41D. Furthermore, the uppermost inter-pad dielectric layer 39, the inter-pad dielectric layer 39 between the first layer L1 and the second layer L2, the inter-pad dielectric layer 39 between the second layer L2 and the third layer L3, and the inter-pad dielectric layer 39 between the third layer L3 and the fourth layer LV4 can be etched to form the fourth contact hole 41D. The fourth contact hole 41D exposes the upper surface of the pad sideplates 13PS at the fourth layer L4.

[0208] As described above, after forming the first contact hole 41A, the first contact hole 41A can be masked to form the second contact hole 41B. When forming the third contact hole 41C, the first contact hole 41A and the second contact hole 41B can be masked. When forming the fourth contact hole 41D, the first, second, and third contact holes 41A, 41B, and 41C can be masked. In some embodiments, the formation order of the first to fourth contact holes 41A to 41D can be adjusted in various ways.

[0209] Through the above-described series of contact hole formation processes, a first contact hole 41A, a second contact hole 41B, a third contact hole 41C, and a fourth contact hole 41D can be formed sequentially. The first contact hole 41A may be shallower than the second contact hole 41B, the second contact hole 41B may be shallower than the third contact hole 41C, and the third contact hole 41C may be shallower than the fourth contact hole 41D. The depth of the first to fourth contact holes 41A to 41D can gradually decrease along the stacking direction of the pad side sheet 13PS (i.e., the first direction D1).

[0210] The second contact hole 41B can penetrate the pad sideplate 13PS located in the first layer L1. The third contact hole 41C can penetrate the pad sideplate 13PS located in the first layer L1 and the second layer L2. The fourth contact hole 41D can penetrate the pad sideplate 13PS located in the first to third layers L1, L2 and L3. The first contact hole 41A does not penetrate the pad sideplate 13PS located in the first layer L1.

[0211] In some embodiments, a plurality of contact holes 41A, 41B, 41C, and 41D may be formed sequentially, starting with the deepest contact hole. For example, a fourth contact hole 41D, a third contact hole 41C, a second contact hole 41B, and a first contact hole 41A may be formed sequentially. Various modifications may be made to the order in which the fourth contact hole 41D, the third contact hole 41C, the second contact hole 41B, and the first contact hole 41A are formed.

[0212] Figure 24A A planar view of the nanosheet hierarchical structure is shown to describe the method of forming contact spacers 42A to 42D and sacrificial plugs 43A to 43D. Figure 24B For along Figure 24A A cross-sectional view of the structure intercepted by line B-B' in the diagram. Figure 24C For along Figure 24A The cross-sectional view of the structure intercepted by line B1-B1'.

[0213] refer to Figures 24A to 24C Contact spacers 42A to 42D can be formed on the sidewalls of the first to fourth contact holes 41A to 41D, respectively. Contact spacers 42A to 42D can be formed by a dielectric material deposition and etching process. Contact spacers 42A to 42D can all contain silicon oxide, silicon nitride, or a combination thereof. Contact spacers 42A to 42D can all contain low-k materials. Contact spacers 42A to 42D can all contain low-k materials with a dielectric constant of 4 or less, for example, a dielectric constant of 2.0 to 3.5. Contact spacers 42A to 42D can all contain SiCOH, SiOF, or a combination thereof. The dielectric constant of SiCOH can be approximately 3, lower than the dielectric constant of SiCO. The dielectric constant of SiCO can be approximately 4.

[0214] Subsequently, sacrificial plugs 43A to 43D can be formed to fill the first to fourth contact holes 41A to 41D on the contact spacers 42A to 42D, respectively. The sacrificial plugs 43A to 43D can be formed by a deposition and planarization process of sacrificial plug material. The sacrificial plugs 43A to 43D may comprise a metal-based material. For example, the sacrificial plugs 43A to 43D can be formed by a tungsten layer deposition and chemical mechanical polishing (CMP) process.

[0215] The sacrificial plugs 43A to 43D may include a structure in which the height gradually decreases in the stacking direction of the pad sideplates 13PS (i.e., the first direction D1).

[0216] As described above, the pad side sheet 13PS, contact spacers 42A to 42D, and sacrificial plugs 43A to 43D may be formed in the second region R2.

[0217] The first contact spacer 42A may be disposed on the side wall of the first sacrificial plug 43A, and the second contact spacer 42B may be disposed on the side wall of the second sacrificial plug 43B. The third contact spacer 42C may be disposed on the side wall of the third sacrificial plug 43C, and the fourth contact spacer 42D may be disposed on the side wall of the fourth sacrificial plug 43D. The vertical height of the fourth sacrificial plug 43D may be greater than the vertical height of the third sacrificial plug 43C, and the vertical height of the third sacrificial plug 43C may be greater than the vertical height of the second sacrificial plug 43B. The vertical height of the second sacrificial plug 43B may be greater than the vertical height of the first sacrificial plug 43A. The vertical height may refer to the height in the first direction D1.

[0218] The fourth sacrificial plug 43D and the fourth contact spacer 42D can penetrate the pad sideplates 13PS and the inter-pad dielectric layer 39 in the first to third layers L1, L2 and L3. The fourth sacrificial plug 43D can be electrically isolated from the pad sideplates 13PS in the first to third layers L1, L2 and L3 through the fourth contact spacer 42D.

[0219] The third sacrificial plug 43C and the third contact spacer 42C can penetrate the pad side 13PS and the inter-pad dielectric layer 39 in the first layer L1 and the second layer L2. The third sacrificial plug 43C can be electrically isolated from the pad side 13PS in the first layer L1 and the second layer L2 through the third contact spacer 42C.

[0220] The second sacrificial plug 43B and the second contact spacer 42B can penetrate the pad side 13PS and the inter-pad dielectric layer 39 in the first layer L1. The second sacrificial plug 43B can be electrically isolated from the pad side 13PS in the first layer L1 through the second contact spacer 42B.

[0221] Figure 25A A planar view of the nanosheet hierarchical structure is shown to describe the method of forming the pad-shaped opening 45. Figure 25B For along Figure 25A A cross-sectional view of the structure intercepted by line B-B' in the diagram. Figure 25C For along Figure 25A The cross-sectional view of the structure intercepted by line B1-B1'.

[0222] refer to Figures 25A to 25C This allows the pad isolation layers 40A and 40B to be recessed. Therefore, a pad isolation opening 44 with a reduced height can be defined on the upper part of the recessed pad isolation layers 40A and 40B.

[0223] The outer surface of the pad side sheet 13PS and the inter-pad dielectric layer 39 can be exposed through the pad isolation opening 44. The dummy sheet 13DP may not be exposed by the recessed pad isolation layers 40A and 40B.

[0224] Subsequently, the pad sidesheets 13PS can be selectively removed to form pad-shaped openings 45 between the inter-pad dielectric layers 39. The pad-shaped openings 45 may include inner edges 45E that expose the nanosheet dielectric layer 25.

[0225] Subsequently, the nanosheet dielectric layer 25 can be cut through the inner edge 45 of the pad-shaped opening 45. Therefore, the edge portion 29E of the horizontal conductor 29 can be exposed.

[0226] Figure 26A A planar view of the nanosheet hierarchical structure is shown to describe the method of forming pad 46. Figure 26B For along Figure 26A A cross-sectional view of the structure intercepted by line B-B' in the diagram. Figure 26C For along Figure 26A The cross-sectional view of the structure intercepted by line B1-B1'.

[0227] refer to Figures 26A to 26C A pad 46 can be formed to fill the pad-shaped opening 45. A deposition and etching process for the pad material can be performed to form the pad 46. The pad 46 can be horizontally oriented and electrically coupled to a horizontal conductor 29. The pad 46 and the horizontal conductor 29 can be made of the same material. The pad 46 can contain titanium nitride, tungsten, or a combination thereof. The pad 46 may include an inner edge 46E, which can be coupled to an edge portion 29E of the horizontal conductor 29.

[0228] As described above, an inter-pad dielectric layer 39 can be disposed between each pad 46. When the inter-pad dielectric layers 39 all contain a low-k material, the parasitic capacitance between the pads 46 can be reduced. Therefore, the parasitic capacitance between the horizontal conductors 29 can also be reduced.

[0229] Figure 27A A planar view of the nanosheet hierarchical structure is shown to describe the method of forming plug openings 47A to 47D. Figure 27B For along Figure 27A A cross-sectional view of the structure intercepted by line B-B' in the diagram. Figure 27C For along Figure 27A The cross-sectional view of the structure intercepted by line B1-B1'.

[0230] refer to Figures 27A to 27C A third pad isolation layer 40C can be formed to fill the pad isolation opening 44.

[0231] Subsequently, the sacrificial plugs 43A to 43D can be removed, and plug openings 47A to 47D can be formed. Then, the bottom surfaces of the contact spacers 42A to 42D can be cut, and the plug openings 47A to 47D can be enlarged.

[0232] The first plug opening 47A may be shallower than the second plug opening 47B, the second plug opening 47B may be shallower than the third plug opening 47C, and the third plug opening 47C may be shallower than the fourth plug opening 47D. The depth of the plug openings 47A to 47D may gradually become shallower along the stacking direction of the pads 46 (i.e., the first direction D1) (i.e., the plug openings 47A to 47D may have different depths).

[0233] The second plug opening 47B can penetrate the pad 46 in the first layer L1, and the third plug opening 47C can penetrate the pads 46 in the first layer L1 and the second layer L2. The fourth plug opening 47D can penetrate the pads 46 in the first to third layers L1, L2 and L3. The first plug opening 47A does not penetrate the pads 46 in the first layer L1.

[0234] The first plug opening 47A exposes the upper surface of the pad 46 in the first layer, the second plug opening 47B exposes the upper surface of the pad 46 in the second layer, the third plug opening 47C exposes the upper surface of the pad 46 in the third layer, and the fourth plug opening 47D exposes the upper surface of the pad 46 in the fourth layer. The first to fourth layers have been referenced. Figure 23B It has been described.

[0235] Figure 28A A planar diagram illustrating the nanosheet hierarchical structure is used to describe the method of forming contact plugs 48A to 48D. Figure 28B For along Figure 28A A cross-sectional view of the structure intercepted by line B-B' in the diagram. Figure 28C For along Figure 28A The cross-sectional view of the structure intercepted by line B1-B1'.

[0236] refer to Figures 28A to 28C Contact plugs 48A to 48D can be formed to fill plug openings 47A to 47D. Contact plugs 48A to 48D can be formed by deposition and planarization processes of plug material. Contact plugs 48A to 48D can all contain a metal-based material. For example, contact plugs 48A to 48D can be formed by deposition of a tungsten layer and chemical mechanical polishing (CMP).

[0237] Contact plugs 48A to 48D may include a structure in which their height gradually decreases along the stacking direction of the pads 46 (i.e., the first direction D1). Contact plugs 48A to 48D may be oriented perpendicularly along the first direction D1. Contact plugs 48A to 48D may be referred to as "contact posts".

[0238] As described above, pads 46, contact spacers 42A to 42D, and contact plugs 48A to 48D may be formed in the second region R2.

[0239] A first contact spacer 42A may be disposed on the side wall of a first contact plug 48A, and a second contact spacer 42B may be disposed on the side wall of a second contact plug 48B. A third contact spacer 42C may be disposed on the side wall of a third contact plug 48C, and a fourth contact spacer 42D may be disposed on the side wall of a fourth contact plug 48D. The vertical height of the fourth contact plug 48D may be greater than the vertical height of the third contact plug 48C, and the vertical height of the third contact plug 48C may be greater than the vertical height of the second contact plug 48B. The vertical height of the second contact plug 48B may be greater than the vertical height of the first contact plug 48A. Vertical height may refer to the height in the first direction D1.

[0240] The fourth contact plug 48D and the fourth contact spacer 42D can penetrate the first pad 46 and the inter-pad dielectric layer 39 in the first to third layers L1 to L3. The fourth contact plug 48D can be electrically isolated from the pads 46 in the first to third layers L1 to L3 through the fourth contact spacer 42D. The fourth contact plug 48D can be electrically coupled to the pad 46 in the fourth layer L4.

[0241] The third contact plug 48C and the third contact spacer 42C can penetrate the pads 46 in the first layer L1 and the second layer L2 and the inter-pad dielectric layer 39. The third contact plug 48C can be electrically isolated from the pads 46 in the first layer L1 and the second layer L2 through the third contact spacer 42C. The third contact plug 48C can be electrically coupled to the pads 46 in the third layer L3.

[0242] The second contact plug 48B and the second contact spacer 42B can penetrate the pad 46 and the inter-pad dielectric layer 39 in the first layer L1. The second contact plug 48B can be electrically isolated from the pad 46 in the first layer L1 through the second contact spacer 42B. The second contact plug 48B can be electrically coupled to the pad 46 in the second layer L2.

[0243] The first contact plug 48A can be electrically coupled to the pad 46 in the first level L1.

[0244] The second to fourth contact plugs 48B to 48D can form a stepless contact structure. In some embodiments, the number of contact plugs can be modified in various ways depending on the number of stacked memory cells.

[0245] Figure 29A A planar view of the nanosheet hierarchical structure is shown to describe the method for forming the second linear opening 49. Figure 29B For along Figure 29AThe cross-sectional view of the structure intercepted by line A-A' in the diagram.

[0246] refer to Figure 29A and Figure 29B The second linear sacrificial layer 19L can be removed using a fourth hard mask layer 49T as a blocking layer. This forms the second linear opening 49.

[0247] After the second linear opening 49 is formed, the first mold layer 12A can be selectively recessed through the second linear opening 49. To selectively recess the first mold layer 12A, the difference in etching selectivity between the first mold layer 12A and the original body portion 13A can be utilized. The first mold layer 12A can be removed using a wet etching process or a dry etching process. For example, when the first mold layer 12A comprises a silicon-germanium layer and the original body portion 13A comprises a monocrystalline silicon layer, an etchant or etching gas selective relative to the monocrystalline silicon layer can be used to etch the silicon-germanium layer.

[0248] Subsequently, the original body portion 13A can be recessed. To recess the original body portion 13A, a wet etching process or a dry etching process can be used. The vertical thickness of the original body portion 13A can be reduced, as indicated by the reference numeral "13S" in the attached figure. Hereinafter, the original body portion with reduced vertical thickness will be referred to as "recessed body portion 13S".

[0249] Each recess 12R between the body portions can be formed between the vertically arranged recessed body portions 13S.

[0250] Figure 30A This is a planar diagram showing the hierarchical structure of the narrow sheet, used to describe the method for forming nanosheets HL. Figure 30B It is along Figure 30A The cross-sectional view of the structure intercepted by line A-A' in the diagram.

[0251] refer to Figure 30A and Figure 30B A third inter-unit dielectric layer 50 can be formed to fill the inter-unit recess 12R. The third inter-unit dielectric layer 50 may contain silicon oxide.

[0252] After forming the third inter-unit dielectric layer 50, a second bottom protective layer 51T may be formed at the bottom of the second linear opening 49. The second bottom protective layer 51T may contain a material with etch selectivity relative to the substrate 11. The second bottom protective layer 51T may contain a dielectric material. The second bottom protective layer 51T may contain silicon oxide, silicon nitride, silicon carbide, or a combination thereof.

[0253] After forming the second bottom protective layer 51T, a storage opening 51 can be formed by a horizontal recess in the recessed body portion 13S. The storage opening 51 may be referred to as a "capacitor opening". The nanosheet HL can be formed by a horizontal recess in the recessed body portion 13S. Each nanosheet HL may include a narrow sheet 13N and a wide sheet 13W. The wide sheet 13W of the nanosheet HL may refer to the recessed body portion 13S retained after the recess. The average vertical height of the wide sheet 13W of the nanosheet HL in the first direction D1 may be greater than the average vertical height of the narrow sheet 13N. The thickness of the wide sheet 13W of the nanosheet HL may gradually increase in the second direction D2. The horizontal length of the wide sheet 13W in the second direction D2 may be less than the horizontal length of the narrow sheet 13N. The wide sheet 13W of the nanosheet HL may have a fan-shaped shape. The wide sheet 13W may be referred to as a "fan-shaped sheet", and the narrow sheet 13N may be referred to as a "flat sheet".

[0254] To form nanosheets HL, each including a wide wafer 13W, the recessed body portion 13S can be etched isotropically or anisotropically. One side of the wide wafer 13W, i.e., the side exposed by each storage opening 44, can have a flat shape. One side of the wide wafer 13W can have various shapes.

[0255] One side of the wide plate 13W can have various shapes. For example, one side of the wide plate 13W can have a rounded concave shape, a rounded convex shape, an angular concave shape, or an angular convex shape.

[0256] The second bottom protective layer 51T and the bottommost third inter-unit dielectric layer 50 can prevent the loss of substrate 11 during the recessing process of the recessed body portion 13S.

[0257] Each storage opening 51 can be disposed between the third inter-cell dielectric layers 50 along the first direction D1.

[0258] In some embodiments, the horizontal recess of the recessed body portion 13S used to form the wide piece 13W may stop at the boundary region between the narrow piece 13N and the wide piece 13W.

[0259] The first spacer 26 may surround a wide strip 13W that is positioned at the same level along the third direction D3. The second spacer 30 may surround a narrow strip 13N that is positioned at the same level along the third direction D3.

[0260] Figure 31A A plan view of the narrow-slice hierarchical structure is shown to describe the method of forming the second contact node 52. Figure 31B To show along Figure 31A The cross-sectional view of the structure intercepted by line A-A' in the diagram.

[0261] refer to Figure 31A and Figure 31B It can perform a pre-cleaning process on the surface of a 13W wide sheet.

[0262] The second contact node 52 may be formed on the wafer 13W. The method for forming the second contact node 52 may include selective epitaxial growth (SEG). For example, semiconductor material may be grown from the side surface of the wafer 13W via SEG. The second contact node 52 may contain SEG Si. Since the wafer 13W contains monocrystalline silicon, a silicon layer may be epitaxially grown along the crystal plane of the side surface of the wafer 13W.

[0263] The second contact node 52 may contain a dopant. When growing a silicon layer using SEG, dopant can be doped in situ. Therefore, the second contact node 52 may be a doped epitaxial layer. The second contact node 52 may contain an N-type dopant as a dopant. The N-type dopant may include phosphorus, arsenic, antimony, or a combination thereof. The second contact node 52 may include a phosphorus-doped silicon epitaxial layer formed by SEG, i.e., phosphorus-doped SEG silicon (SiP or Si:P). In some embodiments, the second contact node 52 may be formed by a deposition and etch-back process of doped polysilicon.

[0264] Each second contact node 52 may be disposed between the vertically stacked third inter-cell dielectric layers 50. The second contact node 52 may correspond to Figure 4B The second contact node SNC is shown.

[0265] The second doped region 53 may be formed in the wide wafer 13W. A thermal processing step may be performed to form the second doped region 53, so that the dopant can diffuse from the second contact node 52.

[0266] The channel 54 can be defined between the first doped region 34 and the second doped region 53. The horizontal arrangement of the first doped region 34, the channel 54 and the second doped region 53 can form each nanosheet HL.

[0267] Each nanosheet HL may include a first doped region 34, a second doped region 53, and a channel 54. The first doped region 34 and the channel 54 may be formed in a narrow wafer 13N. The second doped region 53 may be formed in a wide wafer 13W. A portion of each second doped region 53 may extend into the narrow wafer 13N. One side of each second doped region 53 of the nanosheet HL may be coupled to the channel 54. The other side of the second doped region 53 of the nanosheet HL may be coupled to a second contact node 52.

[0268] The first spacer 26 may surround a second doped region 53 at the same level as a third-direction D3. The second spacer 30 may surround a first doped region 34 at the same level as a third-direction D3. The horizontal conductor 29 may surround a channel 54 at the same level as a third-direction D3.

[0269] In some embodiments, an ohmic contact layer comprising metal silicide may also be formed after the second contact node 52 is formed.

[0270] As described above, the nanosheets HL can be formed by a subsequent selective recessing process performed on the second mold layer 13 of the mold stack SB. Each nanosheet HL may include a narrow wafer 13N and a wide wafer 13W. A first doped region 34 and a channel 54 may be formed in the narrow wafer 13N, and a second doped region 53 may be formed in the wide wafer 13W.

[0271] Figure 32A A plan view of the narrow-layer structure is shown to describe the method of forming the first electrode 55. Figure 32B For along Figure 32A A cross-sectional view of the structure intercepted by line A-A'.

[0272] refer to Figure 32A and Figure 32B The first electrode 55 of the data storage element may be formed on the second contact node 52. Each first electrode 55 may have a horizontally oriented cylindrical shape, and each first electrode 55 may be disposed in a different storage opening 51. First electrodes 55 adjacent to each other in the second direction D2 may be spaced apart by a second linear opening 49. First electrodes 55 adjacent to each other in the first direction D1 may be spaced apart by a third inter-cell dielectric layer 50. Forming the first electrode 55 may include: depositing a metallic material, filling a gap with a sacrificial material, and isolating a metallic material in the vertical / horizontal directions. The sacrificial material may include oxide or polysilicon.

[0273] Each first electrode 55 may include an internal space and multiple outer surfaces. The internal space of the first electrode 55 may include multiple inner surfaces. The outer surfaces of the first electrode 55 may include a vertical outer surface and multiple horizontal outer surfaces. The vertical outer surface of the first electrode 55 may extend vertically along a first direction D1. The horizontal outer surfaces of the first electrode 55 may extend horizontally along a second direction D2 or a third direction D3. The internal space of the first electrode 55 may be three-dimensional, and the first electrode 55 may have a cylindrical shape.

[0274] In the outer surface of the first electrode 55, the vertical outer surface can be electrically coupled to the nanosheet HL and the second contact node 52.

[0275] The first electrode 55 may comprise a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 55 may comprise titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, or a combination thereof.

[0276] Figure 33A To illustrate the plan view of the narrow-layer structure, a method for describing the partial recess of the third inter-unit dielectric layer 50 is used. Figure 33B For along Figure 33A The cross-sectional view of the structure intercepted by line A-A' in the diagram.

[0277] refer to Figure 33A and Figure 33B The first inter-unit dielectric layer 23 and the third inter-unit dielectric layer 50 may be partially recessed horizontally (refer to reference numeral "56" in the figures). Therefore, the outer wall of the first electrode 55 may be partially exposed. Each first electrode 55 may have a semi-cylindrical shape. The horizontal recess depth of the third inter-unit dielectric layer 50 may be a depth that does not expose the second contact node 52. The semi-cylindrical shape of each first electrode 55 may include a cylindrical inner surface and a semi-cylindrical outer surface.

[0278] Figure 34A A planar diagram illustrating the nanosheet hierarchical structure is used to describe the method for forming the second electrode 58. Figure 34B For along Figure 34A The cross-sectional view of the structure intercepted by line A-A' in the diagram.

[0279] refer to Figure 34A and Figure 34B A dielectric layer 57 and a second electrode 58 may be sequentially formed on the first electrode 55. The first electrode 55, the dielectric layer 57, and the second electrode 58 may be data storage elements CAP. The second electrodes 58 of the data storage elements CAP may be merged together to form a common electrode plate PL.

[0280] The dielectric layer 57 and the second electrode 58 may be disposed on the cylindrical inner surface of the first electrode 55. A portion of the dielectric layer 57 and a portion of the second electrode 58 may extend to be disposed on the semi-cylindrical outer surface of the first electrode 55.

[0281] The dielectric layer 57 may be referred to as a "capacitor dielectric layer" or a "storage layer". The dielectric layer 57 may comprise silicon oxide, silicon nitride, high-k materials, ferroelectric materials, antiferroelectric materials, perovskite materials, or combinations thereof. The dielectric layer 57 may comprise hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or titanium strontium oxide (SrTiO3). Dielectric layer 57 may comprise ZA (ZrO2 / Al2O3) stacks, ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stacks, ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stacks, HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stacks, HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stacks, and HZAZH (HfO2 / ZrO2 / Al2O3 / ZrO2) stacks. Stacked in the following formats: / HfO2), ZHZAZHZ(ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2), HZHZ(HfO2 / ZrO2 / HfO2 / ZrO2), AHZAZHA(Al2O3 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / Al2O3), or AHZAHZA(Al2O3 / HfO2 / ZrO2 / Al2O3 / HfO2 / ZrO2 / Al2O3).

[0282] The second electrode 58 may comprise a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the second electrode 58 may comprise titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, titanium silicon nitride / titanium nitride / tungsten (TiSiN / TiN / W) stacks, or a combination thereof. The second electrode 58 may also comprise a combination of metal-based materials and silicon-based materials. For example, titanium nitride, tungsten, and polycrystalline silicon may be sequentially stacked in the second electrode 58.

[0283] In some embodiments, multiple interface control layers may be included between the first electrode 55 and the dielectric layer 57, and between the dielectric layer 57 and the second electrode 58, to mitigate leakage current. Each interface control layer may comprise titanium dioxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), niobium oxynitride (NbON), or combinations thereof. The data storage element CAP may include a first interface control layer, a second interface control layer, or a combination thereof. The first and second interface control layers may be conductive layers or dielectric layers, wherein the first interface control layer may be formed between the first electrode 55 and the dielectric layer 57, and the second interface control layer may be formed between the dielectric layer 57 and the second electrode 58. The first and second interface control layers may be made of the same material or different materials. For example, the structure of the data storage element CAP, in which the first interface control layer, the dielectric layer 57 and the second interface control layer are stacked in sequence, may include NZHZAZHZATN (Nb2O5 / ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2 / Nb2O5) stack.

[0284] In some embodiments, this can be omitted. Figure 33B The recesses in the first inter-unit dielectric layer 23 and the third inter-unit dielectric layer 50 are shown. Thereafter, as... Figure 34B As shown, a dielectric layer 57 and a second electrode 58 can be formed. Therefore, a data storage element CAP including a first electrode 55 having a concave shape can be formed.

[0285] Figures 35 to 37 This is a schematic cross-sectional view of semiconductor devices 200, 210 and 220 according to an embodiment of the present disclosure. Figures 35 to 37 Can be with Figures 4A to 4E The semiconductor device 100 shown is similar. (See above for reference.) Figures 4A to 4E The overlapping component is described in detail.

[0286] refer to Figures 35 to 37 Semiconductor devices 200, 210, and 220 may each include a first region R1 and a second region R2. Each second conductor WL in the first region R1 may be coupled to a different pad among pads WP1 to WP4. Each second conductor WL may include an edge portion WE with a concave shape. Each pad WP1 to WP4 may include an inner edge PE. The inner edge PE of each pad WP1 to WP4 may have a convex shape. The inner edge PE of each pad WP1 to WP4 may be disposed within the internal space of the edge portion WE of the second conductor WL. The inner edge PE of each pad WP1 to WP4 may be electrically coupled to the edge portion WE of the second conductor WL. The inner edge PE of each pad WP1 to WP4 and the edge portion WE of the second conductor WL may contact a first spacer SP1.

[0287] The second region R2 may include an alternating stack of pads WP1 to WP4 and an inter-pad dielectric layer P1L, and an array of contact plugs CT1 to CT4 disposed in the alternating stack. These contact plugs are laterally spaced from each other in a first horizontal direction (i.e., the third horizontal direction D3) and have different heights. The top surfaces of the contact plugs CT1 to CT4 may be disposed on the same horizontal plane, and the bottom surfaces of the contact plugs CT1 to CT4 may be adjacent to the pads WP1 to WP4 respectively.

[0288] The first contact plug CT1 is electrically coupled to the first pad WP1 in the first layer L1, and can be electrically coupled to the second conductor WL in the first layer L1 through the first pad WP1. The second contact plug CT2 is electrically coupled to the second pad WP2 in the second layer L2, and can be electrically coupled to the second conductor WL in the second layer L2 through the second pad WP2. The third contact plug CT3 is electrically coupled to the third pad WP3 in the third layer L3, and can be electrically coupled to the second conductor WL in the third layer L3 through the third pad WP3. The fourth contact plug CT4 is electrically coupled to the fourth pad WP4 in the fourth layer L4, and can be electrically coupled to the second conductor WL in the fourth layer L4 through the fourth pad WP4.

[0289] The first contact spacer CTS1 can be disposed on the side wall of the first contact plug CT1, and the second contact spacer CTS2 can be disposed on the side wall of the second contact plug CT2. The third contact spacer CTS3 can be disposed on the side wall of the third contact plug CT3, and the fourth contact spacer CTS4 can be disposed on the side wall of the fourth contact plug CT4. The vertical height of the fourth contact plug CT4 can be greater than the vertical height of the third contact plug CT3, and the vertical height of the third contact plug CT3 can be greater than the vertical height of the second contact plug CT2. The vertical height of the second contact plug CT2 can be greater than the vertical height of the first contact plug CT1. The vertical height can refer to the height in the first direction D1.

[0290] The fourth contact plug CT4 and the fourth contact spacer CTS4 can penetrate the pads WP1, WP2, and WP3 located in the first layer L1, the second layer L2, and the third layer L3. The fourth contact plug CT4 can be electrically isolated from the pads WP1, WP2, and WP3 located in the first layer L1, the second layer L2, and the third layer L3 through the fourth contact spacer CTS4.

[0291] The third contact plug CT3 and the third contact spacer CTS3 can penetrate the pads WP1 and WP2 located in the first layer L1 and the second layer L2. The third contact plug CT3 can be electrically isolated from the pads WP1 and WP2 located in the first layer L1 and the second layer L2 by the third contact spacer CTS3.

[0292] The second contact plug CT2 and the second contact spacer CTS2 can penetrate the pad WP1 in the first layer L1. The second contact plug CT2 can be electrically isolated from the pad WP1 in the first layer L1 by the second contact spacer CTS2.

[0293] The first pad WP1 may surround the sides of the second to fourth contact plugs CT2, CT3, and CT4. The second pad WP2 may surround the sides of the third contact plug CT3 and the fourth contact plug CT4. The third pad WP3 may surround the side of the fourth contact plug CT4.

[0294] The first pad WP1 can directly contact the bottom surface of the first contact plug CT1. The second pad WP2 can directly contact the bottom surface of the second contact plug CT2. The third pad WP3 can directly contact the bottom surface of the third contact plug CT3. The fourth pad WP4 can directly contact the bottom surface of the fourth contact plug CT4.

[0295] refer to Figure 35 The contact spacers CTS1 to CTS4 can all contain low-k materials, such as SiCOH and SiOF.

[0296] Contact pads (CTLs) can be formed on the sidewalls of individual contact spacers (CTS1 to CTS4). The contact pads (CTLs) and contact spacers (CTS1 to CTS4) can be made of different materials. The contact pads (CTLs) can all contain oxides, nitrides, or combinations thereof. The contact pads (CTLs) enhance the interfacial adhesion between the contact spacers (CTS1 to CTS4) and the dielectric layer (PIL) between the pads. The contact pads (CTLs) can also be used to reduce silicon loss.

[0297] The inter-pad dielectric layer (PIL) can contain low-k materials, such as SiCOH or SiOF.

[0298] refer to Figure 36 Contact spacers CTS1 to CTS4 may each contain low-k materials, such as SiCOH and SiOF. Contact pads CTL may be formed on the sidewalls of each contact spacer CTS1 to CTS4. Contact pads CTL may each contain oxides, nitrides, or combinations thereof.

[0299] Inter-pad spacers (ILLs) can be formed between the inter-pad dielectric layer (PIL) and pads WP1 to WP4. The inter-pad spacers (ILLs) can cover the outer surface of the inter-pad dielectric layer (PIL). The inter-pad spacers (ILLs) can directly contact pads WP1 to WP4. The inter-pad spacers (ILLs) and the inter-pad dielectric layer (PIL) can be made of different materials. The inter-pad dielectric layer (PIL) can be a low-k material, and the inter-pad spacers (ILLs) can have a higher dielectric constant than the inter-pad dielectric layer (PIL). The inter-pad spacers (ILLs) can contain oxides, nitrides, or combinations thereof. The inter-pad spacers (ILLs) can enhance the interfacial adhesion between the pad sidesheets and the inter-pad dielectric layer (PIL) during the formation of the inter-pad dielectric layer (PIL).

[0300] The inter-pad dielectric layer (PIL) can contain low-k materials, such as SiCOH or SiOF.

[0301] refer to Figure 37 Contact spacers CTS1 to CTS4 may contain low-k materials, such as SiCOH and SiOF. The inter-pad dielectric layer PIL may contain low-k materials, such as SiCOH or SiOF. Inter-pad spacers ILL may be formed between the inter-pad dielectric layer PIL and the pads WP1 to WP4. Inter-pad spacers ILL may contain oxides, nitrides, or combinations thereof.

[0302] Figure 35 The semiconductor device 200 shown may not include the pad spacer ILL. Figure 37 The semiconductor device 220 shown may not include the contact pad layer CTL. Figure 36 The semiconductor device 210 shown may include inter-pad pads ILL and contact pads CTL.

[0303] exist Figures 4A to 4E In the semiconductor device 100 shown, the inter-pad dielectric layer PIL and the contact spacers CTS1 to CTS4 may each contain low-k material. The semiconductor device 100 may not include the inter-pad pad ILL and the contact pad CTL.

[0304] Figure 35 and Figure 36 The semiconductor devices 200 and 210 shown can reduce the parasitic capacitance between the pads WP1 to WP3 surrounding the contact plugs CT2 to CT4 because the contact spacers CTS1 to CTS4 all contain low-k material.

[0305] Figures 35 to 37The semiconductor devices 200, 210, and 220 shown can reduce the parasitic capacitance between pads WP1 to WP4 because the inter-pad dielectric layers PIL all contain low-k materials with a dielectric constant of 4 or lower (e.g., 2.0 to 3.5). Therefore, the operating speed of semiconductor devices 200, 210, and 220 can be increased, and the power consumption of semiconductor devices 200, 210, and 220 can be reduced.

[0306] because Figure 35 and Figure 36 The semiconductor devices 200 and 210 shown both include contact pads CTL, which enhances the interfacial adhesion between the contact spacers CTS1 to CTS4 and the dielectric layer PIL between the pads.

[0307] because Figure 36 and Figure 37 The semiconductor devices 210 and 220 shown both include inter-pad pads ILL, which enhances the interfacial adhesion between the pad sidesheets and the inter-pad dielectric layer PIL.

[0308] exist Figures 35 to 37 In the semiconductor devices 200, 210, and 220 shown, the pads WP1 to WP4 in the second region R2 may have a stepless structure. Since the pads WP1 to WP4 are formed with a stepless structure, the area or volume occupied by the pads WP1 to WP4 in the second region R2 can be reduced.

[0309] Figure 38 This is a schematic cross-sectional view of a semiconductor device 230 according to an embodiment of the present disclosure. Figure 38 The semiconductor device 230 shown can be used with Figures 4A to 4E The semiconductor device 100 shown is similar. (See above for reference.) Figures 4A to 4E The overlapping components are described in detail.

[0310] refer to Figure 38 The semiconductor device 230 may include a first vertical conductor BLA and a second vertical conductor BLB. The bottom BLBs of the first vertical conductor BLA and the second vertical conductor BLB may be isolated from each other (refer to the reference numeral "BLT" in the figures).

[0311] Figure 39A and Figure 39B These are schematic cross-sectional views of semiconductor devices 300 and 301 according to embodiments of the present disclosure.

[0312] refer to Figure 39ASemiconductor device 300 may include a memory cell array MCA, a peripheral circuit portion PERI, and a bonding interface BS. The bonding interface BS may be disposed between the memory cell array MCA and the peripheral circuit portion PERI. In semiconductor device 300, the memory cell array MCA may be disposed at a level higher than the peripheral circuit portion PERI. Semiconductor device 300 may be referred to as a "peri (PUC) structure under a cell array". The memory cell array MCA may include a substrate on which back-side grinding has been performed and a memory cell array. For example, as referenced... Figure 34B After forming the data storage element CAP, the substrate 11 can be flipped by wafer flipping, and then the back side of the substrate 11 can be partially ground.

[0313] refer to Figure 39B Semiconductor device 301 may include a memory cell array (MCA), a peripheral circuitry section (PERI), and a bonding interface (BS). The bonding interface BS may be disposed between the memory cell array (MCA) and the peripheral circuitry section (PERI). In semiconductor device 301, the memory cell array (MCA) may be disposed below the level of the peripheral circuitry section (PERI). Semiconductor device 301 may be referred to as a "peri-under-cell array (CUP) structure". Forming the peripheral circuitry section (PERI) may include forming multiple control circuits on the peripheral circuitry substrate and forming multi-level interconnects on the control circuits.

[0314] exist Figure 39A and Figure 39B In this context, the bonding interface BS may include pad bonding, hybrid bonding, oxide-oxide bonding, metal-metal bonding, or a combination thereof. Hybrid bonding may refer to a combination of pad bonding and oxide-oxide bonding. Pad bonding may include: cell bonding pads forming the memory cell array (MCA); peripheral circuit bonding pads forming the peripheral circuit portion (PERI); performing wafer flipping to make the cell bonding pads and peripheral circuit bonding pads face each other; and performing wafer bonding.

[0315] Figure 39A After forming cell bonding pads and peripheral circuit bonding pads, the semiconductor device 300 shown can perform wafer flipping on the substrate on which the memory cell array is formed, so that the cell bonding pads and peripheral circuit bonding pads face each other. Figure 39B The semiconductor device 301 shown can perform wafer flipping on the substrate on which the peripheral circuit portion is formed after forming the unit bonding pads and the peripheral circuit bonding pads, so that the unit bonding pads and the peripheral circuit bonding pads face each other.

[0316] Figure 40A and Figure 40B Various views of stacked components 400 and 500 according to embodiments of this disclosure are shown.

[0317] refer to Figure 40A The stacked assembly 400 may include a component of semiconductor dies. For example, the stacked assembly 400 may include a first semiconductor die BSD and a plurality of second semiconductor dies 401. The first semiconductor die BSD may include logic circuitry. Each second semiconductor die 401 may include a memory cell array according to the above embodiments.

[0318] Each second semiconductor die 401 may include a structure in which a memory cell array stack and a peripheral circuit portion are stacked, for example Figure 39A The semiconductor device 300 shown Figure 39B The semiconductor device 301 is shown. The logic circuitry of the first semiconductor die BSD may differ from the peripheral circuitry of the second semiconductor die 401. The second semiconductor die 401 may be chip-level or wafer-level.

[0319] The second semiconductor die 401 can be electrically coupled to each other through multiple through-silicon vias (TSVs) and bonding interfaces (CBSs). The first semiconductor die BSD and the bottommost second semiconductor die 401 can be electrically coupled to each other through the bonding interface (CBS). The second semiconductor die 401 can be referred to as a "core die", "semiconductor chip", or "memory chip".

[0320] Bonding interfaces (CBS) may include microbump bonding, pad bonding, hybrid bonding, oxide-oxide bonding, metal-metal bonding, or combinations thereof.

[0321] refer to Figure 40B The stacked assembly 500 may include a component of semiconductor dies. For example, the stacked assembly 500 may include a first semiconductor die BSD, a plurality of second semiconductor dies 501, and a plurality of third semiconductor dies 502. The first semiconductor die BSD may include logic circuitry. Each second semiconductor die 501 and each third semiconductor die 502 may include a memory cell array according to the above embodiments. The second semiconductor dies 501 and the third semiconductor dies 502 may have different structures.

[0322] Each second semiconductor die 501 may include Figure 39A The semiconductor device 300 shown includes a memory cell array stacked on top of a peripheral circuitry portion. Each third semiconductor die 502 may include... Figure 39B The semiconductor device 301 shown has a peripheral circuit portion stacked on top of the memory cell array.

[0323] In some embodiments, each second semiconductor die may include Figure 39B The semiconductor device 301 shown includes peripheral circuitry stacked on top of a memory cell array, and each third semiconductor die 502 may include... Figure 39A The semiconductor device 300 shown has a memory cell array stacked on top of a peripheral circuit portion.

[0324] The logic circuitry of the first semiconductor die BSD may differ from the peripheral circuitry of the second semiconductor die 501 and the third semiconductor die 502. The second semiconductor die 501 and the third semiconductor die 502 may be chip-level or wafer-level.

[0325] The second semiconductor die 501 and the third semiconductor die 502 are electrically coupled to each other through multiple through-silicon vias (TSVs) and bonding interfaces (CBSs). The first semiconductor die BSD and the bottommost second semiconductor die 501 are electrically coupled to each other through the bonding interface (CBS). The second semiconductor die 501 and the third semiconductor die 502 may be referred to as "core dies," "semiconductor chips," or "memory chips."

[0326] Bonding interfaces (CBS) may include microbump bonding, pad bonding, hybrid bonding, oxide-oxide bonding, metal-metal bonding, or combinations thereof.

[0327] refer to Figure 40A and Figure 40B The stacked components 400 and 500 described may be high-bandwidth memories.

[0328] According to various embodiments of this disclosure, parasitic capacitance between pads surrounding the contact plug can be reduced because the contact spacers all contain a low-k material.

[0329] According to various embodiments of this disclosure, the contact spacers provided in the embodiments of this disclosure all contain low-k materials, which can improve the speed of semiconductor devices and reduce power consumption.

[0330] According to various embodiments of this disclosure, the reliability of 3D storage devices can be improved, including data retention, durability (program / erase P / E cycles), temperature cycling, and electrostatic discharge (ESD) resistance.

[0331] While embodiments of this disclosure have been described and illustrated in conjunction with specific examples and accompanying drawings, the disclosed embodiments are not intended to limit this disclosure. Furthermore, it will be noted that those skilled in the art will recognize from this disclosure that embodiments can be implemented in various ways through substitutions, changes, and modifications without departing from the spirit and / or scope of this disclosure and the appended claims. Moreover, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: Vertically and horizontally arranged nanosheets; Horizontal wires surrounding the horizontally arranged nanosheets; A pad that is coupled to the edge portion of the horizontal conductor; A dielectric layer between the pads is disposed between the pads; Contact plugs, each of the contact plugs being coupled to a different pad among the pads; and Contact spacers, each of the contact spacers comprising a first low-k material and each of the contact spacers being formed on the sidewall of each of the contact plugs.

2. The semiconductor device according to claim 1, wherein, The first low-k material has a lower dielectric constant than silicon oxide (SiO2).

3. The semiconductor device according to claim 1, wherein, The first low-k material has a lower dielectric constant than silicon carbide (SiCO).

4. The semiconductor device according to claim 1, wherein, The first low-k material includes SiCOH, SiOF, or a combination thereof.

5. The semiconductor device according to claim 1, wherein, Each of the said inter-pad dielectric layers contains a second low-k material.

6. The semiconductor device according to claim 5, wherein, The second low-k material has a lower dielectric constant than silicon carbide (SiCO).

7. The semiconductor device according to claim 6, wherein, The second low-k material includes SiCOH, silicon oxyfluoride (SiOF), or a combination thereof.

8. The semiconductor device according to claim 1, wherein, The horizontal lengths of the pads have the same structure.

9. The semiconductor device according to claim 1, wherein, The edge portions of the horizontal conductors all include concave shapes, and the pads include edges, the edges of which all have convex shapes, and the edges of the pads directly contact the inner surface of the edge portions of the horizontal conductors.

10. The semiconductor device according to claim 1, further comprising: Vertical wires coupled to the vertically arranged nanosheets; and Data storage element, each of the data storage elements being coupled to a different nanosheet among the vertically arranged and horizontally arranged nanosheets.

11. The semiconductor device of claim 10, further comprising: A first contact node is formed between the nanosheet and the vertical wire; and A second contact node is formed between the nanosheet and the data storage element.

12. The semiconductor device according to claim 1, further comprising: A contact pad is formed on the sidewall of the contact spacer.

13. The semiconductor device according to claim 1, further comprising: An inter-pad pad is formed between the inter-pad dielectric layer and the pad.

14. The semiconductor device according to claim 1, further comprising: A contact pad is formed on the sidewall of the contact spacer; and Inter-pad spacers are formed between the inter-pad dielectric layer and the pads. Both the contact pads and the pads between the solder pads contain dielectric material.

15. The semiconductor device according to claim 1, wherein, The contact plugs have different vertical heights.

16. A semiconductor device, comprising: Vertically and horizontally arranged nanosheets; Horizontal wires surrounding the horizontally arranged nanosheets; A stepless structure comprising horizontally oriented pads coupled to the edge portion of the horizontal conductor and a low-k inter-pad dielectric layer formed between the horizontally oriented pads. Vertically oriented contact plugs, each of which is coupled to a different pad among the horizontally oriented pads; and A low-k spacer surrounds the outer wall of the corresponding contact plug.

17. The semiconductor device of claim 16, further comprising: Contact pads are formed on the sidewalls of the low-k spacer; and Pad spacers are formed between the low-k pad dielectric layer and the pads.

18. The semiconductor device according to claim 16, wherein, Both the low-k spacer and the dielectric layer between the low-k pads have lower dielectric constants than silicon carbide (SiCO) and silicon oxide (SiO2).

19. The semiconductor device according to claim 16, wherein, Both the low-k spacer and the dielectric layer between the low-k pads contain SiCOH, SiOF, or a combination thereof.

20. The semiconductor device of claim 16, further comprising: Vertical wires coupled to the vertically arranged nanosheets; Data storage element, each of the data storage elements being coupled to a different nanosheet among the vertically arranged and horizontally arranged nanosheets; A first contact node is formed between the nanosheet and the vertical wire; and A second contact node is formed between the nanosheet and the data storage element.

21. A method for manufacturing a semiconductor device, the method comprising: An alternating stack of dielectric layers between sacrificial wafers and pads is formed on the substrate; A contact hole is formed, the height of which gradually decreases along the stacking direction of the dielectric layer between the sacrificial piece and the pad in the alternating stack; A low-k spacer is formed on the sidewall of the contact hole; A sacrificial plug is formed, and each of the sacrificial plugs fills a different contact hole in the contact hole on the low-k spacer; Remove the alternately stacked sacrificial pieces and form a pad-shaped opening; Forming a pad that fills the pad-shaped opening; Remove the sacrificial plug and form a plug opening; Cut a portion of the low-k spacer through the plug opening and expose the pads; as well as A contact plug is formed that fills the plug opening and is coupled to the pad.

22. The method of claim 21, further comprising: Before forming the low-k spacer, a contact pad is formed on the sidewall of the contact hole.

23. The method according to claim 22, wherein, The contact pad comprises oxides, nitrides, or combinations thereof.

24. The method according to claim 21, wherein, Both the low-k spacer and the inter-pad dielectric layer contain SiCOH, SiOF, or a combination thereof.

25. The method according to claim 21, wherein, The contact holes are formed horizontally spaced apart from each other and have different depths.

26. The method according to claim 21, wherein, Forming the contact hole includes etching the alternating stacks to have a stepless structure by using multiple masking processes and multiple etching processes.

27. The method of claim 21, further comprising: Before the alternating stacks are formed A vertically stacked layer of nanosheet targets spaced apart from each other is formed on the substrate; Trim the first portion of the nanosheet target layer and form a flat sheet; Form horizontally oriented wires surrounding the flat sheet; as well as A vertical conductor is formed that is coupled to the flat plate.

28. The method of claim 27, further comprising: After the pads are formed The second portion of the nanosheet target layer is horizontally recessed to form a fan-shaped sheet; Contact nodes are selectively grown on the side of the corresponding sector; as well as Data storage elements are formed, each of which is coupled to a different contact node among the contact nodes.

29. The method according to claim 21, wherein, The alternating stacking of the dielectric layer between the sacrificial wafer and the pad on the substrate includes: Forming, on the substrate, inter-pad recesses between the sacrificial pads and the sacrificial pads; and A low-k dielectric layer is formed to fill the depressions between the pads, thereby forming the inter-pad dielectric layer.

30. The method of claim 29, further comprising: Before forming the low-k dielectric layer, an inter-pad pad is conformally formed on the inter-pad recess.

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