Image processing device

Abstract

To improve the overall productivity of the equipment. [Solution] In an image processing device 1 that uses a single bus line for both image data transfer and register setting, the device includes a CPU that transmits image data and sets the registers, an FPGA that processes the repeated use of received image data, and an image data detection unit 21 located in the CPU that detects the repetition of blank area images and notifies the FPGA. When a blank area image is detected, the CPU transmits the first line of image data and stops transmitting subsequent image data. The FPGA, upon receiving the notification, processes the repeated use of image data by reusing the received image data instead of the next line of image data, thereby allocating the freed bus line to register setting.

Description

Technical Field

[0001] The present invention relates to an image processing apparatus that improves the productivity of the entire apparatus.

Background Art

[0002] Conventionally, an apparatus that connects between two chips with a single bus and uses that bus for both register control and image data transfer is well known.

[0003] In such an apparatus, when transferring a plurality of image data continuously, since register updates specific to the image data enter between the image data, the overall transfer time is the sum of the transfer times of the image data and the register.

[0004] Generally, in an apparatus having such a configuration, it is difficult to take measures to ensure bandwidth using techniques such as increasing the bus clock speed or data compression technology due to insufficient hardware resources. As a result, the productivity of transferring a plurality of image data is limited by the sum of the bus usage times for image data and register access. <##

[0005] Patent Document 1 discloses a technique for reducing the number of accesses to memory, simplifying video data transfer processing, and reducing the burden on the system bus.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] This invention has been made in view of the above problems, and aims to provide an image processing apparatus that can improve the overall productivity of the apparatus. [Means for solving the problem]

[0009] To achieve the above objective, the first feature of the image processing apparatus according to the present invention is: In an image processing device that uses a single bus line for both image data transfer and register setting, The master control unit that transmits the image data and sets the register, A slave control unit that processes the received image data for repeated use, The master control unit includes an image data detection unit that detects repetitions of margin images and notifies the slave control unit, When the aforementioned blank area image is detected, the master control unit transmits the image data for the first line and stops transmitting subsequent image data. The slave control unit, upon receiving the notification, then performs a process of repeatedly using the image data, reusing the received image data instead of the next line of image data, and allocates the freed bus line to the register setting. [Effects of the Invention]

[0010] The features of the image processing apparatus according to the present invention make it possible to improve the productivity of the entire apparatus. [Brief explanation of the drawing]

[0011] [Figure 1] This is a schematic functional configuration diagram of the image processing apparatus of Embodiment 1 of the present invention. [Figure 2] This figure shows an example of image data used for printing by the image processing apparatus of Embodiment 1 of the present invention. [Figure 3] This is an explanatory diagram illustrating the effects of the image processing apparatus in Example 1 of the present invention. [Figure 4]Figure 4(a) is a timing chart showing the processing time in the image processing apparatus of the embodiment of the present invention when there is no margin, and Figure 4(b) is a timing chart showing the processing time in the image processing apparatus of Embodiment 1 of the present invention when there is a margin. [Figure 5] This flowchart shows the processing details of the image transfer process at the top of the image data in the image processing apparatus of Embodiment 1 of the present invention. [Figure 6] This flowchart shows the processing details of the image transfer process at the bottom of the image data in the image processing apparatus of Embodiment 1 of the present invention. [Modes for carrying out the invention]

[0012] Embodiments of the present invention will be described below with reference to the drawings. Throughout the drawings, identical or equivalent parts and components are denoted by the same or equivalent reference numerals. However, it should be noted that the drawings are schematic and may differ from reality. Furthermore, there are parts where the dimensional relationships and proportions differ between drawings.

[0013] Furthermore, the embodiments shown below are illustrative examples of devices and the like for realizing the technical concept of this invention, and the technical concept of this invention is not limited to the arrangement of each component as described below. The technical concept of this invention can be modified in various ways within the scope of the claims.

[0014] <Example 1> Figure 1 is a schematic functional configuration diagram of the image processing apparatus 1 of Embodiment 1 of the present invention.

[0015] As shown in Figure 1, the image processing apparatus 1 of Embodiment 1 of the present invention has a CPU (reference numeral 2) which is a master control unit and an FPGA (reference numeral 4) which is a slave control unit, connected by a bus 10.

[0016] An FPGA (symbol: 4) is electrically connected to a print head 5. The print head 5 prints by ejecting ink onto paper based on image data transmitted from the FPGA (symbol: 4).

[0017] A CPU (symbol: 2) is electrically connected to a memory 3. The memory 3 is composed of, for example, a DRAM (Dynamic Random Access Memory) and temporarily stores image data and the like.

[0018] The CPU (symbol: 2) executes central processing including transmission of image data and has its functions, an image data detection unit 21 and a register setting unit 22.

[0019] The image data detection unit 21, which is inside the CPU (symbol: 2), detects repetition of the margin part image and notifies the FPGA (symbol: 4) of the detection result of the repetition of the margin part image via a bus 10.

[0020] The register setting unit 22 performs register setting inside the CPU (symbol: 2).

[0021] The FPGA (symbol: 4) executes processing for repeated use of the image data received from the CPU (symbol: 2).

[0022] FIG. 2 is a diagram showing an example of image data used for printing by the image processing apparatus 1 according to Embodiment 1 of the present invention.

[0023] As shown in FIG. 2, the image data G includes an image portion G2 containing characters, photographs, and the like. The image data G includes a margin portion G1, which is white paper not containing characters, photographs, etc., above the image portion G2, and a margin portion G3, which is white paper not containing characters, photographs, etc., below the image portion G2.

[0024] The margin areas G1 and G3 are margins, and therefore contain repeated data. By transferring only the first line of the image in these margin areas G1 and G3, and notifying the recipient that the data within the margin section will be repeated from the next time onward, the transfer can be made more efficient.

[0025] Therefore, when the image data detection unit 21 detects a blank area image, the CPU (code: 2) transmits the image data for the first line and stops transmitting subsequent image data.

[0026] Upon receiving notification that a blank area has been detected, FPGA (symbol 4) performs an image data reuse process, reusing the image data for the first line received instead of the next line image data, which is the blank area. Meanwhile, FPGA (symbol 4) assigns the now-empty bus line to register settings.

[0027] Figure 3 is an explanatory diagram illustrating the effects of the image processing apparatus 1 in Embodiment 1 of the present invention.

[0028] Figure 3 shows, for comparison, the processing time TM1 using the conventional technology and the processing time TM2 using the image processing apparatus 1 of Example 1 of the present invention.

[0029] As shown in processing time TM1, in the conventional technology, register setting starts at time t11, image data transfer starts at time t13, and the transfer of the first image data is completed at time t15.

[0030] Then, between time t15 and t17, the transfer of the second image data is completed, and between time t17 and t19, the transfer of the third image data is completed. In other words, it takes the time from time t1 to t19 to transfer three image data files. Thus, in conventional technology, when multiple image data files are transferred sequentially, register updates specific to each image data file occur between the image data files, so the total transfer time is the sum of the transfer times between the image data files and the registers.

[0031] On the other hand, as shown in processing time TM2, in the image processing apparatus 1 of Embodiment 1 of the present invention, register setting is started at time t11, image data transfer is started at time t13, and at time t21, when the image data detection unit 21 detects a blank area image, it transmits the image data for the first line and stops transmitting subsequent image data.

[0032] From the time point t21 when it stopped until time point t15, the FPGA (code: 4) performs image data reuse processing, reusing the image data of the first line received instead of the next line image data which is blank space.

[0033] From time t23, FPGA (code: 4) assigns the available bus lines to register settings, and then begins transferring the second image data. This process is repeated. As a result, the time from time t1 to time t29 is sufficient to transfer all three image data.

[0034] In this way, when image data is sent from the CPU (code: 2) to the FPGA (code: 4) via bus 10, if there is any blank image in the image data to be sent, this can be detected and the image data can be reused, thereby reducing the time that bus 10 is occupied and improving the productivity of the entire device.

[0035] Figure 4(a) is a timing chart showing the processing time in the image processing apparatus 1 of Embodiment 1 of the present invention when there is no margin, and Figure 4(b) is a timing chart showing the processing time in the image processing apparatus 1 of Embodiment 1 of the present invention when there is a margin.

[0036] As shown in Figure 4(a), if there is no space at the beginning, after the time D101 for register setting, there is an image data transmission request R1 synchronized with the horizontal synchronization frequency, and the image data is transferred during the image data transfer time D105. Similarly, thereafter, whenever there is an image data transmission request R1 synchronized with the horizontal synchronization frequency, the process of transferring the image data is repeatedly executed.

[0037] On the other hand, as shown in Figure 4(b), if there is a blank space at the beginning, after the time D201 for register setting, there is an image data transmission request R1 synchronized with the horizontal synchronization frequency.

[0038] In the example shown in Figure 4(b), there is a blank space at the beginning, so the first line of image data is transmitted during the image data transfer time D205, and then the transmission of subsequent image data is stopped.

[0039] Then, while DT01 is repeatedly using the first line of image data it received, without transferring any image data, the FPGA (code: 4) allocates the free bus line to register settings.

[0040] Specifically, during the available DT01 interval, register settings are performed between the time of ACK signal reception D207 and time D209. Similarly, register settings are performed between the time of ACK signal reception D211 and time D213. Furthermore, between the time of ACK signal reception D215 and time D217, the process of accessing the register for the next image data is performed.

[0041] Figure 5 is a flowchart showing the processing details of the image transfer process at the top of the image data in the image processing apparatus 1 of Embodiment 1 of the present invention.

[0042] In step S101, the image data detection unit 21 determines whether or not there is a margin image at the top of the image data.

[0043] If it is determined that there is no margin image at the top of the image data (step S101; no margin), in step S103, the register setting unit 22 of the CPU (symbol: 2) performs register setting.

[0044] In step S105, the CPU (symbol: 2) synchronizes the image data to the horizontal synchronization frequency and transfers it line by line.

[0045] On the other hand, if it is determined that there is a margin image at the top of the image data (step S101; margin present), in step S111, the register setting unit 22 of the CPU (symbol: 2) performs register setting.

[0046] In step S113, the CPU (code: 2) transmits the image data for the first line of the blank area and stops transmitting subsequent image data.

[0047] In step S115, FPGA (symbol: 4) turns on a mode that reuses the first line of image data received.

[0048] In step S117, while the register setting unit 22 of the CPU (symbol 2) is reusing DT01, the FPGA (symbol 4) performs register setting.

[0049] Once the register configuration is complete, in step S119, FPGA (sign: 4) turns off the reuse mode.

[0050] In step S121, the CPU (code: 2) transfers the image data of line 50, which is the image unit, and in step S123, the CPU (code: 2) continues to transfer the image data line by line, synchronized to the horizontal synchronization frequency.

[0051] Figure 6 is a flowchart showing the processing details of the image transfer process at the bottom of the image data in the image processing apparatus 1 of Embodiment 1 of the present invention.

[0052] In step S201, the image data detection unit 21 determines whether or not there is a margin image at the bottom of the image data.

[0053] If it is determined that there is no margin image at the bottom of the image data (step S201; no margin), in step S203, the register setting unit 22 of the CPU (symbol: 2) performs register setting.

[0054] In step S205, the CPU (symbol: 2) transfers the image data line by line, synchronized to the horizontal synchronization frequency.

[0055] In step S207, the register setting unit 22 of the CPU (symbol: 2) performs register setting.

[0056] On the other hand, if it is determined that there is a margin image at the top of the image data (step S101; margin present), in step S211, the register setting unit 22 of the CPU (symbol: 2) performs register setting.

[0057] In step S213, the CPU (symbol: 2) continues to transfer the image data line by line while synchronizing it to the horizontal synchronization frequency.

[0058] In step S215, the FPGA (symbol: 4) turns on a mode that reuses the image data for the first line of the received blank portion.

[0059] In step S217, while the register setting unit 22 of the CPU (symbol 2) is reusing DT02, the FPGA (symbol 4) performs register setting.

[0060] Once the register configuration is complete, in step S219, FPGA (sign: 4) turns off reuse mode.

[0061] (Note) This application discloses the following invention:

[0062] (Note 1) In an image processing device that uses a single bus line for both image data transfer and register setting, The master control unit that transmits the image data and sets the register, A slave control unit that processes the received image data for repeated use, The master control unit includes an image data detection unit that detects repetitions of margin images and notifies the slave control unit, When the aforementioned blank area image is detected, the master control unit transmits the image data for the first line and stops transmitting subsequent image data. The slave control unit, upon receiving the notification, performs a process of repeatedly using the received image data, reusing the image data instead of the next line of image data, and then allocates the freed bus line to the register setting. An image processing apparatus characterized by the following:

[0063] This allows the system to detect and reuse any blank images in the image data sent from the master control unit to the slave control unit via the bus, thereby reducing the bus occupancy time and improving the overall productivity of the system. [Explanation of Symbols]

[0064] 1 Image Processing Device 3 memory 5 Printheads 10 buses 21 Image data detection unit 22 Register setting section

Claims

[Claim 1] In an image processing device that uses a single bus line for both image data transfer and register setting, The master control unit that transmits the image data and sets the register, A slave control unit that processes the received image data for repeated use, The master control unit includes an image data detection unit that detects repetitions of margin images and notifies the slave control unit, When the aforementioned blank area image is detected, the master control unit transmits the image data for the first line and stops transmitting subsequent image data. The slave control unit, upon receiving the notification, performs a process of repeatedly using the received image data, reusing the image data instead of the next line of image data, and then allocates the freed bus line to the register setting. An image processing apparatus characterized by the following:

Images