Tracking and compensation for the aging of integrated circuits

Abstract

The present invention provides an integrated circuit device, method, and circuit for tracking and compensating for the aging degradation of integrated circuits. [Solution] In the integrated circuit device 12, the aging compensation controller 26 simultaneously acquires the oscillator count measurement via the new replica logic circuit 20 and the oscillator count measurement via the aging replica logic circuit 18. The voltage supplied to the new replica logic circuit may not be gated to provide power to the new replica logic circuit that enables the measurement. The counter 24 measures any suitable defined oscillator count via the new replica logic circuit. The programmable VR 14A remains programmed with a voltage level based on the time when aging compensation was last applied. The counter 24 simultaneously measures the oscillator count via the aging replica logic circuit over the time it took to measure the defined oscillator count via the new replica logic circuit.

Description

Background Art

[0001] The present disclosure relates to a circuit for tracking the aging deterioration of an integrated circuit and compensating for operation changes due to the aging deterioration.

[0002] This section is intended to introduce the reader to various aspects of technology that may relate to various aspects of the present disclosure, which are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of various aspects of the present disclosure. Accordingly, these descriptions should be understood as being interpreted from this perspective rather than an approval as prior art.

[0003] Integrated circuits (ICs) are incorporated into numerous electronic devices and provide a variety of functions. Over time, integrated circuits can degrade in performance and their operation can change due to aging. Furthermore, advanced integrated circuits are increasingly being manufactured using advanced process technologies. In advanced integrated circuits, transistor aging can occur more rapidly, resulting in reliability issues and a gradual decline in the performance of these devices. Examples of these effects include bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB). The recent introduction of nitrogen into transistor gates has worsened negative bias temperature instability (NBTI) in P-channel metal-oxide-semiconductor (PMOS) devices, potentially resulting in a positive shift in the PMOS threshold voltage due to hole trapping in the dielectric bulk and breakdown of silicon-hydrogen (Si-H) bonds at the dielectric interface. The use of high dielectric constant (high K) dielectrics is increasing the aging degradation of N-channel metal-oxide-semiconductor (NMOS) devices, accelerating the effects of positive bias temperature instability (PBTI) on NMOS devices. The main effect of BTI aging degradation is the increase in propagation delay of various circuit components over time. If this performance degradation exceeds the circuit's time margin, it can lead to system failure and reduced long-term reliability.

[0004] To delay the onset of these aging effects, techniques can be used to reverse the Hall trapping effect through power gating and the use of low-frequency clocks. However, while this can slow down the degradation of integrated circuits, the effects of aging still occur, albeit at a slower pace. To ensure that integrated circuits still meet performance specifications even after many years of operation, integrated circuit designers may over-design their systems. For example, in integrated circuit design, a sufficiently high voltage may be used so that the integrated circuit still meets its performance specifications even at the end of its lifespan. This ensures that the integrated circuit meets its performance specifications at the end of its lifespan, but it can cause additional energy consumption and potentially lead to further aging of the integrated circuit over time. [Brief explanation of the drawing]

[0005] Various aspects of this disclosure can be better understood by reading the detailed description below and referring to the drawings.

[0006] [Figure 1] This is a block diagram of a system for tracking and compensating for the aging degradation of integrated circuits in integrated circuit devices.

[0007] [Figure 2] When tracking and compensating for aging degradation, this is a time-varying voltage curve that shows that the voltage changes over time to obtain the same frequency, increasing more gradually over time.

[0008] [Figure 3] This is a time-varying voltage curve applicable to circuit design to guarantee the target frequency, both when tracking and compensating for aging degradation is performed and when not tracking and compensating for aging degradation.

[0009] [Figure 4] This is a flowchart of a method for tracking and compensating for the aging degradation of integrated circuits.

[0010] [Figure 5] This is a block diagram of a circuit for detecting aging using an aging replica logic circuit with usage equivalent to that of the actual logic circuit of an integrated circuit.

[0011] [Figure 6] This is a block diagram of a circuit for detecting aging degradation, and uses a novel replica logic circuit that is not used to provide a reference operation for comparison with the aging degradation replica logic circuit.

[0012] [Figure 7] This is a block diagram of a data processing system that may incorporate a system for tracking and compensating for the aging degradation of integrated circuits. [Modes for carrying out the invention]

[0013] One or more specific embodiments are described below. Not all features of actual implementations are described herein in order to provide a concise description of these embodiments. It will be understood that in developing such actual implementations, such as any engineering or design project, a number of implementation-specific decisions will need to be made to achieve the developer's specific goals, such as adapting to system-related and business-related constraints that may vary from implementation to implementation. Furthermore, it should be understood that while such development work can be complex and time-consuming, it is a routine task in design, fabrication, and manufacturing for those with the usual skills who would benefit from this disclosure.

[0014] Where introducing elements of various embodiments of this disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more elements. The terms “equip,” “include,” and “have” are intended to be inclusive and mean that there may be additional elements other than those listed. Furthermore, it should be understood that any reference in this disclosure to “one embodiment” or “embodiment” is not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the described features. Furthermore, the phrase “A is based on B” is intended to mean that A is based at least partially on B. Also, the term “or” is intended to be inclusive (e.g., logical OR) rather than exclusive (e.g., logical XOR). In other words, the phrase “A or B” is intended to mean A, B, or both A and B.

[0015] To mitigate the effects of aging on integrated circuits without over-designing them, integrated circuits may employ systems for tracking and adjusting the voltage of the integrated circuit design to compensate for aging. For this purpose, an integrated circuit may include the actual logic circuit of the integrated circuit design, an aged replica logic circuit, and a new replica logic circuit. By measuring and comparing the operation of the aged replica logic circuit and the new replica logic circuit, the amount of aging of the integrated circuit design can be determined and tracked, and the voltage consumed by the integrated circuit can be adjusted and compensated for. This allows the performance specifications to still be achieved throughout the lifespan of the integrated circuit while preventing energy loss and excessive aging due to over-design of the integrated circuit.

[0016] Aged replica logic circuits and new replica logic circuits can each replicate the same portion of the actual logic circuit. For example, both aged replica logic circuits and new replica logic circuits may include a replica of the critical path of the actual logic circuit (e.g., the section of the actual logic circuit that has the greatest impact on the maximum frequency the actual logic circuit can achieve). The aged replica logic circuit may operate continuously while the actual logic circuit is in use. Therefore, the aged replica logic circuit is expected to age at the same rate as the actual logic circuit. In contrast, the new replica logic circuit may be operated only occasionally for measurement purposes. Therefore, the new replica logic circuit may experience operational variations due to environmental factors (e.g., temperature, location, altitude) similar to the aged replica logic circuit, but may not experience operational aging. This allows the new replica logic circuit to function as a reference for the aged replica logic circuit. The controller can use the difference between the new replica logic circuit and the aged replica logic circuit to determine the appropriate voltage to supply to the actual logic circuit. The controller can select a voltage that ensures proper operation of the actual logic circuit. Especially during the early stages of an integrated circuit's lifecycle, this voltage can be significantly lower than the over-engineered voltage chosen to ensure operation at the end of the integrated circuit's lifecycle.

[0017] Figure 1 shows a system 10 for tracking and compensating for aging degradation in an integrated circuit device 12. The integrated circuit device 12 may include any suitable integrated circuit. For example, the integrated circuit device 12 may include a programmable logic device (PLD) such as a field programmable gate array (FPGA), or an application-specific integrated circuit (ASIC). Additionally or alternatively, the integrated circuit device 12 may include a processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU)), an artificial intelligence (AI) computing circuit, memory, or storage (e.g., random access memory (RAM), read-only memory (ROM), non-volatile memory, high-bandwidth memory (HBM)).

[0018] The integrated circuit device 12 may include several programmable voltage regulators (VRs) 14A, 14B that can be digitally programmed to provide specific voltage levels. In the example in Figure 1, programmable VR 14A supplies voltage to the actual logic circuit 16 and the aging replica logic circuit 18. Programmable VR 14B supplies voltage to the new replica logic circuit 20. The actual logic circuit 16 may represent any data utilization circuit that performs data processing functions. Both the aging replica logic circuit 18 and the new replica logic circuit 20 may contain replicas of parts of the actual logic circuit 16 (e.g., the critical path, which is the section of the actual logic circuit 16 that has the greatest impact on the maximum frequency that the actual logic circuit 16 can achieve). The aging replica logic circuit 18 can receive voltage from programmable VR 14A and may operate continuously while the actual logic circuit is in use. Therefore, the aging replica logic circuit 18 is expected to age at the same rate as the actual logic circuit 16. In contrast, the programmable VR14B may only supply voltage to the new replica logic circuit 20 during measurement. That is, for most of the time, the voltage supply to the new replica logic circuit 20 may be power-gated (e.g., driven to ground, driven to 0V). Therefore, the new replica logic circuit 20 may experience operational variations due to environmental factors (e.g., temperature, location, altitude), similar to the aged replica logic circuit 18, but the new replica logic circuit 20 may not experience operational degradation due to aging.

[0019] Counters 22 and 24 may occasionally measure the operation of the aged replica logic circuit 18 and the new replica logic circuit 20, respectively. The circuits of the integrated circuit device 12 may become slower at certain voltage levels after operating for a long period of time (e.g., weeks, months, or years). Counter 22 may provide oscillator counts from the aged replica logic circuit 18, and counter 24 may provide oscillator counts from the new replica logic circuit 20. Due to aging, over time the aged replica logic circuit 18 (and consequently the actual logic circuit 16) operates more slowly than the new replica logic circuit 20, which may cause a discrepancy in the counts.

[0020] The aging compensation controller 26 may treat the count from counter 24 as a reference and compare it with the count from counter 22. The aging compensation controller 26 may determine the difference between the count from counter 24 and the count from counter 22. This can be from an absolute perspective (e.g., the difference in total counts) or a relative perspective (e.g., the difference in count rates). Based on the difference, the aging compensation controller 26 may program the programmable VR 14A to supply voltage to the actual logic circuit 16 (and the aging replica logic circuit 18) that compensates for the difference in counts. For example, the voltage programmed by the aging compensation controller 26 may be selected to make the count from counter 22 equal to or greater than the count from counter 24. The aging compensation controller 26 may increase the voltage output by the programmable VR 14A until the count from counter 22 is greater than the count from counter 24 by a value equal to or greater than some threshold. The aging compensation controller 26 may take any suitable form. For example, the aging compensation controller 26 may include a microcontroller that runs firmware loaded from a finite state machine (FSM) or a tangible, non-transient, machine-readable medium located on or outside the integrated circuit device 12.

[0021] The integrated circuit device 12 may have any suitable number of regions containing the circuit shown in Figure 1. In fact, the circuit shown in Figure 1 may be repeated at various locations throughout the integrated circuit device 12. The actual logic circuit may have many different regions with different operating patterns, which may undergo different degrees of aging. Therefore, it may be beneficial to track and adjust the voltages supplied to other actual logic circuits as well. For example, the integrated circuit device 12 may include a first actual logic circuit that operates substantially continuously and a second actual logic circuit that operates only for a limited time (e.g., it may have a low duty cycle and power-gate for part of the time the first actual logic circuit is operating). Other regions of these actual logic circuits may be supplied with different voltages from different programmable VRs, each of which may be tested using its own corresponding aging and new logic replica circuits.

[0022] As a specific example, the integrated circuit device 12 may include a programmable logic circuit (for example, an FPGA circuit as seen in Altera®'s Agilex®, Stratix®, Arria®, MAX®, or Cyclone® devices). This programmable logic circuit can be programmed to handle the circuit design of the actual logic circuit 16, the aging logic circuit 18, and the new logic circuit 20. Later, the aging regions of the actual logic circuit 16 and the aging logic circuit 18 can be reprogrammed (e.g., partially reconfigured) using the new circuit design in these regions where the integrated circuit has deteriorated due to the operation of the previous design. The new replica logic circuit 20 can be reprogrammed (e.g., partially reconfigured) with a new replica logic circuit 20 corresponding to the aged logic circuit 18, and since the new replica logic circuit 20 had not been operating previously except for occasional measurements, the new replica logic circuit 20 can still effectively continue to perform the function of representing a non-aged circuit so as to serve as a reference for the new aged replica logic circuit 18.

[0023] Tracking and compensating for the aging degradation of an integrated circuit can not only reduce the total power consumption of the integrated circuit device 12, but also mitigate the aging degradation of the entire integrated circuit. FIG. 2 provides an example of a plot 40 of the minimum voltage used to achieve a certain target operating frequency for an actual logic circuit over the device life of the integrated circuit device. The vertical axis 42 represents voltage levels (shown as V0, V1, and V2), and the horizontal axis 44 represents the number of years elapsed from the start of the life of the integrated circuit device (t0) to the end of the life (t1). Due to the aging degradation of the integrated circuit device, in order to maintain the same operating target frequency, a higher voltage is required as time passes. Without the aging degradation compensation of the present disclosure, the voltage level increases at a higher rate as shown by line 46. When using the aging degradation compensation of the present disclosure, the voltage level is at a lower rate as shown by line 48, but still increases.

[0024] This is because, as shown by the plot 60 in FIG. 3, when no aging degradation compensation is performed, the maximum voltage level is applied during the life period of the integrated circuit device. The vertical axis 62 represents the same voltage levels as those shown in plot 40 (shown as V0, V1, V2), and the horizontal axis 64 represents the same number of years elapsed from the start of the life of the integrated circuit device (t0) to the end of the life (t1). Without aging degradation compensation, the circuit designer can ensure that it always operates at that voltage level so that the operating target frequency is still achieved at the end of the life (t1), as shown by line 66. In contrast, as shown by line 68, when using the aging degradation compensation of the present disclosure, the voltage level can be adaptively increased based on the amount of aging degradation detected over time. As described, the aging degradation compensation of the present disclosure not only reduces the total power consumption over the life of the integrated circuit device, but also reduces the total amount of aging degradation of the integrated circuit. This is because the greater the voltage applied to the integrated circuit, the greater the aging degradation of the integrated circuit.

[0025] FIG. 4 is a flowchart 70 of a method for performing aging compensation using the circuit shown in FIG. 1. The method of flowchart 70 can be executed periodically or upon request. For example, the aging compensation controller 26 can initiate or be prompted to initiate the method of flowchart 70. At the start of flowchart 70, the aging compensation controller 26 can simultaneously obtain a measured value of the oscillator count via the new replica logic circuit 20 (block 72), and a measured value of the oscillator count via the aging replica logic circuit 18 (block 74). For example, the programmable VR14B can be programmed at a defined voltage of the integrated circuit to provide a desired target frequency (e.g., the defined voltage can be V0 that results in the target frequency at the start of the lifetime (t1) in plots 40 and 60 of FIGS. 2 and 3). The voltage supplied to the new replica logic circuit 20 may not be gated to provide power to the new replica logic circuit 20 that enables measurement. The counter 24 can measure any suitable defined number of oscillator counts via the new replica logic circuit 20. On the other hand, the programmable VR14A can remain programmed at a voltage level based on the time when the previous aging compensation was applied. The counter 22 can simultaneously measure the oscillator count via the aging replica logic circuit 18 over the time it takes for the counter 24 to measure the defined number of oscillator counts via the new replica logic circuit 20. For example, the counter 22 can be disabled as soon as the counter 24 counts the defined number of oscillator counts. Additionally or alternatively, the counters 22 and 24 can operate for an equal number of clock cycles defined based on a common clock signal.

[0026] The aging compensation controller 26 may adjust the voltage level of the programmable VR 14A to compensate for the difference between the oscillator counts from counters 22 and 24 (block 76). In one example, the aging compensation controller 26 may gradually increase or decrease a voltage control signal (e.g., a digital or analog control signal) by a predetermined amount, and then repeat the method of flowchart 70. This operation may continue until the oscillator counts from counters 22 and 24 substantially match, or until the oscillator count from counter 22 exceeds the oscillator count from counter 24 by a threshold amount (e.g., a guard band). Additionally or alternatively, the aging compensation controller 26 may obtain voltage regulation by applying a function (e.g., performing a calculation to index a lookup table that stores the function) based on the difference between the oscillator counts from counters 22 and 24.

[0027] Figure 5 shows a schematic of a programmable VR 14A that supplies voltage to the actual logic circuit 16 and the aging replica logic circuit 18. In the example in Figure 5, a 10-bit digital reference target voltage signal (VrefTarget[9:0]) (provided, for example, by the aging compensation controller 26) can be used by a 10-bit digital-to-analog converter (DAC) 80 to generate a reference voltage signal (Vref) based on a reference power supply voltage (VccRef), when activated by an amplifier activation signal (LDO_En). Although the DAC 80 is described as a 10-bit DAC, the DAC 80 may have any suitable, larger or smaller bit width (e.g., 4 bits, 5 bits, 6 bits, 7 bits, 8 bits, 9 bits, 11 bits, 12 bits, etc.). The multiplexer 82 may be selectable to use either the programmable reference voltage signal (Vref) or the global power supply reference voltage signal (Vcc) as a reference to the operational amplifier (op-amp) 84. The selected voltage signal from the multiplexer 82 can be conditioned by an optional suitable filter circuit 86 to prevent abrupt changes. The operational amplifier 84 can receive the amplifier power supply voltage (vcca) and can be activated by the amplifier activation signal (LDO_En). The operational amplifier 84 generates a signal that is applied to the gate of transistor M1 connected between the circuit power supply rail voltages (vcn). The output voltage of transistor M1, which supplies the actual logic circuit 16 and the aged replica logic circuit 18, changes based on the signal applied to the gate of transistor M1. Due to feedback to the operational amplifier, the output voltage of transistor M1 is equal to the reference voltage (Vref) output by the DAC 80. Another transistor M2 could be used for power gating purposes, but it is not used in the circuit of Figure 5. Since both the drain and gate of transistor M2 are connected to the same voltage level, transistor M2 remains open and therefore does not power gate the circuit of Figure 5.

[0028] The actual logic circuit 16 and the aging replica logic circuit 18 can be selectively enabled by the Functional_Enable signal. The Functional_Enable signal activates both the actual logic circuit 16 and the aging replica logic circuit 18 so that the aging replica logic circuit 18 is always operating (aging) while the actual logic circuit 16 is operating. Furthermore, even when the actual logic circuit 16 is not in use, the aging replica logic circuit 18 may be selectively (but briefly) activated by the TrackingAgingEnable signal. This is to allow measurement of the aging replica logic circuit 18 even when the actual logic circuit 16 is not operating (for example, to determine the reference voltage Vref of the actual logic circuit 16 before the actual logic circuit 16 is activated). For this reason, the TrackingAgingEnable signal and the Functional_Enable signal can be input to the OR gate 88 supplied to the aging replica logic circuit 18.

[0029] As shown in Figure 5, the aging replica logic circuit 18 may be arranged in a ring oscillator configuration. Thus, the AND gate 90 may be connected to the output of a combinational logic 92 that represents some replica of the combinational logic 94 from the actual logic circuit 16. The output of the OR gate 88 is also supplied to the AND gate 90. The oscillations output by the combinational logic 92 of the aging replica logic circuit 18 may be counted by the counter 22. The actual logic circuit 16 may also include an AND gate 96. Additionally or alternatively, the actual logic circuit 16 may be selectively operated in a ring oscillator configuration with the AND gate 96 using the aging replica logic circuit 18, additionally or alternatively. Thus, if necessary, the actual logic circuit 16 may be measured directly (e.g., by the counter 22) instead of the aging replica logic circuit 18 (e.g., the aging replica logic circuit 18 may not be shown in this example). However, this may only be possible if the actual logic circuit 16 is not being used. Thus, this may be done to the extent that it is expected that the actual logic circuit 16 will not be used all the time.

[0030] Figure 6 shows the circuit diagram of the programmable VR14B that supplies voltage to the new replica logic circuit 20. In the example in Figure 6, elements with the same element number can be understood as equivalent to those described above with reference to Figure 5. However, in the example in Figure 6, the DAC80 and op-amp 84 are activated by the TrackingAgingEnable signal, not the amplifier activation signal (LDO_En). Furthermore, the inverter 98 outputs the inverted TrackingAgingEnable signal to the gate of the M2 transistor. Therefore, if the TrackingAgingEnable signal does not activate the DAC80, op-amp 84, and the new replica logic circuit 20, the transistor M2 performs power gating of the new replica logic circuit 20, ensuring that the new replica logic circuit 20 remains grounded except during measurement. This eliminates the effects of aging on the new replica logic circuit 20 when it is not being measured. When the TrackingAgingEnable signal activates the DAC80, op-amp84, and the new replica logic circuit20, transistor M2 allows power to be supplied to the new replica logic circuit20. The new replica logic circuit20 may be arranged in a ring oscillator configuration using AND gates 100, using the same combinational logic 92 used in the aging replica logic circuit18. The oscillations output by the combinational logic 92 of the new replica logic circuit20 may be counted by counter 24.

[0031] Before any measurement begins, the aging compensation controller 26 may calibrate the programmable VRs 14A and 14B. To calibrate the programmable VRs 14A and 14B, they may be programmed to the same Vref, or one or both of the multiplexer 82 may be set to provide Vcc. The aging compensation controller 26 may compare the outputs resulting from transistor M1 of the programmable VR 14A and transistor M1 of the programmable VR 14B. The aging compensation controller 26 may set offset compensation for one of the programmable VRs 14A and 14B so that both programmable VRs 14A and 14B output the same value for a predetermined target voltage. Offset compensation may be implemented as a change in the reference target voltage signal (VrefTarget), a change in the operation of the DAC 80 (e.g., adjustment of tap position or voltage), and / or a change in the power supply voltage to the op-amp 84 of either one or both of the programmable VRs 14A or 14B. This calibration may be performed before each measurement of the integrated circuit device 12, or it may be performed only once at the start of its life (BOL).

[0032] The aging tracking and compensation system 10 may be provided in any suitable integrated circuit device of a data processing system, such as the data processing system 500 shown in Figure 7. The data processing system 500 may include the integrated circuit device 12 of the Disclosure, a host processor 502, memory and / or storage circuits 504, and a network interface 506. The data processing system 500 may include more or fewer components (e.g., electronic displays, user interface structures, application-specific integrated circuits (ASICs)). Furthermore, any circuit components shown in Figure 7 may include various embodiments of the aging tracking and compensation system of the Disclosure. The host processor 502 may include any suitable processor capable of managing data processing requests for the data processing system 500 (e.g., to perform encryption, decryption, machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern recognition, spatial navigation, cryptocurrency operations, etc.). The memory and / or storage circuit 504 may include random access memory (RAM), read-only memory (ROM), one or more hard drives, flash memory, etc. The memory and / or storage circuit 504 may hold data processed by the data processing system 500. In some cases, if the memory and / or storage circuit 504 includes programmable logic circuits (e.g., FPGA circuit configurations), it may store configuration programs (e.g., bitstreams, mapping functions) for programming the integrated circuit device 12. The network interface 506 may enable the data processing system 500 to communicate with other electronic devices. The data processing system 500 may include several different packages or be housed in a single package on a single package substrate. For example, the components of the data processing system 500 may be located in several different packages at one location (e.g., a data center) or multiple locations. For example, the components of the data processing system 500 may be located in separate geographical locations or regions such as cities, states, or countries.

[0033] The data processing system 500 may be part of a data center that handles a variety of different requests. For example, the data processing system 500 may receive data processing requests via the network interface 506 to perform encryption, decryption, machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern recognition, spatial navigation, digital signal processing, or other specific tasks.

[0034] The techniques and methods described herein are applicable to other types of integrated circuit systems. For example, the aging tracking and compensation system of this disclosure may be used in conjunction with a central processing unit (CPU), graphics card, hard drive, or other components.

[0035] While the embodiments described herein may be subject to various modifications and alternative forms, certain embodiments are illustrated by the drawings and described in detail herein. However, this disclosure is not intended to be limited to any particular form disclosed. This disclosure covers all variations, equivalents, and alternatives that fall within the spirit and scope of this disclosure as defined by the claims appended below.

[0036] The technologies described and claimed herein are based on and applied to tangible objects and specific examples of a practical nature that clearly improve the art, and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification includes one or more elements designated as “means for carrying out a certain function” or “stages for carrying out a certain function,” such elements are intended to be construed under Section 112(f) of the United States Patent Act. However, any claim that includes elements designated in any other form is intended not to be construed under Section 112(f) of the United States Patent Act. [Example Embodiments]

[0037] Exemplary embodiment 1.

[0038] First logic circuit;

[0039] A first replica of a part of the first logic circuit;

[0040] A second replica of the part of the first logic circuit;

[0041] A first programmable voltage regulator for supplying a first programmable voltage to the first logic circuit and the first replica of a portion of the first logic circuit;

[0042] A second programmable voltage regulator for supplying a second programmable voltage to the second replica of the portion of the first logic circuit;

[0043] A counter circuit for measuring the first oscillator count from the first replica of the first logic circuit and the second oscillator count from the second replica of the first logic circuit; and

[0044] A controller for controlling the first programmable voltage regulator in order to adjust the first programmable voltage based on the first oscillator count and the second oscillator count. An integrated circuit device equipped with the following features.

[0045] Exemplary embodiment 2. The integrated circuit device according to exemplary embodiment 1, wherein the replicated portion of the first logic circuit is the critical path of the first logic circuit.

[0046] Exemplary embodiment 3. The integrated circuit device according to exemplary embodiment 1, wherein the first programmable voltage regulator supplies the first programmable voltage to the portion of the first replica of the first logic circuit while the first logic circuit operates to cause the portion of the first replica of the first logic circuit to age at the same rate as the first logic circuit.

[0047] Exemplary embodiment 4. The integrated circuit device according to exemplary embodiment 3, wherein, when the counter circuit is not used to measure the first oscillator count from the portion of the first replica of the first logic circuit and the second oscillator count from the portion of the second replica of the first logic circuit, the second programmable voltage regulator is configured to power gate the second programmable voltage from the portion of the second replica of the first logic circuit.

[0048] Exemplary embodiment 5. The integrated circuit device according to exemplary embodiment 1, wherein the counter circuit is configured to measure the first oscillator count from the first replica of the portion of the first logic circuit until the second oscillator count from the portion of the first logic circuit reaches a defined value.

[0049] Exemplary embodiment 6. The integrated circuit device according to exemplary embodiment 1, wherein the counter circuit is configured to measure the first oscillator count from a portion of the first replica of the first logic circuit and the second oscillator count from a portion of the second replica of the first logic circuit for a defined number of clock cycles.

[0050] Exemplary embodiment 7. The controller is an integrated circuit device according to exemplary embodiment 1, having a finite state machine.

[0051] Exemplary embodiment 8. The controller is an integrated circuit device according to exemplary embodiment 1, comprising a microcontroller.

[0052] Exemplary embodiment 9. The integrated circuit device according to exemplary embodiment 1, wherein the controller is configured to control the first programmable voltage regulator to adjust the first programmable voltage based on the difference between the first oscillator count and the second oscillator count.

[0053] Exemplary embodiment 10. The integrated circuit device according to exemplary embodiment 9, wherein the controller is configured to control the first programmable voltage regulator to adjust the first programmable voltage so that the first oscillator count or the rate of the first oscillator count matches or exceeds the rate of the second oscillator count.

[0054] Exemplary embodiment 11. The controller is configured to control the first programmable voltage regulator by issuing a digital control signal to the first programmable voltage regulator, the digital control signal causing the first programmable voltage regulator to adjust the first programmable voltage, as described in exemplary embodiment 1 of the integrated circuit device.

[0055] Exemplary embodiment 12. The integrated circuit device according to exemplary embodiment 11, wherein the controller is configured to increase or decrease the digital control signal based on the difference between the first oscillator count and the second oscillator count.

[0056] Exemplary embodiment 13.

[0057] In the step of measuring the first oscillator count via an aged replica logic circuit having a first replica of a portion of the actual logic circuit, the aged replica logic circuit was running for the entire operating life of the actual logic circuit;

[0058] The step of measuring the second oscillator count via a new replica logic circuit having a second replica of the part of the actual logic circuit, wherein the new replica logic circuit has not been started during the operating life of the actual logic circuit; and

[0059] Steps to adjust the voltage level of the actual logic circuit based on the first oscillator count and the second oscillator count. A method for providing this.

[0060] Exemplary embodiment 14. The method according to exemplary embodiment 13, wherein the novel replica logic circuit is configured to be power-gated except during measurement.

[0061] Exemplary embodiment 15. The method according to an exemplary embodiment 13, wherein the voltage level is adjusted based on the difference between the first oscillator count and the second oscillator count.

[0062] Exemplary embodiment 16. The method according to exemplary embodiment 13, wherein the voltage level is adjusted to increase over time to account for the actual aging of the logic circuit, as indicated by the change in the first oscillator count over time relative to the second oscillator count over time.

[0063] Exemplary embodiment 17. The method according to an exemplary embodiment 13, comprising the step of repeating the above action until the first oscillator count or the rate of the first oscillator count is equal to or greater than the second oscillator count or the rate of the second oscillator count.

[0064] Exemplary embodiment 18.

[0065] A first logic circuit for performing data processing operations;

[0066] An aging replica logic circuit having a first replica of a segment of the first logic circuit, configured to operate substantially while the first logic circuit is operating;

[0067] A new replica logic circuit having a second replica of the segment of the first logic circuit, configured to have a shorter operating time than the aforementioned aging replica logic circuit; and

[0068] A controller configured to adjust the voltage level of the first logic circuit to compensate for the aging of the actual logic circuit, based on the difference in operation between the aged replica logic circuit and the new replica logic circuit. A circuit equipped with this feature.

[0069] Exemplary embodiment 19. The difference in operation between the aged replica logic circuit and the new replica logic circuit includes a difference in oscillator count, as described in exemplary embodiment 18 of the circuit.

[0070] Exemplary embodiment 20. The circuit according to exemplary embodiment 18, comprising an OR logic gate configured to activate the aging replica logic circuit based on receiving a first or second activation signal which also enables the operation of the first logic circuit, thereby enabling the measurement of the operation of the aging replica logic circuit. [Other adjacent items] [Item 1] First logic circuit; A first replica of a part of the first logic circuit; A second replica of the part of the first logic circuit; A first programmable voltage regulator for supplying a first programmable voltage to the first logic circuit and the first replica of a portion of the first logic circuit; A second programmable voltage regulator for supplying a second programmable voltage to the second replica of the portion of the first logic circuit; A counter circuit for measuring the first oscillator count from the first replica of the first logic circuit and the second oscillator count from the second replica of the first logic circuit; and A controller for controlling the first programmable voltage regulator in order to adjust the first programmable voltage based on the first oscillator count and the second oscillator count. An integrated circuit device equipped with the following features. [Item 2] The integrated circuit device according to item 1, wherein the replicated portion of the first logic circuit is the critical path of the first logic circuit. [Item 3] The integrated circuit device according to item 1, wherein the first programmable voltage regulator supplies the first programmable voltage to the portion of the first replica of the first logic circuit while the first logic circuit operates to cause the portion of the first replica of the first logic circuit to degrade at the same rate as the first logic circuit. [Item 4] The integrated circuit device according to item 3, wherein, when the counter circuit is not used to measure the first oscillator count from the portion of the first replica of the first logic circuit and the second oscillator count from the portion of the second replica of the first logic circuit, the second programmable voltage regulator is configured to power gate the second programmable voltage from the portion of the second replica of the first logic circuit. [Item 5] The integrated circuit device according to item 1, wherein the counter circuit is configured to measure the first oscillator count from the first replica of the portion of the first logic circuit until the second oscillator count from the portion of the first logic circuit reaches a defined value. [Item 6] The integrated circuit device according to item 1, wherein the counter circuit is configured to measure the first oscillator count from a portion of the first logic circuit and the second oscillator count from a portion of the first logic circuit's second replica for a defined number of clock cycles. [Item 7] The controller is an integrated circuit device according to item 1, having a finite state machine. [Item 8] The controller is an integrated circuit device according to item 1, comprising a microcontroller. [Item 9] The integrated circuit device according to item 1, wherein the controller is configured to control the first programmable voltage regulator to adjust the first programmable voltage based on the difference between the first oscillator count and the second oscillator count. [Item 10] The integrated circuit device according to item 9, wherein the controller is configured to control the first programmable voltage regulator to adjust the first programmable voltage so that the first oscillator count or the rate of the first oscillator count matches or exceeds the rate of the second oscillator count. [Item 11] The controller is configured to control the first programmable voltage regulator by issuing a digital control signal to the first programmable voltage regulator, the digital control signal causing the first programmable voltage regulator to adjust the first programmable voltage, as described in item 1. [Item 12] The integrated circuit device according to item 11, wherein the controller is configured to increase or decrease the digital control signal based on the difference between the first oscillator count and the second oscillator count. [Item 13] In the step of measuring the first oscillator count via an aged replica logic circuit having a first replica of a portion of the actual logic circuit, the aged replica logic circuit was running for the entire operating life of the actual logic circuit; The step of measuring the second oscillator count via a new replica logic circuit having a second replica of the part of the actual logic circuit, wherein the new replica logic circuit has not been started during the operating life of the actual logic circuit; and Steps to adjust the voltage level of the actual logic circuit based on the first oscillator count and the second oscillator count. A method for providing this. [Item 14] The method according to item 13, wherein the novel replica logic circuit is configured to be power-gated except during measurement. [Item 15] The method according to item 13, wherein the voltage level is adjusted based on the difference between the first oscillator count and the second oscillator count. [Item 16] The method according to item 13, wherein the voltage level is adjusted to increase over time, taking into account the actual aging of the logic circuit, as indicated by the change in the first oscillator count over time relative to the second oscillator count over time. [Item 17] The method according to item 13, further comprising the step of repeating the preceding action until the first oscillator count or rate of the first oscillator count is equal to or greater than the second oscillator count or rate of the second oscillator count. [Item 18] A first logic circuit for performing data processing operations; An aging replica logic circuit having a first replica of a segment of the first logic circuit, configured to operate substantially while the first logic circuit is operating; A new replica logic circuit having a second replica of the segment of the first logic circuit, configured to have a shorter operating time than the aforementioned aging replica logic circuit; and A controller configured to adjust the voltage level of the first logic circuit to compensate for the aging of the actual logic circuit, based on the difference in operation between the aged replica logic circuit and the new replica logic circuit. A circuit equipped with this feature. [Item 19] The difference in operation between the aged replica logic circuit and the new replica logic circuit is the circuit described in item 18, including the difference in oscillator count. [Item 20] The circuit according to item 18, comprising an OR logic gate configured to activate the aging replica logic circuit based on receiving a first or second activation signal which also enables the operation of the first logic circuit, thereby enabling the measurement of the operation of the aging replica logic circuit.

Claims

1. First logic circuit; A first replica of a part of the first logic circuit; A second replica of the part of the first logic circuit; A first programmable voltage regulator for supplying a first programmable voltage to the first logic circuit and the first replica of a part of the first logic circuit; A second programmable voltage regulator for supplying a second programmable voltage to the second replica of the first logic circuit; A counter circuit for measuring the first oscillator count from the first replica of the first logic circuit and the second oscillator count from the second replica of the first logic circuit; and A controller for controlling the first programmable voltage regulator in order to adjust the first programmable voltage based on the first oscillator count and the second oscillator count. An integrated circuit device equipped with the following features.

2. The integrated circuit device according to claim 1, wherein the replicated portion of the first logic circuit is the critical path of the first logic circuit.

3. The integrated circuit device according to claim 1, wherein the first programmable voltage regulator supplies a first programmable voltage to the portion of the first replica of the first logic circuit while the first logic circuit operates such that the portion of the first replica of the first logic circuit degrades at the same rate as the first logic circuit.

4. The integrated circuit device according to claim 3, wherein, when the counter circuit is not used to measure the first oscillator count from the first replica of the portion of the first logic circuit and the second oscillator count from the second replica of the portion of the first logic circuit, the second programmable voltage regulator is configured to power gate the second programmable voltage from the second replica of the portion of the first logic circuit.

5. The integrated circuit device according to claim 1, wherein the counter circuit is configured to measure the first oscillator count from the first replica of the part of the first logic circuit until the second oscillator count from the part of the first logic circuit reaches a defined value.

6. The integrated circuit device according to claim 1, wherein the counter circuit is configured to measure the first oscillator count from a portion of the first replica of the first logic circuit and the second oscillator count from a portion of the second replica of the first logic circuit for a defined number of clock cycles.

7. The integrated circuit device according to any one of claims 1 to 6, wherein the controller has a finite state machine.

8. The integrated circuit device according to any one of claims 1 to 6, wherein the controller comprises a microcontroller.

9. The integrated circuit device according to any one of claims 1 to 6, wherein the controller is configured to control the first programmable voltage regulator to adjust the first programmable voltage based on the difference between the first oscillator count and the second oscillator count.

10. The integrated circuit device according to claim 9, wherein the controller is configured to control the first programmable voltage regulator to adjust the first programmable voltage so that the first oscillator count or the rate of the first oscillator count matches or exceeds the rate of the second oscillator count.

11. The integrated circuit device according to any one of claims 1 to 6, wherein the controller is configured to control the first programmable voltage regulator by issuing a digital control signal to the first programmable voltage regulator, and the digital control signal causes the first programmable voltage regulator to adjust the first programmable voltage.

12. The integrated circuit device according to claim 11, wherein the controller is configured to increase or decrease the digital control signal based on the difference between the first oscillator count and the second oscillator count.

13. In the step of measuring the first oscillator count via an aged replica logic circuit having a first replica of a portion of the actual logic circuit, the aged replica logic circuit was running for the entire operating life of the actual logic circuit; The step of measuring the second oscillator count via a novel replica logic circuit having a second replica of the portion of the actual logic circuit, wherein the novel replica logic circuit has not been activated over the operating life of the actual logic circuit; and A step of adjusting the voltage level of the actual logic circuit based on the first oscillator count and the second oscillator count. A method for providing this.

14. The method according to claim 13, wherein the novel replica logic circuit is configured to be power-gated except during measurement.

15. The method according to claim 13 or 14, wherein the voltage level is adjusted based on the difference between the first oscillator count and the second oscillator count.

16. The method according to claim 13 or 14, wherein the voltage level is adjusted to increase over time, taking into account the actual aging of the logic circuit as indicated by the change in the first oscillator count relative to the second oscillator count over time.

17. The method according to claim 13 or 14, further comprising the step of repeating the preceding action until the first oscillator count or the rate of the first oscillator count is equal to or greater than the second oscillator count or the rate of the second oscillator count.

18. A first logic circuit for performing data processing operations; An aging replica logic circuit having a first replica of a segment of the first logic circuit, configured to operate substantially while the first logic circuit is operating; A new replica logic circuit having a second replica of the segment of the first logic circuit, configured to have a shorter operating time than the aforementioned aging replica logic circuit; and A controller configured to adjust the voltage level of the first logic circuit to compensate for the aging of the actual logic circuit, based on the difference in operation between the aged replica logic circuit and the new replica logic circuit. A circuit equipped with this feature.

19. The circuit according to claim 18, wherein the difference in operation between the aged replica logic circuit and the new replica logic circuit includes a difference in oscillator count.

20. The circuit according to claim 18 or 19, further comprising an OR logic gate configured to activate the aging-degraded replica logic circuit based on receiving a first or second activation signal that also enables the operation of the first logic circuit, thereby enabling the measurement of the operation of the aging-degraded replica logic circuit.

21. Means for measuring a first oscillator count via an aging replica logic circuit having a first replica of a portion of the actual logic circuit, wherein the aging replica logic circuit was activated over the operating life of the actual logic circuit; Means for measuring a second oscillator count via a novel replica logic circuit having a second replica of the portion of the actual logic circuit, wherein the novel replica logic circuit has not been activated over the operating life of the actual logic circuit; and Means for adjusting the voltage level of the actual logic circuit based on the first oscillator count and the second oscillator count. A system equipped with these features.

22. The system according to claim 21, wherein the novel replica logic circuit is configured to be power-gated except during measurement.

23. The system according to claim 21 or 22, wherein the voltage level is adjusted based on the difference between the first oscillator count and the second oscillator count.

24. A step of supplying a first programmable voltage to a first logic circuit and a first replica of a part of the first logic circuit; A step of supplying a second programmable voltage to a second replica of the part of the first logic circuit; A step of measuring the first oscillator count from the first replica of the part of the first logic circuit and the second oscillator count from the second replica of the part of the first logic circuit; and A step of controlling the first programmable voltage regulator to adjust the first programmable voltage based on the first oscillator count and the second oscillator count. A method for providing this.

25. The method according to claim 24, wherein the replicated portion of the first logic circuit is the critical path of the first logic circuit.

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