Gate drive unit and display device including gate drive unit

Abstract

The present invention provides a gate drive unit capable of controlling the drive frequency for each area of ​​the display panel, and a display device including the same. [Solution] A gate drive unit according to one embodiment of this specification includes a plurality of stages that are coupled together and output a plurality of gate signals based on an input signal, a plurality of clock signals, a plurality of control clock signals, a first power supply, and a second power supply having a lower voltage level than the first power supply. Each of the plurality of stages includes a carry unit that outputs a carry signal based on an input signal, at least one of the plurality of clock signals, a first power supply, and a second power supply, and a carry unit that outputs a gate signal based on the carry signal, at least one of the plurality of control clock signals, a first power supply, and a second power supply, and the output of the gate signal of the output unit is controlled based on at least one control clock signal.

Description

Technical Field

[0001] This specification relates to a gate driving unit and a display device including the gate driving unit, and more particularly, to a gate driving unit capable of controlling a driving frequency and a display device including the gate driving unit.

Background Art

[0002] As the information age has arrived, the field of displays that visually represent electrical information signals has been rapidly developing. In response, various display devices with excellent performance such as being thinner, lighter, and having lower power consumption have been developed. Examples of such display devices include liquid crystal display devices (LCDs), organic light emitting display devices (OLEDs), and the like.

[0003] Such a display device can include a display panel on which a plurality of pixels for displaying an image are arranged, a data driving unit that supplies data signals to the plurality of pixels through a plurality of data wirings, a gate driving unit that supplies gate signals to the plurality of pixels through a plurality of gate wirings, and a driving circuit such as a timing control unit that controls the data driving unit and the gate driving unit.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by this specification is to provide a gate driving unit capable of controlling the driving frequency for each region of the display panel and a display device including the gate driving unit.

[0005] The problems of this specification are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0006] A gate drive unit according to one embodiment of this specification may include a plurality of stages that are coupled in a subordinate manner and output a plurality of gate signals based on an input signal, a plurality of clock signals, a plurality of control clock signals, a first power supply, and a second power supply having a lower voltage level than the first power supply. Each of the plurality of stages includes a carry unit that outputs a carry signal based on the input signal, at least one of the plurality of clock signals, the first power supply, and the second power supply, and a carry unit that outputs a gate signal based on the carry signal, at least one of the plurality of control clock signals, the first power supply, and the second power supply, and the output of the gate signal of the output unit may be controlled based on the at least one control clock signal.

[0007] A display device according to one embodiment of this specification may include a display panel including a plurality of pixels, and a first scan drive unit, a second scan drive unit, a third scan drive unit, and a fourth scan drive unit that output a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to the plurality of pixels, respectively, based on an input signal, a plurality of clock signals, a plurality of control clock signals, a first power supply, and a second power supply having a lower voltage level than the first power supply. In a first display period, each of the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal has a gate-on level pulse, and in a second display period different from the first display period, the third scan signal has a gate-on level pulse, and the first scan signal, the second scan signal, and the fourth scan signal are maintained at a gate-off level, and at least a portion of the first scan drive unit, the second scan drive unit, and the fourth scan drive unit can control the signal level of the scan signal based on the same control clock signal among the plurality of control clock signals.

[0008] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0009] Each stage of the gate drive unit described herein may include a carry unit for generating a carry signal and an output unit for controlling the output of the gate signal.

[0010] This allows the display area to be freely divided in accordance with the displayed image, rather than being limited to a fixed area, and the drive frequency can be controlled for each area.

[0011] Furthermore, since the drive frequency is controlled according to the display area, power consumption may be improved.

[0012] The effects relating to the examples in this specification are not limited to those exemplified above, and a wider variety of effects are described herein. [Brief explanation of the drawing]

[0013] [Figure 1] This is a block diagram showing a display device according to one embodiment of this specification. [Figure 2a] This figure shows an example of a display panel included in the display device shown in Figure 1. [Figure 2b] This figure shows an example of a display panel included in the display device shown in Figure 1. [Figure 3] This is a circuit diagram showing an example of pixels included in the display device shown in Figure 1. [Figure 4a] This waveform diagram illustrates an example of pixel driving in Figure 3. [Figure 4b] This waveform diagram illustrates an example of pixel driving in Figure 3. [Figure 5] This is a block diagram showing a gate drive unit according to one embodiment of this specification. [Figure 6] Figure 5 is a block diagram showing an example of a gate drive unit. [Figure 7] This is a circuit diagram showing an example of the first stage included in the gate drive unit of Figure 6. [Figure 8] This waveform diagram illustrates an example of the first stage drive shown in Figure 7. [Figure 9a]It is a waveform diagram for explaining an example of the driving of the gate driving unit in FIG. 6. [Figure 9b] It is a waveform diagram for explaining an example of the driving of the gate driving unit in FIG. 6. [Figure 9c] It is a waveform diagram for explaining an example of the driving of the gate driving unit in FIG. 6. [Figure 10] It is a block diagram showing another example of the gate driving unit in FIG. 5. [Figure 11a] It is a waveform diagram for explaining an example of the driving of the gate driving unit in FIG. 10. [Figure 11b] It is a waveform diagram for explaining an example of the driving of the gate driving unit in FIG. 10. [Figure 11c] It is a waveform diagram for explaining an example of the driving of the gate driving unit in FIG. 10. [Figure 12] It is a block diagram showing another example of the gate driving unit in FIG. 5. [Figure 13a] It is a waveform diagram for explaining an example of the driving of the gate driving unit in FIG. 12. [Figure 13b] It is a waveform diagram for explaining an example of the driving of the gate driving unit in FIG. 12. [Figure 13c] It is a waveform diagram for explaining an example of the driving of the gate driving unit in FIG. 12. [Figure 14] It is a block diagram showing an example of the arrangement relationship of the light emission driving unit, a plurality of scan driving units, and a plurality of signal wirings included in the gate driving unit in FIG. 5. [Figure 15] It is a block diagram showing another example of the arrangement relationship of the light emission driving unit, a plurality of scan driving units, and a plurality of signal wirings included in the gate driving unit in FIG. 5. [Figure 16] It is a waveform diagram for explaining another example of the driving of the pixel in FIG. 3. [Figure 17] It is a waveform diagram for explaining an example of the driving of the first scan driving unit and the fourth scan driving unit in FIG. 15.

Embodiments for Carrying Out the Invention

[0014] The advantages and features of this specification, and the methods for achieving them, will become clearer with reference to the examples described below in detail with the accompanying drawings. However, this specification is not limited to the examples disclosed below, but can be embodied in a variety of different forms, and these examples are provided merely to make the disclosure of this specification complete and to fully inform a person with ordinary skill in the art to which this specification belongs.

[0015] The shapes, areas, proportions, angles, numbers, etc. disclosed in the drawings illustrating the embodiments of this specification are illustrative and the specification is not limited to those illustrated. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing this specification, if it is determined that a specific explanation of related prior art would unnecessarily obscure the gist of this specification, such detailed explanation will be omitted. Where "includes," "has," "is made," etc., are used in this specification, other parts may be added unless "only" is used. When a component is expressed singularly, it includes cases where it includes multiple components unless otherwise explicitly stated.

[0016] When interpreting the constituent elements, they shall be interpreted as including a margin of error, even if not explicitly stated otherwise.

[0017] Furthermore, while terms such as "first," "second," etc., are used to describe a variety of components, these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0018] Throughout the specification, the same reference numeral refers to the same component.

[0019] The area and thickness of each component shown in the drawings are provided for illustrative purposes only, and this specification is not necessarily limited to the area and thickness of the components shown.

[0020] The features of each of the various embodiments described herein can be combined or combined with one another, either partially or as a whole, enabling a variety of technically diverse interoperability and drive, and each embodiment may be implemented independently of the others or together in relation to one another.

[0021] In the following, this specification will be described with reference to the drawings.

[0022] Figure 1 is a block diagram showing a display device according to one embodiment of this specification.

[0023] Figures 2a and 2b show examples of display panels included in the display device shown in Figure 1.

[0024] Referring to Figure 1, the display device 100 according to one embodiment of this specification may include a timing control unit 110, a gate drive unit 120, a data drive unit 130, and a display panel 140.

[0025] The display panel 140 can generate an image to be provided to the user. For example, the display panel 140 may include a display area in which multiple pixels PX, each having a pixel circuit, are arranged, and a non-display area excluding the display area.

[0026] Each of the multiple pixels PX is connected to a corresponding gate wiring GL and data wiring DL, and can display an image in response to the gate signal provided to the gate wiring GL and the data signal provided to the data wiring DL.

[0027] In one embodiment, the display area of ​​the display panel 140 may be divided into multiple areas. For example, the display area may include multiple sub-display areas. For example, referring further to Figure 2a, the display area AA of the display panel 140 may be divided into a first sub-display area AA1 and a second sub-display area AA2.

[0028] The first sub-display area AA1 and the second sub-display area AA2, which are included in the display area AA, may each contain at least one pixel PX. For example, at least one pixel PX may be placed on the first sub-display area AA1 and the second sub-display area AA2, respectively.

[0029] In one embodiment, the display area AA is divided into sub-display areas of the same size, so that the first sub-display area AA1 and the second sub-display area AA2 can contain the same number of pixels PX. However, this is illustrative, and the first sub-display area AA1 and the second sub-display area AA2 included in the display area AA may share one or more pixels PX, and / or the number of pixels PX in one of the sub-display areas may be greater than the number of pixels PX in the other sub-display area.

[0030] On the other hand, for the sake of explanation, Figure 2a describes the case where the display area AA is divided into two sub-display areas, but the embodiments described herein are not limited to this, and the display area AA may be divided into three or more sub-display areas. For example, as shown in Figure 2b, the display area AA may be divided into a second sub-display area AA2, and a first sub-display area AA1 and a third sub-display area AA3 located on either side of the second sub-display area AA2.

[0031] Referring to Figure 1, the timing control unit 110 can control the gate drive unit 120 and the data drive unit 130 based on input video RGB and input control signal CS provided from an external source (e.g., a host system). For example, the input control signal CS includes timing signals such as a horizontal synchronization signal, a vertical synchronization signal, a data enable signal, and a clock signal, and the timing control unit 110 can generate a gate control signal GCS and a data control signal DCS based on the input control signal CS. The gate control signal GCS may be provided to the gate drive unit 120, and the data control signal DCS may be provided to the data drive unit 130.

[0032] Furthermore, the timing control unit 110 can rearrange the input video RGB in digital video data format to match the resolution of the display panel 140 to generate video data DATA, and provide it to the data drive unit 130.

[0033] The gate drive unit 120 can generate gate signals based on the gate control signal GCS and output gate signals to multiple gate wirings GL. For example, the gate drive unit 120 can sequentially output gate signals to multiple gate wirings GL on a pixel row basis. The gate control signal GCS may include a start signal for gate signal generation, multiple clock signals, etc.

[0034] In one embodiment, the gate drive unit 120 can generate scan signals and light emission signals based on the gate control signal GCS. For example, the gate drive unit 120 may include at least one scan drive unit and at least one light emission drive unit. The scan drive unit can generate scan signals in a row-by-row manner to drive at least one scan wiring connected for each pixel row and supply them to a plurality of scan wirings. The light emission drive unit can generate light emission signals in a row-by-row manner to drive at least one light emission signal wiring connected for each pixel row and supply them to a plurality of light emission signal wirings.

[0035] The data drive unit 130 can convert the digital video data DATA provided by the timing control unit 110 into an analog data signal based on the data control signal DCS and supply it to multiple data wirings DL.

[0036] A display device 100 according to one embodiment of this specification can display images at various drive frequencies depending on the driving conditions. Here, the drive frequency may mean the number of times a data signal is substantially written to the drive transistor included in the pixel PX. For example, the drive frequency may indicate the number of times the display image is reproduced per second. That is, the display device 100 can display images in response to various drive frequencies. On the other hand, in this specification, the drive frequency may also be named the image refresh rate, screen reproduction rate, or screen scanning rate.

[0037] In one embodiment, the output frequency of the data drive unit 130 and / or the output frequency of the gate drive unit 120 that outputs a gate signal for a single horizontal line, for example, a single pixel row, can be determined in accordance with the drive frequency of the display device 100. For example, the drive frequency for driving video may be approximately 60Hz or higher, for example, 60Hz, 80Hz, 96Hz, 120Hz, 240Hz, etc., which may be considered a relatively high frequency. As another example, the drive frequency for driving still images, etc., may be approximately 30Hz or lower, for example, 30Hz, 10Hz, 1Hz, etc., which may be considered a relatively low frequency. Therefore, the display device 100 can adjust the output frequency of the gate drive unit 120 and the corresponding output frequency of the data drive unit 130 for a single horizontal line, for example, a single pixel row, depending on the drive conditions.

[0038] In one embodiment, the display device 100 can independently drive multiple sub-display areas included in display area AA. For example, depending on the drive mode of the display device 100, the display device 100 can drive multiple sub-display areas included in display area AA at the same drive frequency, or drive at least some of the multiple sub-display areas at different drive frequencies.

[0039] On the other hand, when the display device 100 controls the drive frequency for each sub-display area of ​​display area AA, the corresponding sub-display area does not have to be a fixed area. That is, the display device 100 according to one embodiment of this specification can divide display area AA into two or more sub-display areas based on a position where the drive frequency is to be divided in accordance with the displayed image, for example, a horizontal wiring where the drive frequency is to be divided, and drive each sub-display area with a different drive frequency.

[0040] Thus, the display device 100 according to one embodiment of this specification is not limited to a fixed area, but can be freely divided into display area AA of the display device 100 in accordance with the displayed image, and the drive frequency can be controlled for each area. Therefore, by controlling the drive frequency for each area in accordance with the displayed image, power consumption can be improved.

[0041] In the following, the pixel PX and its driving method will be described in more detail with reference to Figures 3 to 4b, and the driving method by which the display device 100 according to the embodiment of this specification displays images at various driving frequencies will be described in more detail with reference to Figures 5 to 17.

[0042] Figure 3 is a circuit diagram showing an example of pixels included in the display device shown in Figure 1.

[0043] Referring to Figure 3, a pixel PX may include a light-emitting element ED, a drive transistor DT, multiple switching transistors M1 to M7, and a storage capacitor Cst.

[0044] A drive transistor DT may be connected between a first power supply wire PL1 providing a high potential supply voltage VDD and a second power supply wire PL2 providing a low potential supply voltage VSS. The drive transistor DT can control the drive current applied to the light-emitting element ED by the source-gate voltage. For example, the drive transistor DT can control the drive current flowing from the first power supply wire PL1, which provides a high potential supply voltage VDD in accordance with the voltage of the gate electrode, through the light-emitting element ED to the second power supply wire PL2, which provides a low potential supply voltage VSS. For this purpose, the high potential supply voltage VDD may be set to a higher voltage than the low potential supply voltage VSS. For example, the high potential supply voltage VDD may be a positive voltage, and the low potential supply voltage VSS may be a negative voltage.

[0045] The first switching transistor M1 may be connected between the data trace DL, which provides the data signal Vdata, and the first electrode of the drive transistor DT, for example, the source electrode, which is the second node N2. The gate electrode of the first switching transistor M1 may be connected to the second scan trace SL2. The first switching transistor M1 can be turned on when the second scan signal SCAN2 is supplied to the second scan trace SL2, thereby electrically connecting the data trace DL and the second node N2.

[0046] The second switching transistor M2 may be connected between the second electrode of the driving transistor DT, for example, the drain electrode at the third node N3 and the gate electrode at the first node N1. The gate electrode of the second switching transistor M2 may be connected to the first scan wiring SL1. The second switching transistor M2 can be turned on when the first scan signal SCAN1 is supplied to the first scan wiring SL1, thereby electrically connecting the gate electrode and drain electrode of the driving transistor DT, for example, the first node N1 and the third node N3. When the second switching transistor M2 is turned on, the driving transistor DT may be connected in diode form.

[0047] A third switching transistor M3 may be connected between the first node N1 and the third power supply wiring PL3, which provides the first initialization voltage Vini. The gate electrode of the third switching transistor M3 may be connected to the fourth scan wiring SL4. The third switching transistor M3 can be turned on when the fourth scan signal SCAN4 is supplied to the fourth scan wiring SL4, supplying the first initialization voltage Vini to the first node N1. In this case, the gate electrode of the drive transistor DT, which is the first node N1, may be initialized to the first initialization voltage Vini. For this purpose, the first initialization voltage Vini may be set to a voltage lower than the lowest level of the data signal Vdata supplied to the data wiring DL.

[0048] A fourth switching transistor M4 may be connected between a fourth node N4, which is the first electrode of the light-emitting element ED, and a fourth power supply line PL4, which provides a second initialization voltage VAR. The gate electrode of the fourth switching transistor M4 may be connected to a third scan line SL3. The fourth switching transistor M4 can be turned on when a third scan signal SCAN3 is supplied to the third scan line SL3, supplying the second initialization voltage VAR to the fourth node N4, which is the first electrode of the light-emitting element ED. In this case, the parasitic capacitor of the light-emitting element ED may be discharged. This may prevent unintended micro-emissions, thereby improving the black representation capability of the pixel PX.

[0049] On the other hand, the voltage levels of the first initialization voltage Vini and the second initialization voltage VAR may be different from each other. That is, the voltage used to initialize the first node N1 and the voltage used to initialize the fourth node N4 may be set to be different from each other.

[0050] In low-frequency driving, where the length of a single frame period is long, if the first initialization voltage Vini supplied to the first node N1 is too low, a strong on-bias is applied to the drive transistor DT, which can cause a shift in the threshold voltage of the drive transistor DT during that frame period. Such hysteresis characteristics can cause flicker in low-frequency driving. Therefore, in a low-frequency driven display device 100, a first initialization voltage Vini higher than the low-potential power supply voltage VSS may be required.

[0051] However, if the voltage level of the second initialization voltage VAR supplied to the fourth node N4 for the initialization of the light-emitting element ED is higher than a predetermined standard, the voltage of the parasitic capacitor of the light-emitting element ED may not be discharged but rather charged. Therefore, the voltage level of the second initialization voltage VAR must be low enough to discharge the voltage of the parasitic capacitor of the light-emitting element ED. For example, taking into account the threshold voltage of the light-emitting element ED, the voltage level of the second initialization voltage VAR may be set so that it is lower than the sum of the threshold voltage of the light-emitting element ED and the low-potential power supply voltage VSS.

[0052] However, this is illustrative, and the voltage levels of the first initialization voltage Vini and the second initialization voltage VAR can be set in various ways. For example, the voltage levels of the first initialization voltage Vini and the second initialization voltage VAR may be substantially the same.

[0053] A fifth switching transistor M5 may be connected between the first power supply wiring PL1 and the second node N2. The gate electrode of the fifth switching transistor M5 may be connected to the light emission control wiring EL. The fifth switching transistor M5 may be turned off when a light emission control signal EM is supplied to the light emission control wiring EL, and turned on otherwise. When the fifth switching transistor M5 is turned on, the second node N2 may be electrically connected to the first power supply wiring PL1.

[0054] The sixth switching transistor M6 may be connected between the drain electrode of the drive transistor DT, for example, the third node N3, and the first electrode of the light-emitting element ED, for example, the fourth node N4. The gate electrode of the sixth switching transistor M6 may be connected to the light-emitting control wiring EL. The sixth switching transistor M6 may be controlled substantially identically to the fifth switching transistor M5. When the sixth switching transistor M6 is turned on, the third node N3 and the fourth node N4 may be electrically coupled.

[0055] The seventh switching transistor M7 may be connected between the second node N2 and the fifth power supply wiring PL5, which provides the bias voltage Vobs. The gate electrode of the seventh switching transistor M7 may be connected to the third scan wiring SL3. The seventh switching transistor M7 can be turned on when the third scan signal SCAN3 is supplied to the third scan wiring SL3 and supply the bias voltage Vobs to the second node N2, which is the source electrode of the drive transistor DT.

[0056] In one embodiment, the bias voltage Vobs may have a level similar to the voltage level of the black tone data signal Vdata. For example, the bias voltage Vobs may have a voltage level of approximately 5-7V, but this is illustrative and the voltage level of the bias voltage Vobs is not limited thereto.

[0057] As a result, a predetermined high voltage can be applied to the source electrode of the drive transistor DT by turning on the seventh switching transistor M7. At this time, if the second switching transistor M2 is in the turned-off state, the drive transistor DT may be in an on-bias state.

[0058] Here, by periodically supplying a bias voltage Vobs to the second node N2, the bias state of the drive transistor DT changes periodically, and the threshold voltage characteristics of the drive transistor DT can be altered. Therefore, it is possible to prevent the characteristics of the drive transistor DT from becoming fixed in a specific state and degrading during low-frequency driving.

[0059] A storage capacitor Cst may be connected between the first power supply wiring PL1 and the first node N1. By connecting one electrode of the storage capacitor Cst to the first power supply wiring PL1, a constant high-potential power supply voltage VDD can be continuously supplied to that electrode of the storage capacitor Cst. Therefore, the voltage at the first node N1 can be maintained at the voltage level of the voltage supplied to the first node N1 without being affected by other parasitic capacitors. In other words, the storage capacitor Cst can store the voltage applied to the first node N1.

[0060] On the other hand, the drive transistor DT, the first switching transistor M1, the fourth switching transistor M4, the fifth switching transistor M5, the sixth switching transistor M6, and the seventh switching transistor M7 may be composed of polysilicon semiconductor transistors, such as PMOS transistors, and the second switching transistor M2 and the third switching transistor M3 may be composed of oxide semiconductor transistors, such as NMOS transistors, but are not limited to these.

[0061] The first electrode of the light-emitting element ED, for example, the anode electrode, may be connected to a fourth node N4, and the second electrode, for example, the cathode electrode, may be connected to a second power supply wiring PL2 that provides a low potential power supply voltage VSS. The light-emitting element ED can generate light of a predetermined brightness in response to the drive current supplied from the drive transistor DT.

[0062] Figures 4a and 4b are waveform diagrams illustrating an example of pixel driving in Figure 3.

[0063] For example, Figure 4a shows an example of a signal supplied to pixel PX during the first display period DP1, and Figure 4b shows an example of a signal supplied to pixel PX during the second display period DP2.

[0064] Referring to Figures 3, 4a, and 4b, the pixel PX can be driven during a first display period DP1 and a second display period DP2.

[0065] With variable frequency drive that controls the frame frequency, one frame period may include a first display period DP1. Furthermore, depending on the frame frequency, a second display period DP2 may occur at least once. For example, in one frame period, the display device 100 may be driven during the first display period DP1, and then during the second display period DP2.

[0066] The first display period DP1 may include a first non-emitting period NEP1 and a first emitting period EP1. The second display period DP2 may include a second non-emitting period NEP2 and a second emitting period EP2. For example, the first non-emitting period NEP1 and the second non-emitting period NEP2 may represent a period during which the path of the drive current flowing from the first power supply wiring PL1 through the light-emitting element ED to the second power supply wiring PL2 is interrupted, and the first emitting period EP1 and the second emitting period EP2 may represent a period during which the path of the drive current is formed and the light-emitting element ED emits light based on the drive current.

[0067] The first display period DP1 may include a period during which data signals Vdata corresponding to the displayed image are written to pixels PX. For example, data signals Vdata may be written during the first non-emitting period NEP1 of the first display period DP1.

[0068] During the second display period DP2, the data signal Vdata is not supplied, and the third scan signal SCAN3 may be supplied to the third scan wiring SL3 to control the drive transistor DT of the pixel PX to an on-bias state and initialize the light-emitting element ED.

[0069] As shown in Figures 4a and 4b, the first non-emission period NEP1 includes the first to sixth drive periods S1 to S6, and the second non-emission period NEP2 may include the seventh drive period S7.

[0070] In one embodiment, the first scan signal SCAN1, the second scan signal SCAN2, and the fourth scan signal SCAN4 may be supplied only during the first non-emitting period NEP1. On the other hand, the first scan signal SCAN1 may be supplied multiple times during the first non-emitting period NEP1.

[0071] In one embodiment, the third scan signal SCAN3 may be supplied during the first non-emission period NEP1 and the second non-emission period NEP2. Furthermore, as shown in Figures 4a and 4b, the third scan signal SCAN3 may be supplied multiple times during the first non-emission period NEP1 and once during the second non-emission period NEP2. However, the embodiments herein are not limited thereto; for example, the third scan signal SCAN3 may also be supplied multiple times during the second non-emission period NEP2.

[0072] On the other hand, the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, and the fourth scan signal SCAN4 are supplied from at least one scan drive unit included in the gate drive unit 120, and the light emission control signal EM may be supplied from at least one light emission drive unit included in the gate drive unit 120.

[0073] The light emission control signal EM can be maintained at a gate-off level, for example, a high level H, during the first non-emission period NEP1 and the second non-emission period NEP2. This keeps the fifth switching transistor M5 and the sixth switching transistor M6 in a turned-off state, respectively, during the first non-emission period NEP1 and the second non-emission period NEP2, thereby interrupting the path of the drive current flowing from the first power supply wiring PL1 through the light-emitting element ED to the second power supply wiring PL2.

[0074] First, to explain the first display period DP1, referring to Figures 3 and 4a, during the first drive period S1, the first scan signal SCAN1 is supplied to the first scan wiring SL1, and the second switching transistor M2 can be turned on. This connects the gate electrode and drain electrode of the drive transistor DT, and a diode connection can be established.

[0075] Thereafter, during the second drive period S2, the first scan signal SCAN1 may be supplied to the first scan wiring SL1, and the third scan signal SCAN3 may be supplied to the third scan wiring SL3. For example, the supply of the first scan signal SCAN1 supplied during the first drive period S1 may be maintained until the second drive period S2. That is, after the second switching transistor M2 is turned on during the first drive period S1 and the second drive period S2, the fourth switching transistor M4 and the seventh switching transistor M7 may be turned on.

[0076] As a result, when the seventh switching transistor M7 is turned on with the gate electrode and drain electrode of the driving transistor DT connected, the bias voltage Vobs can be transmitted from the second node N2 to the first node N1. For example, the voltage difference between the second node N2 and the first node N1 can be reduced to the threshold voltage level of the driving transistor DT. Therefore, the magnitude of the gate-source voltage of the driving transistor DT can be very low during the second driving period S2. For example, the driving transistor DT can be set to an off-bias state. Thus, in order to prevent an unintended increase in brightness due to the supply of the bias voltage Vobs before writing the data signal during the second driving period S2, the supply of the first scan signal SCAN1 and the third scan signal SCAN3 can be controlled so that the seventh switching transistor M7 is turned on while the second switching transistor M2 is turned on.

[0077] Furthermore, a third scan signal SCAN3 supplied during the second drive period S2 can turn on a fourth switching transistor M4. This can supply a second initialization voltage VAR to the first electrode of the light-emitting element ED, for example, at the fourth node N4. This initializes the first electrode of the light-emitting element ED based on the voltage level of the second initialization voltage VAR, and can discharge the parasitic capacitor of the light-emitting element ED. This can improve the black representation capability of the pixel PX.

[0078] Subsequently, during the third drive period S3, the fourth scan signal SCAN4 is supplied to the fourth scan wiring SL4, and the third switching transistor M3 can be turned on. When the third switching transistor M3 is turned on, the first initialization voltage Vini can be supplied to the gate electrode of the drive transistor DT. This allows the gate voltage of the drive transistor DT to be initialized based on the first initialization voltage Vini. Consequently, a strong on-bias is applied to the drive transistor DT, and its hysteresis characteristics may change. For example, the threshold voltage may be shifted.

[0079] On the other hand, the supply of the fourth scan signal SCAN4 can be maintained even after the third drive period S3. For example, as shown in Figure 4a, the fourth scan signal SCAN4 can maintain a gate-on level, for example, a high level H, during the fourth drive period S4 after the third drive period S3.

[0080] Subsequently, during the fourth drive period S4, the first scan signal SCAN1 is supplied to the first scan wiring SL1, and the second switching transistor M2 can be turned on again.

[0081] Thereafter, the second scan signal SCAN2 may be supplied to the second scan wiring SL2 in superimposition with at least a portion of the period during which the first scan signal SCAN1 is supplied in the fifth drive period S5. As a result, the first switching transistor M1 may be turned on by the second scan signal SCAN2, and the data signal Vdata may be provided to the second node N2.

[0082] Here, the drive transistor DT is connected in diode form by the turned-on second switching transistor M2, so that both data signal writing and threshold voltage compensation can be performed. On the other hand, the first scan signal SCAN1 is supplied before the supply of the second scan signal SCAN2 and after the supply of the second scan signal SCAN2 is interrupted, so that the threshold voltage of the drive transistor DT can be compensated for a sufficient amount of time.

[0083] Subsequently, during the sixth drive period S6, the third scan signal SCAN3 is again supplied to the third scan wiring SL3, and the fourth switching transistor M4 and the seventh switching transistor M7 may be turned on. Turning on the seventh switching transistor M7 may supply a bias voltage Vobs to the first node N1.

[0084] On the other hand, the effect of the strong on-bias applied during the third drive period S3 can be eliminated by writing the data signal Vdata and performing threshold voltage compensation. For example, threshold voltage compensation during the supply interval of the first scan signal SCAN1, including the fourth drive period S4 and the fifth drive period S5, can significantly reduce the voltage difference between the gate voltage and source voltage of the drive transistor DT. This then changes the characteristics of the drive transistor DT, and an increase in the drive current during the first light emission period EP1 or a lifting of the black gradation may be observed.

[0085] To prevent such characteristic changes, the seventh switching transistor M7 can be turned on during the sixth drive period S6 by supplying the third scan signal SCAN3. Accordingly, the drive transistor DT can be set to an on-bias state during the sixth drive period S6 by supplying a bias voltage Vobs to the first electrode of the drive transistor DT, for example, the source electrode.

[0086] Furthermore, a second initialization voltage VAR can be supplied to the first electrode of the light-emitting element ED by the fourth switching transistor M4, which is turned on during the sixth drive period S6. This allows the first electrode of the light-emitting element ED to be initialized based on the voltage level of the second initialization voltage VAR.

[0087] After the sixth drive period S6, the supply of the light emission control signal EM to the light emission control wiring EL is interrupted, for example, the light emission control signal EM transitions to a low level L, ending the first non-light emission period NEP1 and allowing the first light emission period EP1 to proceed. In this case, the fifth switching transistor M5 and the sixth switching transistor M6 may be turned on.

[0088] During the first light emission period EP1, a drive current corresponding to the data signal Vdata written in the fifth drive period S5 is supplied to the light-emitting element ED, and the light-emitting element ED can emit light based on the drive current.

[0089] Next, referring to Figures 3 and 4b to describe the second display period DP2, the second display period DP2 may include a second non-emitting period NEP2 and a second emitting period EP2, and the second non-emitting period NEP2 may include a seventh drive period S7.

[0090] In one embodiment, the waveform of the light emission control signal EM during the second display period DP2 may be substantially the same as the waveform of the light emission control signal EM during the first display period DP1.

[0091] In one embodiment, the first scan signal SCAN1, the second scan signal SCAN2, and the fourth scan signal SCAN4 may not be supplied during the second display period DP2. For example, during the second display period DP2, the first scan signal SCAN1 and the fourth scan signal SCAN4 may be maintained at a gate-off level, e.g., a low level L, and the second scan signal SCAN2 may be maintained at a gate-off level, e.g., a high level H. This allows the first switching transistor M1, the second switching transistor M2, and the third switching transistor M3 to be maintained in a turn-off state during the second display period DP2.

[0092] During the second non-emitting period NEP2, the third scan signal SCAN3 is supplied during the seventh driving period S7, which can turn on the fourth switching transistor M4 and the seventh switching transistor M7. As a result, the turned-on fourth switching transistor M4 supplies the second initialization voltage VAR to the first electrode of the light-emitting element ED, thereby initializing the first electrode of the light-emitting element ED based on the second initialization voltage VAR, and the turned-on seventh switching transistor M7 can supply the bias voltage Vobs to the source electrode of the driving transistor DT, for example, the first node N1.

[0093] After the seventh drive period S7, the supply of the light emission control signal EM to the light emission control wiring EL is interrupted, for example, the light emission control signal EM transitions to a low level L, ending the second non-light emission period NEP2 and allowing the second light emission period EP2 to proceed. In this case, the fifth switching transistor M5 and the sixth switching transistor M6 may be turned on.

[0094] During the second light emission period EP2, a drive current corresponding to the data signal Vdata written during the first display period DP1 is supplied to the light-emitting element ED, and the light-emitting element ED can emit light based on the drive current.

[0095] On the other hand, while Figure 4b describes the case where the third scan signal SCAN3 is supplied to the third scan wiring SL3 once, the embodiments of this specification are not limited thereto, and for example, the third scan signal SCAN3 may be supplied multiple times during the second non-emitting period NEP2.

[0096] Figure 5 is a block diagram showing a gate drive unit according to one embodiment of this specification.

[0097] On the other hand, Figure 5 shows both the gate drive unit 120, the display panel 140 (as described with reference to Figure 1), and the pixels PX arranged on the display panel 140.

[0098] Referring to Figures 1 to 5, the gate drive unit 120 can include a first scan drive unit SDV1, a second scan drive unit SDV2, a third scan drive unit SDV3, a fourth scan drive unit SDV4, and a light emission drive unit EDV.

[0099] The gate control signal GCS provided from the timing control unit 110 to the gate drive unit 120 may include a first scan start signal SVST1, a second scan start signal SVST2, a third scan start signal SVST3, a fourth scan start signal SVST4, and an illumination start signal EVST. The first scan start signal SVST1, the second scan start signal SVST2, the third scan start signal SVST3, the fourth scan start signal SVST4, and the illumination start signal EVST may be supplied to the first scan drive unit SDV1, the second scan drive unit SDV2, the third scan drive unit SDV3, the fourth scan drive unit SDV4, and the illumination drive unit EDV, respectively.

[0100] The width, supply timing, etc., of the first scan start signal SVST1, the second scan start signal SVST2, the third scan start signal SVST3, the fourth scan start signal SVST4, and the light emission start signal EVST may be determined by the pixel PX driving conditions and the frame frequency. For example, the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4, and the light emission control signal EM may be output based on the first scan start signal SVST1, the second scan start signal SVST2, the third scan start signal SVST3, the fourth scan start signal SVST4, and the light emission start signal EVST, respectively.

[0101] The first scan drive unit SDV1 can sequentially supply the first scan signal SCAN1 to a plurality of first scan lines S11 to S1n in response to the first scan start signal SVST1 (where n is an integer greater than 0). For example, the first scan drive unit SDV1 can include a plurality of first scan stages SST11 to SST1n that sequentially output the first scan signal SCAN1 to a plurality of first scan lines S11 to S1n on a pixel row basis.

[0102] The second scan drive unit SDV2 can sequentially supply the second scan signal SCAN2 to a plurality of second scan wirings S21 to S2n in response to the second scan start signal SVST2. For example, the second scan drive unit SDV2 can include a plurality of second scan stages SST21 to SST2n that sequentially output the second scan signal SCAN2 to a plurality of second scan wirings S21 to S2n on a pixel row basis.

[0103] The third scan drive unit SDV3 can sequentially supply the third scan signal SCAN3 to a plurality of third scan wirings S31 to S3n in response to the third scan start signal SVST3. For example, the third scan drive unit SDV3 may include a plurality of third scan stages SST31 to SST3n that sequentially output the third scan signal SCAN3 to a plurality of third scan wirings S31 to S3n on a pixel row basis.

[0104] The fourth scan drive unit SDV4 can sequentially supply the fourth scan signal SCAN4 to a plurality of fourth scan wirings S41 to S4n in response to the fourth scan start signal SVST4. For example, the fourth scan drive unit SDV4 can include a plurality of fourth scan stages SST41 to SST4n that sequentially output the fourth scan signal SCAN4 to a plurality of fourth scan wirings S41 to S4n on a pixel row basis.

[0105] The light-emitting drive unit EDV can sequentially supply light-emitting control signals EM to multiple light-emitting control wires EL1 to ELn in response to the light-emitting start signal EVST. For example, the light-emitting drive unit EDV may include multiple light-emitting stages EST1 to ESTn that sequentially output light-emitting control signals EM to multiple light-emitting control wires EL1 to ELn on a pixel row basis.

[0106] On the other hand, as described above, the display device 100 according to one embodiment of this specification can display images at various drive frequencies depending on the driving conditions. For example, the display device 100 can control the drive frequency of the display panel 140 by adjusting the number of times the second display period DP2, as described with reference to Figures 3 to 4b. For example, in the second display period DP2, the third scan drive unit SDV3 can sequentially supply the third scan signal SCAN3 to a plurality of third scan wirings S31 to S3n, and the light emission drive unit EDV can sequentially supply the light emission control signal EM to a plurality of light emission control wirings EL1 to ELn. On the other hand, in the second display period DP2, the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4 may not supply the first scan signal SCAN1, the second scan signal SCAN2, and the fourth scan signal SCAN4, respectively. That is, in the second display period DP2, the first scan signal SCAN1, the second scan signal SCAN2, and the fourth scan signal SCAN4 may each be maintained at the gate-off level.

[0107] Furthermore, as explained with reference to Figures 1 to 2b, in one embodiment, the display device 100 can independently drive the drive frequencies of multiple sub-display areas included in the display area AA. For example, in the display panel 140 of Figure 2b, when the first sub-display area AA1 and the third sub-display area AA3 are driven at a low frequency and the second sub-display area AA2 is driven at a high frequency, the number of times the pixels PX located in the first sub-display area AA1 and the pixels PX located in the third sub-display area AA3 are driven during the second display period DP2 during one frame period may be greater than the number of times the pixels PX located in the second sub-display area AA2 are driven during the second display period DP2. That is, in the display panel 140 of Figure 2b, when the first sub-display area AA1 and the third sub-display area AA3 are driven at a low frequency and the second sub-display area AA2 is driven at a high frequency, the display device 100 can increase the number of times the pixels PX are driven during the second display period DP2 in the first sub-display area AA1 and the third sub-display area AA3 to drive them at a low frequency.

[0108] On the other hand, in the case of a typical conventional gate drive unit, it is implemented using a shift register method, in which the current stage outputs a gate signal in response to a carry signal output from a previous stage. In order to control the drive frequency of pixels arranged on the display panel, a conventional display device can either provide the gate drive unit with a start signal for generating the corresponding scan signals at a gate-off level to maintain the signal levels of the first scan signal SCAN1, the second scan signal SCAN2, and the fourth scan signal SCAN4 at a gate-off level during the second display period DP2 described above, or it can control the gate drive unit so that the carry signal is output at a gate-off level.

[0109] However, as mentioned above, when the first sub-display area AA1 and the third sub-display area AA3 of the display panel 140 are driven at a low frequency, and the second sub-display area AA2 is driven at a high frequency, in the case of a conventional gate drive unit implemented using a general shift register method, the carry signal output from the stage for providing the gate signal (scan signal) to the pixels located in the first sub-display area AA1 is output at the gate-off level. Therefore, the gate signal (scan signal) provided to the pixels located in the second sub-display area AA2 is inevitably maintained at the gate-off level. Thus, conventional gate drive units and display devices including them have limitations in controlling the drive frequency by dividing the display area into separate areas.

[0110] Therefore, in the case of the gate drive unit 120 according to one embodiment of this specification, one stage may include a carry unit for outputting a carry signal and an output unit for controlling whether or not a gate signal (scan signal) is output. As a result, the gate drive unit 120 according to one embodiment of this specification and the display device 100 including it can divide the display area AA into areas and control the drive frequency.

[0111] For a more detailed explanation of this, please refer to Figures 6 through 17 below.

[0112] Figure 6 is a block diagram showing an example of the gate drive unit in Figure 5.

[0113] For example, the multiple stages STG1 to STG4 included in the gate drive unit 620 shown in Figure 6 may correspond to multiple scan stages included in any one of the drive units included in the gate drive unit 120 described with reference to Figure 5: the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4. That is, at least one of the scan drive units among the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4 is embodied in the gate drive unit 620 shown in Figure 6, and the output frequency of the scan signal of the corresponding scan drive unit can be controlled. For example, the start signal VST shown in Figure 6 may correspond to any one of the first scan start signal SVST1 supplied to the first scan drive unit SDV1, the second scan start signal SVST2 supplied to the second scan drive unit SDV2, and the fourth scan start signal SVST4 supplied to the fourth scan drive unit SDV4, as described with reference to Figure 5. However, this is merely illustrative, and the embodiments of this specification are not limited thereto.

[0114] On the other hand, for the sake of explanation, Figure 6 shows the four stages STG1 to STG4 included in the gate drive unit 620 and the multiple gate signals GATE1 to GATE4 output from them.

[0115] Referring to Figure 6, the gate drive unit 620 can include multiple stages STG1 to STG4. Each of the multiple stages STG1 to STG4 is connected to its corresponding gate wiring GL1 to GL4, and can output gate signals GATE1 to GATE4 based on multiple clock signals CLK1 and CLK2 and multiple control clock signals CCLK1 and CCLK2.

[0116] In one embodiment, the multiple stages STG1 to STG4 included in the gate drive unit 620 can be linked (cascade) in a subordinate manner.

[0117] For example, the second stage STG2 may be linked to the first stage STG1, the third stage STG3 may be linked to the second stage STG2, and the fourth stage STG4 may be linked to the third stage STG3. Here, multiple stages STG1 to STG4 may have substantially the same configuration.

[0118] Each of the multiple stages STG1 to STG4 may include a carry section for outputting a carry signal and an output section for controlling the output of a gate signal. For example, the first stage STG1 includes a first carry section CRY1 for generating a first carry signal CR1 and a first output section OUT1 for controlling the output of a first gate signal GATE1; the second stage STG2 includes a second carry section CRY2 for generating a second carry signal CR2 and a second output section OUT2 for controlling the output of a second gate signal GATE2; the third stage STG3 includes a third carry section CRY3 for generating a third carry signal CR3 and a third output section OUT3 for controlling the output of a third gate signal GATE3; and the fourth stage STG4 includes a fourth carry section CRY4 for generating a fourth carry signal CR4 and a fourth output section OUT4 for controlling the output of a fourth gate signal GATE4.

[0119] Each of the multiple carry units CRY1 to CRY4 contained within the multiple stages STG1 to STG4 can receive an input signal. For example, the first carry unit CRY1 can receive the start signal VST. In addition, each of the second to fourth carry units CRY2 to CRY4 can receive one of the carry signals output from the carry unit of the previous stage, for example, the first to third carry signals CR1 to CR3. For example, the second carry unit CRY2 can receive the first carry signal CR1 output from the first carry unit CRY1, the third carry unit CRY3 can receive the second carry signal CR2 output from the second carry unit CRY2, and the fourth carry unit CRY4 can receive the third carry signal CR3 output from the third carry unit CRY3.

[0120] Furthermore, each of the multiple carry units CRY1 to CRY4 may be provided with one of multiple clock signals, for example, either a first clock signal CLK1 or a second clock signal CLK2.

[0121] In one embodiment, the carry units included in even-numbered stages can receive the first clock signal CLK1, and the carry units included in odd-numbered stages can receive the second clock signal CLK2. For example, the first carry unit CRY1 and the third carry unit CRY3 can each receive the second clock signal CLK2, and the second carry unit CRY2 and the fourth carry unit CRY4 can each receive the first clock signal CLK1. However, this is illustrative, and the carry units included in odd-numbered stages may receive the first clock signal CLK1, and the carry units included in even-numbered stages may receive the second clock signal CLK2.

[0122] The first clock signal CLK1 and the second clock signal CLK2 may have waveforms with the same period but no phase superimposition. For example, the second clock signal CLK2 may be set to a signal shifted by approximately half a period from the first clock signal CLK1.

[0123] Each of the multiple carry units CRY1 to CRY4 outputs a carry signal CR1 to CR4 through its output terminal, which can then be provided to the carry unit of the next stage. For example, the first carry signal CR1 output from the first carry unit CRY1 can be provided to the second carry unit CRY2, the second carry signal CR2 output from the second carry unit CRY2 can be provided to the third carry unit CRY3, and the third carry signal CR3 output from the third carry unit CRY3 can be provided to the fourth carry unit CRY4.

[0124] Furthermore, the multiple carry signals CR1 to CR4 output from the multiple carry units CRY1 to CRY4 contained in each of the multiple stages STG1 to STG4 can be provided to the output units OUT1 to OUT4 of the corresponding stage.

[0125] For example, the first carry signal CR1 output from the first carry unit CRY1 of the first stage STG1 is provided to the first output unit OUT1, the second carry signal CR2 output from the second carry unit CRY2 of the second stage STG2 is provided to the second output unit OUT2, the third carry signal CR3 output from the third carry unit CRY3 of the third stage STG3 is provided to the third output unit OUT3, and the fourth carry signal CR4 output from the fourth carry unit CRY4 of the fourth stage STG4 is provided to the fourth output unit OUT4.

[0126] Furthermore, each of the multiple output units OUT1 to OUT4 may be provided with one of multiple control clock signals, for example, either a first control clock signal CCLK1 or a second control clock signal CCLK2.

[0127] In one embodiment, output units included in odd-numbered stages can receive the first control clock signal CCLK1, and output units included in even-numbered stages can receive the second control clock signal CCLK2. For example, the first output unit OUT1 and the third output unit OUT3 can each receive the first control clock signal CCLK1, and the second output unit OUT2 and the fourth output unit OUT4 can each receive the second control clock signal CCLK2. However, this is illustrative, and output units included in even-numbered stages can receive the first control clock signal CCLK1, and output units included in odd-numbered stages can receive the second control clock signal CCLK2.

[0128] The first control clock signal CCLK1 and the second control clock signal CCLK2 may have waveforms with the same period and no phase superimposition. For example, the second control clock signal CCLK2 may be set to a signal shifted by approximately 1 / 2 period from the first control clock signal CCLK1.

[0129] In one embodiment, the signal level of at least one of the first control clock signal CCLK1 and the second control clock signal CCLK2 can be controlled by the drive mode. For example, the signal levels of the first control clock signal CCLK1 and the second control clock signal CCLK2 can be controlled independently. As an example, as described above, in order to drive the pixel PX during the second display period DP2, at least one of the first control clock signal CCLK1 and the second control clock signal CCLK2 is maintained at a gate-off level, for example, a high level, during that period, so that the output unit to which the control clock signal is applied can provide a gate signal at the gate-off level. A more detailed explanation of this will be given later with reference to Figures 7 to 9c.

[0130] Multiple output units OUT1 to OUT4 included in multiple stages STG1 to STG4 can each output gate signals GATE1 to GATE4. In one embodiment, the multiple gate signals GATE1 to GATE4 output by each of the multiple output units OUT1 to OUT4 can be provided to the corresponding gate wiring GL1 to GL4.

[0131] On the other hand, although not shown separately in Figure 6, each of the multiple stages STG1 to STG4 includes multiple power input terminals, and the power supply voltage required to drive the multiple stages STG1 to STG4 can be applied through these multiple power input terminals.

[0132] For example, each of the multiple stages STG1 to STG4 can receive the voltage of a first power supply (e.g., the first power supply VGH in Figure 7) and the voltage of a second power supply (e.g., the second power supply VGL in Figure 7). The voltages of the first and second power supplies may have DC voltage levels. Here, the voltage level of the first power supply may be set higher than the voltage level of the second power supply.

[0133] In one embodiment, the multiple stages STG1 to STG4 included in the gate drive unit 620 may have substantially the same configuration, except for the type of input signal. For example, the first stage STG1, which is the first stage to receive the start signal VST, and the remaining stages, for example, the second to fourth stages STG2 to STG4, which receive the carry signals from previous stages, may have substantially the same circuit configuration, except for the input signal, i.e., the start signal VST or the carry signals from previous stages, and may operate substantially identically.

[0134] Accordingly, for the sake of clarity, in the following explanation, when describing the multiple stages STG1 to STG4 included in the gate drive unit 620, the configuration and drive method of the multiple stages STG1 to STG4 included in the gate drive unit 620 will be described based on the first stage STG1.

[0135] On the other hand, the transistors constituting each stage can be embodied in n-type or p-type MOSFET transistors. In the following embodiments, p-type transistors are used as examples, but the embodiments herein are not limited thereto.

[0136] Figure 7 is a circuit diagram showing an example of the first stage included in the gate drive unit of Figure 6.

[0137] Referring to Figures 6 and 7, the first stage STG1 may include a first carry unit CRY1 that outputs a first carry signal CR1 and a first output unit OUT1 that outputs a first gate signal GATE1. More specifically, the first output unit OUT1 may output a first gate signal GATE1 having a gate-on level pulse, or a first gate signal GATE1 that is maintained at a gate-off level, depending on the drive mode.

[0138] The first carry unit CRY1 receives an input signal, for example, a start signal VST, through a first input terminal 621, receives a second clock signal CLK2 through a second input terminal 622, is connected to a first power supply VGH through a first power supply input terminal 628, and can be connected to a second power supply VGL through a second power supply input terminal 629. Based on the start signal VST, the second clock signal CLK2, the first power supply VGH, and the second power supply VGL, the first carry unit CRY1 can generate and output a first carry signal CR1 through a first output terminal 623.

[0139] The first output unit OUT1 receives a first carry signal CR1 through a third input terminal 624, for example, a third input terminal 624 connected to the first output terminal 623 of the first carry unit CRY1, receives a first control clock signal CCLK1 through a fourth input terminal 625, is connected to a first power supply VGH through a first power supply input terminal 628, and is connected to a second power supply VGL through a second power supply input terminal 629. Based on the first carry signal CR1, the first control clock signal CCLK1, the first power supply VGH, and the second power supply VGL, the first output unit OUT1 can generate and output a first gate signal GATE1 through a second output terminal 626, for example, a first gate wiring GL1.

[0140] More specifically, the first carry portion CRY1 of the first stage STG1 may include first to sixth transistors T1 to T6, a first capacitor C1, a second capacitor C2, and a third capacitor C3. Depending on the embodiment, the first carry portion CRY1 may further include a first bridge voltage transistor Tbv1.

[0141] The first transistor T1 is connected between the first input terminal 621 and the first control node CN1 and may include a gate electrode connected to the second input terminal 622. The first transistor T1 is turned on when the second clock signal CLK2 supplied through the second input terminal 622 has a gate-on level, for example, a low level, thereby electrically coupling the first input terminal 621 and the first control node CN1. When the first transistor T1 is turned on, a start signal VST supplied through the first input terminal 621 may be supplied to the first control node CN1.

[0142] In one embodiment, the first transistor T1 may include first and second subtransistors T1a and T1b connected in series with each other. Each of the first and second subtransistors T1a and T1b may include a gate electrode commonly connected to the second input terminal 622. For example, the first transistor T1 may have a dual-gate structure. This can minimize current leakage from the first transistor T1.

[0143] The second transistor T2 is connected between the first power input terminal 628 and the second control node CN2 and may include a gate electrode connected to the first input terminal 621. The second transistor T2 can be turned on when the start signal VST supplied through the first input terminal 621 has a gate-on level, e.g., a low level, and can provide the second control node CN2 with a gate-off level, e.g., a high level voltage of the first power supply VGH provided from the first power input terminal 628.

[0144] In one embodiment, the second transistor T2 may include third and fourth subtransistors T2a and T2b connected in series with each other. Each of the third and fourth subtransistors T2a and T2b may include a gate electrode commonly connected to the first input terminal 621. For example, the second transistor T2 may have a dual-gate structure. This may minimize current leakage from the second transistor T2.

[0145] The third transistor T3 is connected between the second input terminal 622 and the first QB node QB1 and may include a gate electrode connected to the second control node CN2. The third transistor T3 can be turned on or turned off based on the voltage of the second control node CN2. When the third transistor T3 is turned on, the second input terminal 622 and the first QB node QB1 are electrically connected, and the second clock signal CLK2 provided to the second input terminal 622 may be provided to the first QB node QB1.

[0146] In one embodiment, the third transistor T3 may include fifth and sixth subtransistors T3a and T3b connected in series with each other. Each of the fifth and sixth subtransistors T3a and T3b may include a gate electrode commonly connected to the second control node CN2. For example, the third transistor T3 may have a dual-gate structure. This can minimize current leakage from the third transistor T3.

[0147] The fourth transistor T4 is connected between the first power input terminal 628 and the first QB node QB1 and may include a gate electrode connected to the first control node CN1. The fourth transistor T4 can be turned on or turned off based on the voltage of the first control node CN1. When the fourth transistor T4 is turned on, the voltage of the first power supply VGH provided through the first power input terminal 628 can be supplied to the first QB node QB1.

[0148] In one embodiment, the fourth transistor T4 may include seventh and eighth subtransistors T4a and T4b connected in series with each other. Each of the seventh and eighth subtransistors T4a and T4b may include a gate electrode commonly connected to the first control node CN1. For example, the fourth transistor T4 may have a dual-gate structure. This can minimize current leakage from the fourth transistor T4.

[0149] The fifth transistor T5 is connected between the second power input terminal 629 and the first output terminal 623 and may include a gate electrode connected to the first Q node Q1. For example, the gate electrode of the fifth transistor T5 connected to the first Q node Q1 may be connected to the first control node CN1 via the first bridge voltage transistor Tbv1. The fifth transistor T5 can be turned on or turned off by the voltage of the first Q node Q1.

[0150] Here, the first bridge voltage transistor Tbv1 is connected between the first control node CN1 and the first Q node Q1 and may include a gate electrode connected to the second power input terminal 629. Since the gate electrode of the first bridge voltage transistor Tbv1 is connected to the second power input terminal 629, which is supplied with the voltage of the second power supply VGL having a gate-on level, e.g., a low level, the first bridge voltage transistor Tbv1 can always remain turned on. This allows the voltage at the first control node CN1 and the voltage at the first Q node Q1 to have substantially the same value. Thus, the fifth transistor T5 can be turned on or turned off by the voltage at the first control node CN1.

[0151] For example, the fifth transistor T5 can be turned on when the voltage at the first Q node Q1 or the voltage at the first control node CN1 is at a gate-on level, e.g., a low level, thereby electrically connecting the second power input terminal 629 and the first output terminal 623. This allows the first carry signal CR1 output through the first output terminal 623 during the period when the fifth transistor T5 is turned on to be at a gate-on level, e.g., a low level.

[0152] The sixth transistor T6 is connected between the first power input terminal 628 and the first output terminal 623 and may include a gate electrode connected to the first QB node QB1. The sixth transistor T6 can be turned on or turned off by the voltage at the first QB node QB1.

[0153] For example, the sixth transistor T6 can be turned on when the voltage at the first QB node QB1 is at the gate-on level, e.g., a low level, thereby electrically connecting the first power input terminal 628 and the first output terminal 623. This allows the first carry signal CR1 output through the first output terminal 623 during the period when the sixth transistor T6 is turned on to be at the gate-off level, e.g., a high level.

[0154] Thus, the fifth transistor T5 of the first carry unit CRY1 can perform the pull-up function, and the sixth transistor T6 of the first carry unit CRY1 can perform the pull-down function.

[0155] A first capacitor C1 (or first boosting capacitor) may be connected between the second input terminal 622 and the second control node CN2. For example, the first capacitor C1 may include a first electrode connected to the second input terminal 622 and a second electrode connected to the second control node CN2.

[0156] The second capacitor C2 may be connected between the first Q node Q1 and the first output terminal 623. For example, the second capacitor C2 may include a first electrode connected to the first Q node Q1 and a second electrode connected to the first output terminal 623. The third capacitor C3 may be connected between the first QB node QB1 and the first output terminal 623. For example, the third capacitor C3 may include a first electrode connected to the first QB node QB1 and a second electrode connected to the first output terminal 623.

[0157] Next, the first output section OUT1 of the first stage STG1 may have a similar circuit structure to the first carry section CRY1, differing only in the input and output signals. For example, the first output section OUT1 may include the seventh to twelfth transistors T7 to T12, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6. In some embodiments, the first output section OUT1 may further include the second bridge voltage transistor Tbv2.

[0158] The seventh transistor T7 is connected between the third input terminal 624 and the third control node CN3 and may include a gate electrode connected to the fourth input terminal 625. The seventh transistor T7 can be turned on when the first control clock signal CCLK1 supplied through the fourth input terminal 625 has a gate-on level, for example, a low level, thereby electrically coupling the third input terminal 624 and the third control node CN3. When the seventh transistor T7 is turned on, the first carry signal CR1 supplied through the third input terminal 624 may be supplied to the third control node CN3.

[0159] In one embodiment, the seventh transistor T7 may include ninth and tenth subtransistors T7a and T7b connected in series with each other. Each of the ninth and tenth subtransistors T7a and T7b may include a gate electrode commonly connected to the fourth input terminal 625. For example, the seventh transistor T7 may have a dual-gate structure. This can minimize current leakage from the seventh transistor T7.

[0160] The eighth transistor T8 is connected between the first power input terminal 628 and the fourth control node CN4 and may include a gate electrode connected to the third input terminal 624. The eighth transistor T8 can be turned on when the first carry signal CR1 supplied through the third input terminal 624 has a gate-on level, e.g., a low level, and can provide the fourth control node CN4 with a gate-off level, e.g., a high level first power supply voltage VGH provided from the first power input terminal 628.

[0161] In one embodiment, the eighth transistor T8 may include eleventh and twelfth subtransistors T8a and T8b connected in series with each other. Each of the eleventh and twelfth subtransistors T8a and T8b may include a gate electrode commonly connected to the third input terminal 624. For example, the eighth transistor T8 may have a dual-gate structure. This may minimize current leakage from the eighth transistor T8.

[0162] The ninth transistor T9 is connected between the fourth input terminal 625 and the second QB node QB2 and may include a gate electrode connected to the fourth control node CN4. The ninth transistor T9 can be turned on or turned off based on the voltage at the fourth control node CN4. When the ninth transistor T9 is turned on, the fourth input terminal 625 and the second QB node QB2 are electrically connected, and a first control clock signal CCLK1 provided to the fourth input terminal 625 can be provided to the second QB node QB2.

[0163] In one embodiment, the ninth transistor T9 may include thirteenth and fourteenth subtransistors T9a and T9b connected in series with each other. Each of the thirteenth and fourteenth subtransistors T9a and T9b may include a gate electrode commonly connected to the fourth control node CN4. For example, the ninth transistor T9 may have a dual-gate structure. This can minimize current leakage from the ninth transistor T9.

[0164] The tenth transistor T10 is connected between the first power input terminal 628 and the second QB node QB2 and may include a gate electrode connected to the third control node CN3. The tenth transistor T10 can be turned on or turned off based on the voltage of the third control node CN3. When the tenth transistor T10 is turned on, the voltage of the first power supply VGH provided through the first power input terminal 628 can be supplied to the second QB node QB2.

[0165] In one embodiment, the tenth transistor T10 may include the fifteenth and sixteenth subtransistors T10a and T10b connected in series with each other. Each of the fifteenth and sixteenth subtransistors T10a and T10b may include a gate electrode commonly connected to the third control node CN3. For example, the tenth transistor T10 may have a dual-gate structure. This may minimize current leakage from the tenth transistor T10.

[0166] The 11th transistor T11 is connected between the second power input terminal 629 and the second output terminal 626 and may include a gate electrode connected to the second Q node Q2. For example, the gate electrode of the 11th transistor T11 connected to the second Q node Q2 may be connected to the third control node CN3 via the second bridge voltage transistor Tbv2. The 11th transistor T11 can be turned on or turned off by the voltage at the second Q node Q2.

[0167] Here, since the second bridge voltage transistor Tbv2 includes a gate electrode connected to the second power input terminal 629, just like the first bridge voltage transistor Tbv1, the second bridge voltage transistor Tbv2 can always remain in the turned-on state. As a result, the voltage at the third control node CN3 and the voltage at the second Q node Q2 can have substantially the same value. Thus, the eleventh transistor T11 can be turned on or turned off by the voltage at the third control node CN3.

[0168] For example, the 11th transistor T11 is turned on when the voltage at the second Q node Q2 or the voltage at the third control node CN3 is at a gate-on level, such as a low level, thereby electrically connecting the second power input terminal 629 and the second output terminal 626. As a result, the first gate signal GATE1 output through the second output terminal 626 during the period when the 11th transistor T11 is turned on may have a gate-on level, such as a low level.

[0169] The twelfth transistor T12 is connected between the first power input terminal 628 and the second output terminal 626 and may include a gate electrode connected to the second QB node QB2. The twelfth transistor T12 can be turned on or turned off by the voltage at the second QB node QB2.

[0170] For example, the 12th transistor T12 is turned on when the voltage at the second QB node QB2 is at the gate-on level, e.g., a low level, thereby electrically connecting the first power input terminal 628 and the second output terminal 626. As a result, the first gate signal GATE1 output through the second output terminal 626 during the period when the 12th transistor T12 is turned on may have a gate-off level, e.g., a high level.

[0171] Thus, the 11th transistor T11 of the first output unit OUT1 can perform the pull-up function, and the 12th transistor T12 of the first output unit OUT1 can perform the pull-down function.

[0172] A fourth capacitor C4 (or a second boosting capacitor) may be connected between the fourth input terminal 625 and the fourth control node CN4. For example, the fourth capacitor C4 may include a first electrode connected to the fourth input terminal 625 and a second electrode connected to the fourth control node CN4.

[0173] A fifth capacitor C5 may be connected between the second Q node Q2 and the second output terminal 626. For example, the fifth capacitor C5 may include a first electrode connected to the second Q node Q2 and a second electrode connected to the second output terminal 626.

[0174] The sixth capacitor C6 may be connected between the second QB node QB2 and the second output terminal 626. For example, the sixth capacitor C6 may include a first electrode connected to the second QB node QB2 and a second electrode connected to the second output terminal 626.

[0175] Figure 8 is a waveform diagram illustrating an example of the first stage drive shown in Figure 7.

[0176] As explained with reference to Figure 8, the gate electrodes of the first bridge voltage transistor Tbv1 and the second bridge voltage transistor Tbv2 are each connected to the second power supply input terminal 629 to which the voltage of the second power supply VGL is supplied. Therefore, the first bridge voltage transistor Tbv1 and the second bridge voltage transistor Tbv2 can maintain a turned-on state for all periods in which the gate drive unit 620 is driven, for example, the first to fifth periods S1 to S5, the period before and all periods thereafter. As a result, the voltage at the first control node CN1 and the voltage at the first Q node Q1 can be substantially the same in all periods, and the voltage at the third control node CN3 and the voltage at the second Q node Q2 can be substantially the same in all periods.

[0177] Referring to Figures 7 and 8, the first clock signal CLK1 and the second clock signal CLK2 may be supplied at different timings. For example, the second clock signal CLK2 may be set to a signal that is shifted by half a period from the first clock signal CLK1, for example, by one horizontal period of 1H.

[0178] Furthermore, the first control clock signal CCLK1 and the second control clock signal CCLK2 may be supplied at different timings. For example, the second control clock signal CCLK2 may be set to a signal that is shifted by half a period, for example, by one horizontal period 1H, from the first control clock signal CCLK1.

[0179] On the other hand, the high voltage level shown in Figure 8, for example, high level H, corresponds to the voltage of the first power supply VGH, and the low voltage level, for example, low level L, may correspond to the voltage of the second power supply VGL. For example, the voltage of the first power supply VGH may be a positive voltage, and the voltage of the second power supply VGL may be a negative voltage. However, this is illustrative, and high level H and low level L are not limited to these. For example, the voltages of high level H and low level L may be set depending on the type of transistor, the operating environment of the display device, etc.

[0180] In the following, with reference to Figures 6 to 8, we will examine the drive of the gate drive unit 620 according to one embodiment of this specification, for example, the drive of the first stage STG1. For the sake of convenience, we will first describe the operation of the first carry unit CRY1, and then the operation of the first output unit OUT1.

[0181] First, considering the operation of the first carry section CRY1, during the period prior to the first period P1, the first Q node Q1 may be maintained at a high level H, and the first QB node QB1 may be maintained at a low level L. As a result, the fifth transistor T5 is maintained in the turned-off state, and the sixth transistor T6 is maintained in the turned-on state, so that the first carry signal CR1 can be output at a high level H.

[0182] During the first period P1 and the second period P2, the start signal VST supplied through the first input terminal 621 may have a low level L. This allows the second transistor T2 to be turned on or remain in the turned-on state during the first period P1 and the second period P2.

[0183] As a result, during the first period P1 and the second period P2, the voltage of the first power supply VGH supplied at the first power input terminal 628 is supplied to the second control node CN2 through the turned-on second transistor T2, so the second control node CN2 may have a high level H. Also, due to the high level H of the second control node CN2, the third transistor T3 may be turned off or in a turned-off state during the first period P1 and the second period P2.

[0184] Furthermore, during the first period P1, the second clock signal CLK2 supplied through the second input terminal 622 may have a high level H. This allows the first transistor T1 to be turned off or remain in the turned-off state during the first period P1.

[0185] Thus, since the first transistor T1 and the third transistor T3 are turned off or kept in a turned-off state during the first period P1, the first Q node Q1 and the first QB node QB1 can be maintained at the voltage levels of the period prior to the first period P1. For example, during the first period P1, the first Q node Q1 may have a high level H, and the first QB node QB1 may have a low level L.

[0186] Next, during the second period P2, the second clock signal CLK2 supplied through the second input terminal 622 has a low level L, so the first transistor T1 can be turned on during the second period P2. As a result, a low-level L start signal VST is supplied to the first control node CN1 through the turned-on first transistor T1, and the first control node CN1 and the first Q node Q1 can transition from their existing high level H to a low level L.

[0187] Furthermore, during the second period P2, the first control node CN1 has a low level L, so the fourth transistor T4 can be turned on and the first QB node QB1 can transition from its existing low level L to a high level H. As a result, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off, and the first carry signal CR1 can be output at a low level L.

[0188] Next, during the third period P3, the start signal VST and the second clock signal CLK2 may transition to a high level H. This may cause the first transistor T1 and the second transistor T2 to be turned off or kept in a turned-off state, respectively.

[0189] Furthermore, during the third period P3, the voltage at the second control node CN2 may have the voltage of the first power supply VGH supplied through the second transistor T2, which was turned on during the previous second period P2, i.e., a high-level H voltage level. This may cause the third transistor T3 to be turned off or kept in the turned-off state during the third period P3.

[0190] Thus, in the third period P3, the first transistor T1 and the third transistor T3 are turned off or kept in a turned-off state, so that in the third period P3, the first Q node Q1 and the first QB node QB1 can be maintained at the voltage levels of the second period P2 prior to the third period P3. For example, in the third period P3, the first Q node Q1 may have a low level L and the first QB node QB1 may have a high level H. As a result, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off, and the first carry signal CR1 may be output at a low level L.

[0191] Next, in the fourth period P4, a high-level H start signal VST and a low-level L second clock signal CLK2 may be supplied. Here, the high-level H start signal VST keeps the second transistor T2 in a turned-off state, and the second clock signal CLK2 transitions from the existing high-level H to a low-level L, so the voltage at the second control node CN2 may transition from the existing high-level H to a low-level L due to the coupling of the first capacitor C1. As a result, in the fourth period P4, the first transistor T1 and the third transistor T3 are turned on, the high-level H start signal VST is supplied to the first control node CN1 so that the first Q node Q1 has a high-level H, and the low-level L second clock signal CLK2 is supplied to the first QB node QB1 so that the first QB node QB1 has a low-level L. As a result, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the first carry signal CR1 may be output at a high-level H.

[0192] Thereafter, even if the second clock signal CLK2 toggles between a low level L and a high level H during the period after the fifth period P5, including the fifth period P5, the start signal VST remains at a high level H for the duration of that period. Therefore, the first Q node Q1 can remain at a high level H, and the first QB node QB1 can remain at a low level L.

[0193] Next, considering the operation of the first output OUT1, during the period including the first period P1 and prior to the second period P2, the second Q node Q2 may be maintained at a high level H, and the second QB node QB2 may be maintained at a low level L. As a result, the 11th transistor T11 is maintained in the turn-off state, the 12th transistor T12 is maintained in the turn-on state, and the first gate signal GATE1 may be output at a high level H.

[0194] As mentioned above, the first carry signal CR1 can be output at a low level L during the second period P2 and the third period P3. This allows the eighth transistor T8 to be turned on or remain turned on during the second period P2 and the third period P3.

[0195] As a result, during the second period P2 and the third period P3, the voltage of the first power supply VGH supplied at the first power supply input terminal 628 through the turned-on eighth transistor T8 is supplied to the fourth control node CN4, so the fourth control node CN4 may have a high level H. Also, due to the high level H of the fourth control node CN4, the ninth transistor T9 may be turned off or in a turned-off state during the second period P2 and the third period P3.

[0196] Furthermore, during the second period P2, the first control clock signal CCLK1 supplied through the fourth input terminal 625 may have a high level H. This allows the seventh transistor T7 to be turned off or remain in the turned-off state during the second period P2.

[0197] Thus, in the second period P2, the seventh transistor T7 and the ninth transistor T9 are turned off or kept in a turned-off state, so in the second period P2, the second Q node Q2 and the second QB node QB2 may be maintained at the voltage levels of the period prior to the second period P2, for example, the voltage levels of the first period P1. For example, in the second period P2, the second Q node Q2 may have a high level H, and the second QB node QB2 may have a low level L.

[0198] Next, during the third period P3, the first control clock signal CCLK1 supplied through the fourth input terminal 625 has a low level L, so the seventh transistor T7 can be turned on during the third period P3. This supplies a first carry signal CR1 with a low level L to the third control node CN3 through the turned-on seventh transistor T7, and the third control node CN3 and the second Q node Q2 can transition from their existing high level H to a low level L.

[0199] Furthermore, during the third period P3, the third control node CN3 has a low level L, so the tenth transistor T10 can be turned on and the second QB node QB2 can transition from its existing low level L to a high level H. As a result, the eleventh transistor T11 is turned on and the twelfth transistor T12 is turned off, and the first gate signal GATE1 can be output at a low level L.

[0200] Next, during the fourth period P4, the first carry signal CR1 and the first control clock signal CCLK1 may transition to a high level H. This may cause the seventh transistor T7 and the eighth transistor T8 to be turned off or kept in the turned-off state, respectively.

[0201] Furthermore, during the fourth period P4, the voltage at the fourth control node CN4 may have the voltage of the first power supply VGH supplied through the eighth transistor T8, which was turned on during the previous third period P3, i.e., a high-level H voltage level. This may cause the ninth transistor T9 to also be turned off or kept in the turned-off state during the fourth period P4.

[0202] Thus, in the fourth period P4, the seventh transistor T7 and the ninth transistor T9 are turned off or kept in the turned-off state, so in the fourth period P4, the second Q node Q2 and the second QB node QB2 can be maintained at the voltage levels of the third period P3 prior to the fourth period P4. For example, in the fourth period P4, the second Q node Q2 may have a low level L and the second QB node QB2 may have a high level H. As a result, the eleventh transistor T11 is turned on and the twelfth transistor T12 is turned off, so that the first gate signal GATE1 can be output at a low level L.

[0203] Next, in the fifth period P5, a high-level H first carry signal CR1 and a low-level L first control clock signal CCLK1 may be supplied. Here, the high-level H first carry signal CR1 keeps the eighth transistor T8 in a turned-off state, and the first control clock signal CCLK1 transitions from the existing high level H to a low level L, so the voltage at the fourth control node CN4 may transition from the existing high level H to a low level L due to the coupling of the fourth capacitor C4. As a result, in the fifth period P5, the seventh transistor T7 and the ninth transistor T9 are turned on, the high-level H first carry signal CR1 is supplied to the third control node CN3 so that the second Q node Q2 has a high level H, and the low-level L first control clock signal CCLK1 is supplied to the second QB node QB2 so that the second QB node QB2 has a low level L. As a result, the 11th transistor T11 is turned off, the 12th transistor T12 is turned on, and the first gate signal GATE1 can be output at a high level H.

[0204] Thereafter, during the period from the fifth period P5 onward, even if the first control clock signal CCLK1 toggles between a low level L and a high level H, the first carry signal CR1 remains at a high level H during that period. Therefore, the second Q node Q2 may remain at a high level H, and the second QB node QB2 may remain at a low level L.

[0205] Thus, the first gate signal GATE1 output from the first output unit OUT1 in response to the first carry signal CR1 output by the first carry unit CRY1 may have the same pulse width as the first carry signal CR1, but with a waveform shifted by 1 horizontal period 1H.

[0206] On the other hand, as described above, in the case of the gate drive unit 620 and the display device 100 including it according to one embodiment of this specification, the voltage level of the gate signal can be controlled by utilizing the output units included in each stage for controlling the drive frequency.

[0207] For example, unlike the waveform diagram in Figure 8, if the first control clock signal CCLK1 applied to the first output OUT1 of the first stage STG1 is maintained at a gate-off level, for example, a high level H, the seventh transistor T7 may be maintained in a turn-off state. As a result, the first carry signal CR1, which is low level L and supplied to the third input terminal 624, is not supplied to the third control node CN3, so that the eleventh transistor T11 remains in a turn-off state for the duration that the first control clock signal CCLK1 is maintained at a high level H, and the first gate signal GATE1 output to the first gate wiring GL1 may be maintained at a gate-off level, for example, a high level H.

[0208] As a result, the gate drive unit 620 and the display device 100 including it according to one embodiment of this specification can adjust the output frequencies of the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4 included in the gate drive unit 620 by controlling the signal level of the first control clock signal CCLK1 or the second control clock signal CCLK2 applied to the output unit of each stage. Therefore, the gate drive unit 620 and the display device 100 including it according to one embodiment of this specification can freely control the drive frequency for each area of ​​the display area AA, for example, for each pixel row.

[0209] For a more detailed explanation of this, please refer to Figures 9a to 9c.

[0210] Figures 9a to 9c are waveform diagrams illustrating an example of the drive operation of the gate drive unit in Figure 6.

[0211] For example, Figures 9a to 9c show waveform diagrams of the signals applied to the gate drive unit 620 in the first mode (indicated as "Mode1" in Figure 9a) and the second mode (indicated as "Mode2" in Figures 9b and 9c, respectively), including the start signal VST, the first clock signal CLK1, the second clock signal CLK2, the first control clock signal CCLK1, and the second control clock signal CCLK2, along with multiple carry signals CR1 to CR4 output from multiple carry units CRY1 to CRY4 and multiple gate signals GATE1 to GATE4 output from multiple output units OUT1 to OUT4.

[0212] On the other hand, in this specification, the first mode means a mode in which multiple gate signals GATE1 to GATE4 are sequentially output to all pixel rows, and pixels PX located in all pixel rows are driven by a first display period DP1 as described with reference to Figure 4a, and the second mode may mean a mode in which the gate signal output to pixels PX located in at least one of the multiple pixel rows is driven by a second display period DP2 in which the gate signal is maintained at a gate-off level.

[0213] First, to explain the first mode, referring to Figures 6, 7, and 9a, the start signal VST, the first clock signal CLK1, and the second clock signal CLK2 allow the multiple carry units CRY1 to CRY4 contained in the multiple stages STG1 to STG4 to sequentially output multiple carry signals CR1 to CR4. For example, multiple carry signals CR1 to CR4 can be output sequentially in units of one horizontal period of 1H.

[0214] In one embodiment, in the first mode, the first control clock signal CCLK1 and the second control clock signal CCLK2 can toggle between a high level H and a low level L. For example, in the first mode, the first control clock signal CCLK1 and the second control clock signal CCLK2 can each transition from a high level H to a low level L or from a low level L to a high level H every 1 / 2 period.

[0215] As a result, by driving the stages as described with reference to Figures 7 and 8, each of the multiple output units OUT1 to OUT4 included in the multiple stages STG1 to STG4 can sequentially output multiple gate signals GATE1 to GATE4 having gate-on level pulses, for example, low-level L pulses, based on the carry signals CR1 to CR4 provided from the carry units CRY1 to CRY4 of the corresponding stage and the control clock signal.

[0216] Next, to explain the second mode, referring to Figures 6, 7, and 9b, the multiple carry units CRY1 to CRY4 included in the multiple stages STG1 to STG4 can sequentially output multiple carry signals CR1 to CR4, using the start signal VST, the first clock signal CLK1, and the second clock signal CLK2, substantially the same as described with reference to Figure 9a.

[0217] In one embodiment, in the second mode, at least one of the first control clock signal CCLK1 and the second control clock signal CCLK2 may be maintained at a gate-off level, for example, a high level H, for at least a portion of the interval. For example, in the second mode, at least one of the first control clock signal CCLK1 and the second control clock signal CCLK2 may not perform a toggle operation for at least a portion of the interval. On the other hand, as an example relating to this, Figure 9b shows a case where the second control clock signal CCLK2 is maintained at a high level H for the period after the conversion point PP.

[0218] In this case, in the second mode, the first control clock signal CCLK1 is toggled throughout the entire interval, so the output sections of the stages to which the first control clock signal CCLK1 is applied, specifically the odd-numbered stages, for example, the first output section OUT1 of the first stage STG1 and the third output section OUT3 of the third stage STG3, can output a first gate signal GATE1 and a third gate signal GATE3, both having low-level L pulses.

[0219] On the other hand, in the second mode, the second control clock signal CCLK2 is maintained at a high level H after the transition point PP. Therefore, in the output section of the stage to which the second control clock signal CCLK2 is applied, gate signals output from even-numbered stages, for example, the second output section OUT2 of the second stage STG2 and the fourth output section OUT4 of the fourth stage STG4, which should output a low-level L pulse after the transition point PP, can be maintained at a gate-off level of high level H without outputting a low-level L pulse. For example, as shown in Figure 9b, the second gate signal GATE2 output before the transition point PP has a low-level L pulse, but the fourth gate signal GATE4 can be maintained at a high level H by the second control clock signal CCLK2, which is maintained at a high level H after the transition point PP.

[0220] As another example, as shown in Figure 9c, if both the first control clock signal CCLK1 and the second control clock signal CCLK2 are maintained at a high level H during the period after the transition point PP in the second mode, then among the multiple gate signals GATE1 to GATE4 output from the output sections OUT1 to OUT4 of each of the multiple stages STG1 to STG4, the gate signals that should output a low-level L pulse after the transition point PP may not output a low-level L pulse and may be maintained at a high-level H gate-off level. For example, as shown in Figure 9c, the first gate signal GATE1 and the second gate signal GATE2 output before the transition point PP have low-level L pulses, but the third gate signal GATE3 and the fourth gate signal GATE4 may be maintained at a high level H by the first control clock signal CCLK1 and the second control clock signal CCLK2, respectively, which are maintained at a high level H after the transition point PP.

[0221] On the other hand, Figures 9b and 9c exemplify the case in which the first control clock signal CCLK1 and / or the second control clock signal CCLKK2 are maintained at a high level H during the period after the transition point PP in the second mode, but the embodiments of this specification are not limited thereto.

[0222] For example, in the second mode, the first control clock signal CCLK1 and / or the second control clock signal CCLKK2 may be maintained at a high level H during the period prior to the transition point PP, and the first control clock signal CCLK1 and the second control clock signal CCLK2 may toggle between a high level H and a low level L during the period after the transition point PP.

[0223] As another example, in the second mode, during the period prior to the transition point PP, either the first control clock signal CCLK1 or the second control clock signal CCLKK2 may be maintained at a high level H, and during the period after the transition point PP, the other of the first control clock signal CCLK1 and the second control clock signal CCLKK2 may be maintained at a high level H.

[0224] Another example is that the first control clock signal CCLK1 and / or the second control clock signal CCLKK2 may be maintained at a high level (H) for the entire duration of operation in the second mode.

[0225] Figure 10 is a block diagram showing another example of the gate drive unit shown in Figure 5.

[0226] Figures 11a to 11c are waveform diagrams illustrating an example of the drive operation of the gate drive unit in Figure 10.

[0227] The gate drive unit 1020 shown in Figure 10 represents a modified embodiment of the gate drive unit 620 described with reference to Figure 6 in relation to the multiple control clock signals CCLK1, CCLK2, CCLK3, CCLK4 and their coupling relationships. For the sake of clarity, redundant explanations will not be repeated.

[0228] On the other hand, for the sake of explanation, Figure 10 shows the eight stages STG1 to STG8 included in the gate drive unit 1020 and the multiple gate signals GATE1 to GATE8 output from them.

[0229] Referring to Figure 10, the gate drive unit 1020 can include multiple stages STG1 to STG8. Each of the multiple stages STG1 to STG8 is connected to the corresponding gate wiring GL1 to GL8 and can output gate signals GATE1 to GATE8.

[0230] Each of the multiple stages STG1 to STG8 can include carry sections CRY1 to CRY8 for outputting carry signals and output sections OUT1 to OUT8 for controlling whether or not gate signals are output.

[0231] Each of the multiple carry sections CRY1 to CRY8 contained within the multiple stages STG1 to STG8 can output carry signals CR1 to CR8 based on an input signal, such as a start signal VST or a carry signal provided from the carry section of a previous stage, and multiple clock signals CLK1 and CLK2.

[0232] Each of the multiple output units OUT1 to OUT8 may be provided with one of several control clock signals, for example, a first control clock signal CCLK1, a second control clock signal CCLK2, a third control clock signal CCLK3, and a fourth control clock signal CCLK4.

[0233] In one embodiment, the output units included in the k-th stage (where k is an integer greater than 0) and the k+2 stage can receive the first control clock signal CCLK1, the output units included in the k+1-th stage and the k+3-th stage can receive the second control clock signal CCLK2, the output units included in the k+4-th stage and the k+6-th stage can receive the third control clock signal CCLK3, and the output units included in the k+5-th stage and the k+7-th stage can receive the fourth control clock signal CCLK4.

[0234] For example, the first output unit OUT1 and the third output unit OUT3 can each receive the first control clock signal CCLK1, the second output unit OUT2 and the fourth output unit OUT4 can each receive the second control clock signal CCLK2, the fifth output unit OUT5 and the seventh output unit OUT7 can each receive the third control clock signal CCLK3, and the sixth output unit OUT6 and the eighth output unit OUT8 can each receive the fourth control clock signal CCLK4.

[0235] The first control clock signal CCLK1 and the second control clock signal CCLK2 may have waveforms with the same period and no phase superimposition. For example, the second control clock signal CCLK2 may be set to a signal shifted by approximately 1 / 2 period from the first control clock signal CCLK1.

[0236] Furthermore, the third control clock signal CCLK3 and the fourth control clock signal CCLK4 may have the same period and waveforms whose phases do not overlap with each other. For example, the fourth control clock signal CCLK4 may be set to a signal that is shifted by approximately 1 / 2 period from the third control clock signal CCLK3.

[0237] In one embodiment, as described above, except when the gate drive unit 1020 is driven in the second mode and one of the control clock signals CCLK1, CCLK2, CCLK3, and CCLK4 is maintained at a high level H, the first control clock signal CCLK1 and the third control clock signal CCLK3 may have the same waveform, and the second control clock signal CCLK2 and the fourth control clock signal CCLK4 may have the same waveform.

[0238] In one embodiment, the signal level of at least one of the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 can be controlled by the drive mode. For example, the signal levels of the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 can be controlled independently. As an example, as described above, in order to drive the pixel PX during the second display period DP2, at least one of the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 is maintained at a gate-off level, for example, a high level H, during that period, so that the output unit to which the control clock signal is applied can provide a gate signal at a gate-off level, for example, a high level H.

[0239] For example, referring further to Figure 11a, in the first mode, the start signal VST, the first clock signal CLK1, and the second clock signal CLK2 allow the multiple carry units CRY1 to CRY8 contained in the multiple stages STG1 to STG8 to sequentially output the multiple carry signals CR1 to CR8.

[0240] In one embodiment, in the first mode, the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 can each toggle between a high level H and a low level L. For example, in the first mode, the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 can each transition from a high level H to a low level L or from a low level L to a high level H every 1 / 2 period.

[0241] As a result, each of the multiple output units OUT1 to OUT8 included in the multiple stages STG1 to STG8 can sequentially output multiple gate signals GATE1 to GATE8 having gate-on level pulses, for example, low-level L pulses, based on the carry signals CR1 to CR8 provided from the carry units CRY1 to CRY8 of the corresponding stage and the control clock signal.

[0242] Next, to explain the second mode, referring to Figure 11b, the multiple carry units CRY1 to CRY8 contained in the multiple stages STG1 to STG8 can sequentially output multiple carry signals CR1 to CR8, using the start signal VST, the first clock signal CLK1, and the second clock signal CLK2, which are substantially the same as those explained with reference to Figure 11a.

[0243] In one embodiment, in the second mode, at least one of the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 may be maintained at a gate-off level, for example, a high level H, for at least a portion of the interval. For example, in the second mode, at least one of the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 may not perform the toggle operation for at least a portion of the interval. On the other hand, as an example relating to this, Figure 11b shows a case where the third control clock signal CCLK3 and the fourth control clock signal CCLK4 are maintained at a high level H for the period after the conversion point PP.

[0244] In this case, in the second mode, the first control clock signal CCLK1 and the second control clock signal CCLK2 are toggled throughout the entire interval, so the output sections of the stages to which the first control clock signal CCLK1 and the second control clock signal CCLK2 are applied, specifically the first to fourth output sections OUT1 to OUT4 of the k to k+3 stages, for example, the first to fourth stages STG1 to STG4, can output first to fourth gate signals GATE1 to GATE4 having low-level L pulses.

[0245] On the other hand, in the second mode, the third control clock signal CCLK3 and the fourth control clock signal CCLK4 are maintained at a high level H after the transition point PP. Therefore, the gate signals output from the 5th to 8th output sections OUT5 to OUT8 of the k+4th to k+7th stages, for example, the 5th to 8th stages STG5 to STG8, can be maintained at a gate-off level, which is a high level H, without outputting a low-level L pulse after the transition point PP.

[0246] As another example, as shown in Figure 11c, in the second mode, if the second control clock signal CCLK2 and the fourth control clock signal CCLK4 are maintained at a high level H for the period after the transition point PP, the gate signal output from the output section of the stage to which the second control clock signal CCLK2 and the fourth control clock signal CCLK4 are applied may be maintained at a gate-off level, which is a high level H, without outputting a low-level L pulse after the transition point PP.

[0247] Figure 12 is a block diagram showing yet another example of the gate drive unit in Figure 5.

[0248] Figures 13a to 13c are waveform diagrams illustrating an example of the drive operation of the gate drive unit in Figure 12.

[0249] The gate drive unit 1220 shown in Figure 12 represents a modified embodiment of the gate drive unit 620 described with reference to Figure 6 in relation to the multiple control clock signals CCLK1 to CCLK8 and their coupling relationships. For the sake of clarity, redundant explanations will not be repeated.

[0250] On the other hand, for the sake of explanation, Figure 12 shows the 16 stages STG1 to STG16 included in the gate drive unit 1220 and the multiple gate signals GATE1 to GATE16 output from them.

[0251] Referring to Figure 12, the gate drive unit 1220 can include multiple stages STG1 to STG16. Each of the multiple stages STG1 to STG16 is connected to the corresponding gate wiring GL1 to GL16 and can output gate signals GATE1 to GATE16.

[0252] Each of the multiple stages STG1 to STG16 can include a carry section CRY1 to CRY16 for outputting a carry signal, and an output section OUT1 to OUT16 for controlling whether or not a gate signal is output.

[0253] Each of the multiple carry sections CRY1 to CRY16 contained within the multiple stages STG1 to STG16 can output carry signals CR1 to CR16 based on an input signal, such as a start signal VST or a carry signal provided from the carry section of a previous stage, and multiple clock signals CLK1 and CLK2.

[0254] Each of the multiple output units OUT1 to OUT16 may be provided with one of multiple control clock signals, for example, one of the first to eighth control clock signals CCLK1 to CCLK8.

[0255] In one embodiment, the output units included in the k-th stage (where k is an integer greater than 0) and the k+2 stage receive the first control clock signal CCLK1, the output units included in the k+1-th stage and the k+3-th stage receive the second control clock signal CCLK2, the output units included in the k+4-th stage and the k+6-th stage receive the third control clock signal CCLK3, the output units included in the k+5-th stage and the k+7-th stage receive the fourth control clock signal CCLK4, the output units included in the k+8-th stage and the k+10-th stage receive the fifth control clock signal CCLK5, the output units included in the k+9-th stage and the k+11-th stage receive the sixth control clock signal CCLK6, the output units included in the k+12-th stage and the k+14-th stage receive the seventh control clock signal CCLK7, and the output units included in the k+13-th stage and the k+15-th stage receive the eighth control clock signal CCLK8.

[0256] For example, the first output unit OUT1 and the third output unit OUT3 can each receive the first control clock signal CCLK1, the second output unit OUT2 and the fourth output unit OUT4 can each receive the second control clock signal CCLK2, the fifth output unit OUT5 and the seventh output unit OUT7 can each receive the third control clock signal CCLK3, the sixth output unit OUT6 and the eighth output unit OUT8 can each receive the fourth control clock signal CCLK4, the ninth output unit OUT9 and the eleventh output unit OUT11 can each receive the fifth control clock signal CCLK5, the tenth output unit OUT10 and the twelfth output unit OUT12 can each receive the sixth control clock signal CCLK6, the thirteenth output unit OUT13 and the fifteenth output unit OUT15 can each receive the seventh control clock signal CCLK7, and the fourteenth output unit OUT14 and the sixteenth output unit OUT16 can each receive the eighth control clock signal CCLK8.

[0257] The first control clock signal CCLK1 and the second control clock signal CCLK2 may have waveforms with the same period and no phase superimposition. For example, the second control clock signal CCLK2 may be set to a signal shifted by approximately 1 / 2 period from the first control clock signal CCLK1.

[0258] Furthermore, the third control clock signal CCLK3 and the fourth control clock signal CCLK4 may have the same period and waveforms whose phases do not overlap with each other. For example, the fourth control clock signal CCLK4 may be set to a signal that is shifted by approximately 1 / 2 period from the third control clock signal CCLK3.

[0259] Furthermore, the fifth control clock signal CCLK5 and the sixth control clock signal CCLK6 may have the same period and waveforms whose phases do not overlap with each other. For example, the sixth control clock signal CCLK6 may be set to a signal that is shifted by approximately 1 / 2 period from the fifth control clock signal CCLK5.

[0260] Furthermore, the seventh control clock signal CCLK7 and the eighth control clock signal CCLK8 may have the same period and waveforms whose phases do not overlap with each other. For example, the eighth control clock signal CCLK8 may be set to a signal that is shifted by approximately half a period from the seventh control clock signal CCLK7.

[0261] In one embodiment, as described above, except when the gate drive unit 1220 is driven in the second mode and one of the first to eighth control clock signals CCLK1 to CCLK8 is maintained at a high level H, the first control clock signal CCLK1, the third control clock signal CCLK3, the fifth control clock signal CCLK5, and the seventh control clock signal CCLK7 have the same waveform, and the second control clock signal CCLK2, the fourth control clock signal CCLK4, the sixth control clock signal CCLK6, and the eighth control clock signal CCLK8 may have the same waveform.

[0262] In one embodiment, the signal level of at least one of the first to eighth control clock signals CCLK1 to CCLK8 can be controlled by the drive mode. For example, the signal levels of the first to eighth control clock signals CCLK1 to CCLK8 can be controlled independently. As an example, as described above, in order to drive the pixel PX during the second display period DP2, at least one of the first to eighth control clock signals CCLK1 to CCLK8 is maintained at a gate-off level, for example, a high level H, during that period, so that the output unit to which the control clock signal is applied can provide a gate signal at a gate-off level, for example, a high level H.

[0263] For example, referring further to Figure 13a, in the first mode, the start signal VST, the first clock signal CLK1, and the second clock signal CLK2 allow the multiple carry units CRY1 to CRY16 contained in the multiple stages STG1 to STG16 to sequentially output multiple carry signals CR1 to CR16.

[0264] In one embodiment, in the first mode, each of the first to eighth control clock signals CCLK1 to CCLK8 can toggle between a high level H and a low level L. For example, in the first mode, each of the first to eighth control clock signals CCLK1 to CCLK8 can transition from a high level H to a low level L or from a low level L to a high level H every half period.

[0265] As a result, each of the multiple output units OUT1 to OUT16 included in the multiple stages STG1 to STG16 can sequentially output multiple gate signals GATE1 to GATE16 having gate-on level pulses, for example, low-level L pulses, based on the carry signals CR1 to CR16 provided from the carry units CRY1 to CRY16 of the corresponding stage and the control clock signal.

[0266] Next, to explain the second mode, referring to Figure 13b, the multiple carry units CRY1 to CRY16 contained in the multiple stages STG1 to STG16 can sequentially output multiple carry signals CR1 to CR16, using the start signal VST, the first clock signal CLK1, and the second clock signal CLK2, which are substantially the same as those explained with reference to Figure 13a.

[0267] In one embodiment, in the second mode, at least one of the first to eighth control clock signals CCLK1 to CCLK8 may be maintained at a gate-off level, for example, a high level H, for at least a portion of the interval. For example, in the second mode, at least one of the first to eighth control clock signals CCLK1 to CCLK8 may not perform a toggle operation for at least a portion of the interval. On the other hand, as an example relating to this, Figure 13b shows a case where the fifth to eighth control clock signals CCLK5 to CCLK8 are maintained at a high level H for the period after the conversion point PP.

[0268] In this case, in the second mode, the first to fourth control clock signals CCLK1 to CCLK4 are toggled throughout the entire interval, so the output sections of the stages to which the first to fourth control clock signals CCLK1 to CCLK4 are applied, specifically the first to eighth output sections OUT1 to OUT8 of the k to k+7th stages, for example, the first to eighth stages STG1 to STG8, can output the first to eighth gate signals GATE1 to GATE8 having low-level L pulses.

[0269] On the other hand, in the second mode, the 5th to 8th control clock signals CCLK5 to CCLK8 are maintained at a high level H after the transition point PP. Therefore, the gate signals output from the 9th to 16th output sections OUT9 to OUT16 of the k+8th to k+15th stages, for example, the 9th to 16th stages STG9 to STG16, can be maintained at a high level H gate-off level after the transition point PP, without outputting any low-level L pulses.

[0270] As another example, as shown in Figure 13c, in the second mode, if the third to eighth control clock signals CCLK3 to CCLK8 are maintained at a high level H for the period after the transition point PP, the gate signal output from the output section of the stage to which the third to eighth control clock signals CCLK3 to CCLK8 are applied may be maintained at a gate-off level, which is a high level H, without outputting a low-level L pulse after the transition point PP.

[0271] Figure 14 is a block diagram showing an example of the arrangement of the light-emitting drive unit, multiple scan drive units, and multiple signal wiring included in the gate drive unit of Figure 5.

[0272] Referring to Figure 14, the gate drive unit 1420 according to one embodiment of this specification may include a first scan drive unit SDV1, a second scan drive unit SDV2, a third scan drive unit SDV3, a fourth scan drive unit SDV4, and a light emission drive unit EDV.

[0273] On the other hand, as explained with reference to Figure 5, the output frequencies of the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4 can be controlled in order to independently drive the drive frequencies of multiple sub-display areas included in display area AA. For this purpose, the scan drive unit can be embodied in any one of the gate drive unit 620 explained with reference to Figure 6, the gate drive unit 1020 explained with reference to Figure 10, and the gate drive unit 1220 explained with reference to Figure 12.

[0274] Here, each pulse width of the control clock signal provided to the output section of each stage has a horizontal period of 1H. In the case of the gate drive unit 620 in Figure 6, as mentioned above, there are two control clock signals applied to the multiple output sections OUT1 to OUT4. Therefore, the gate signal output from the gate drive unit 620 in Figure 6 can have a pulse width of a maximum of two horizontal periods of 2H. As a result, among the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4, only the scan drive unit whose scan signal pulse width is set to two horizontal periods of 2H or less can be realized in the gate drive unit 620 in Figure 6. For example, when the second scan signal SCAN2 is set to two horizontal periods of 2H or less at pixel PX for writing the data signal Vdata, the second scan drive unit SDV2 is realized in the gate drive unit 620 in Figure 6 and can output the second scan signal SCAN2 based on two control clock signals (shown as SC2_CCLK1 and SC2_CCLK2 in Figure 14).

[0275] On the other hand, in the case of the gate drive unit 1020 in Figure 10 or the gate drive unit 1220 in Figure 12, as mentioned above, the number of control clock signals applied to the multiple output units is 4 or 8. Therefore, through the pulse width of the start signal VST and the deformation of the control clock signal waveform, the gate signals output from the gate drive unit 1020 in Figure 10 and the gate drive unit 1220 in Figure 12 may also have pulse widths of 2 horizontal periods of 2H or more. As a result, the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4 can be implemented in the gate drive unit 1020 in Figure 10 or the gate drive unit 1220 in Figure 12, regardless of the pulse width of the scan signal. For example, as shown in Figure 14, the first scan drive unit SDV1 is implemented in the gate drive unit 1220 of Figure 12 and outputs a first scan signal SCAN1 based on eight control clock signals (shown as SC1_CCLK1 to SC1_CCLK8 in Figure 14), and the fourth scan drive unit SDV4 is implemented in the gate drive unit 1220 of Figure 12 and outputs a fourth scan signal SCAN4 based on eight control clock signals (shown as SC4_CCLK1 to SC4_CCLK8 in Figure 14).

[0276] FIG. 15 is a block diagram showing another example of the arrangement relationship of the light emission driving unit, a plurality of scan driving units, and a plurality of signal wirings included in the gate driving unit of FIG. 5.

[0277] FIG. 16 is a waveform diagram for explaining another example of driving of the pixel of FIG. 3.

[0278] FIG. 17 is a waveform diagram for explaining an example of driving of the first scan driving unit and the fourth scan driving unit of FIG. 15.

[0279] On the other hand, the gate driving unit 1520 shown in FIG. 15 shows a modified embodiment of the gate driving unit 1420 described with reference to FIG. 14 in relation to a plurality of control clock signals and their connection relationships.

[0280] Also, in the first display period DP1_1 shown in FIG. 16, the waveform diagram shows a modified embodiment of the waveform diagram in the first display period DP1 described with reference to FIG. 4a in relation to the first scan signal SCAN1 and the fourth scan signal SCAN4. For the sake of convenience of explanation, repeated explanations will not be repeated.

[0281] Referring to FIG. 15, the gate driving unit 1520 according to an embodiment of the present specification may include a first scan driving unit SDV1, a second scan driving unit SDV2, a third scan driving unit SDV3, a fourth scan driving unit SDV4, and a light emission driving unit EDV. Here, as described above, in order to independently drive the driving frequencies of a plurality of sub-display areas included in the display area AA, the output frequencies of the first scan driving unit SDV1, the second scan driving unit SDV2, and the fourth scan driving unit SDV4 can be controlled. For example, as described with reference to FIG. 14, the second scan driving unit SDV2 is embodied in the gate driving unit 620 of FIG. 6, and the first scan driving unit SDV1 and the fourth scan driving unit SDV4 may be embodied in the gate driving unit 1220 of FIG. 12, respectively.

[0282] On the other hand, if multiple control clock signals are formed separately for each of the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4, whose output frequencies are controlled, a problem may arise where the number of signal wirings for providing the control clock signals, such as control clock signal wirings, increases, and the bezel area of ​​the display device 100 increases.

[0283] As a result, in one embodiment, the first scan drive unit SDV1 and the fourth scan drive unit SDV4 can share multiple control clock signals (SC14_CCLK1 to SC14_CCLK8 in Figure 15).

[0284] To this end, referring further to Figure 16, the first scan signal SCAN1 and the fourth scan signal SCAN4 output from the first scan drive unit SDV1 may have the same pulse width and be supplied at different timings. For example, the first scan signal SCAN1 and the fourth scan signal SCAN4 may each have one high-level H pulse, and the first scan signal SCAN1 may have a waveform shifted by 4 horizontal periods (4H) from the fourth scan signal SCAN4. For example, since the first scan drive unit SDV1 and the fourth scan drive unit SDV4 share multiple control clock signals SC14_CCLK1 to SC14_CCLK8, the first scan signal SCAN1 and the fourth scan signal SCAN4 may have the same magnitude and number of pulse widths, and the pulse widths of the first scan signal SCAN1 and the fourth scan signal SCAN4 may be designed to differ by a multiple of 4 horizontal periods (4H) so as to be synchronized with the timing at which the signal levels of the control clock signals transition.

[0285] On the other hand, unlike the embodiment described with reference to Figure 4a, in the embodiment of Figure 16, the first scan signal SCAN1 has a gate-off level, for example, a low level L, during the first drive period S1 and the second drive period S2. As a result, the second switching transistor M2 of the pixel PX is kept in a turned-off state during the first drive period S1 and the second drive period S2. However, the third scan signal SCAN3 supplied during the second drive period S2 turns on the fourth switching transistor M4 and the seventh switching transistor M7, providing a second initialization voltage VAR to the first electrode of the light-emitting element ED and a bias voltage Vobs to the source electrode of the drive transistor DT, thereby enabling normal initialization and bias operations.

[0286] Next, referring further to Figure 17 to explain the driving of the gate drive unit 1520 in the second mode, the start signal VST, the first clock signal CLK1, and the second clock signal CLK2 cause the carry units of each of the multiple first scan stages SST11 to SST1n included in the first scan drive unit SDV1 to sequentially output multiple carry signals (shown as SC1_CR1 to SC1_CR4 in Figure 17), and the carry units of each of the multiple fourth scan stages SST41 to SST4n included in the fourth scan drive unit SDV4 to sequentially output multiple carry signals SC4_CR1 to SC4_CR4.

[0287] In one embodiment, in the second mode, at least one of the multiple control clock signals SC14_CCLK1 to SC14_CCLK8 shared by the first scan drive unit SDV1 and the fourth scan drive unit SDV4 may be maintained at a gate-off level, for example, a high level H, for at least a portion of the interval. As an example of this, Figure 17 shows the case where the third to eighth control clock signals SC14_CCLK3 to SC14_CCLK8 are maintained at a high level H for the period after the transition point PP. In this case, in the second mode, the first scan signal SCAN1 and the fourth scan signal SCAN4 after the transition point PP, i.e., the first scan signals (e.g., SCAN13, SCAN14) and the fourth scan signals (e.g., SCAN43, SCAN44) output to the third and fourth pixel rows, may be output at a high level H, which is the gate-off level.

[0288] As described above, in the case of a gate drive unit and a display device including the same according to one embodiment of this specification, each stage of the gate drive unit may include a carry unit for generating a carry signal and an output unit for controlling the output of the gate signal.

[0289] As a result, the gate drive unit and the display device including it according to one embodiment of this specification are not limited to a fixed area, but can freely divide the display area in accordance with the displayed image and control the drive frequency for each area.

[0290] Furthermore, since the drive frequency is controlled in accordance with the display area, power consumption may be improved.

[0291] The gate drive unit according to the embodiments of this specification can be described as follows.

[0292] A gate drive unit according to one embodiment of this specification may include a plurality of stages that are coupled together and output a plurality of gate signals based on an input signal, a plurality of clock signals, a plurality of control clock signals, a first power supply, and a second power supply having a lower voltage level than the first power supply. Each of the plurality of stages includes a carry unit that outputs a carry signal based on an input signal, at least one of the plurality of clock signals, a first power supply, and a second power supply, and a carry unit that outputs a gate signal based on the carry signal, at least one of the plurality of control clock signals, a first power supply, and a second power supply, and the output of the gate signal of the output unit may be controlled based on at least one control clock signal.

[0293] According to other features of this specification, each of the multiple control clock signals may have a waveform that toggles between gate-on and gate-off levels or is maintained at the gate-off level.

[0294] According to another feature of this specification, the output unit may output a gate signal having a gate-on pulse during a interval in which at least one control clock signal toggles between a gate-on level and a gate-off level, and the output unit may output a gate signal that is maintained at a gate-off level during a interval in which at least one control clock signal has a gate-off level.

[0295] According to other features of this specification, the plurality of control clock signals include a first control clock signal and a second control clock signal whose signal levels are independently controlled and whose phases do not overlap, and the output section included in each of the odd-numbered stages of the plurality of stages can receive the first control clock signal, and the output section included in each of the even-numbered stages of the plurality of stages can receive the second control clock signal.

[0296] According to other features of this specification, the plurality of control clock signals may include a first control clock signal and a second control clock signal whose signal levels are independently controlled and whose phases do not overlap, and a third control clock signal and a fourth control clock signal whose signal levels are independently controlled and whose phases do not overlap.

[0297] According to other features of this specification, the output units included in the k-th (where k is an integer greater than 0) stage and the k+2 stage of the multiple stages can receive a first control clock signal, the output units included in the k+1-th and k+3-th stages of the multiple stages can receive a second control clock signal, the output units included in the k+4-th and k+6-th stages of the multiple stages can receive a third control clock signal, and the output units included in the k+5-th and k+7-th stages of the multiple stages can receive a fourth control clock signal.

[0298] According to other features of this specification, the first control clock signal and the third control clock signal may have the same waveform in at least some sections, and the second control clock signal and the fourth control clock signal may have the same waveform in at least some sections.

[0299] According to other features of this specification, the plurality of control clock signals may further include a fifth and sixth control clock signal whose signal levels are independently controlled and whose phases do not overlap with each other, and a seventh and eighth control clock signal whose signal levels are independently controlled and whose phases do not overlap with each other.

[0300] According to another feature of the present specification, the output parts included in the (k + 8)-th stage and the (k + 10)-th stage among the plurality of stages receive the fifth control clock signal, and the output parts included in the (k + 9)-th stage and the (k + 11)-th stage among the plurality of stages receive the sixth control clock signal, and the output parts included in the (k + 12)-th stage and the (k + 14)-th stage among the plurality of stages receive the seventh control clock signal, and the output parts included in the (k + 13)-th stage and the (k + 15)-th stage among the plurality of stages can receive the eighth control clock signal.

[0301] According to another feature of the present specification, in at least a part of intervals, the first control clock signal, the third control clock signal, the fifth control clock signal, and the seventh control clock signal may have the same waveform, and in at least a part of intervals, the second control clock signal, the fourth control clock signal, the sixth control clock signal, and the eighth control clock signal may have the same waveform.

[0302] According to other features of this specification, the carry section may include a first transistor having a gate electrode connected between a first input terminal to which an input signal is provided and a first control node, and connected to a second input terminal to which at least one clock signal is provided; a second transistor having a gate electrode connected between a second control node and a first power input terminal to which the voltage of a first power supply is supplied, and connected to the first input terminal; a third transistor having a gate electrode connected between a second input terminal and a first QB node, and connected to the second control node; a fourth transistor having a gate electrode connected between a first power input terminal and a first QB node, and connected to the first control node; a fifth transistor having a gate electrode connected between a second power input terminal to which the voltage of a second power supply is supplied and a first output terminal to which a carry signal is output, and connected to a first Q node; a sixth transistor having a gate electrode connected between a first power input terminal and a first output terminal, and connected to a first QB node; a first bridge voltage transistor having a gate electrode connected between a first control node and a first Q node, and connected to a second power input terminal; and a first capacitor connected between a second input terminal and a second control node.

[0303] According to other features of this specification, the carrier section may further include a second capacitor connected between the first Q node and the first output terminal, and a third capacitor connected between the first QB node and the first power input terminal.

[0304] According to other features of this specification, the output section may include a seventh transistor with a gate electrode connected between a third input terminal to which a carry signal is provided and a third control node, and connected to a fourth input terminal to which at least one control clock signal is provided; an eighth transistor with a gate electrode connected between a fourth control node and a first power input terminal to which the voltage of a first power supply is supplied, and connected to a third input terminal; a ninth transistor with a gate electrode connected between a fourth input terminal and a second QB node, and connected to a fourth control node; a tenth transistor with a gate electrode connected between a first power input terminal and a second QB node, and connected to a third control node; an eleventh transistor with a gate electrode connected between a second power input terminal to which the voltage of a second power supply is supplied and a second output terminal to which a gate signal is output, and connected to a second Q node; a twelfth transistor with a gate electrode connected between a first power input terminal and a second output terminal, and connected to a second QB node; a second bridge voltage transistor with a gate electrode connected between a third control node and a second Q node, and connected to a second power input terminal; and a fourth capacitor connected between a fourth input terminal and a fourth control node.

[0305] According to other features of this specification, the output section may further include a fifth capacitor connected between the second Q node and the second output terminal, and a sixth capacitor connected between the second QB node and the first power input terminal.

[0306] The display devices according to the embodiments of this specification can be described as follows.

[0307] An embodiment of the Specified Display Device includes a display panel containing a plurality of pixels, and a first scan drive unit, a second scan drive unit, a third scan drive unit, and a fourth scan drive unit that output a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to the plurality of pixels, respectively, based on an input signal, a plurality of clock signals, a plurality of control clock signals, a first power supply, and a second power supply having a lower voltage level than the first power supply. In a first display period, each of the first scan signal, second scan signal, third scan signal, and fourth scan signal has a gate-on level pulse, and in a second display period different from the first display period, the third scan signal has a gate-on level pulse, and the first scan signal, second scan signal, and fourth scan signal are maintained at a gate-off level. At least a portion of the first scan drive unit, second scan drive unit, and fourth scan drive unit can control the signal level of the scan signal based on the same control clock signal from among a plurality of control clock signals.

[0308] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to these embodiments and can be modified and implemented in various ways within the scope of the technical concept of this specification. Accordingly, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

Claims

1. It includes multiple stages that are coupled together and output multiple gate signals based on an input signal, multiple clock signals, multiple control clock signals, a first power supply, and a second power supply having a lower voltage level than the first power supply, Each of the aforementioned multiple stages is A carry unit that outputs a carry signal based on the input signal, at least one clock signal from the plurality of clock signals, the first power supply and the second power supply, and An output unit that outputs a gate signal based on the carry signal, at least one control clock signal from the plurality of control clock signals, the first power supply, and the second power supply. Includes, Based on the at least one control clock signal, the output of the gate signal in the output unit is controlled. Gate drive unit.

2. The gate drive unit according to claim 1, wherein each of the plurality of control clock signals has a waveform that toggles between a gate-on level and a gate-off level or is maintained at a gate-off level.

3. During the interval in which the at least one control clock signal toggles between a gate-on level and a gate-off level, the output unit outputs the gate signal having a gate-on level pulse. In the interval where the at least one control clock signal has a gate-off level, the output unit outputs the gate signal which is maintained at the gate-off level. The gate drive unit according to claim 2.

4. The aforementioned plurality of control clock signals are It includes a first control clock signal and a second control clock signal whose signal levels are independently controlled and whose phases do not overlap with each other. The output unit included in each of the odd-numbered stages among the plurality of stages receives the first control clock signal. The output unit included in each of the even-numbered stages among the plurality of stages receives the second control clock signal. The gate drive unit according to claim 1.

5. The aforementioned plurality of control clock signals are A first control clock signal and a second control clock signal whose signal levels are independently controlled and whose phases do not overlap, and The system includes a third control clock signal and a fourth control clock signal whose signal levels are independently controlled and whose phases do not overlap with each other. The gate drive unit according to claim 1.

6. The output units included in the k-th stage (where k is an integer greater than 0) and the k+2 stage among the plurality of stages receive the first control clock signal. The output units included in the k+1th stage and the k+3rd stage, respectively, receive the second control clock signal. The output units included in the k+4th stage and the k+6th stage, respectively, receive the third control clock signal. The output units included in the k+5th stage and the k+7th stage, respectively, receive the fourth control clock signal. The gate drive unit according to claim 5.

7. In at least a portion of the section, the first control clock signal and the third control clock signal have the same waveform, In at least a portion of the section, the second control clock signal and the fourth control clock signal have the same waveform. The gate drive unit according to claim 5.

8. The aforementioned plurality of control clock signals are A fifth control clock signal and a sixth control clock signal whose signal levels are independently controlled and whose phases do not overlap with each other, and The system further includes a seventh control clock signal and an eighth control clock signal whose signal levels are independently controlled and whose phases do not overlap with each other. The gate drive unit according to claim 6.

9. The output units included in the k+8th stage and the k+10th stage, respectively, receive the fifth control clock signal. The output units included in the k+9th stage and the k+11th stage, respectively, receive the sixth control clock signal. The output units included in the k+12th stage and the k+14th stage, respectively, receive the seventh control clock signal. The output units included in the k+13th stage and the k+15th stage, respectively, receive the eighth control clock signal. The gate drive unit according to claim 8.

10. In at least a portion of the section, the first control clock signal, the third control clock signal, the fifth control clock signal, and the seventh control clock signal have the same waveform. In at least a portion of the section, the second control clock signal, the fourth control clock signal, the sixth control clock signal, and the eighth control clock signal have the same waveform. The gate drive unit according to claim 8.

11. The aforementioned carrying section is, A first transistor including a gate electrode connected between a first input terminal to which the input signal is provided and a first control node, and connected to a second input terminal to which at least one clock signal is provided, A second transistor, including a gate electrode connected to the first input terminal, is connected between the second control node and the first power input terminal to which the voltage of the first power supply is supplied. A third transistor, including a gate electrode connected between the second input terminal and the first QB node and connected to the second control node, A fourth transistor, including a gate electrode connected between the first power input terminal and the first QB node and connected to the first control node, A fifth transistor, including a gate electrode connected to the first Q node, is connected between the second power supply input terminal to which the voltage of the second power supply is supplied and the first output terminal to which the carry signal is output. A sixth transistor, including a gate electrode connected between the first power input terminal and the first output terminal and connected to the first QB node, A first bridge voltage transistor, which includes a gate electrode connected between the first control node and the first Q node and connected to the second power input terminal, and The first capacitor connected between the second input terminal and the second control node. The gate drive unit according to claim 1, including the gate drive unit according to claim 1.

12. The aforementioned carrying section is, A second capacitor connected between the first Q node and the first output terminal, and A third capacitor connected between the first QB node and the first power input terminal. The gate drive unit according to claim 11, further comprising:

13. The output unit is, A seventh transistor, including a gate electrode connected between the third input terminal to which the carry signal is provided and the third control node, and connected to the fourth input terminal to which the at least one control clock signal is provided, An eighth transistor, including a gate electrode connected to the third input terminal, is connected between the fourth control node and the first power input terminal to which the voltage of the first power supply is supplied. A ninth transistor, including a gate electrode connected between the fourth input terminal and the second QB node and connected to the fourth control node, A tenth transistor, including a gate electrode connected between the first power input terminal and the second QB node and connected to the third control node, An eleventh transistor, including a gate electrode connected to the second Q node, is connected between the second power supply input terminal to which the voltage of the second power supply is supplied and the second output terminal to which the gate signal is output. A twelfth transistor, including a gate electrode connected between the first power input terminal and the second output terminal and connected to the second QB node, A second bridge voltage transistor, which includes a gate electrode connected between the third control node and the second Q node and connected to the second power input terminal, and The fourth capacitor is connected between the fourth input terminal and the fourth control node. The gate drive unit according to claim 1, including the gate drive unit according to claim 1.

14. The output unit is, A fifth capacitor connected between the second Q node and the second output terminal, and The sixth capacitor is connected between the second QB node and the first power input terminal. The gate drive unit according to claim 13, further comprising:

15. The input signal to the carry section of the first of the aforementioned multiple stages is the first signal. The input signal to the carry section of the second stage among the aforementioned multiple stages is the carry signal output from the carry section of the first stage. The gate drive unit according to claim 11.

16. A display panel containing multiple pixels, and A first scan drive unit, a second scan drive unit, a third scan drive unit, and a fourth scan drive unit each output a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to the plurality of pixels based on an input signal, a plurality of clock signals, a plurality of control clock signals, a first power supply, and a second power supply having a lower voltage level than the first power supply. Includes, During the first display period, each of the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal has a gate-on level pulse. In a second display period different from the first display period, the third scan signal has a gate-on level pulse, and the first scan signal, the second scan signal, and the fourth scan signal are maintained at the gate-off level. At least a portion of the first scan drive unit, the second scan drive unit, and the fourth scan drive unit controls the signal level of the scan signal based on the same control clock signal among the plurality of control clock signals. Display device.

17. The display panel includes a display area and a non-display area. The aforementioned display area includes a plurality of sub-display areas that are divided according to the displayed image. The display device according to claim 16.

18. A display panel including a display area that is divided into multiple sub-display areas corresponding to the displayed image, and Gate drive unit including first scan drive unit and second scan drive unit Includes, The display panel is configured such that the drive frequencies of the plurality of sub-display areas are controlled based on the display area. The first scan drive unit and the second scan drive unit are, A carry unit that generates a carry signal, and Output section that controls whether or not to output a gate signal. Includes, The first scan drive unit is configured to use a first drive frequency for a first sub-display area among the plurality of sub-display areas, and to drive at least a first pixel within the first sub-display area based on at least a first control clock signal. The first control clock signal controls whether or not to output the first gate signal of the first scan drive unit to the first pixel at a predetermined period. The second scan drive unit is configured to use a second drive frequency for the second sub-display area among the plurality of sub-display areas, and to drive at least a second pixel within the second sub-display area based on at least a second control clock signal. The second control clock signal controls whether or not the second gate signal of the second scan drive unit is output to the second pixel at a predetermined period. Display device.

19. The display device is configured to determine the first drive frequency and the second drive frequency in correspondence with the displayed image, and to determine the first sub-display area and the second sub-display area based on the position driven by the first drive frequency and the second drive frequency. The display device further includes a timing control unit configured to determine a first control clock signal and a second control clock signal based on a first drive frequency and a second drive frequency, The first drive frequency differs from the second drive frequency, The first control clock signal is different from the second control clock signal. The display device according to claim 18.

20. The display device according to claim 18, wherein the display device is configured to dynamically select the first drive frequency and the second drive frequency in real time in response to the displayed image, and to dynamically divide the plurality of sub-display areas into a first sub-display area and a second sub-display area in real time in response to the displayed image, and to determine the position of the first sub-display area and the second sub-display area, respectively.

Images