Single event transient resistant voltage controlled oscillator circuit and phase locked loop circuit

Abstract

This invention relates to the field of circuit hardening technology, and provides a voltage-controlled oscillator (VCO) circuit and phase-locked loop (PLL) circuit that are resistant to single-event transients. Addressing the issue that traditional three-mode relaxation oscillator (VCO) circuits are unsuitable for low-voltage conditions, especially when the power supply voltage drops to around 0.8V, this invention employs six oscillation branches coupled into three large oscillation loop circuits to improve loop gain. Furthermore, by combining bias circuits, comparators, and voting circuits for each path, the problem of increasing nonlinearity is avoided. This achieves a combination of large oscillation loops, bias circuits, and a three-mode VCO architecture, resulting in a VCO circuit that maintains high-frequency stable operation under ultra-low voltage conditions such as 0.8V, thus achieving a single-event transient resistance effect, especially at low voltages of 0.8V.

Description

Technical Field

[0001] This invention belongs to the field of circuit hardening technology and relates to a voltage-controlled oscillator circuit and a phase-locked loop circuit that are resistant to single-event transients. Background Technology

[0002] The voltage-controlled oscillator (VCO) circuit is the core component of the phase-locked loop (PLL) circuit, and its resistance to single-event transients (SET) is a key indicator for evaluating the radiation resistance performance of the PLL. As the power supply voltage decreases, especially below 1V, traditional three-mode relaxation oscillator VCO circuits face problems of insufficient loop gain and increased nonlinearity. For example, a high-speed differential output VCO with a low soft error rate cannot adapt to low power supply voltages; its circuit architecture and auxiliary circuitry are completely inoperable below 1V. Therefore, designing a SET-resistant VCO circuit that adapts to low power supply voltages has become one of the technical problems to be solved. Summary of the Invention

[0003] To address the problems existing in the above-mentioned traditional methods, this invention proposes a voltage-controlled oscillator circuit and a phase-locked loop circuit that are resistant to single-event transients, and can adapt to the anti-SET effect under low power supply voltage.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a voltage-controlled oscillator circuit resistant to single-event transients is provided, including three identical oscillation ring modules, a first voting device, a second voting device, a first digital buffer, and a second digital buffer. Each oscillation ring module includes a bias circuit, an oscillation ring circuit, and two comparators. Each oscillation ring circuit is composed of two coupled ring oscillators. For each oscillating ring module: the input terminal of the bias circuit is used to receive the input voltage signal, the output terminal of the bias circuit is connected to the bias control terminal of the oscillating ring circuit, the non-inverting input terminal and the inverting input terminal of any comparator are respectively connected to the output terminals of the two ring oscillators in the oscillating ring circuit, the output terminal of one comparator is connected to one input terminal of the first voting device, and the output terminal of the other comparator is connected to one input terminal of the second voting device. The output of the first voting device is connected to the input of one ring oscillator in each oscillation ring circuit and to the input of the first digital buffer. The output of the second voting device is connected to the input of another ring oscillator in each oscillation ring circuit and to the input of the second digital buffer. The outputs of the first and second digital buffers are used to output clock signals.

[0005] In one embodiment, the bias circuit includes a PMOS transistor, a current mirror PMOS transistor, an NMOS transistor, and a resistor. The source of the PMOS transistor and the source of the current mirror PMOS transistor are connected to the power supply. The gate of the PMOS transistor and the gate of the current mirror PMOS transistor are connected and then connected to the drain of the PMOS transistor. The drain of the PMOS transistor is connected to the drain of the NMOS transistor. The source of the NMOS transistor is grounded through the resistor. The gate of the NMOS transistor is used to receive the input voltage signal. The drain of the current mirror PMOS transistor is connected to the bias control terminal of the oscillation ring circuit.

[0006] In one embodiment, the oscillating ring circuit includes a coupling unit and two ring oscillators. One ring oscillator includes a first voltage-controlled ring oscillator to a third voltage-controlled ring oscillator connected in series. The coupling unit includes a fourth voltage-controlled ring oscillator to a ninth voltage-controlled ring oscillator. The other ring oscillator includes a tenth voltage-controlled ring oscillator to a twelfth voltage-controlled ring oscillator connected in series. The input terminal of the first voltage-controlled ring oscillator is connected to the output terminal of the first voting device, and the input terminal of the twelfth voltage-controlled ring oscillator is connected to the output terminal of the second voting device. The output terminal of the fourth voltage-controlled ring resonator is connected to the input terminal of the fifth voltage-controlled ring resonator and the input terminal of the second voltage-controlled ring resonator. The input terminal of the fourth voltage-controlled ring resonator is connected to the output terminal of the fifth voltage-controlled ring resonator and the input terminal of the tenth voltage-controlled ring resonator. The output terminal of the sixth voltage-controlled ring resonator is connected to the input terminal of the seventh voltage-controlled ring resonator and the input terminal of the third voltage-controlled ring resonator. The input terminal of the sixth voltage-controlled ring resonator is connected to the output terminal of the seventh voltage-controlled ring resonator and the input terminal of the eleventh voltage-controlled ring resonator. The output terminal of the eighth voltage-controlled ring resonator is connected to the input terminal of the ninth voltage-controlled ring resonator and the output terminal of the third voltage-controlled ring resonator. The input terminal of the eighth voltage-controlled ring resonator is connected to the output terminal of the ninth voltage-controlled ring resonator and the output terminal of the eleventh voltage-controlled ring resonator. The non-inverting and inverting inputs of one comparator are connected to the outputs of the third and eleventh voltage-controlled ring resonator units, respectively. Similarly, the non-inverting and inverting inputs of another comparator are connected to the outputs of the eleventh and third voltage-controlled ring resonator units, respectively. The bias control terminals of all voltage-controlled ring resonator units are connected to the output of the bias circuit.

[0007] In one embodiment, the ring oscillator includes a series of three-stage voltage-controlled ring oscillator units, a series of five-stage voltage-controlled ring oscillator units, or a series of seven-stage voltage-controlled ring oscillator units.

[0008] In one embodiment, the voltage-controlled ring oscillator unit includes a PMOS transistor M01 and an NMOS transistor M02. The source of the PMOS transistor M01 is the bias control terminal, the gate of the PMOS transistor M01 is connected to the gate of the NMOS transistor M02 and serves as the input terminal, the drain of the PMOS transistor M01 is connected to the drain of the NMOS transistor M02 and serves as the output terminal, and the source of the NMOS transistor M02 is grounded.

[0009] On the other hand, a phase-locked loop circuit is also provided, wherein the voltage-controlled oscillator circuit in the phase-locked loop circuit adopts the above-mentioned voltage-controlled oscillator circuit that resists single-event transients.

[0010] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned voltage-controlled oscillator (VCO) and phase-locked loop (PLL) circuits designed to combat single-event transients (SETs) address the issue of traditional three-mode relaxation oscillator (VCO) circuits being unsuitable for low-voltage conditions, especially when the power supply voltage drops to around 0.8V. By coupling six oscillation branches into three large oscillation loops to improve loop gain, and combining bias circuits, comparators, and voting circuits for each path, the traditional differential ring oscillator is disassembled and connected to comparators separately. The differential clock is converted to a single-ended clock for voting, and the voting result is fed back to each oscillation loop circuit. This ensures the normal operation of the VCO and guarantees that when any oscillation loop circuit is subjected to a SET, two oscillation loop circuits remain operational, ensuring the accuracy of the voting result. Therefore, the voting output serves as the clock. Furthermore, this design combines large oscillation loops, bias circuits, and a three-mode VCO architecture, thus avoiding the problem of increasing nonlinearity. This results in a SET-resistant VCO circuit capable of maintaining high-frequency stable operation under ultra-low voltage conditions such as 0.8V, achieving SET resistance, especially at 0.8V. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the circuit structure of a voltage-controlled oscillator circuit resistant to single-event transients in one embodiment; Figure 2 This is a schematic diagram of one specific circuit structure of a voltage-controlled oscillator circuit resistant to single-event transients in one embodiment; Figure 3 This is a schematic diagram of the circuit structure of the voltage-controlled ring resonator unit in one embodiment. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0014] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0015] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0016] Existing technologies, such as a high-speed differential output voltage-controlled oscillator with low soft error rate, employ voltage bias control. Single-loop differential low-gain oscillators are only suitable for higher voltage circuits. This application provides a novel voltage-controlled oscillator circuit resistant to single-event transients. Its core improvement lies in using six oscillation branches coupled into three large oscillation loops to increase gain. Compared to existing technologies, besides employing the existing voting circuit, other circuit structures are entirely redesigned.

[0017] In one embodiment, such as Figure 1 As shown, a voltage-controlled oscillator circuit resistant to single-event transients is provided, comprising three identical oscillation ring modules 10, a first voting unit T1, a second voting unit T2, a first digital buffer M49, and a second digital buffer M50. Each oscillation ring module 10 includes a bias circuit 101, an oscillation ring circuit 102, and two comparators. Each oscillation ring circuit 102 is composed of two coupled ring oscillators.

[0018] For each oscillating ring module 10: the input terminal of the bias circuit 101 is used to receive the input voltage signal VCO_IN, the output terminal of the bias circuit 101 is connected to the bias control terminal of the oscillating ring circuit 102, the non-inverting input terminal and the inverting input terminal of any comparator are respectively connected to the output terminals of the two ring oscillators in the oscillating ring circuit 102, the output terminal of one comparator is connected to one input terminal of the first voting unit T1, and the output terminal of the other comparator is connected to one input terminal of the second voting unit T2.

[0019] The output of the first voting device T1 is connected to the input of one ring oscillator in each oscillating ring circuit 102 and to the input of the first digital buffer M49. The output of the second voting device T2 is connected to the input of another ring oscillator in each oscillating ring circuit 102 and to the input of the second digital buffer M50. The outputs of the first digital buffer M49 and the second digital buffer M50 are used to output clock signals (such as OUTP and OUTN).

[0020] Understandable, such as Figure 1 As shown, a SET-resistant VCO circuit was designed by combining a large oscillating loop, a bias circuit, and a three-mode VCO architecture. This circuit can operate stably at an ultra-low voltage of 0.8V. The circuit has six oscillating branches, which are coupled in pairs to form three large oscillating loop circuits to improve loop gain.

[0021] The aforementioned voltage-controlled oscillator (VCO) circuit for single-event transient immunity addresses the issue of traditional three-mode relaxation oscillator (VCO) circuits being unsuitable for low-voltage conditions, especially when the power supply voltage drops to around 0.8V. It employs a six-branch coupling system to form three large oscillating loops to improve loop gain. By combining bias circuits, comparators, and voting circuits for each loop, the traditional differential ring oscillator is disassembled and connected to comparators separately. The differential clock is converted to a single-ended clock for voting, and the voting result is fed back to each oscillating loop circuit. This ensures the normal operation of the VCO and guarantees that even if any oscillating loop circuit is subjected to a single-event attack, two oscillating loop circuits will remain operational, guaranteeing the accuracy of the voting result. Therefore, the voting output serves as the clock. Furthermore, this design combines large oscillating loops, bias circuits, and a three-mode VCO architecture, thus avoiding the problem of increasing nonlinearity. This results in a single-event transient immunity VCO circuit capable of maintaining high-frequency stable operation at ultra-low voltages such as 0.8V, achieving a single-event immunity effect, especially at 0.8V.

[0022] In one embodiment, the bias circuit includes a PMOS transistor, a current mirror PMOS transistor, an NMOS transistor, and a resistor. The source of the PMOS transistor and the source of the current mirror PMOS transistor are connected to the power supply. The gate of the PMOS transistor and the gate of the current mirror PMOS transistor are connected and then connected to the drain of the PMOS transistor. The drain of the PMOS transistor is connected to the drain of the NMOS transistor. The source of the NMOS transistor is grounded through the resistor. The gate of the NMOS transistor is used to receive the input voltage signal. The drain of the current mirror PMOS transistor is connected to the bias control terminal of the oscillation ring circuit.

[0023] Understandable, such as Figure 2 As shown, each bias circuit in this embodiment has the same structure and is used to provide a bias voltage input to a corresponding oscillation loop circuit. For example, the first bias circuit includes a first PMOS transistor M1, a first current mirror PMOS transistor MI1, a first NMOS transistor M2, and a first resistor R1. The second bias circuit includes a second PMOS transistor M3, a second current mirror PMOS transistor MI2, a second NMOS transistor M4, and a second resistor R2. The third bias circuit includes a third PMOS transistor M5, a third current mirror PMOS transistor MI3, a third NMOS transistor M6, and a third resistor R3. The gates of the first NMOS transistor M2, the second NMOS transistor M4, and the third NMOS transistor M6 are all used to connect to the input voltage signal VCO_IN. The gate voltage VP1 of the first PMOS transistor M1 is connected to the bias control terminal (i.e., VB terminal) of the first oscillating ring circuit through the drain of the first current mirror PMOS transistor MI1. The gate voltage VP2 of the second PMOS transistor M3 is connected to the bias control terminal of the second oscillating ring circuit through the drain of the second current mirror PMOS transistor MI2. The gate voltage VP3 of the third PMOS transistor M5 is connected to the bias control terminal of the third oscillating ring circuit through the drain of the third current mirror PMOS transistor MI3.

[0024] The bias circuit in this embodiment is specifically designed for the aforementioned large oscillating loop circuit, exhibiting excellent performance in terms of large bias current, high gain, and high matching. Existing bias circuits, such as those in a high-speed differential output voltage-controlled oscillator with low soft error rate, are not suitable for the operation of the voltage-controlled oscillator circuit resistant to single-event transients in this embodiment. By utilizing three such bias circuits to provide bias functions for the corresponding three oscillating loop circuits, the stable and effective bias input required for reliable operation of the oscillating loop circuit under low voltage is ensured.

[0025] In one embodiment, such as Figure 2As shown, the oscillating ring circuit (taking the first oscillating ring circuit as an example) includes a coupling unit and two ring oscillators. One ring oscillator includes the first to the third voltage-controlled ring oscillator units (i.e., M7 to M9) connected in series. The coupling unit includes the fourth to the ninth voltage-controlled ring oscillator units (i.e., M10 to M15). The other ring oscillator includes the tenth to the twelfth voltage-controlled ring oscillator units (i.e., M16 to M18) connected in series. The input terminal of the first voltage-controlled ring oscillator unit M7 is connected to the output terminal of the first voting device T1, and the input terminal of the twelfth voltage-controlled ring oscillator unit M18 is connected to the output terminal of the second voting device T2.

[0026] The output terminal of the fourth voltage-controlled ring resonator M10 is connected to the input terminal of the fifth voltage-controlled ring resonator M11 and the input terminal of the second voltage-controlled ring resonator M8. The input terminal of the fourth voltage-controlled ring resonator M10 is connected to the output terminal of the fifth voltage-controlled ring resonator M11 and the input terminal of the tenth voltage-controlled ring resonator M16.

[0027] The output terminal of the sixth voltage-controlled ring resonator M12 is connected to the input terminal of the seventh voltage-controlled ring resonator M13 and the input terminal of the third voltage-controlled ring resonator M9. The input terminal of the sixth voltage-controlled ring resonator M12 is connected to the output terminal of the seventh voltage-controlled ring resonator M13 and the input terminal of the eleventh voltage-controlled ring resonator M17.

[0028] The output terminal of the eighth voltage-controlled ring resonator M14 is connected to the input terminal of the ninth voltage-controlled ring resonator M15 and the output terminal of the third voltage-controlled ring resonator M9. The input terminal of the eighth voltage-controlled ring resonator M14 is connected to the output terminal of the ninth voltage-controlled ring resonator M15 and the output terminal of the eleventh voltage-controlled ring resonator M17.

[0029] The non-inverting and inverting inputs of comparator M19 are connected to the outputs of the third voltage-controlled ring resonator unit M9 and the eleventh voltage-controlled ring resonator unit M17, respectively. Correspondingly, the non-inverting and inverting inputs of another comparator M20 are connected to the outputs of the eleventh voltage-controlled ring resonator unit M17 and the third voltage-controlled ring resonator unit M9, respectively. The bias control terminals of all voltage-controlled ring resonators are connected to the output of bias circuit 101.

[0030] Understandable, such as Figure 2 As shown, the second oscillating ring circuit has a similar structure, consisting of corresponding voltage-controlled ring oscillator units M21 to M32, comparator M33, and comparator M34. The third oscillating ring circuit also has a similar structure, consisting of corresponding voltage-controlled ring oscillator units M35 to M46, comparator M47, and comparator M48. By disassembling the traditional differential ring oscillator as described above and connecting each part to a corresponding comparator, the differential clock is converted into a single-ended clock for voting, which more effectively ensures the gain under low power supply voltage.

[0031] In one embodiment, the ring oscillator includes a series of three-stage voltage-controlled ring oscillator units, a series of five-stage voltage-controlled ring oscillator units, or a series of seven-stage voltage-controlled ring oscillator units.

[0032] It is understandable that, based on the aforementioned three-mode hardening approach combining a ring oscillator and a relaxation oscillator, it is also possible to, for example... Figure 3 The voltage-controlled ring resonator units M7, M8, and M9 are extended from three-stage voltage-controlled ring resonator units to five-stage or seven-stage voltage-controlled ring resonator units. The corresponding oscillation loop circuit design is obtained through the above design concept. Specifically, the five-stage or seven-stage resonator unit is based on the three-stage voltage-controlled ring resonator unit, with basic voltage-controlled ring resonator units connected in series, transforming a single-loop resonator into a five-stage or seven-stage circuit to further improve the loop gain.

[0033] In one embodiment, such as Figure 3 As shown, the voltage-controlled ring oscillator unit includes a PMOS transistor M01 and an NMOS transistor M02. The source of the PMOS transistor M01 is the bias control terminal. The gate of the PMOS transistor M01 is connected to the gate of the NMOS transistor M02 and serves as the input terminal. The drain of the PMOS transistor M01 is connected to the drain of the NMOS transistor M02 and serves as the output terminal. The source of the NMOS transistor M02 is grounded.

[0034] It is understandable that the specific structure of the pressure-controlled ring resonator is as follows: Figure 3 As shown, it includes a PMOS transistor M01 and an NMOS transistor M02, wherein the source of the PMOS transistor M01 is the bias control terminal (i.e., the VB terminal).

[0035] Traditional anti-SET voltage-controlled oscillator (VCO) circuits employ a relaxation oscillator structure. Under low supply voltages, this structure exhibits very low gain, high nonlinearity, and is prone to failure to oscillate. This embodiment designs an oscillation loop circuit using a current-controlled inverter structure, replacing the relaxation oscillator structure with a combination of ring oscillation and relaxation oscillation. This maximizes the gain under low supply voltages, preventing failure to oscillate due to excessively low gain in the VCO ring oscillator unit. Furthermore, the ring oscillator's higher speed compared to the relaxation oscillator makes it more suitable for high-frequency, high-speed applications. For example, it ensures normal VCO operation even with a minimum supply voltage greater than 0.8V and possesses single-event transient immunity. This ensures that when any point in the circuit other than the first digital buffer M49 and the second digital buffer M50 is subjected to a single-event attack, the VCO's output frequency deviation will not exceed 5%.

[0036] In one embodiment, a phase-locked loop circuit is also provided, wherein the voltage-controlled oscillator circuit in the phase-locked loop circuit adopts the above-described voltage-controlled oscillator circuit resistant to single-event transients.

[0037] It is understood that the specific limitations of the voltage-controlled oscillator circuit for single-event transient resistance in phase-locked loop circuits can be found in the corresponding limitations of the voltage-controlled oscillator circuit for single-event transient resistance mentioned above, and will not be repeated here.

[0038] By applying the aforementioned voltage-controlled oscillator circuit that resists single-event transients, this phase-locked loop circuit can effectively achieve single-event immunity at low voltages, especially at 0.8V, thereby improving the reliability of the phase-locked loop circuit in a radiation environment.

[0039] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0040] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A voltage-controlled oscillator circuit resistant to single-event transients, characterized in that, It includes three identical oscillating ring modules, a first voting device, a second voting device, a first digital buffer, and a second digital buffer. Each oscillating ring module includes a bias circuit, an oscillating ring circuit, and two comparators. Each oscillating ring circuit is composed of two coupled ring oscillators. For each oscillating ring module: the input terminal of the bias circuit is used to receive the input voltage signal, the output terminal of the bias circuit is connected to the bias control terminal of the oscillating ring circuit, the non-inverting input terminal and the inverting input terminal of any comparator are respectively connected to the output terminals of the two ring oscillators in the oscillating ring circuit, the output terminal of one comparator is connected to one input terminal of the first voting device, and the output terminal of the other comparator is connected to one input terminal of the second voting device. The output of the first voting device is connected to the input of one ring oscillator in each oscillation ring circuit and to the input of the first digital buffer. The output of the second voting device is connected to the input of another ring oscillator in each oscillation ring circuit and to the input of the second digital buffer. The outputs of the first and second digital buffers are used to output clock signals.

2. The voltage-controlled oscillator circuit resistant to single-event transients according to claim 1, characterized in that, The bias circuit includes a PMOS transistor, a current mirror PMOS transistor, an NMOS transistor, and a resistor. The sources of the PMOS transistor and the current mirror PMOS transistor are connected to the power supply. The gates of the PMOS transistor and the current mirror PMOS transistor are connected and then connected to the drain of the PMOS transistor. The drain of the PMOS transistor is connected to the drain of the NMOS transistor. The source of the NMOS transistor is grounded through the resistor. The gate of the NMOS transistor is used to receive the input voltage signal. The drain of the current mirror PMOS transistor is connected to the bias control terminal of the oscillation ring circuit.

3. The voltage-controlled oscillator circuit resistant to single-event transients according to claim 1 or 2, characterized in that, The oscillating ring circuit includes a coupling unit and two ring oscillators. One ring oscillator includes a first voltage-controlled ring oscillator unit to a third voltage-controlled ring oscillator unit connected in series. The coupling unit includes a fourth voltage-controlled ring oscillator unit to a ninth voltage-controlled ring oscillator unit. The other ring oscillator includes a tenth voltage-controlled ring oscillator unit to a twelfth voltage-controlled ring oscillator unit connected in series. The input terminal of the first voltage-controlled ring oscillator unit is connected to the output terminal of the first voting device, and the input terminal of the twelfth voltage-controlled ring oscillator unit is connected to the output terminal of the second voting device. The output terminal of the fourth voltage-controlled ring resonator is connected to the input terminal of the fifth voltage-controlled ring resonator and the input terminal of the second voltage-controlled ring resonator. The input terminal of the fourth voltage-controlled ring resonator is connected to the output terminal of the fifth voltage-controlled ring resonator and the input terminal of the tenth voltage-controlled ring resonator. The output terminal of the sixth voltage-controlled ring resonator is connected to the input terminal of the seventh voltage-controlled ring resonator and the input terminal of the third voltage-controlled ring resonator. The input terminal of the sixth voltage-controlled ring resonator is connected to the output terminal of the seventh voltage-controlled ring resonator and the input terminal of the eleventh voltage-controlled ring resonator. The output terminal of the eighth voltage-controlled ring resonator is connected to the input terminal of the ninth voltage-controlled ring resonator and the output terminal of the third voltage-controlled ring resonator. The input terminal of the eighth voltage-controlled ring resonator is connected to the output terminal of the ninth voltage-controlled ring resonator and the output terminal of the eleventh voltage-controlled ring resonator. The non-inverting and inverting inputs of one comparator are connected to the outputs of the third and eleventh voltage-controlled ring resonator units, respectively. Similarly, the non-inverting and inverting inputs of another comparator are connected to the outputs of the eleventh and third voltage-controlled ring resonator units, respectively. The bias control terminals of all voltage-controlled ring resonator units are connected to the output of the bias circuit.

4. The voltage-controlled oscillator circuit resistant to single-event transients according to claim 1, characterized in that, Ring oscillators include three-stage voltage-controlled ring oscillator units, five-stage voltage-controlled ring oscillator units, or seven-stage voltage-controlled ring oscillator units connected in series.

5. The voltage-controlled oscillator circuit resistant to single-event transients according to claim 3, characterized in that, The voltage-controlled ring oscillator unit includes a PMOS transistor M01 and an NMOS transistor M02. The source of the PMOS transistor M01 is the bias control terminal. The gate of the PMOS transistor M01 is connected to the gate of the NMOS transistor M02 and serves as the input terminal. The drain of the PMOS transistor M01 is connected to the drain of the NMOS transistor M02 and serves as the output terminal. The source of the NMOS transistor M02 is grounded.

6. A phase-locked loop circuit, characterized in that, The voltage-controlled oscillator circuit in the phase-locked loop circuit adopts the voltage-controlled oscillator circuit resistant to single-event transients as described in any one of claims 1 to 5.

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