A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. A first gate field plate electrically connected with a gate metal is added between a source field plate and a drain metal, and the first gate field plate is electrically connected with the gate metal through a resistor. In this way, the first gate field plate has a lower potential. On one hand, the first gate field plate can shield the electric field between the drain and the gate, and can further deplete the two-dimensional electron gas at the channel, so as to reduce the Cgd of the device, improve the gain and stability of the device, and avoid self-excitation of the device. On the other hand, the first gate field plate can shield the electric field between the drain and the source, reduce the Cds of the device, and thus improve the drain efficiency of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for fabricating the same. Background Technology

[0002] For RF GaN devices, parasitic capacitance has a significant impact on the device's RF performance at high frequencies. Among these, the parasitic capacitance between the source and drain (Cds) and the parasitic capacitance between the gate and drain (Cgd) have a crucial influence on the device's RF performance. Therefore, it is generally necessary to reduce Cds and Cgd to improve the device's RF performance.

[0003] Although existing devices use source field plates to reduce device Cgd, the reduced Cgd still increases device instability and makes the device prone to self-oscillation. Furthermore, the addition of source field plates also increases the device's Cds, resulting in lower drain efficiency. Summary of the Invention

[0004] The purpose of this application is to address the shortcomings of the prior art by providing a semiconductor device and its fabrication method, thereby solving the problems of self-oscillation caused by large Cgd and low drain efficiency caused by increased Cds in existing devices.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0006] In one aspect of this application, a semiconductor device is provided, including a substrate and a functional layer disposed on the substrate. The functional layer includes an active region and a passive region located around the active region. A source metal, a drain metal, and a gate metal located between the source metal and the drain metal are respectively disposed in the active region of the functional layer. A source field plate is disposed on the side of the gate metal near the drain metal, and a first dielectric layer is disposed between the gate metal and the source field plate. A first gate field plate is disposed between the source field plate and the drain metal, the first gate field plate is electrically connected to the gate metal via a resistor, and a second dielectric layer is disposed between the source field plate and the first gate field plate.

[0007] Optionally, the resistor is a thin-film resistor.

[0008] Optionally, a first metal part and a second metal part are respectively provided in the passive region of the functional layer. The first metal part is electrically connected to the gate metal, and the second metal part is electrically connected to the first gate field plate. The resistor includes a two-dimensional electron gas resistor located in the passive region of the functional layer. The first metal part and the second metal part are electrically connected through the two-dimensional electron gas resistor.

[0009] Optionally, the resistance value can be greater than 100Ω.

[0010] Optionally, at least one interconnect hole is provided on the second dielectric layer between the source field plate and the drain metal, and the first gate field plate includes a vertical field plate located in the interconnect hole.

[0011] Optionally, the first gate field plate further includes a lateral field plate, which is connected to the vertical field plate and extends toward the gate metal.

[0012] Optionally, the second dielectric layer includes a stacked first sublayer and a second sublayer, the second sublayer having an interconnect via located between the source field plate and the drain metal, and the first gate field plate including a lateral field plate located between the first sublayer and the second sublayer and a vertical field plate located within the interconnect via, the vertical field plate being connected to the lateral field plate.

[0013] Optionally, the gate metal includes a gate pillar in contact with the functional layer and a second gate field plate located on top of the gate pillar.

[0014] Optionally, a source via is provided on the back side of the substrate, extending to the source metal, and a back metal is provided on the back side of the substrate, the back metal being connected to the source metal through the source via.

[0015] Another aspect of this application provides a method for fabricating a semiconductor device, the method comprising: fabricating a functional layer on a substrate; fabricating a source metal, a drain metal, and a gate metal located between the source metal and the drain metal on the functional layer; forming a first dielectric layer on the gate metal; fabricating a source field plate located on the side of the gate metal closer to the drain metal on the first dielectric layer; forming a second dielectric layer on the source field plate; and fabricating a first gate field plate located between the source field plate and the drain metal on the second dielectric layer, wherein the first gate field plate is electrically connected to the gate metal via a resistor.

[0016] Optionally, the resistor can be a thin-film resistor or a two-dimensional electronic gas resistor.

[0017] The beneficial effects of this application include:

[0018] This application provides a semiconductor device and its fabrication method. By adding a first gate field plate electrically connected to the gate metal between the source field plate and the drain metal, and electrically connecting the first gate field plate to the gate through a resistor, the first gate field plate has a low potential. On the one hand, it can not only shield the electric field between the drain and the gate, but also further deplete the two-dimensional electron gas at the channel, which is conducive to reducing the Cgd of the device, improving the gain and stability of the device, and avoiding self-oscillation of the device. On the other hand, the first gate field plate can also shield the electric field between the drain and the source, reduce the Cds of the device, and thus improve the drain efficiency of the device. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of the drain-side equivalent circuit of a gallium nitride high electron mobility transistor device;

[0021] Figure 2 This is one of the schematic diagrams of a semiconductor device provided in the embodiments of this application;

[0022] Figure 3 This is a second schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0023] Figure 4 This is the third schematic diagram of the structure of a semiconductor device provided in the embodiments of this application;

[0024] Figure 5 This is the fourth schematic diagram of the structure of a semiconductor device provided in the embodiments of this application;

[0025] Figure 6 This is a graph showing the relationship between the gate-drain parasitic capacitance and the gate voltage of a traditional device.

[0026] Figure 7 For based on Figure 3 The diagram shows the relationship between the gate-drain parasitic capacitance and the gate voltage of the device shown.

[0027] Figure 8 The graph shows the relationship between source / drain parasitic capacitance and gate voltage for this application and conventional devices;

[0028] Figure 9 This is the fifth schematic diagram of the structure of a semiconductor device provided in the embodiments of this application;

[0029] Figure 10 This is the sixth schematic diagram of the structure of a semiconductor device provided in the embodiments of this application;

[0030] Figure 11 for Figure 10 A magnified view of a portion of the image;

[0031] Figure 12 for Figure 11 Cross-sectional view.

[0032] Icons: 100-Substrate; 110-Functional layer; 120-Source metal; 121-Source via; 122-Back metal; 130-Drain metal; 140-Gate metal; 141-First metal portion; 150-Source field plate; 160-First gate field plate; 161-Vertical field plate; 162-Lateral field plate; 163-Second metal portion; 170-Third dielectric layer; 180-First dielectric layer; 190-Second dielectric layer; 191-First sublayer; 192-Second sublayer; 210-Resistor; 211-Thin film resistor; 212-Two-dimensional electron gas resistor; 220-Active region; 230-Passive region. Detailed Implementation

[0033] The embodiments described below represent the information necessary for those skilled in the art to practice the embodiments and illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will recognize the application of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0034] It should be understood that while the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] It should be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element" or "extending to another element," it may be directly on or directly extended to the other element, or there may be an intermediate element. Conversely, when an element is referred to as "directly on another element" or "directly extending to another element," there is no intermediate element. Similarly, it should be understood that when an element (such as a layer, region, or substrate) is referred to as "above another element" or "extending above another element," it may be directly on or directly extended to the other element, or there may be an intermediate element. Conversely, when an element is referred to as "directly on another element" or "extending directly to another element," there is no intermediate element. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0036] Related terms such as “below”, “above”, “upper”, “lower”, “horizontal”, or “vertical” are used herein to describe the relationship of one element, layer, or region to another, as illustrated in the figures. It should be understood that these terms, and those discussed above, are intended to cover different orientations of the device other than those depicted in the figures.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “described” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that, when used herein, the term “comprising” indicates the presence of the stated feature, integer, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that the terms used herein should be interpreted as having the same meaning as they would in the context of this specification and the relevant field, and not in an idealized or overly formal sense, unless explicitly defined herein.

[0039] One aspect of this application provides a semiconductor device. By adding a first gate field plate electrically connected to the gate metal between the source field plate and the drain metal, and electrically connecting the first gate field plate to the gate through a resistor, the first gate field plate has a low potential. This not only shields the electric field between the drain and the gate, but also further depletes the two-dimensional electron gas at the channel, facilitating a reduction in the device's Cgd, improving the device's gain and stability, and preventing self-oscillation. Furthermore, the first gate field plate also shields the electric field between the drain and the source, reducing the device's Cds, thereby improving the device's drain efficiency. The embodiments of this application will now be described with reference to the accompanying drawings.

[0040] Please see Figure 2This illustration shows a semiconductor device including a substrate 100 and a functional layer 110 disposed on the substrate 100. The substrate 100 can be a substrate for supporting semiconductor integrated circuit components, such as GaN, GaAs, or SiC. The functional layer 110 can include multiple stacked active semiconductor layers, and a two-dimensional electron gas is present at the heterojunction between at least two of the multiple active semiconductor layers. Specifically, when the semiconductor device is a high electron mobility transistor device, the functional layer 110 can include a channel layer and a barrier layer. Of course, the functional layer 110 can also include a nucleation layer, a buffer layer, an insertion layer, etc., to enable the semiconductor device to have better performance. In some embodiments, the channel layer can be a GaN layer, and the barrier layer can be an AlGaN layer.

[0041] like Figure 10 As shown, the functional layer 110 includes an active region 220 and a passive region 230 located around the active region 220. The passive region 230 and the active region 220 can be defined on the functional layer 110 by mesa isolation or insulating ion implantation. Please continue reading. Figure 2 On the side of the functional layer 110 facing away from the substrate 100, a source metal 120 and a drain metal 130 are respectively disposed, and a gate metal 140 is disposed between the source metal 120 and the drain metal 130. Figure 10 As shown, source metal 120, drain metal 130, and gate metal 140 are all located in the active region 220 of the device. A first dielectric layer 180 and a second dielectric layer 190 are then sequentially stacked on the device surface with gate metal 140. A source field plate 150 is disposed between the first dielectric layer 180 and the second dielectric layer 190. Thus, the first dielectric layer 180 isolates the gate metal 140 and the source field plate 150, and the second dielectric layer 190 covers the source field plate 150. The source field plate 150 is located on the side of the gate metal 140 closest to the drain metal 130. Therefore, the source field plate 150 can shield the electric field between the gate and drain, thereby improving device performance. The source field plate 150 can be configured in a semi-enclosed form with the gate metal 140. The source field plate 150 is electrically connected to the source metal 120. This application does not limit the specific connection method; conventional methods in the art can be used, which will not be elaborated here.

[0042] A first gate field plate 160 is disposed on the second dielectric layer 190. Specifically, it may be disposed inside and / or above the second dielectric layer 190. The first gate field plate 160 is located between the source field plate 150 and the drain metal 130, and the first gate field plate 160 is electrically connected to the gate metal 140 through a resistor 210 to obtain a lower potential.

[0043] The first gate field plate 160 can shield the electric field between the drain metal 130 and the gate metal 140, and can further deplete the two-dimensional electron gas at the channel. This facilitates a reduction in the device's Cgd, thereby improving the device's gain and stability and preventing self-oscillation. Given... Figure 1 The diagram illustrates the leakage detection equivalent circuit of a gallium nitride high electron mobility transistor device, constructed from... Figure 1 As can be seen, due to the presence of Cds, the drain RF signal can directly form a signal loop through Cds, Rd and Rs, resulting in energy loss. Therefore, this application connects the first gate field plate 160 to the gate metal 140 via resistor 210, so that the RF signal fed back by the drain metal 130 can be coupled to the first gate field plate 160 and consumed by resistor 210, thus avoiding device self-oscillation.

[0044] The first gate field plate 160 can also shield the electric field between the drain and the source, reduce the Cds of the device, and thus improve the drain efficiency of the device.

[0045] In one implementation, such as Figure 2 As shown, interconnect holes are provided on the second dielectric layer 190, extending from the top surface of the second dielectric layer 190 into the second dielectric layer. In other words, interconnect holes are provided on the second dielectric layer 190 extending inward from the surface of the second dielectric layer 190 away from the substrate 100. Correspondingly, the first gate field plate 160 is a vertical field plate 161, which is located within the interconnect holes and is electrically connected to the gate metal 140 through a resistor 210, thereby enabling the vertical field plate 161 to obtain a lower potential. Specifically, this application does not limit the extension depth of the interconnect holes, as long as the vertical field plate 161 located therein can be insulated from the source field plate 150, the drain metal 130, the active region of the functional layer, and other structures that require insulation. For example, in one embodiment, when the second dielectric layer 190 includes a first sub-layer 191 and a second sub-layer 192 sequentially stacked on the source field plate 150, the interconnect holes may only penetrate the second sub-layer 192 (e.g., Figure 2 (as shown); In one embodiment, the interconnect can also pass through the second sub-layer 192 and the first sub-layer 191 in sequence; In one embodiment, when the semiconductor device further includes a third dielectric layer 170 located between the functional layer 110 and the first dielectric layer 180, the interconnect can also pass through the second sub-layer 192, the first sub-layer 191 and the first dielectric layer 180 in sequence.

[0046] In one implementation, such as Figure 3As shown, interconnect holes are provided on the second dielectric layer 190, extending inward from the surface of the second dielectric layer 190 away from the substrate 100. Correspondingly, the first gate field plate 160 includes a vertical field plate 161 and a horizontal field plate 162. The vertical field plate 161 is located within the interconnect holes, and the horizontal field plate 162 is located on the surface of the second dielectric layer 190 away from the substrate 100. One end of the horizontal field plate 162 is connected to the vertical field plate 161, and the other end of the horizontal field plate 162 extends towards the gate metal 140, thus forming an inverted L-shaped structure. The horizontal field plate 162 or the vertical field plate 161 is electrically connected to the gate metal 140 through a resistor 210, thereby enabling the first gate field plate 160 to obtain a lower potential. By adding the horizontal field plate 162, the shielding capability of the first gate field plate 160 can be further improved, achieving further reduction of Cgd and Cds, thereby improving device performance.

[0047] For example, regarding the Cgd of a device: Figure 6 The diagram shows the relationship between Cgd and the gate voltage when the device structure does not include the first gate field plate 160 (conventional device); Figure 7 As shown, the first gate field plate 160 is configured as an inverted L-shape in this application. Figure 3 The relationship between Cgd and gate voltage for the structure shown is illustrated; through... Figure 6 and Figure 7 It can be seen that the Cgd of the device in this application is lower than that of traditional devices. Regarding the Cds of the device: Figure 8 The diagram shows curve 010 of Cds for a conventional device and curve 020 of the device of this application (with the first gate field plate 160 configured as an inverted L-shape) within the gate voltage range of 0-80V. Figure 8 It is evident that the Cds of this application is also lower than that of traditional devices.

[0048] In one implementation, Figure 3 Based on the first gate field plate 160 shown, the end where the horizontal field plate 162 connects to the vertical field plate 161 can extend slightly toward the drain metal 130, such as... Figure 4 As shown, a positive T-shaped structure is formed.

[0049] In one implementation, such as Figure 5As shown, the second dielectric layer 190 includes a first sublayer 191 and a second sublayer 192 stacked together. The second sublayer 192 has an interconnect via located between the source field plate 150 and the drain metal 130. The first gate field plate 160 includes a lateral field plate 162 located between the first sublayer 191 and the second sublayer 192 and a vertical field plate 161 located within the interconnect via. The vertical field plate 161 and the lateral field plate 162 are connected to form an inverted T-shaped structure. Thus, the lateral field plate 162 can further deplete the two-dimensional electron gas at the channel, which helps to reduce the Cgd of the device. It should be understood that the present application does not specifically limit the location of the lateral field plate 162. For example, in one embodiment, the lateral field plate 162 may also be located between the first dielectric layer 180 and the first sublayer 191; in another embodiment, the lateral field plate 162 may also be located between the first dielectric layer 180 and the third dielectric layer 170.

[0050] In some implementations, such as Figure 9 As shown, resistor 210 is a thin-film resistor 211, such as a TaN thin-film resistor or a NiCr thin-film resistor. From the perspective of the planar distribution parallel to the substrate 100, the thin-film resistor 211 can be located directly above the source field plate 150. Figure 9 (as shown), or, located diagonally above the source field plate 150 (not shown in the figure), or, located in the passive region of the functional layer; from the vertical distribution of the substrate 100, the thin film resistor 211 can be located between any two of the first dielectric layer, the second dielectric layer, and the third dielectric layer, or, located on the upper surface of the second dielectric layer (as shown in the figure). Figure 9 (As shown). Setting resistor 210 as a thin-film resistor 211 can effectively simplify the resistor setting process and reduce manufacturing costs.

[0051] In some implementations, such as Figures 10 to 12 As shown, resistor 210 includes a two-dimensional electron gas resistor 212 located in the passive region 230 of functional layer 110. When the two-dimensional electron gas resistor 212 is formed, the active region 220 and the passive region 230 can be defined in the aforementioned manner, and the two-dimensional electron gas of functional layer 110 located in the resistive region can be retained within the passive region 230, thereby utilizing the two-dimensional electron gas of the resistive region as the two-dimensional electron gas resistor 212. For example... Figures 10 to 12 As shown, when defining the active region 220 and the passive region 230 by insulating ion implantation, a mask layer can be used to block the functional layer 110 of the resistive region of the passive region 230, thereby forming a non-implanted region (i.e., the resistive region).

[0052] To achieve good electrical connection, after the functional layer 110 is formed, a first metal portion 141 and a second metal portion 163 can be pre-fabricated in the passive region 230 of the functional layer 110. Both the first metal portion 141 and the second metal portion 163 are at least partially located in the resistive region. The first metal portion 141 and the second metal portion 163 can respectively form ohmic contacts with the resistive region of the passive region 230, thereby achieving a good electrical connection between the first metal portion 141 and the second metal portion 163 through the two-dimensional electron gas resistance 212 of the resistive region. The first metal portion 141 can be electrically connected to the gate metal 140, and the second metal portion 163 can be electrically connected to the first gate field plate 160 (during connection, the second metal portion 163 can be connected to the vertical field plate or the horizontal field plate). In some embodiments, the first metal portion 141 and the second metal portion 163 can be fabricated in the same process step as the ohmic metals of the source and drain of the active region. When resistor 210 is a two-dimensional electronic gas resistor 212, the structure of the semiconductor device itself can be fully utilized to fabricate the resistor, thereby integrating the resistor into the semiconductor device, which helps to reduce the size of the semiconductor device.

[0053] In some implementations, the resistor region can be positioned close to the active region, but a certain distance must be maintained between them to avoid interference from the two-dimensional electronic gas resistor to the active region.

[0054] In some implementations, the resistance of resistor 210 can be greater than 100Ω, thereby enabling resistor 210 to effectively dissipate the RF signal fed back by the drain metal 130 and avoid device self-oscillation.

[0055] In some implementations, such as Figures 2 to 5 As shown, the gate metal 140 can be a T-type gate, that is, the gate metal 140 includes a gate pillar and a second gate field plate located on the top of the gate pillar. The gate pillar forms a Schottky contact with the functional layer 110, and the second gate field plate can modulate the peak electric field near the gate, thereby enabling the device to have a high breakdown voltage.

[0056] In some implementations, such as Figures 2 to 5 As shown, a source via 121 is provided on the back side of the substrate 100, extending through to the source metal 120, so that the back metal 122 provided on the back side of the substrate 100 can be connected to the source metal 120 through the source via 121, thereby enabling the source metal 120 to be led out from the back side of the device.

[0057] In some implementations, such as Figures 2 to 5 As shown, a third dielectric layer 170 may also be provided to isolate the gate metal 140 and the source / drain.

[0058] In some embodiments, the first dielectric layer 180, the second dielectric layer 190, and the third dielectric layer 170 may be made of materials such as SiN and SiO2, and this application does not limit them.

[0059] In some embodiments, the first gate field plate 160 is a metal field plate.

[0060] Another aspect of this application provides a method for fabricating a semiconductor device, the method comprising:

[0061] S010: Fabricate a functional layer 110 on a substrate 100.

[0062] A functional layer 110 is deposited on the substrate 100. The deposition method can be chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc. This application does not limit the method, and the specific method can be reasonably selected according to actual needs.

[0063] S020: Source metal 120, drain metal 130 and gate metal 140 located between source metal 120 and drain metal 130 are fabricated on functional layer 110.

[0064] Source metal 120 and drain metal 130 are fabricated on functional layer 110, which can be formed by processes such as photolithography, evaporation, and lift-off. Source metal 120 and drain metal 130 can be fabricated in the same step. After forming source metal 120 and drain metal 130 on functional layer 110, a third dielectric layer 170 is deposited and etched to form a gate trench. Gate metal 140 is fabricated through the gate trench, and the gate metal 140 forms a Schottky contact with functional layer 110.

[0065] S030: A first dielectric layer 180 is formed on the gate metal 140.

[0066] Then, the entire first dielectric layer 180 is deposited, which covers the gate metal 140 for isolation.

[0067] S040: A source field plate 150 is formed on the first dielectric layer 180 on the side of the gate metal 140 near the drain metal 130.

[0068] Next, the source field plate 150 is fabricated on the first dielectric layer 180 through processes such as photolithography, evaporation, and stripping.

[0069] S050: A second dielectric layer 190 is formed on the source field plate 150.

[0070] A second dielectric layer 190 is deposited on the source field plate 150 to cover and isolate the source field plate 150.

[0071] S060: A first gate field plate 160 is fabricated on the second dielectric layer 190 between the source field plate 150 and the drain metal 130. The first gate field plate 160 is electrically connected to the gate metal 140 via a resistor 210.

[0072] Next, a first gate field plate 160 is fabricated on the second dielectric layer 190 using processes such as photolithography, evaporation, and lift-off. The first gate field plate 160 is then electrically connected to the gate metal 140 via a resistor 210. The specific configuration of the resistor 210 and the configuration of the first gate field plate 160 can be found in the aforementioned embodiments and will not be repeated here.

[0073] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, It includes a substrate and a functional layer disposed on the substrate, the functional layer including an active region and a passive region located around the active region; In the active region of the functional layer, an active metal, a drain metal, and a gate metal located between the source metal and the drain metal are respectively disposed; A source field plate is disposed on the side of the gate metal near the drain metal, and a first dielectric layer is disposed between the gate metal and the source field plate; A first gate field plate is disposed between the source field plate and the drain metal. The first gate field plate is electrically connected to the gate metal via a resistor, and a second dielectric layer is disposed between the source field plate and the first gate field plate.

2. The semiconductor device as claimed in claim 1, characterized in that, The resistor is a thin-film resistor.

3. The semiconductor device as described in claim 1, characterized in that, A first metal portion and a second metal portion are respectively provided in the passive region of the functional layer. The first metal portion is electrically connected to the gate metal, and the second metal portion is electrically connected to the first gate field plate. The resistor includes a two-dimensional electron gas resistor located in the passive region of the functional layer. The first metal portion and the second metal portion are electrically connected through the two-dimensional electron gas resistor.

4. The semiconductor device as claimed in claim 1, characterized in that, The resistance value of the resistor is greater than 100Ω.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, At least one interconnect is provided on the second dielectric layer between the source field plate and the drain metal, and the first gate field plate includes a vertical field plate located in the interconnect.

6. The semiconductor device as claimed in claim 5, characterized in that, The first gate field plate further includes a lateral field plate, which is connected to the vertical field plate and extends toward the gate metal.

7. The semiconductor device as claimed in claim 1, characterized in that, The gate metal includes a gate pillar in contact with the functional layer and a second gate field plate located on top of the gate pillar.

8. The semiconductor device as claimed in claim 1, characterized in that, A source via is provided on the back side of the substrate, extending through to the source metal. A back metal is provided on the back side of the substrate, and the back metal is connected to the source metal through the source via.

9. A method for fabricating a semiconductor device, characterized in that, The method includes: Fabricate functional layers on a substrate; A source metal, a drain metal, and a gate metal located between the source metal and the drain metal are respectively fabricated on the functional layer; A first dielectric layer is formed on the gate metal; A source field plate is fabricated on the first dielectric layer on the side of the gate metal near the drain metal; A second dielectric layer is formed on the source field plate; A first gate field plate is fabricated on the second dielectric layer between the source field plate and the drain metal, and the first gate field plate is electrically connected to the gate metal via a resistor.

10. The method for fabricating a semiconductor device as described in claim 9, characterized in that, The resistor is a thin-film resistor or a two-dimensional electronic gas resistor.

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