Image sensor package

Abstract

This provides an image sensor package that ensures the reliability of electrical connections. [Solution] The first substrate has a first surface and a second surface facing the first surface, and includes a sensor section on which a plurality of active pixels are arranged; the second substrate has a third surface and a fourth surface facing the third surface, and has through holes extending from the fourth surface to the third surface; a wiring layer disposed between the first surface and the third surface; a through electrode section formed on the through hole and connected to the wiring layer; a lower electrode layer including a back wiring section covering a part of the fourth surface; a connection terminal disposed on the fourth surface and electrically connected to the back wiring section; and a pad structure interposed between the back wiring section and the connection terminal and electrically connecting the back wiring section and the connection terminal. The pad structure includes a contact pad disposed on the back wiring section and a conductive capping layer disposed in a first direction between the contact pad and the connection terminal and connected to the contact pad and the connection terminal.

Description

Technical Field

[0001] The present invention relates to an image sensor package, and more particularly to an image sensor package capable of ensuring the reliability of electrical connection.

Background Art

[0002] Image sensors that capture images and convert them into electrical signals are used not only in consumer electronic devices such as digital cameras, mobile phone cameras, and portable video cameras, but also in cameras mounted on automobiles, security devices, and robots. Therefore, an image sensor package in which an image sensor is implemented as a package has been developed and is used as a main component.

[0003] Therefore, improving the reliability of image sensor packages has become an everyday issue.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention has been made in view of the problems in the above-mentioned conventional image sensor packages, and an object of the present invention is to provide an image sensor package capable of ensuring the reliability of electrical connection.

Means for Solving the Problems

[0006] To achieve the above objective, the present invention provides an image sensor package comprising: a first substrate having a first surface and a second surface facing the first surface, and including a sensor portion on which a plurality of active pixels are arranged; a second substrate having a third surface and a fourth surface facing the third surface, and having a through hole extending from the fourth surface to the third surface; a wiring layer disposed between the first surface and the third surface; a lower electrode layer including a through electrode portion formed on the through hole and connected to the wiring layer, and a back surface wiring portion covering a part of the fourth surface; a connection terminal disposed on the fourth surface and electrically connected to the back surface wiring portion; and a pad structure interposed between the back surface wiring portion and the connection terminal, electrically connecting the back surface wiring portion and the connection terminal, wherein the pad structure includes a contact pad disposed on the back surface wiring portion and a conductive capping layer disposed in a first direction between the contact pad and the connection terminal, and connected to the contact pad and the connection terminal.

[0007] Furthermore, the image sensor package according to the present invention, made to achieve the above objective, comprises: a first substrate having a first surface and a second surface facing the first surface, and including a sensor portion on which a plurality of active pixels are arranged; an upper wiring structure disposed on the first surface; a second substrate having a third surface and a fourth surface facing the third surface, and including a trench portion extending inward from the fourth surface, and a through hole extending from the bottom surface of the trench portion to the third surface; a lower wiring structure disposed on the third surface and in contact with the upper wiring structure; and the inner wall and bottom surface of the through hole and extending into the lower wiring structure, The lower electrode layer includes a through electrode portion connected to a part of the lower wiring structure and a back wiring portion covering a part of the fourth surface; a plurality of connection terminals arranged on the fourth surface and electrically connected to the back wiring portion; and a pad structure interposed between the back wiring portion and the plurality of connection terminals and electrically connecting the back wiring portion and the plurality of connection terminals, wherein the pad structure includes a plurality of contact pads arranged on the back wiring portion and a plurality of conductive capping layers arranged on the plurality of contact pads and partially separated from the plurality of contact pads.

[0008] Furthermore, the image sensor package according to the present invention, made to achieve the above objective, comprises: a first substrate having a first surface and a second surface facing the first surface, and including a sensor portion on which a plurality of active pixels are arranged; a glass plate disposed on the second surface of the first substrate; a dam structure interposed between the glass plate and the first substrate, having an outer surface aligned perpendicularly to the side surface of the glass plate; an upper wiring structure disposed on the first surface of the first substrate, including a plurality of upper wiring patterns and a stacked structure of a plurality of upper wiring vias; a second substrate having a third surface and a fourth surface facing the third surface, including a trench portion extending inward from the fourth surface, and a through hole extending from the bottom surface of the trench portion to the third surface; a lower wiring structure disposed on the third surface of the second substrate, in contact with the upper wiring structure, and including a plurality of lower wiring patterns and a stacked structure of a plurality of lower wiring vias; and a first package covering the inner wall of the trench portion, the inner wall of the through hole, and the fourth surface of the second substrate. A lower electrode layer comprising: a sivation layer; a through electrode portion on the first passivation layer that covers the inner wall and bottom surface of the through hole and extends into the lower wiring structure and is connected to a portion of the plurality of lower wiring patterns; a back wiring portion that is electrically connected to the through electrode portion and is disposed on a portion of the first passivation layer that covers the fourth surface of the second substrate; a second passivation layer that covers a portion of the lower electrode layer and includes a plurality of first openings that expose the lower electrode layer; a contact pad disposed in the first opening and electrically connected to the lower electrode layer; a third passivation layer that covers the second passivation layer and includes a plurality of second openings that expose a portion of the contact pad; a conductive capping layer, a portion of which is disposed in the second opening and electrically connected to the contact pad; and a plurality of connection terminals disposed on the conductive capping layer and electrically connected to the back wiring portion, the contact pad, and the conductive capping layer. [Effects of the Invention]

[0009] According to the image sensor package of the present invention, as the width and height of the contact pad increase, the volume of the contact pad increases, and the thermal expansion coefficient of the contact pad increases. As the thermal expansion coefficient of the contact pad increases, the difference in thermal expansion coefficient with the external connection terminal decreases. This improves the stability of the connection terminal electrically connected to the contact pad, and also improves the reliability of the electrical connection of the connection terminal. Furthermore, the horizontal width of the base portion is smaller than the width of the connector terminal, while the horizontal width of the peripheral portion is larger than the width of the connector terminal. This increases the contact area between the conductive capping layer and the connector terminal, improving the reliability of the electrical connection between the conductive capping layer and the connector terminal. Furthermore, the structure includes a through-electrode section that covers the inner wall and bottom surface of the through-hole, and the contact area between the through-electrode section and the stacked structure of multiple lower wiring patterns and multiple lower wiring vias included in the lower wiring structure is increased, thereby reducing contact resistance. [Brief explanation of the drawing]

[0010] [Figure 1] This is a cross-sectional view showing the schematic configuration of an image sensor package according to an embodiment of the present invention. [Figure 2] This is an enlarged view showing region IB in Figure 1. [Figure 3] This is an enlarged view showing the IC region in Figure 1. [Figure 4] This is an enlarged view showing the region ID in Figure 1. [Figure 5] This is a cross-sectional view illustrating a method for manufacturing an image sensor package according to an embodiment of the present invention. [Figure 6] This is a cross-sectional view illustrating a method for manufacturing an image sensor package according to an embodiment of the present invention. [Figure 7] This is a cross-sectional view illustrating a method for manufacturing an image sensor package according to an embodiment of the present invention. [Figure 8] This is a cross-sectional view illustrating a method for manufacturing an image sensor package according to an embodiment of the present invention. [Figure 9] It is a cross-sectional view for explaining a method of manufacturing an image sensor package according to an embodiment of the present invention. [Figure 10] It is a cross-sectional view for explaining a method of manufacturing an image sensor package according to an embodiment of the present invention. [Figure 11] It is a cross-sectional view for explaining a method of manufacturing an image sensor package according to an embodiment of the present invention. [Figure 12] It is a cross-sectional view for explaining a method of manufacturing an image sensor package according to an embodiment of the present invention. [Figure 13] It is a cross-sectional view for explaining a method of manufacturing an image sensor package according to an embodiment of the present invention. [Figure 14] It is a cross-sectional view for explaining a method of manufacturing an image sensor package according to an embodiment of the present invention. [Figure 15] It is a cross-sectional view for explaining a method of manufacturing an image sensor package according to an embodiment of the present invention. [Figure 16] It is a cross-sectional view for explaining a method of manufacturing an image sensor package according to an embodiment of the present invention. [Figure 17] It is a block diagram showing a schematic configuration of an image sensor package according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0011] Next, specific examples of embodiments for implementing the image sensor package according to the present invention will be described clearly and in detail to such an extent that a person having ordinary knowledge in the technical field of the present invention can easily implement it while referring to the drawings.

[0012] FIG. 1 is a cross-sectional view showing a schematic configuration of an image sensor package according to an embodiment of the present invention, FIG. 2 is an enlarged view showing region IB in FIG. 1, FIG. 3 is an enlarged view showing region IC in FIG. 1, and FIG. 4 is an enlarged view showing region ID in FIG. 1. <00…<00…<00…Referring to Figure 1, the image sensor package 1 includes a first substrate portion 100, a second substrate portion 200, a dam structure 310, and a glass plate 300. The image sensor package 1 has a first substrate portion 100 stacked vertically (in the Z direction) on a second substrate portion 200, a dam structure 310 attached to the first substrate portion 100, and a glass plate 300 stacked vertically (in the Z direction) on the dam structure 310. The first substrate section 100 includes a first substrate 110, a sensor section 120, and an upper wiring structure 140. The first substrate 110 includes a semiconductor substrate.

[0014] For example, the first substrate 110 may include a group IV semiconductor material, a group III-V semiconductor material, or a group II-VI semiconductor material. Group IV semiconductor materials may include, for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe). III-V semiconductor materials may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimony (InSb), or indium gallium arsenide (InGaAs). Group II-VI semiconductor materials may include, for example, zinc telluride (ZnTe) or cadmium sulfide (CdS). In one embodiment, the first substrate 110 is made of a P-type silicon substrate. In other embodiments, the first substrate 110 may include a P-type bulk substrate and a P-type or N-type epitaxial layer grown thereon. In other embodiments, the first substrate 110 may include an N-type bulk substrate and a P-type or N-type epitaxial layer grown on the N-type bulk substrate. In other embodiments, the first substrate 110 is made of an organic plastic substrate.

[0015] The sensor unit 120 may include, for example, a CMOS image sensor (CIS) or a CCD (Charge-Coupled Device). In one embodiment, the sensor unit 120 may have multiple active pixels (APX in Figure 2) arranged in a matrix. The upper wiring structure 140 will be explained in detail with reference to Figure 3. The second substrate section 200 includes a second substrate 210 and a lower wiring structure 240. The second substrate portion 200 is stacked on the first substrate portion 100 such that the lower wiring structure 240 is in contact with the upper wiring structure 140. The second substrate 210 includes a semiconductor substrate. In one embodiment, the second substrate 210 is made of the same or similar material as the first substrate 110. The lower wiring structure 240 will be explained in detail with reference to Figure 3.

[0016] The second substrate portion 200 includes a second substrate 210, a lower electrode layer 280, a first passivation layer 270, a second passivation layer 290, a contact pad 250, a third passivation layer 295, and a conductive capping layer 260. Specifically, the second substrate portion 200 includes a lower electrode layer 280 that penetrates the second substrate 210 and is connected to the lower wiring structure 240, a first passivation layer 270 interposed between the lower electrode layer 280 and the second substrate 210, a second passivation layer 290 covering the lower electrode layer 280, and a third passivation layer 295 covering the second passivation layer 290. The lower electrode layer 280 penetrates the second substrate 210 and is connected to the lower wiring structure 240. The lower electrode layer 280 is interposed between the first passivation layer 270 and the second passivation layer 290. The lower electrode layer 280 penetrates the first passivation layer 270 and connects to the lower wiring structure 240.

[0017] The first passivation layer 270 is interposed between the lower electrode layer 280 and the second substrate 210. The first passivation layer 270 consists of, for example, an oxide, a nitride, an oxynitride, or a combination thereof. In one embodiment, the first passivation layer 270 consists of a layered structure of hafnium oxide, silicon nitride, and hafnium oxide. For example, the first passivation layer 270 has a thickness of approximately 100 μm to approximately 300 μm. The lower electrode layer 280 is made of a metallic substance such as titanium, titanium nitride, tantalum, tantalum nitride, titanium tungsten, tungsten, aluminum, cobalt, nickel, or copper, or an alloy containing such a substance. In one embodiment, the lower electrode layer 280 is formed by a CVD process or an ALD process. For example, the lower electrode layer 280 has a thickness of approximately 2 μm to approximately 4 μm.

[0018] The second passivation layer 290 is made of an insulating material such as silicon oxide or silicon nitride. In one embodiment, the second passivation layer 290 comprises TEOS (Tetraethyl orthosilicate) or PE-TEOS (plasma-enhanced TEOS). The contact pad 250 is embedded in the second passivation layer 290. The contact pad 250 is located on the same vertical plane as the second passivation layer 290. The contact pad 250 is located on the area where the second passivation layer 290 has been partially removed and is physically and electrically connected to the lower electrode layer 280. The contact pad 250 is formed of a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), or solder, but is not limited to these. The third passivation layer 295 covers a portion of the second passivation layer 290 and a portion of the contact pad 250. The third passivation layer 295 is made of an insulating material such as silicon oxide or silicon nitride. In one embodiment, the third passivation layer 295 comprises TEOS (Tetraethyl orthosilicate) or PE-TEOS (plasma-enhanced TEOS). In one embodiment, the third passivation layer 295 is made of the same material as the second passivation layer 290.

[0019] A portion of the conductive capping layer 260 is embedded in the third passivation layer 295. The conductive capping layer 260 is located in the region where the third passivation layer 295 has been partially removed, and is situated on the contact pad 250. The conductive capping layer 260 is electrically connected to the lower electrode layer 280 via the contact pad 250. The conductive capping layer 260 is formed from a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), or solder, but is not limited to these. Multiple connection terminals 400 are attached to the lower surface of the second circuit board 200. For example, multiple connection terminals 400 are arranged on the fourth surface (reference numeral 210F2 in Figure 3) of the second substrate 210. The second passivation layer 290 leaves a portion of the lower electrode layer 280 exposed, and the contact pads 250 and conductive capping layer 260 on the lower electrode layer 280 connect to a portion of the lower electrode layer 280. Each of the multiple connection terminals 400 is electrically connected to the lower wiring structure 240 via the lower electrode layer 280, the contact pad 250, and the conductive capping layer 260.

[0020] The glass plate 300 is placed on the first substrate portion 100. For example, the glass plate 300 is placed on the second surface (reference numeral 110F2 in Figures 2 and 3) of the first substrate 110. A dam structure 310 is interposed between the glass plate 300 and the first substrate 110. The glass plate 300 is positioned at a certain distance from the first substrate portion 100 in the vertical direction (Z direction). For example, the glass plate 300 is positioned at a distance from the sensor unit 120 in the vertical direction (Z direction). The glass plate 300 is made of a transparent material that allows light for image formation to flow into the sensor unit 120. In one embodiment, the glass plate 300 includes an infrared cut-off filter (IRCF) and / or blue glass (blue filter) for infrared filtering. In other embodiments, the glass plate 300 is replaced with a film filter made of film material. However, the material of the glass plate 300 is not limited to this and may include a material configured such that light for image formation is incident on the sensor unit 120.

[0021] The horizontal area of ​​the glass plate 300 is larger than the horizontal area of ​​the sensor unit 120. In one embodiment, the horizontal area of ​​the glass plate 300 is substantially the same as the horizontal area of ​​the first substrate portion 100. In one embodiment, the horizontal area of ​​the first substrate portion 100 is substantially the same as the horizontal area of ​​the second substrate portion 200. For example, the horizontal areas of the first substrate portion 100, the second substrate portion 200, and the glass plate 300 are substantially the same and are all superimposed on each other in the perpendicular direction (Z direction). In one embodiment, the horizontal area of ​​the glass plate 300 is substantially the same as the horizontal area occupied by the internal space defined by the outer surface of the dam structure 310. For example, the side surfaces of the first substrate portion 100, the second substrate portion 200, the glass plate 300, and the outer surface of the dam structure 310 are aligned in the vertical direction (Z direction). The lower surface of the glass plate 300 is substantially in the same plane as the upper surface of the dam structure 310. Therefore, the glass plate 300 and the first substrate portion 100 are connected to each other via the dam structure 310.

[0022] Referring to Figures 1 and 2, the first substrate portion 100 of the image sensor package 1 includes a first substrate 110, a sensor portion 120, and an upper wiring structure 140. The first substrate 110 includes a first surface 110F1 and a second surface 110F2 that face each other. For convenience, here we will refer to the surface of the first substrate 110 on which the color filter layer 158 is placed at the top as the second surface 110F2, and the surface opposite the second surface 110F2 as the first surface 110F1. However, the technical concept of this invention is not limited to this. The sensor unit 120 includes a plurality of active pixel APXs arranged in a matrix within the first substrate 110. Multiple photoelectric conversion regions 126, each containing a photodiode region 122 and a well region 124, are arranged within the multiple active pixel APX. A pixel element isolation film 130 is placed within the first substrate 110, and multiple active pixel APXs are defined by the pixel element isolation film 130.

[0023] The pixel element isolation film 130 is positioned between one of the multiple photoelectric conversion regions 126 and an adjacent photoelectric conversion region 126. One photoelectric conversion region 126 and another photoelectric conversion region 126 adjacent to it are physically and electrically separated by a pixel element isolation film 130. The pixel element isolation film 130 is positioned between each of the multiple photoelectric conversion regions 126 arranged in a matrix, and has a grid or mesh-like structure in a plan view. The pixel element isolation film 130 is formed inside the pixel trench 130T that penetrates the first substrate 110 from the first surface 110F1 to the second surface 110F2. The pixel element isolation film 130 includes an insulating liner 132 conformally formed on the side wall of the pixel trench 130T, and a filling conductive layer 134 that fills the inside of the pixel trench 130T on the insulating liner 132. In one embodiment, the insulating liner 132 may contain a metal oxide such as hafnium oxide, aluminum oxide, or tantalum oxide. In other embodiments, the insulating liner 132 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The embedded conductive layer 134 may include, for example, at least one of doped polysilicon, metal, metal silicide, metal nitride, or metal-containing film. In one embodiment, the pixel element isolation film 130 has a tapered shape that extends from the same vertical level as the first surface 110F1 of the first substrate 110 to the same vertical level as the second surface 110F2, such that its horizontal width gradually narrows in the first horizontal direction (X direction).

[0024] An element isolation film STI is formed on the first surface 110F1 of the first substrate 110, which defines an active region (not shown) and a floating diffusion region (FD). In one embodiment, gate electrodes constituting multiple transistors are formed on the first surface 110F1 of the first substrate 110. For example, the transistors include a transfer transistor configured to transfer the charge generated in the photoelectric conversion region 126 to the floating diffusion region FD; a reset transistor configured to periodically reset the charge accumulated in the floating diffusion region FD; a drive transistor configured to function as a source follower buffer amplifier and buffer the signal according to the charge accumulated in the floating diffusion region; and a selection transistor that plays a role in switching and addressing for selecting the active pixel region APR. However, multiple transistors are not limited to this.

[0025] Figure 2 illustrates a transfer gate TG, which constitutes a transfer transistor among the gate electrodes that make up multiple transistors. The example shown illustrates a transfer gate TG constituting a transfer transistor, formed as a recessed gate type extending from the first surface 110F1 of the first substrate 110 into the interior of the first substrate 110. However, the shape of the transfer gate TG is not limited to this. In other embodiments, the reset gate constituting the reset transistor, the source follower gate constituting the drive transistor, and the selection gate constituting the selection transistor among the plurality of transistors are formed on the second substrate 210 so as to be included in the second substrate portion 200.

[0026] An upper wiring structure 140 is arranged on the first surface 110F1 of the first substrate 110. The upper wiring structure 140 is electrically connected to the gate electrode or the active region of the first substrate 110. For example, the upper wiring structure 140 may include conductive materials such as tungsten, aluminum, copper, tungsten silicide, titanium silicide, tungsten nitride, titanium nitride, and doped polysilicon, and insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. A cover insulating layer 152 is placed on the second surface 110F2 of the first substrate 110. In one embodiment, the cover insulating layer 152 completely covers the portion of the second surface 110F2 of the first substrate 110 corresponding to the sensor portion 120. The cover insulating layer 152 is in contact with the upper surface of the pixel element isolation film 130, which is positioned at the same vertical level as the second surface 110F2 of the first substrate 110. In one embodiment, the cover insulating layer 152 may contain a metal oxide such as aluminum oxide or tantalum oxide.

[0027] The front passivation layer 154 covers the cover insulating layer 152 on the second surface 110F2 of the first substrate 110. The front passivation layer 154 consists of, for example, an oxide, a nitride, an oxynitride, or a combination thereof. In one embodiment, the front passivation layer 154 consists of a laminated structure of hafnium oxide, silicon nitride, and hafnium oxide. A guide pattern 156 is formed on the front passivation layer 154. In a plan view, the guide pattern 156 has a grid-like or mesh-like structure. The guide pattern 156 prevents light incident at an oblique angle into one photoelectric conversion region 126 from entering an adjacent photoelectric conversion region 126. The guide pattern 156 may include, for example, at least one metallic substance from among tungsten, aluminum, titanium, ruthenium, cobalt, nickel, copper, gold, silver, or platinum.

[0028] On the front passivation layer 154 on which the guide pattern 156 is formed, a color filter layer 158 that overlaps with the photoelectric conversion region 126 and a microlens 160 that is placed on the color filter layer 158 are formed. The color filter layer 158 allows light incident through the microlens 160 to pass through, and only light of the required wavelength is incident on the photoelectric conversion region 126. The color filter layer 158 includes, for example, an R (red) filter, a B (blue) filter, and a G (green) filter. Alternatively, the color filter layer 158 includes a C (cyan) filter, a Y (yellow) filter, and an M (magenta) filter. Each active pixel APX has a color filter layer 158 formed on it, which is either an R filter, a B filter, or a G filter, or a C filter, a Y filter, or an M filter. Each active pixel APX senses the separated components of the incident light and recognizes a single color. The microlens 160 focuses the light incident on the image sensor package 1 onto the active pixel APX. In one embodiment, the microlens 160 consists of an organic layer 162 and an inorganic layer 164 that conformally covers the surface of the organic layer 162. For example, the organic layer 162 is made of TMR-type resin (manufactured by Tokyo Ohka Kogyo Co., Ltd.) or MFR-type resin (manufactured by Nippon Synthetic Rubber Co., Ltd.).

[0029] Referring to Figures 1 and 3, the first substrate portion 100 of the image sensor package 1 includes the first substrate 110 and the upper wiring structure 140. The first substrate 110 includes a first surface 110F1 and a second surface 110F2 that face each other. An upper wiring structure 140 is arranged on the first surface 110F1 of the first substrate 110. The upper wiring structure 140 consists of a stacked structure of multiple upper wiring patterns 142 and multiple upper wiring vias 144, and an upper interlayer insulating film 146 surrounding the multiple upper wiring patterns 142 and multiple upper wiring vias 144. In one embodiment, the upper wiring structure 140 can be formed using a damascene process. In one embodiment, at least one of the plurality of upper wiring patterns 142 and at least one of the plurality of upper wiring vias 144 are formed together to form a single unit.

[0030] In one embodiment, each of the multiple upper wiring patterns 142 and the multiple upper wiring vias 144 has a tapered shape that extends from the bottom to the top such that the horizontal width gradually narrows. In other words, the horizontal width of the multiple upper wiring patterns 142 and the multiple upper wiring vias 144 increases as they move away from the first substrate 110. Multiple upper wiring patterns 142 include multiple upper patterns located at other vertical levels. For example, the multiple upper wiring patterns 142 include a first upper pattern (M1-1), a second upper pattern (M2-1), a third upper pattern (M3-1), a fourth upper pattern (M4-1), a fifth upper pattern (M5-1), and a sixth upper pattern (M6-1) located at different vertical levels from one another. Multiple upper wiring vias 144 are connected to at least one of the first upper pattern (M1-1), second upper pattern (M2-1), third upper pattern (M3-1), fourth upper pattern (M4-1), fifth upper pattern (M5-1), and sixth upper pattern (M6-1).

[0031] The upper interlayer insulating film 146 is arranged on the first surface 110F1 of the first substrate 110 so as to surround a plurality of upper wiring patterns 142 and a plurality of upper wiring vias 144. The upper interlayer insulating film 146 may contain insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. In one embodiment, the upper wiring structure 140 includes a plurality of first bonding pads BP1. Multiple first bonding pads BP1 are electrically connected to multiple upper wiring patterns 142 and multiple upper wiring vias 144. For example, each of the multiple first bonding pads BP1 is connected to at least one of the multiple upper wiring vias 144. Multiple first bonding pads BP1 are positioned on the underside of the upper wiring structure 140, which faces the lower wiring structure 240. For example, the lower surfaces of multiple first bonding pads BP1 and the lower surface of the upper interlayer insulating film 146 facing the lower wiring structure 240 are coplanar.

[0032] The second substrate portion 200 of the image sensor package 1 includes a second substrate 210 and a lower wiring structure 240. The second substrate 210 includes a third surface 210F1 and a fourth surface 210F2 that face each other. For convenience, the surface of the second substrate 210 on which the lower wiring structure 240 is located at the top will be referred to as the third surface 210F1, and the surface opposite the third surface 210F1 will be referred to as the fourth surface 210F2. However, the technical concept of the present invention is not limited thereto. The lower wiring structure 240 is interposed between the upper wiring structure 140 and the second substrate 210, and is in contact with the upper wiring structure 140. The lower wiring structure 240 consists of a stacked structure of multiple lower wiring patterns 242 and multiple lower wiring vias 244, and a lower interlayer insulating film 246 surrounding the multiple lower wiring patterns 242 and multiple lower wiring vias 244.

[0033] In one embodiment, the lower wiring structure 240 can be formed using a damascene process. In one embodiment, at least one of the plurality of lower wiring patterns 242 and at least one of the plurality of lower wiring vias 244 are formed together to form a single unit. In one embodiment, each of the multiple lower wiring patterns 242 and the multiple lower wiring vias 244 has a tapered shape that extends from the bottom to the top, with the horizontal width gradually narrowing. In other words, the horizontal width of the multiple lower wiring patterns 242 and multiple lower wiring vias 244 increases as they move away from the second substrate 210. Multiple lower wiring patterns 242 include multiple lower patterns located at different vertical levels. For example, the multiple lower wiring patterns 242 include a first lower pattern (M1-2), a second lower pattern (M2-2), a third lower pattern (M3-2), a fourth lower pattern (M4-2), a fifth lower pattern (M5-2), a sixth lower pattern (M6-2), a seventh lower pattern (M7-2), and an eighth lower pattern (M8-2), all located at different vertical levels.

[0034] In this specification, each of the first lower pattern (M1-2), second lower pattern (M2-2), third lower pattern (M3-2), fourth lower pattern (M4-2), fifth lower pattern (M5-2), sixth lower pattern (M6-2), seventh lower pattern (M7-2), and eighth lower pattern (M8-2) may also be referred to as the first wiring pattern (M1-2), second wiring pattern (M2-2), third wiring pattern (M3-2), fourth wiring pattern (M4-2), fifth wiring pattern (M5-2), sixth wiring pattern (M6-2), seventh wiring pattern (M7-2), and eighth wiring pattern (M8-2). Multiple lower wiring vias 244 are connected to at least one of the following lower patterns: first lower pattern (M1-2), second lower pattern (M2-2), third lower pattern (M3-2), fourth lower pattern (M4-2), fifth lower pattern (M5-2), sixth lower pattern (M6-2), seventh lower pattern (M7-2), and eighth lower pattern (M8-2).

[0035] The lower interlayer insulating film 246 is arranged on the third surface 210F1 of the second substrate 210 so as to surround a plurality of lower wiring patterns 242 and a plurality of lower wiring vias 244. The lower interlayer insulating film 246 may contain insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. In one embodiment, the lower wiring structure 240 includes a plurality of second bonding pads BP2. Multiple second bonding pads BP2 are electrically connected to multiple lower wiring patterns 242 and multiple lower wiring vias 244. For example, each of the multiple second bonding pads BP2 is connected to at least one of the multiple lower wiring vias 244. Multiple second bonding pads BP2 are positioned on the upper surface of the lower wiring structure 240, which is opposite the upper wiring structure 140. For example, the upper surfaces of multiple second bonding pads BP2 and the upper surface of the lower interlayer insulating film 246 facing the upper wiring structure 140 are coplane.

[0036] The first bonding pad BP1 and the second bonding pad BP2, which are corresponding to each other, form a bonding pad BP. Multiple bonding pads BP are placed at the interface between the first substrate portion 100 and the second substrate portion 200, that is, at the interface between the upper interlayer insulating film 146 of the upper wiring structure 140 and the lower interlayer insulating film 246 of the lower wiring structure 240. The first bonding pad BP1 and the second bonding pad BP2, which correspond to each other and form a bonding pad BP, are positioned to overlap each other perpendicularly and are attached to each other. For example, the bonding interface, which is the interface between the first bonding pad BP1 and the second bonding pad BP2, is located on the same plane as the interface between the upper interlayer insulating film 146 of the upper wiring structure 140 and the lower interlayer insulating film 246 of the lower wiring structure 240. The first bonding pad BP1 and the second bonding pad BP2, which are corresponding to each other, expand due to heat and come into contact, and then become a single bonded pad BP through diffusion bonding by the diffusion of the metal atoms they contain. For example, the first substrate portion 100 and the second substrate portion 200 are laminated using a metal-oxide hybrid bonding method.

[0037] Referring to Figures 1, 3, and 4, the second substrate portion 200 includes a second substrate 210, a first passivation layer 270, a lower electrode layer 280, a second passivation layer 290, a contact pad 250, a third passivation layer 295, and a conductive capping layer 260. Specifically, the second substrate portion 200 includes a lower electrode layer 280 that penetrates the second substrate 210 and is connected to the lower wiring structure 240, a first passivation layer 270 interposed between the lower electrode layer 280 and the second substrate 210, a second passivation layer 290 covering the lower electrode layer 280, a contact pad 250 embedded inside the second passivation layer 290, a third passivation layer 295 covering the second passivation layer 290, and a conductive capping layer 260 on the contact pad 250. The second substrate 210 has a trench portion TR extending inward from the fourth surface 210F2 of the second substrate 210, and a through hole VH extending from the bottom surface of the trench portion TR to the third surface 210F1 of the second substrate 210. The trench section TR and the through hole VH are connected.

[0038] Figures 3 and 4 show the case where the second substrate 210 has one through-hole VH, but this is for illustrative purposes only, and the technical concept of the present invention is not limited to this. For example, the second substrate 210 has a plurality of through holes VH that extend from the bottom surface of the trench portion TR to the third surface 210F1 of the second substrate 210. The through-hole VH is further extended from the third surface 210F1 of the second substrate 210 into the lower wiring structure 240. For example, the through-hole VH is formed by removing a portion of the second substrate 210 and a portion of the lower interlayer insulating film 246. Within the through-hole VH, portions of multiple lower wiring patterns 242 are exposed. For example, the first lower pattern (M1-2) and the second lower pattern (M2-2) are exposed within the through-hole VH. The first lower pattern (M1-2) and the second lower pattern (M2-2) function as etching stop films during the process of forming the through-hole VH.

[0039] The first passivation layer 270 covers the inner wall of the trench section TR, the inner wall of the through hole VH, and the fourth surface 210F2 of the second substrate 210. In one embodiment, the first passivation layer 270 covers a portion of the bottom surface of the trench section TR. The lower electrode layer 280 covers the first passivation layer 270. The lower electrode layer 280 penetrates the first passivation layer 270 and connects to the lower wiring structure 240. For example, the lower electrode layer 280 is connected to a portion of a plurality of lower wiring patterns 242. For example, the lower electrode layer 280 is electrically connected to the first lower pattern (M1-2) and the second lower pattern (M2-2) by contact. The lower electrode layer 280 includes a through-electrode portion 282 and a back-side wiring portion 284. The through-electrode section 282 and the back wiring section 284 are electrically connected. The through-electrode portion 282 covers the inner wall and bottom surface of the through-hole VH in the lower electrode layer 280 and is connected to a portion of the multiple lower wiring patterns 242. For example, the through-electrode portion 282 is electrically connected to the first lower pattern (M1-2) and the second lower pattern (M2-2) by contact.

[0040] The back wiring section 284 is a portion of the lower electrode layer 280 that is located on the portion of the first passivation layer 270 that covers the fourth surface 210F2 of the second substrate 210. For example, the rear wiring section 284 is a line pattern. In one embodiment, the back wiring portion 284 extends from the portion of the first passivation layer 270 covering the fourth surface 210F2 of the second substrate 210 to the portion of the first passivation layer 270 covering the side surface of the trench portion TR, and is connected to the through electrode portion 282. The rear wiring section 284 is electrically connected to the connection terminal 400 shown in Figure 1 via the contact pad 250 and the conductive capping layer 260.

[0041] The second passivation layer 290 covers a portion of the lower electrode layer 280. The lower electrode layer 280 is interposed between the first passivation layer 270 and the second passivation layer 290. The second passivation layer 290 includes a first embedded portion 292 and a first back surface passivation portion 294. The first embedded portion 292 covers the through-electrode portion 282 within the second passivation layer 290 and fills the through-hole VH. The first back-side passivation section 294 is the portion that covers the back-side wiring section 284 within the second passivation layer 290. For example, the first back surface passivation portion 294 fills at least a portion of the trench portion TR and covers the fourth surface 210F2 of the second substrate 210. The contact pad 250 is located on the same vertical plane as the second passivation layer 290. The contact pad 250 is embedded within the second passivation layer 290.

[0042] In one embodiment, the contact pad 250 is cylindrical. In one embodiment, the contact pad 250 may be polygonal prism-shaped. The horizontal width in the cross-section of the contact pad 250 shown in Figure 4 is called the first width d1. The vertical height in the cross-section of the contact pad 250 shown in Figure 4 is called the first height h1. The first width d1 and the first height h1 may differ for each contact pad 250. In one embodiment, the first width d1 is smaller than the width of the cross-section of the connection terminal 400. Although only examples are shown where the first width d1 is smaller than the width in the cross-section of the connection terminal 400, the present invention is not limited thereto. In other embodiments, the first width d1 may be greater than the width of the cross-section of the connection terminal 400. In one embodiment, the first height h1 is the same as the height of the second passivation layer 290. Although only an example is shown where the first height h1 is the same as the height of the second passivation layer 290, the present invention is not limited thereto. In other embodiments, the first height h1 may be greater than or less than the height of the second passivation layer 290.

[0043] In one embodiment, when the first width d1 and first height h1 of the contact pad 250 are increased, the volume of the contact pad 250 increases, and the coefficient of thermal expansion (CTE) of the contact pad 250 increases. As the thermal expansion coefficient of the contact pad 250 increases, the difference in thermal expansion coefficients with respect to the external connection terminal (not shown) decreases. This improves the stability of the contact pad 250 and the electrically connected terminal 400. Furthermore, the reliability of the electrical connection of the connection terminal 400 is improved.

[0044] The third passivation layer 295 covers a portion of the second passivation layer 290. The third passivation layer 295 is placed on top of the second passivation layer 290. The third passivation layer 295 includes a second embedded portion 296 and a second back surface passivation portion 298. The second embedded portion 296 covers the through-electrode portion 282 and the first embedded portion 292 within the third passivation layer 295, and fills the through-hole VH. The second back-side passivation section 298 is the portion of the third passivation layer 295 that covers the back-side wiring section 284 and the first back-side passivation section 294. For example, the second back surface passivation section 298 fills at least a portion of the trench section TR and covers the fourth surface 210F2 of the second substrate 210. The conductive capping layer 260 is partially embedded within the third passivation layer 295. The conductive capping layer 260 includes a base portion 262 that is in physical contact with the contact pad 250, a peripheral portion 266 that is exposed on the third passivation layer 295, and a connecting portion 264 that connects the base portion 262 and the peripheral portion 266. In one embodiment, the conductive capping layer 260 is cylindrical with a concave center. In other embodiments, the conductive capping layer 260 may be a polygonal prism with a concave center.

[0045] Referring to Figure 4, the horizontal width in the cross-section of the base portion 262 is referred to as the second width d2. The horizontal width of the cross-section of the peripheral portion 266 is called the third width d3. The vertical height in the cross-section of the base portion 262 is referred to as the second height h2. The vertical height in the cross-section of the peripheral portion 266 is called the third height h3. The angle formed by the lower surface of the base portion 262 and the connecting portion 264 is called the first angle a1. The angle formed by the upper surface of the base portion 262 and the connecting portion 264 is called the second angle a2. The second width d2, third width d3, second height h2, third height h3, first angle a1, and second angle a2 may differ for each conductive capping layer 260 and are not limited to those shown in the figure. In one embodiment, the second width d2 is smaller than the width of the cross-section of the connection terminal 400. In one embodiment, the third width d3 is greater than the width of the cross-section of the connection terminal 400. This increases the contact area between the conductive capping layer 260 and the connection terminal 400. Furthermore, the reliability of the electrical connection between the conductive capping layer 260 and the connection terminal 400 is improved.

[0046] In one embodiment, the second height h2 is the same as the height of the third passivation layer 295. The third height h3 may be the same as or different from the second height h2. This example only shows the case where the second height h2 is the same as the height of the third passivation layer 295, but the present invention is not limited thereto. In other embodiments, the first height h1 may be greater than or less than the height of the second passivation layer 290. In one embodiment, the first angle a1 and the second angle a2 are the same. The first angle a1 and the second angle a2 are adjusted to match the shape of the connection terminal 400 and may differ from each other. This increases the contact area between the conductive capping layer 260 and the connection terminal 400. Furthermore, the reliability of the electrical connection between the conductive capping layer 260 and the connection terminal 400 is improved. In one embodiment, when the second width d2, third width d3, second height h2, and third height h3 of the conductive capping layer 260 are increased, the volume of the conductive capping layer 260 increases, and the coefficient of thermal expansion (CTE) of the image sensor package 1 increases. In the image sensor package 1, the thermal expansion coefficient CTE of the image sensor package 1 increases as the volume occupied by the conductive capping layer 260 increases. As the thermal expansion coefficient of the image sensor package 1 increases, the difference in thermal expansion coefficients between the image sensor package 1 and the external connection terminal (not shown) decreases. This improves the stability of the connection terminal 400, which is electrically connected to the conductive capping layer 260 of the image sensor package 1. Furthermore, the reliability of the electrical connection of the connection terminal 400 is improved.

[0047] The through-electrode portion 282, the first embedded portion 292, and the second embedded portion 296 are collectively referred to as the through-electrode structure BVS. The through-electrode structure BVS is called a back via stack. Referring to Figures 1 to 4, the image sensor package 1 includes a through-electrode structure BVS which includes a through-electrode portion 282 that covers the inner wall and bottom surface of the through-hole VH. During the process of forming the through-hole VH, the first lower pattern (M1-2) and the second lower pattern (M2-2) function as etching stop films, and the through-electrode portion 282 is connected to the first lower pattern (M1-2) and the second lower pattern (M2-2). Therefore, in the image sensor package 1 according to the present invention, the contact area between the through electrode portion 282 and the stacked structure of the multiple lower wiring patterns 242 and multiple lower wiring vias 244 included in the lower wiring structure 240 is increased, and the contact resistance is reduced. Furthermore, since the first lower pattern (M1-2) and the second lower pattern (M2-2) function as etching stop films during the process of forming the through-hole VH, an etching process with a high etching selectivity ratio can be performed to form the through-hole VH, thereby improving the reliability of the manufacturing process for forming the image sensor package 1.

[0048] Figures 5 to 12 are cross-sectional views illustrating a method for manufacturing an image sensor package according to an embodiment of the present invention. Figures 5 to 12 show the manufacturing method of the image sensor package 1 shown in Figures 1 to 4, and the image sensor package 1 shown in Figures 1 to 4 is shown inverted from the result in Figures 5 to 16.

[0049] Referring to Figure 5, the dam structure 310 is attached to the glass plate 300. The glass plate 300 includes multiple chip regions CR and scribe lane regions SR interposed between the multiple chip regions CR. Each of the multiple chip regions CR of the glass plate 300 corresponds to the glass plate 300 included in the image sensor package 1 shown in Figure 1. The dam structure 310 adheres to multiple chip regions CR adjacent to the scribedane region SR within the glass plate 300. In one embodiment, the dam structure 310 is attached to the glass plate 300 so as to extend along the edges of each of the multiple chip regions CR. For example, the dam structure 310 has a rectangular ring shape in plan view.

[0050] Referring to Figure 6, the first substrate portion 100, which has the second substrate portion 200 laminated on it, is attached to the glass plate 300 to which the dam structure 310 is attached. The first substrate section 100 and the second substrate section 200 are laminated using a metal-oxide hybrid bonding method. Referring to Figure 7, a portion of the second substrate 210 is removed to form a trench TR. The trench portion TR is formed by removing a portion of the upper side of the second substrate 210 that corresponds to the scribe lane region SR and the portion of the multiple chip regions CR adjacent to the scribe lane region SR. Referring to Figure 8, a portion of the second substrate 210 is removed from the bottom surface of the trench TR to form multiple through holes VH. The trench section TR and the multiple through-holes VH all penetrate the second substrate 210. Each of the multiple through-holes VH is further extended into the lower wiring structure 240, as shown in Figure 3.

[0051] Referring to Figure 9, a first passivation layer 270 is formed to cover the upper surface of the second substrate 210, the inner surface of the trench portion TR, the inner surface of the multiple through holes VH, and the upper surface of the lower wiring structure 240 that is exposed on the bottom surface of the multiple through holes VH. The first passivation layer 270 is formed to conformally cover the upper surface of the lower wiring structure 240 that is exposed on the upper surface of the second substrate 210, the inner surface of the trench portion TR, the inner surface of the multiple through holes VH, and the bottom surface of the multiple through holes VH. The first passivation layer 270 is formed to consist of, for example, an oxide, a nitride, an oxynitride, or a combination thereof. In one embodiment, the first passivation layer 270 is formed to consist of a layered structure of hafnium oxide, silicon nitride, and hafnium oxide. For example, the first passivation layer 270 is formed to have a thickness of approximately 100 μm to approximately 300 μm.

[0052] Referring to Figure 10, at least a portion of the first passivation layer 270 covering the upper surface of the lower wiring structure 240 exposed at the bottom surface of the multiple through holes VH is removed to expose the lower wiring structure 240. Then, a lower electrode layer 280 is formed that covers the first passivation layer 270 and is in contact with a portion of the upper surface of the lower wiring structure 240 exposed at the bottom surface of the multiple through holes VH. The lower electrode layer 280 is formed from, for example, a metallic substance such as titanium, titanium nitride, tantalum, tantalum nitride, titanium tungsten, tungsten, aluminum, cobalt, nickel, or copper, or an alloy containing such a substance. In one embodiment, the lower electrode layer 280 is formed by a CVD process or an ALD process. For example, the lower electrode layer 280 is formed to have a thickness of approximately 2 μm to approximately 4 μm.

[0053] Referring to Figure 11, a second passivation layer 290 is formed to cover the lower electrode layer 280. The second passivation layer 290 is formed from an insulating material such as silicon oxide or silicon nitride. In one embodiment, the second passivation layer 290 is formed to contain TEOS (Tetraethyl orthosilicate) or PE-TEOS (plasma-enhanced-TEOS). The second passivation layer 290 is formed to cover the lower electrode layer 280, fill the through-hole VH, and fill at least a portion of the trench section TR.

[0054] Referring to Figure 12, a portion of the second passivation layer 290 is removed to form a contact pad 250. For example, the region in which the second passivation layer 290 is removed is the region in which the second passivation layer 290 overlaps the lower electrode layer 280 in the direction perpendicular to the Z direction. In one embodiment, a portion of the second passivation layer 290 is removed, and a portion of the lower electrode layer 280 is exposed. In one embodiment, a photomask is used to form the contact pad 250. A photomask with a pattern drawn on it is placed on the upper surface of the second passivation layer 290. The photomask is designed to have a variety of patterns to adjust the shape and width of multiple contact pads 250. In one embodiment, the area where the second passivation layer 290 is removed is the same size as the contact pad 250. Subsequently, the contact pad 250 and the second passivation layer 290 are planarized through a planarization process. The planarization process ensures that the upper surface of the contact pad 250 and the upper surface of the second passivation layer 290 are on the same plane. The planarization process is carried out, for example, by a CMP (Chemical Mechanical Polishing) process.

[0055] Referring to Figure 13, a third passivation layer 295 is formed to cover the upper surface of the second passivation layer 290 and the upper surface of the contact pad 250. The third passivation layer 295 is formed to conformally cover the second passivation layer 290 and the contact pad 250. The third passivation layer 295 is formed to fill the through-hole VH and at least a portion of the trench section TR. In one embodiment, the third passivation layer 295 is made of the same material as the second passivation layer 290. The third passivation layer 295 is formed from an insulating material such as silicon oxide or silicon nitride. In one embodiment, the third passivation layer 295 is formed using a photosensitive resin such as PID (Photo-Imageable Dielectric) or photosolder resist.

[0056] Referring to Figure 14, a portion of the third passivation layer 295 is removed to form a conductive capping layer 260. For example, the region in which the third passivation layer 295 is removed is the region in which the third passivation layer 295 overlaps with the lower electrode layer 280 and the contact pad 250 in the perpendicular direction (Z direction). In one embodiment, a portion of the third passivation layer 295 is removed, and a portion of the contact pad 250 is exposed. In one embodiment, a photomask is used to form a conductive capping layer 260. A photomask with a pattern drawn on it is placed on the upper surface of the third passivation layer 295. The photomask is designed to have a variety of patterns in order to adjust the shape and width of the multiple conductive capping layers 260. The conductive capping layer 260 is formed from a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), or solder, but is not limited to these.

[0057] Referring to Figure 15, multiple connection terminals 400 are formed on the conductive capping layer 260. The connector terminal 400 uses a conductive material, such as a low-melting-point alloy like Sn-Al-Cu. The image sensor package 1 is connected to an external circuit via connection terminal 400. As a result, the connection terminal 400 is electrically connected to the conductive capping layer 260, the contact pad 250, and the lower electrode layer 280.

[0058] Referring to Figure 16, multiple image sensor packages are formed using a sawing process. Specifically, a portion of the second substrate 200, the first substrate 100, and the glass plate 300 are removed along the scribe lane region SR, and multiple chip regions CR are separated from each other to form multiple image sensor packages 1. The manufacturing method for the image sensor package 1 according to the present invention allows for the formation of through-holes VH by performing an etching process with a high etching selectivity ratio, thereby improving the reliability of the manufacturing process. The manufacturing method of the image sensor package 1 according to the present invention allows for adjustment of the portion where the contact pad 250 and the conductive capping layer 260 are connected to the lower electrode layer, thereby improving the reliability of the image sensor package 1. The manufacturing method for the image sensor package 1 according to the present invention allows for diverse adjustments of the shape and width of the contact pad 250 and the conductive capping layer 260, thereby improving the reliability of each image sensor package 1.

[0059] Figure 17 is a block diagram showing a schematic configuration of an image sensor package according to an embodiment of the present invention. Referring to Figure 17, the image sensor package 1100 includes a pixel array 1110, a controller 1130, a raw driver 1120, and a pixel signal processing unit 1140. The image sensor 1100 includes at least one of the image sensor packages 1 described in Figures 1 to 4.

[0060] The pixel array 1110 includes a plurality of unit pixels arranged in two dimensions, and each unit pixel includes a photoelectric conversion element. The photoelectric conversion element absorbs light to generate an electric charge, and the electrical signal (output voltage) corresponding to the generated charge is supplied to the pixel signal processing unit 1140 via a vertical signal line. Each unit pixel in the pixel array 1110 receives an output voltage one at a time in row units, thereby activating all unit pixels belonging to a single row of the pixel array 1110 simultaneously by the selection signal output by the row driver 1120. The unit pixels belonging to the selected row supply an output voltage corresponding to the absorbed light to the output line of the corresponding column.

[0061] The controller 1130 controls the low driver 1120 so that the pixel array 1110 absorbs light and accumulates charge, or temporarily holds the accumulated charge and outputs an electrical signal corresponding to the accumulated charge to the outside of the pixel array 1110. Furthermore, the controller 1130 controls the pixel signal processing unit 1140 to measure the output voltage supplied by the pixel array 1110. The pixel signal processing unit 1140 includes a correlated duplex sampler (CDS) 1142, an analog-to-digital converter (ADC) 1144, and a buffer 1146. The correlated dual sampler 1142 samples and holds the output voltage supplied from the pixel array 1110. The correlated dual sampler 1142 samples a level corresponding to a specific noise level and the generated output voltage twice, and outputs a level corresponding to the difference between them. Furthermore, the correlated dual sampler 1142 receives the input of the ramp signal generated by the ramp signal generator 1148, compares it, and outputs the comparison result.

[0062] The analog-to-digital converter 1144 converts the analog signal corresponding to the level received from the correlated duplex sampler 1142 into a digital signal. Buffer 1146 latches the digital signal, and the latched signal is sequentially output to the outside of the image sensor package 1100 and transmitted to an image processor (not shown). In one embodiment, the pixel array 1110 is arranged on the first substrate portion 100, for example, the sensor portion 120, which is included in the image sensor package 1 described in Figures 1 to 16. In one embodiment, at least a portion of the low driver 1120, controller 1130, and pixel signal processing unit 1140 are arranged on the second substrate 200 included in the image sensor package 1 described in Figures 1 to 16.

[0063] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of Symbols]

[0064] 100 First substrate section 110 First board 120 Sensor section 122 Photodiode region 124-well area 126 Photoelectric Conversion Region 130 Pixel element isolation film 132 Insulating Liner 134 Embedded conductive layer 140 Upper wiring structure 142 Upper wiring pattern 144 Upper wiring via 146 Upper interlayer insulating film 152 Cover insulation layer 154 Front Passivation Layer 156 Guide Patterns 158 color filter layers 160 Microlenses 162 Organic layer 164 Inorganic layer 200 Second substrate part 210 Second board 240 Lower wiring structure 242 Lower wiring pattern 244 Lower wiring via 246 Lower interlayer insulating film 250 Contact pad 260 Conductive capping layer 262 Base section 264 Connecting part 266 Peripheral area 270 First Passivation Layer 280 Lower electrode layer 282 Through electrode section 284 Rear wiring section 290 Second Passivation Layer 292 First embedded section 294 First backside passivation section 295 Third Passivation Layer 296 Second embedded section 298 Second backside passivation section 300 Glass Plates 310 Dam Structure 400 connection terminals BP bonding pad BP1, BP2 (1st, 2nd) bonding pads BVS through electrode structure FD floating diffusion region M1-1~M6-1 (1st to 6th) Upper Pattern M1-2~M8-2 (1st~8th) Lower Pattern STI device isolation membrane TG Transfer Gate TR Trench Section VH through hole

Claims

1. A first substrate having a first surface and a second surface facing the first surface, and including a sensor section on which a plurality of active pixels are arranged, A second substrate having a third surface and a fourth surface facing the third surface, and having a through hole extending from the fourth surface to the third surface, A wiring layer disposed between the first surface and the third surface, A lower electrode layer including a through electrode portion formed on the through hole and connected to the wiring layer, and a back wiring portion covering a part of the fourth surface, A connection terminal is arranged on the fourth surface and electrically connected to the rear wiring section, The system includes a pad structure interposed between the rear wiring section and the connection terminal, which electrically connects the rear wiring section and the connection terminal. The aforementioned pad structure is A contact pad positioned on the rear wiring section, An image sensor package characterized by including a conductive capping layer disposed in a first direction between the contact pad and the connection terminal, and connected to the contact pad and the connection terminal.

2. The conductive capping layer is A base portion parallel to the upper surface of the contact pad, The image sensor package according to claim 1, characterized in that it includes a peripheral portion that is spaced apart from the base portion in the first direction and parallel to the upper surface of the contact pad, and a connecting portion that connects the base portion and the peripheral portion.

3. The image sensor package according to claim 2, characterized in that the connecting portion forms an acute angle with the upper surface of the contact pad.

4. The image sensor package according to claim 2, characterized in that the peripheral portion has an annular shape surrounding the connection terminal.

5. The image sensor package according to claim 2, characterized in that the base portion and the peripheral portion do not overlap in the first direction.

6. The wiring layer comprises an upper wiring structure arranged on the first surface of the first substrate, The image sensor package according to claim 1, further comprising a lower wiring structure disposed on the third surface of the second substrate and in contact with the upper wiring structure.

7. In the first direction, a first passivation layer is disposed between the lower electrode layer and the connection terminal and is located at the same vertical level as the contact pad, The present invention further comprises a second passivation layer disposed between the first passivation layer and the conductive capping layer in the first direction, The image sensor package according to claim 2, characterized in that the second passivation layer is in contact with the contact pad, the peripheral portion, and the connecting portion.

8. A glass plate disposed on the second surface of the first substrate, The image sensor package according to claim 1, further comprising a dam structure interposed between the glass plate and the first substrate.

9. A first substrate having a first surface and a second surface facing the first surface, and including a sensor section on which a plurality of active pixels are arranged, An upper wiring structure arranged on the first surface, A second substrate having a third surface and a fourth surface facing the third surface, a trench portion extending inward from the fourth surface, and a through hole extending from the bottom surface of the trench portion to the third surface, A lower wiring structure is arranged on the third surface and is in contact with the upper wiring structure, The lower electrode layer includes the inner wall and bottom surface of the through hole, a through electrode portion extending into the lower wiring structure and connected to a part of the lower wiring structure, and a back wiring portion covering a part of the fourth surface, A plurality of connection terminals are arranged on the fourth surface and electrically connected to the rear wiring section, The pad structure is interposed between the rear wiring section and the plurality of connection terminals, and electrically connects the rear wiring section and the plurality of connection terminals. The aforementioned pad structure is Multiple contact pads arranged on the rear wiring section, An image sensor package characterized by including a plurality of conductive capping layers disposed on the plurality of contact pads, with a portion of each layer separated from the plurality of contact pads.

10. A first substrate having a first surface and a second surface facing the first surface, and including a sensor section on which a plurality of active pixels are arranged, A glass plate disposed on the second surface of the first substrate, A dam structure interposed between the glass plate and the first substrate, having an outer surface aligned perpendicularly to the side surface of the glass plate, An upper wiring structure disposed on the first surface of the first substrate, including a plurality of upper wiring patterns and a stacked structure of a plurality of upper wiring vias, A second substrate having a third surface and a fourth surface facing the third surface, including a trench portion extending inward from the fourth surface and a through hole extending from the bottom surface of the trench portion to the third surface, A lower wiring structure is disposed on the third surface of the second substrate, in contact with the upper wiring structure, and includes a plurality of lower wiring patterns and a stacked structure of a plurality of lower wiring vias. The inner wall of the trench portion, the inner wall of the through hole, and the first passivation layer covering the fourth surface of the second substrate, A lower electrode layer comprising: a through electrode portion on the first passivation layer that covers the inner wall and bottom surface of the through hole and extends into the lower wiring structure and is connected to a portion of the plurality of lower wiring patterns; and a back wiring portion that is electrically connected to the through electrode portion and is arranged on the portion of the first passivation layer that covers the fourth surface of the second substrate; A second passivation layer having a plurality of first openings that cover a portion of the lower electrode layer and expose the lower electrode layer, A contact pad is placed in the first opening and electrically connected to the lower electrode layer, A third passivation layer covering the second passivation layer and including a plurality of second openings that expose a portion of the contact pad, A conductive capping layer, a portion of which is positioned in the second opening and electrically connected to the contact pad, An image sensor package characterized by comprising a conductive capping layer, a back surface wiring section, a contact pad, and a plurality of connection terminals electrically connected to the conductive capping layer.

Images