Laser diode device

Abstract

The system detects abnormalities in the laser beam pulse width early during use and safely switches off the power supply to the laser diode. [Solution] The laser diode device comprises a laser diode that outputs laser light based on a pulse signal, a power supply unit that supplies power to the laser diode, a detection unit that outputs a logic signal indicating whether the pulse width corresponding to the pulse signal is normal or abnormal, and a control unit that instructs the power supply unit to stop supplying power to the laser diode based on the logic signal.

Description

Technical Field

[0001] The present disclosure relates to a laser diode device.

Background Art

[0002] Patent Document 1 discloses a clock abnormality detection circuit including a one-cycle delay means for delaying a test clock by one cycle, a clock comparison means for comparing the test clock with the output of the one-cycle delay means and outputting an output only during a mismatch period when there is a mismatch, and an abnormality detection means for outputting an abnormality detection signal when the mismatch period exceeds a predetermined allowable range. This clock abnormality detection circuit is used particularly for detecting abnormalities in a clock used inside a CPU or a synchronous clock supplied to an external interface device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In view of the above-described conventional circumstances, the present disclosure has been devised, and an object thereof is to provide a laser diode device that can early detect an abnormality in the pulse width of laser light during use and safely turn off the power supply to the laser diode.

Means for Solving the Problems

[0005] The present disclosure provides a laser diode device including a laser diode that outputs laser light based on a pulse signal, a power supply unit that supplies power to the laser diode, a detection unit that outputs a logic signal indicating a normal or abnormal state of the pulse width corresponding to the pulse signal, and a control unit that instructs the power supply unit to stop supplying power to the laser diode based on the logic signal. [Effects of the Invention]

[0006] According to this disclosure, abnormalities in the pulse width of the laser beam can be detected early during use, and the power supply to the laser diode can be safely turned off. [Brief explanation of the drawing]

[0007] [Figure 1] Block diagram showing an example configuration of a laser diode device according to Embodiment 1. [Figure 2] Circuit diagram showing an example configuration of the LD voltage detection circuit according to Embodiment 1. [Figure 3] (a) A diagram showing the first pattern example of logic signals to the input terminals and logic signals from the output terminals of a logic circuit, (b) A diagram showing the second pattern example of logic signals to the input terminals and logic signals from the output terminals of a logic circuit, (c) A diagram showing the third pattern example of logic signals to the input terminals and logic signals from the output terminals of a logic circuit, (d) A diagram showing the fourth pattern example of logic signals to the input terminals and logic signals from the output terminals of a logic circuit. [Figure 4] This figure shows the first example of outputting a logic signal (H) from a logic circuit. [Figure 5] This figure shows a second example of outputting a logic signal (H) from a logic circuit. [Figure 6] This diagram shows an example of outputting a logic signal that instructs the latch circuit to stop supplying power. [Figure 7] Block diagram showing an example configuration of a laser diode device according to Embodiment 2. [Figure 8] Circuit diagram showing an example configuration of the LD current detection circuit according to Embodiment 2. [Modes for carrying out the invention]

[0008] (Background leading to this disclosure) According to the configuration of Patent Document 1, a delay of at least one cycle is required to detect whether or not there is an abnormality in the clock under test. In other words, since it is not possible to detect whether or not there is an abnormality in the clock under test until a delay of at least one cycle has been waited, there was room for improvement in detecting the presence or absence of abnormalities in the clock under test at an early stage.

[0009] Furthermore, safety standards are set for laser diodes, and there is a demand to set the light intensity to Class 1, which is the safest, when using them. Even in the event of a laser diode malfunction (for example, a malfunction in the Laser Diode (LD) driver circuit), it is necessary to adhere to Class 1. However, conventional technologies, including Patent Document 1, have not provided a method for adhering to Class 1 even in the event of a laser diode malfunction.

[0010] Therefore, the following embodiment describes an example of a laser diode that detects abnormalities in the laser pulse width early during use and safely turns off the power supply to the laser diode.

[0011] Hereinafter, embodiments specifically disclosing the laser diode apparatus according to this disclosure will be described in detail, with reference to the drawings as appropriate. However, unnecessarily detailed explanations may be omitted. For example, detailed explanations of already well-known matters or redundant explanations of substantially identical configurations may be omitted. This is to avoid the following explanation becoming unnecessarily verbose and to facilitate understanding by those skilled in the art. The accompanying drawings and the following explanation are provided to enable those skilled in the art to fully understand this disclosure and are not intended to limit the subject matter described in the claims.

[0012] (Embodiment 1) 1. Configuration of the laser diode device First, an example of a laser diode device according to Embodiment 1 will be described with reference to Figures 1 and 2. Figure 1 is a block diagram showing an example configuration of the laser diode device 1 according to Embodiment 1. Figure 2 is a circuit diagram showing an example configuration of the LD voltage detection circuit 13 according to Embodiment 1. As shown in Figure 1, the laser diode device 1 includes an LD driver circuit 10, a laser diode 11, an LD power supply circuit 12, an LD voltage detection circuit 13, a delay circuit 14, a logic circuit 15, a latch circuit 16, and a control microcontroller 20. Note that the control microcontroller 20 may be configured separately from the laser diode device 1.

[0013] The LD driver circuit 10 includes an Auto Power Control (APC) circuit 10a and a switch 10b. The LD driver circuit 10 controls the output of laser light from the laser diode 11 based on an LD pulse signal (see below) from the control microcontroller 20. In other words, the laser diode device 1 according to Embodiment 1 outputs laser light using a pulse-driven method based on the LD pulse signal.

[0014] The APC circuit 10a acquires an LD pulse signal from the control microcontroller 20 to output laser light according to a predetermined duty cycle. Based on the LD pulse signal, the APC circuit 10a generates a control signal to control the switch 10b and inputs it to the switch 10b, thereby driving the output of laser light from the laser diode 11.

[0015] Switch 10b has a transistor Q1 whose source is connected to ground (GND), which is at a reference potential. Switch 10b switches the output of the laser beam from the laser diode 11 by inputting a control signal from the APC circuit 10a, based on the LD pulse signal, to the gate of transistor Q1.

[0016] The laser diode 11 includes a Laser Diode (LD) as a light emitting element and a Photo Diode (PD) as a light receiving element. In FIG. 2, the illustration of the PD of the laser diode 11 is omitted. As described above, in the laser diode 11, safety standards are generally provided to prevent injury to users. For example, a laser diode positioned in Class1 (Class 1) is required to be used within a range of light amounts such that it is judged to be safe even when direct beam internal observation is performed for a long time or when an observation optical instrument (for example, a loupe or binoculars) is used at that time. For example, the maximum light amount power is within 7 mW. Although it is desired to output the maximum light amount within the range in which the laser diode 11 is classified as Class1, there are so-called individual differences in the LD which is the light emitting element constituting the laser diode 11, and the current value corresponding to the maximum light amount within the range classified as Class1 also varies depending on the individual.

[0017] Here, in the use of Class1, when the wavelength of the laser light is set, according to the product of the power of the light amount and the irradiation time, when one of the power and the irradiation time fluctuates, the other also fluctuates. For example, when the wavelength of the laser light is 650 nm, if the pulse width corresponding to the irradiation on-section of the laser light of the LD pulse signal is 50 μS, the maximum light amount is 4.1 mW. On the other hand, if the pulse width is 100 μS, the maximum light amount is 3.5 mW. Therefore, if any abnormality occurs in the LD driver circuit or the laser diode and the pulse width set to be a certain reference value fluctuates widely (in other words, increases), compliance with Class1 cannot be achieved. Therefore, the laser diode device 1 according to Embodiment 1 monitors the fluctuation of the pulse width corresponding to the LD pulse signal during the use of the laser diode 11, and when it detects that an abnormality has occurred such that the pulse width exceeds the reference value, immediately stops the output of the laser light.

[0018] The LD power supply circuit 12 is an example of a power supply unit and supplies the power necessary for the operation of the laser diode 11. The LD power supply circuit 12 includes a transistor Q2 which is a Pch field effect transistor and a transistor Q3 which is an Nch field effect transistor. The LD power supply circuit 12 uses the transistors Q2 and Q3 to switch on and off the power supply to the laser diode 11. For example, when a power supply of 5V is applied, 5V is applied to the gate of the transistor Q3 via a resistor R9 and the transistor Q3 turns on. When the transistor Q3 turns on, it becomes connected to the ground (GND) via a resistor R7 to the gate of the transistor Q2 and the transistor Q2 also turns on. Thereby, power is supplied to the laser diode 11.

[0019] Also, when the LD power supply circuit 12 obtains a logic signal (to be described later) instructing the stop of the power supply from the output terminal 2 of the latch circuit 16 due to an abnormality occurring in the LD driver circuit 10 or the laser diode 11, it stops the power supply to the laser diode 11 based on that logic signal. That is, in this case, since the logic signal (L) from the latch circuit 16 is applied to the gate of the transistor Q3, the transistor Q3 turns off. When the transistor Q3 turns off, the gate of the transistor Q2 becomes 5V via a resistor R6 and the transistor Q2 also turns off. Thereby, the power supply to the laser diode 11 is stopped and the output of the laser light is forcibly stopped.

[0020] The LD voltage detection circuit 13 is an example of a detection unit and generates a logic signal (L or H) indicating the normal or abnormal state of the pulse width corresponding to the LD pulse signal, and outputs it to the delay circuit 14 and the logic circuit 15, respectively. For example, a logic signal (L: Low) indicates an abnormal pulse width, and a logic signal (H: High) indicates a normal pulse width, but this is just an example, and H and L may be reversed. For example, when the LD voltage detection circuit 13 detects that the voltage applied between the cathode side of the laser diode 11 and the LD driver circuit 10 is smaller than a reference voltage corresponding to a preset reference value for pulse width, it generates a logic signal (L: Low) indicating an abnormal pulse width and outputs it to the delay circuit 14 and the logic circuit 15, respectively.

[0021] For example, when power (e.g., 5V) is supplied from the LD power supply circuit 12, 5V is applied to the anode side of LD1, which is the LD of the laser diode 11. When an LD pulse signal is input to the LD driver circuit 10 from the control microcontroller 20, transistor Q1 turns on. This causes current to flow through LD1 of the laser diode 11. At this time, a voltage drop occurs on the cathode side of LD1. The comparator IC1 provided in the LD voltage detection circuit 13 is, for example, a non-inverting type, and when the voltage on the cathode side of LD1 falls below a preset reference voltage, it outputs a logic signal from 5V (H) to 0V (L) from the output terminal (OUT) to the delay circuit 14 and the logic circuit 15, respectively.

[0022] Here, the logic signal L, which is the output of comparator IC1, indicates a state where the voltage on the cathode side of LD1 of the laser diode 11 is lower than a preset reference voltage due to the voltage drop caused by current flowing through LD1 to the cathode side. On the other hand, the logic signal H, which is the output of comparator IC1, indicates a state where the voltage on the cathode side of LD1 is not lower than a preset reference voltage. The reference voltage is, for example, the midpoint between the voltage on the cathode side of LD1 when current flows through LD1 and the voltage on the cathode side of LD1 when no current flows through LD1, and is preset as the reference voltage for comparator IC1. In other words, the voltage between the cathode side of LD1 and the terminal on the LD1 side of the LD driver circuit 10 is used for comparison with the reference voltage at comparator IC1. This makes it possible to convert the time during which current flows through LD1 into L (i.e., Low) and H (i.e., High) waveforms.

[0023] The delay circuit 14 is an example of a control unit and is composed of an IC chip IC2 having an input terminal 1, an output terminal 2, and a control terminal 3. The control terminal 3 is connected to ground (GND) via a resistor R10. The input terminal 1 is connected to the output terminal (OUT) of the comparator IC1. The output terminal 2 is connected to the input terminal 1 of the logic circuit 15. The delay circuit 14 delays the logic signal (L or H) from the LD voltage detection circuit 13 by a predetermined delay time and outputs it to the logic circuit 15. The delay time in the delay circuit 14 can be adjusted by the resistance value of resistor R10. The delay circuit 14 delays the signal input to input terminal 1 (specifically, the logic signal from the LD voltage detection circuit 13) by the delay time and outputs it to the logic circuit 15 from output terminal 2.

[0024] The logic circuit 15 is an example of a control unit and is composed of an IC chip IC3 having input terminals 1 and 2 and an output terminal 3. Input terminal 1 is connected to the output terminal (OUT) of comparator IC1. Input terminal 2 is connected to the output terminal 2 of delay circuit 14. Output terminal 3 is connected to input terminal 1 of latch circuit 16. The logic circuit 15 receives a logic signal (L or H) from LD voltage detection circuit 13 and a logic signal (L or H) delayed by delay circuit 14, and outputs a logic signal (L or H) corresponding to the logical AND of the two logic signals to latch circuit 16. Specifically, the logic circuit 15 receives the logic signal from LD voltage detection circuit 13 from input terminal 1, the logic signal from delay circuit 14 from input terminal 2, and outputs a logic signal corresponding to the logical AND to latch circuit 16 from output terminal 3. Details of the operation of the logic circuit 15 will be described later with reference to Figures 3(a) to (d), 4 and 5.

[0025] Here, the operation of the logic circuit 15 will be explained in detail with reference to Figures 3(a) to 3(d). Figure 3(a) shows an example of the first pattern of logic signals to input terminals 1 and 2 of the logic circuit 15 and logic signals from output terminal 3, Figure 3(b) shows an example of the second pattern of logic signals to input terminals 1 and 2 of the logic circuit 15 and logic signals from output terminal 3, Figure 3(c) shows an example of the third pattern of logic signals to input terminals 1 and 2 of the logic circuit 15 and logic signals from output terminal 3, and Figure 3(d) shows an example of the fourth pattern of logic signals to input terminals 1 and 2 of the logic circuit 15 and logic signals from output terminal 3.

[0026] In this embodiment, Figure 3(a) is used as an example for explanation, but any of the patterns in Figures 3(b) to (d) may be used. As shown in Figure 3(a), when a logic signal (L: 0V) is input to input terminals 1 and 2 of the logic circuit 15, the logic circuit 15 outputs a logic signal (H: 5V) from output terminal 3. On the other hand, when no logic signal (L: 0V) is input to both input terminals 1 and 2 of the logic circuit 15, the logic circuit 15 outputs a logic signal (L: 0V) from output terminal 3 as a steady state. In other words, when the logic signal (L) directly input to the logic circuit 15 without going through the delay circuit 14 and the logic signal (L) delayed by the delay circuit 14 and input to the logic circuit 15 are in the same state (logic signal (L)), the abnormal state logic signal (H) is output from output terminal 3 from the steady state logic signal (L).

[0027] In the example shown in Figure 3(b), if the logic signal (L) input directly to the logic circuit 15 without passing through the delay circuit 14 and the logic signal (L) input to the logic circuit 15 after being delayed by the delay circuit 14 are in the same state (logic signal (L)), then the logic signal (L) in an abnormal state will be output from the output terminal 3, changing from the steady-state logic signal (H). In the example shown in Figure 3(c), if the logic signal (H) input directly to the logic circuit 15 without passing through the delay circuit 14 and the logic signal (H) input to the logic circuit 15 after being delayed by the delay circuit 14 are in the same state (logic signal (H)), then the logic signal (L) of the abnormal state will be output from the output terminal 3, instead of the logic signal (H) of the steady state. In the example shown in Figure 3(d), if the logic signal (H) input directly to the logic circuit 15 without passing through the delay circuit 14 and the logic signal (H) input to the logic circuit 15 after being delayed by the delay circuit 14 are in the same state (logic signal (H)), then the logic signal (H) of the abnormal state will be output from the output terminal 3, changing from the logic signal (L) of the steady state.

[0028] In Figure 3(a), the comparator IC1 in Figure 2 is a non-inverting type, and the comparator IC1 outputs a logic signal from 5V(H) to 0V(L) when the voltage on the cathode side of LD1 falls below a preset reference voltage. There are a total of four possible combinations depending on whether the comparator is non-inverting or inverting, and whether 5V(H) or 0V(L) is used when the voltage on the cathode side of LD1 falls below a preset reference voltage. Therefore, four patterns are provided as shown in Figures 3(a) to (d).

[0029] The latch circuit 16 is an example of a control unit and is composed of an IC chip IC4 having an input terminal 1, an output terminal 2, and a control terminal 3. Input terminal 1 is connected to output terminal 3 of the logic circuit 15. Output terminal 2 is connected to the gate of transistor Q3 of the LD power supply circuit 12. Control terminal 3 is connected to the control microcontroller 20. The latch circuit 16 receives a logic signal (L or H) from the logic circuit 15 and, if the input logic signal is "H" (i.e., an abnormal pulse width has occurred), generates a logic signal "L" (i.e., the abnormal pulse width continues) and outputs it to the LD power supply circuit 12.

[0030] Here, with reference to Figure 6, the operation of the latch circuit 16 will be explained in detail. Figure 6 shows an example of the latch circuit 16 outputting a logic signal to instruct the cessation of power supply. As shown in Figure 6, when the logic signal input to input terminal 1 is "L" (steady state), the latch circuit 16 outputs a logic signal (H) from output terminal 2. However, when the logic signal input to input terminal 1 is "H" (abnormal state), the latch circuit 16 outputs a logic signal (L) from output terminal 2 and continues in this state of logic signal (L) (abnormal state). When the latch circuit 16 receives a pulse signal for latch release from the control microcontroller 20 via control terminal 3, it releases the state of logic signal (L) and outputs a logic signal (H) from output terminal 2.

[0031] The control microcontroller 20 controls the operation of the pulse-driven laser diode 11, specifically generating an LD pulse signal to output laser light according to a predetermined duty cycle and outputting it to the LD driver circuit 10. After any abnormality in the LD driver circuit 10 or the laser diode 11 is repaired, the control microcontroller 20 generates a latch release pulse signal to release the output state of the logic signal (L) in the latch circuit 16 and outputs it to the latch circuit 16.

[0032] 2. Details of Logic Circuit Operation Next, the operation of the logic circuit 15 will be described in detail with reference to Figures 4 and 5. Figure 4 shows a first example in which the logic circuit 15 outputs a logic signal (H). Figure 5 shows a second example in which the logic circuit 15 outputs a logic signal (H).

[0033] In the example shown in Figure 4, the delay time in the delay circuit 14 is set to 15 μS (microseconds). This delay time is the limit of the output time at which it can be determined that the laser light from the laser diode 11 is being output normally based on the LD pulse signal. In other words, if the output time of the laser light output based on a single LD pulse signal exceeds this delay time, some kind of abnormality has occurred in the laser diode device 1.

[0034] As shown in Figure 4, when the delay time is set to 15 μS, if the output time of the laser light of the LD pulse signal changes from 10 μS → 15 μS → 20 μS, the output of the logic circuit 15 changes when the output time exceeds 15 μS. Specifically, when the output time of the laser light of the LD pulse signal exceeds 15 μS, both the logic signal input to input terminal 1 of the logic circuit 15 and the logic signal input to input terminal 2 of the logic circuit 15 become "L". Therefore, as shown in Figure 3(a), the logic circuit 15 outputs a logic signal (H) from output terminal 3, indicating an abnormal state where the laser light is being output beyond the delay time.

[0035] In a steady state where no abnormal conditions occur, when the control microcontroller 20 outputs an LD pulse signal, the LD driver circuit 10 controls switch 10b to allow current to flow to the LD of the laser diode 11 only for the correct interval (e.g., 10 μS) based on the LD pulse signal. In other words, laser light is output only for a fixed time interval of 10 μS. However, if the LD driver circuit 10 fails, for example, too much current will flow to the LD of the laser diode 11 beyond the pulse interval specified by the LD pulse signal (10 μS → 15 μS → 20 μS). In addition to the failure of the LD driver circuit 10, it is also possible that the control microcontroller 20 has failed, causing it to output an LD pulse signal specifying an interval (e.g., 20 μS) that exceeds the delay time (e.g., 15 μS), even though it was outputting an LD pulse signal specifying the correct interval (e.g., 10 μS).

[0036] In this way, the logic circuit 15 can detect when laser light has been output based on an LD pulse signal that specifies a section exceeding the delay time (e.g., 15 μS). This makes it possible to detect the presence or absence of an abnormality in the laser diode device 1 early, without waiting for the duration of one cycle of the LD pulse signal and without going through the control microcontroller 20.

[0037] In the example shown in Figure 5, the delay time in the delay circuit 14 is set to 20 μS (microseconds). This delay time is the limit of the output time at which it can be determined that the laser light from the laser diode 11 is being output normally based on the LD pulse signal. In other words, if the output time of the laser light output based on a single LD pulse signal exceeds this delay time, some kind of abnormality has occurred in the laser diode device 1.

[0038] As shown in Figure 5, when the delay time is set to 20 μS, if the output time of the laser light of the LD pulse signal changes from 10 μS → 15 μS → 20 μS → 25 μS, the output of the logic circuit 15 changes when the output time exceeds 20 μS. Specifically, when the output time of the laser light of the LD pulse signal exceeds 20 μS, both the logic signal input to input terminal 1 of the logic circuit 15 and the logic signal input to input terminal 2 of the logic circuit 15 become "L". Therefore, as shown in Figure 3(a), the logic circuit 15 outputs a logic signal (H) from output terminal 3 indicating an abnormal state in which the laser light is being output beyond the delay time.

[0039] In a steady state where no abnormal conditions occur, when the control microcontroller 20 outputs an LD pulse signal, the LD driver circuit 10 controls switch 10b to allow current to flow to the LD of the laser diode 11 only for the correct interval based on the LD pulse signal. In other words, laser light is output only for a fixed time interval of 10 μS. However, if the LD driver circuit 10 fails, for example, it will gradually over-current the LD of the laser diode 11 beyond the pulse interval specified by the LD pulse signal (10 μS → 15 μS → 20 μS → 25 μS). In addition to the failure of the LD driver circuit 10, it is also possible that the control microcontroller 20 has failed, causing it to output an LD pulse signal specifying an interval (e.g., 25 μS) that exceeds the delay time (e.g., 20 μS), even though it was outputting an LD pulse signal specifying the correct interval (e.g., 10 μS).

[0040] In this way, the logic circuit 15 can detect when laser light has been output based on an LD pulse signal that specifies a section exceeding the delay time (e.g., 20 μS). This makes it possible to detect the presence or absence of an abnormality in the laser diode device 1 early on, without waiting for the duration of one cycle of the LD pulse signal and without going through the control microcontroller 20.

[0041] (Embodiment 2) 3. Configuration of the laser diode device Next, an example of a laser diode device according to Embodiment 2 will be described with reference to Figures 7 and 8. Figure 7 is a block diagram showing an example configuration of the laser diode device 1A according to Embodiment 2. Figure 8 is a circuit diagram showing an example configuration of the LD current detection circuit 17 according to Embodiment 2. As shown in Figure 7, the laser diode device 1A includes an LD driver circuit 10, a laser diode 11, an LD power supply circuit 12, an LD current detection circuit 17, a delay circuit 14, a logic circuit 15, a latch circuit 16, and a control microcontroller 20. The control microcontroller 20 may be configured separately from the laser diode device 1A. In the following description, if the configuration is the same as that according to Embodiment 1, the same reference numerals will be used to simplify or omit the explanation, and different content will be described.

[0042] The LD current detection circuit 17 is an example of a detection unit. It generates a logic signal (L or H) indicating the normal or abnormal state of the pulse width corresponding to the LD pulse signal and outputs it to the delay circuit 14 and the logic circuit 15, respectively. For example, a logic signal (L: Low) indicates an abnormal pulse width, and a logic signal (H: High) indicates a normal pulse width, but this is just an example, and H and L may be reversed. The LD current detection circuit 17, for example, converts the current flowing to the anode side of the laser diode 11 into a voltage. When it detects that the converted voltage is smaller than a reference voltage corresponding to a preset reference value for pulse width, it generates a logic signal (L: Low) indicating an abnormal pulse width and outputs it to the delay circuit 14 and the logic circuit 15, respectively.

[0043] For example, when power (e.g., 5V) is supplied from the LD power supply circuit 12, 5V is applied to the anode side of LD1, which is the LD of the laser diode 11. When an LD pulse signal is input to the LD driver circuit 10 from the control microcontroller 20, transistor Q1 turns on. As a result, current flows through LD1 of the laser diode 11. At this time, current flows through resistor R11 of the LD current detection circuit 17, and the current flowing through the anode side of the laser diode 11 is amplified and converted into a voltage by the current-voltage converter IC5 provided in the LD current detection circuit 17. The comparator IC1 provided in the LD current detection circuit 17 is, for example, an inverting type, and when the input voltage of the comparator IC1 (see Vout in Figure 8) becomes higher than a preset reference voltage, it outputs a logic signal from 5V (H) to 0V (L) from the output terminal (OUT) of the delay circuit 14 and the logic circuit 15, respectively.

[0044] The input voltage Vout can be expressed by the following formula. Vout=(R3 / R12)×LD current×R11 In other words, when LD current flows, the input voltage Vout rises. Therefore, the time during which current flows to the anode side of the laser diode 11 to such an extent that the input voltage Vout is higher than the reference voltage is converted into an L (Low) or H (High) waveform. The process of stopping the power supply to the laser diode 11 after the LD current detection circuit 17 generates a logic signal (L) is the same as in Embodiment 1, so the following explanation will be omitted.

[0045] (Note) Based on the descriptions of the embodiments described above, the following technologies are disclosed.

[0046] (Item 1) The laser diode device relating to this disclosure is A laser diode (11) that outputs laser light based on a pulse signal, The power supply unit (LD power supply circuit 12) that supplies power to the laser diode, A detection unit (LD voltage detection circuit 13, LD current detection circuit 17) outputs a logic signal indicating whether the pulse width corresponding to the pulse signal is normal or abnormal, The system includes a control unit (delay circuit 14, logic circuit 15, latch circuit 16) that instructs the power supply unit to stop supplying power to the laser diode based on the logic signal, Laser diode device. This allows the laser diode device to detect abnormalities in the pulse width of the laser beam early during use and safely switch off the power to the laser diode.

[0047] (Item 2) The system further includes a drive unit (LD driver circuit 10) that controls the output of the laser light from the laser diode based on the pulse signal, The detection unit outputs the logic signal indicating an abnormality in pulse width when it detects that the voltage applied between the cathode side of the laser diode and the drive unit is smaller than the reference voltage corresponding to the reference value. The laser diode device described in item 1. As a result, the laser diode device can detect that the voltage between the cathode side of the laser diode and the drive unit is lower than a reference voltage corresponding to a reference value, and can stop the output of the laser diode early.

[0048] (Item 3) The aforementioned reference voltage is the value between the first voltage on the cathode side when current flows from the power supply unit to the laser diode and the second voltage on the cathode side when no current flows from the power supply unit to the laser diode. Laser diode device as described in item 1 or 2 As a result, with the laser diode device, it is possible to determine when the laser diode output has stopped by simply comparing the voltage applied between the cathode side of the laser diode and the drive unit with a reference voltage.

[0049] (Item 4) The control unit is composed of a delay circuit (14), a logic circuit (15), and a latch circuit (16). The logic circuit outputs a logic signal indicating an abnormal pulse width to the latch circuit when the first state (L or H) indicated by the logic signal from the detection unit and the second state (L or H) indicated by the signal after the logic signal has been delayed by the delay circuit are the same. The latch circuit, based on the logic signal from the logic circuit indicating an abnormality in the pulse width, instructs the power supply unit to stop supplying power to the laser diode. A laser diode device as described in any one of items 1 to 3. As a result, the laser diode device can stop the output of the laser diode quickly and with a simple configuration, without the need for a control microcontroller.

[0050] (Item 5) The latch circuit further includes a microcontroller (control microcontroller 20) that outputs a signal indicating the release of the instruction to stop the power supply to the laser diode. The laser diode device described in item 4. This makes it possible to easily resume power supply from the control microcontroller to the laser diode after maintenance or other procedures have been performed to restore the abnormal condition of the laser diode device.

[0051] (Item 6) The detection unit detects whether the voltage based on the current flowing on the anode side of the laser diode is greater than a reference voltage corresponding to a reference value. The laser diode device described in item 1. As a result, the laser diode device can detect that the voltage based on the current flowing on the anode side of the laser diode is greater than the reference voltage corresponding to the reference value, and can therefore stop the output of the laser diode early.

[0052] While embodiments have been described above with reference to the attached drawings, this disclosure is not limited to such examples. It is clear to those skilled in the art that various modifications, alterations, substitutions, additions, deletions, and equivalents can be conceived within the scope of the claims, and these are also understood to fall within the technical scope of this disclosure. Furthermore, the components of the embodiments described above can be combined in any way without departing from the spirit of the invention. [Industrial applicability]

[0053] This disclosure is useful as a laser diode device that can detect abnormalities in the pulse width of the laser beam at an early stage during use and safely turn off the power supply to the laser diode. [Explanation of symbols]

[0054] 1. Laser diode device 1A Laser Diode Device 10 LD driver circuit 10a APC circuit 10b switch 11 Laser Diode 12 LD power supply circuit 13 LD voltage detection circuit 14 Delay Circuit 15 Logic Circuits 16. Latch Circuit 17 LD current detection circuit 20 Control microcontroller

Claims

1. A laser diode that outputs laser light based on a pulse signal, A power supply unit that supplies power to the laser diode, A detection unit that outputs a logic signal indicating whether the pulse width corresponding to the pulse signal is normal or abnormal, The system includes a control unit that instructs the power supply unit to stop supplying power to the laser diode based on the aforementioned logic signal, Laser diode device.

2. The system further comprises a drive unit that controls the output of the laser light from the laser diode based on the pulse signal, The detection unit outputs the logic signal indicating an abnormality in pulse width when it detects that the voltage applied between the cathode side of the laser diode and the drive unit is smaller than the reference voltage corresponding to the reference value. The laser diode apparatus according to claim 1.

3. The reference voltage is the value between the first voltage on the cathode side when current flows from the power supply unit to the laser diode and the second voltage on the cathode side when no current flows from the power supply unit to the laser diode. The laser diode apparatus according to claim 2.

4. The control unit is composed of a delay circuit, a logic circuit, and a latch circuit. The logic circuit outputs a logic signal indicating an abnormal pulse width to the latch circuit when the first state indicated by the logic signal from the detection unit and the second state indicated by the signal after the logic signal has been delayed by the delay circuit are the same. The latch circuit, based on the logic signal from the logic circuit indicating an abnormality in the pulse width, instructs the power supply unit to stop supplying power to the laser diode. The laser diode apparatus according to claim 2.

5. The latch circuit further comprises a microcontroller that outputs a signal indicating the release of the instruction to stop the power supply to the laser diode. The laser diode apparatus according to claim 4.

6. The detection unit detects whether the voltage based on the current flowing on the anode side of the laser diode is smaller than a reference voltage corresponding to a reference value. The laser diode apparatus according to claim 1.

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