Storage device and operating method for controlling low-power mode entry delay

Abstract

This invention provides a storage device and its operating method that can improve performance and optimize power consumption by controlling the timing of entry into a low-power mode. [Solution] The storage device 100 includes a memory 110 and a controller 120. The controller determines whether to activate one or more of a plurality of low-power mode delay techniques according to the set power mode. The controller receives setting information regarding the power mode from the host HOST, sets the power mode based on the received setting information, and determines whether to activate the first low-power mode delay technique LOW_PWR_DELAY_1, the second low-power mode delay technique LOW_PWR_DELAY_2, and the third low-power mode delay technique LOW_PWR_DELAY_3.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a storage device for controlling the low-power mode entry delay and an operating method thereof.

[0002] (Cross-reference to related applications) This application claims priority based on 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2024-0197841, filed on December 27, 2024, the entire contents of which are incorporated herein by reference.

Background Art

[0003] A storage device is a device that stores data based on requests from a computer, a mobile terminal such as a smartphone or a tablet, or an external device such as various electronic devices.

[0004] The storage device may further include a controller for controlling a memory (e.g., volatile memory / non-volatile memory), and this controller receives a command from an external device as an input, and based on the received command, executes or controls operations for reading, writing, or erasing data on the memory included in the storage device.

[0005] The storage device can enter the low-power mode in a specific situation to reduce power consumption. However, when entering the low-power mode, the performance of the storage device may decrease, so when performance improvement is required, the storage device can delay entering the low-power mode.

Summary of the Invention

Problems to be Solved by the Invention

[0006] Embodiments of this disclosure can provide a storage device and a method of operating the same that can improve performance and optimize power consumption by controlling the timing of entry into a low-power mode.

[0007] The problems of the embodiments of this disclosure are not limited to those mentioned herein, and further problems not mentioned herein will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] Embodiments of the present disclosure can provide a storage device including a memory for storing data; and a controller that controls the memory for input and output of data and determines whether to activate one or more of a plurality of low-power mode delay techniques according to a set power mode.

[0009] Embodiments of this disclosure can provide a method for operating a storage device, which includes the steps of: receiving configuration information relating to a power mode; and determining whether to activate one or more of a plurality of low-power mode delay techniques according to the power mode. [Effects of the Invention]

[0010] In embodiments of the present disclosure, when controlling the low-power mode entry operation of a storage device that processes data, the storage device can determine whether or not there is a delay in the low-power mode entry operation based on at least one of the following: the history of receiving low-power mode entry requests received from an external source, the history of when the storage device entered low-power mode after satisfying the low-power mode entry conditions, and the history of receiving commands received from an external source.

[0011] The effects of the embodiments of this disclosure are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims. [Brief explanation of the drawing]

[0012] The content of the present disclosure will be more fully understood from the following detailed description and the accompanying drawings. The detailed description and the accompanying drawings are provided for illustrative purposes only and do not limit the content of the present disclosure.

[0013] [Figure 1] It is a schematic configuration diagram of a storage device according to the present disclosure.

[0014] [Figure 2] It is a block diagram schematically showing the memory of FIG. 1.

[0015] [Figure 3] It is a diagram showing a schematic structure of a storage device according to the present disclosure.

[0016] [Figure 4] It is a diagram showing the power mode of a storage device according to the present disclosure.

[0017] [Figure 5] It is a diagram showing an example of a first low power mode delay technique according to the present disclosure.

[0018] [Figure 6] It is a diagram showing another example of a first low power mode delay technique according to the present disclosure.

[0019] [Figure 7] It is a diagram showing yet another example of a first low power mode delay technique according to the present disclosure.

[0020] [Figure 8] It is a diagram showing an example of a second low power mode delay technique according to the present disclosure.

[0021] [Figure 9] It is a diagram showing another example of a second low power mode delay technique according to the present disclosure.

[0022] [Figure 10]This figure shows an example of a third low-power mode delay technique as disclosed herein.

[0023] [Figure 11] This figure shows another example of the third low-power mode delay technique as disclosed herein.

[0024] [Figure 12] This figure shows the operation method of the storage device according to this disclosure. [Modes for carrying out the invention]

[0025] Hereinafter, some embodiments of this disclosure will be described in detail with reference to illustrative drawings. In assigning reference numerals to components in each drawing, the same reference numeral may be used for the same component whenever possible, even if it is shown in other drawings. In describing this disclosure, if it is determined that a specific description of a relevant known configuration or function would obscure the gist of this disclosure, such detailed description will be omitted. Where the terms “includes,” “has,” “consists of,” etc., used herein, other parts may be added unless “only” is used. When a component is expressed singularly, it may include multiple components unless otherwise explicitly stated.

[0026] Furthermore, in describing the components of this disclosure, terms such as 1, 2, A, B, (a), (b), etc., may be used. These terms are used solely to distinguish a component from other components, and do not limit the nature, order, sequence, or number of such components.

[0027] In descriptions of the positional relationships of components, when it is stated that two or more components are “linked,” “joined,” or “connected,” it should be understood that while two or more components can be directly “linked,” “joined,” or “connected,” it is also possible for two or more components to be further “interposed” with other components before being “linked,” “joined,” or “connected.” Here, the other components may be included in one or more of the two or more components that are “linked,” “joined,” or “connected” to each other.

[0028] In descriptions of temporal relationships concerning constituent elements, operating methods, or manufacturing methods, when temporal order or sequential relationships are described using phrases such as "after," "following," "next," or "before," unless "immediately" or "directly" is used, this can include cases that are not continuous.

[0029] On the other hand, if numerical values ​​or corresponding information (e.g., levels) relating to components are mentioned, even without further explicit mention, these numerical values ​​or corresponding information may be interpreted as including a range of errors that can occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0030] Various embodiments of this disclosure will be described in detail below with reference to the attached drawings.

[0031] Figure 1 is a schematic diagram of the storage device according to this disclosure.

[0032] Referring to Figure 1, the storage device 100 according to the embodiment of this disclosure may include a memory 110 for storing data and a controller 120 for controlling the memory 110.

[0033] The memory 110 includes multiple memory blocks and operates in response to the control of the controller 120. The operation of the memory 110 may include, for example, read operations, program operations (also called "write operations"), and erase operations.

[0034] Memory 110 may include a memory cell array containing multiple memory cells (also simply called "cells") that store data. Such a memory cell array may reside within a memory block.

[0035] For example, memory 110 can be implemented in various types, such as NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM®), or spin-transfer torque random access memory (STT-RAM).

[0036] On the other hand, the memory 110 can be implemented as a three-dimensional array structure. Embodiments of this disclosure can be applied not only to flash memory in which the charge storage layer is composed of a conductive floating gate, but also to charge trap flash (CTF) in which the charge storage layer is composed of an insulating film.

[0037] The memory 110 receives commands and addresses from the controller 120 and can access the memory cell array selected by the address. In other words, the memory 110 can execute the operation instructed by the command on the memory cell array selected by the address.

[0038] For example, memory 110 can perform programming, reading, and erasing operations. Specifically, when programming, memory 110 can program data into the area selected by the address. When reading, memory 110 can read data from the area selected by the address. When erasing, memory 110 can erase data stored in the area selected by the address.

[0039] The controller 120 can control write (program), read, erase, and background operations to the memory 110. Background operations may include, for example, one or more of the following: garbage collection (GC), wear leveling (WL), read reclaim (RR), or bad block management (BBM) operations.

[0040] The controller 120 can control the operation of the memory 110 in response to a request from a device located outside the storage device 100 (for example, a host). On the other hand, the controller 120 can also control the operation of the memory 110 regardless of the host's request.

[0041] A host is a computer, UMPC (Ultra Mobile PC), workstation, PDA (Personal Digital Assistant), tablet, mobile phone, smartphone, e-book, PMP (portable multimedia player), portable game console, navigation device, black box, digital camera, DMB (Digital Multimedia Broadcasting) player, smart television, digital audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, storage that makes up a data center, one of the various electronic devices that make up a home network, one of the various electronic devices that make up a computer network, one of the various electronic devices that make up a telematics network, RFID (radio frequency identification) The host may be an identification device, a mobile device that operates under human control or is capable of autonomous operation (e.g., a vehicle, robot, or drone). Alternatively, the host may be a virtual reality (VR) device that provides two-dimensional or three-dimensional virtual reality images, or an augmented reality (AR) device that provides augmented reality images. The host may also be any of the various electronic devices that require a storage device 100 capable of storing data.

[0042] The host may include at least one operating system (OS). The operating system can manage and control the functions and operations of the host overall, and can control the interaction between the host and the storage device 100. Depending on the mobility of the host, the operating system can be classified into a general-purpose operating system and a mobile operating system.

[0043] On the other hand, the controller 120 and the host HOST may be separate devices. In some cases, the controller 120 and the host HOST may be integrated and implemented in a single device. For the sake of explanation, the following description will assume that the controller 120 and the host HOST are separate devices.

[0044] Referring to Figure 1, the controller 120 may include a memory interface 122 and a control circuit 123, and may further include a host interface 121, etc.

[0045] The host interface 121 provides an interface for communication with the host HOST. Exemplarily, the host interface 121 provides an interface using at least one of various interface protocols, such as USB (Universal Serial Bus) protocol, MMC (multimedia card) protocol, PCI (peripheral component interconnection) protocol, PCI-E (PCI-express) protocol, ATA (Advanced Technology Attachment) protocol, Serial-ATA protocol, Parallel-ATA protocol, SCSI (small computer small interface) protocol, ESDI (enhanced small disk interface) protocol, SMBus (System Management Bus) protocol, I2C (Inter-Integrated Circuit) protocol, I3C (Improved Inter-Integrated Circuit) protocol, and IDE (Integrated Drive Electronics) protocol, and private protocol.

[0046] When the control circuit 123 receives a command from the host HOST, it can receive the command via the host interface 121 and perform the operation of processing the received command.

[0047] The memory interface 122 is connected to the memory 110 and can provide an interface for communication with the memory 110. That is, the memory interface 122 can be configured to provide an interface between the memory 110 and the controller 120 in response to the control of the control circuit 123.

[0048] The control circuit 123 controls the operation of the memory 110 by performing the overall control operation of the controller 120. For this purpose, as an example, the control circuit 123 may include one or more of the following: a processor 124, a working memory 125, etc., and may selectively include an error detection and correction circuit (ECC Circuit, 126), etc.

[0049] The processor 124 can control the various operations of the controller 120 and execute logical operations. The processor 124 can communicate with the host HOST via the host interface 121 and with the memory 110 via the memory interface 122.

[0050] Processor 124 can perform the logical operations necessary to execute the functions of the Flash Translation Layer (FTL). Processor 124 can perform logical operations to convert logical block addresses (LBAs) provided by the host to physical block addresses (PBAs) via the Flash Translation Layer (FTL). The Flash Translation Layer (FTL) can accept logical block addresses (LBAs) as input and convert them to physical block addresses (PBAs) using a mapping table.

[0051] There are various address mapping methods for the flash translation layer, depending on the mapping unit. Representative address mapping methods include the page mapping method, the block mapping method, and the hybrid mapping method.

[0052] The processor 124 can randomize data received from the host HOST. For example, the processor 124 can randomize data received from the host HOST using a configured randomizing seed. The randomized data is provided to the memory 110 and can be programmed into the memory cell array of the memory 110.

[0053] The processor 124 can derandomize data received from memory 110 during a read operation. For example, the processor 124 can derandomize data received from memory 110 using a derandomizing seed. The derandomized data can then be output to the host HOST.

[0054] The processor 124 can control the operation of the controller 120 by executing firmware. In other words, the processor 124 can execute (drive) firmware loaded into the working memory 125 at boot time in order to control the various operations of the controller 120 and perform logical operations. The operation of the storage device 100 described below in the embodiments of this disclosure can be realized by the processor 124 executing firmware in which such operation is defined.

[0055] Firmware is a program that runs within the storage device 100 to drive the storage device 100, and can include various functional layers. For example, firmware may include binary data that defines the code for executing each of the aforementioned functional layers.

[0056] For example, the firmware may include one or more of the following: a Flash Translation Layer (FTL) that performs a translation function between the logical address requested from the host HOST to the storage device 100 and the physical address of the memory 110; a Host Interface Layer (HIL) that analyzes commands requested from the host HOST to the storage device 10 and transmits them to the Flash Translation Layer (FTL); and a Flash Interface Layer (FIL) that transmits commands instructed by the Flash Translation Layer (FTL) to the memory 110.

[0057] Such firmware can be loaded into working memory 125 from memory 110 or a separate non-volatile memory located outside of memory 110 (e.g., ROM, NOR Flash). When the processor 124 performs a boot operation after power-on, it can first load all or part of the firmware into working memory 125.

[0058] The processor 124 can execute logical operations defined in the firmware loaded into the working memory 125 in order to control the operations of the controller 120. The processor 124 can store the results of executing the logical operations defined in the firmware into the working memory 125. The processor 124 can control the controller 120 to generate commands or signals according to the results of executing the logical operations defined in the firmware. If the part of the firmware in which the logical operations to be executed are defined is stored in memory 110 but not loaded into working memory 125, the processor 124 can generate an event (e.g., an interrupt) to load that part of the firmware from memory 110 into working memory 125.

[0059] On the other hand, the processor 124 can load metadata necessary to drive the firmware from memory 110. Metadata is data for managing memory 110 and may include management information for user data stored in memory 110.

[0060] On the other hand, the firmware can be updated while the storage device 100 is being manufactured or while the storage device 100 is running. The controller 120 can download new firmware from outside the storage device 100 and update the existing firmware to the new firmware.

[0061] The working memory 125 can store firmware, program code, commands, or data necessary to drive the controller 120. Such working memory 125 may, for example, include one or more volatile memories such as SRAM (Static RAM), DRAM (Dynamic RAM), and SDRAM (Synchronous DRAM). Alternatively, the controller 120 may use additional volatile memories (e.g., SRAM, DRAM, SDRAM) located outside the controller 120, in addition to the working memory 125.

[0062] The error detection and correction circuit 126 can detect error bits in the target data using an error correction code and correct the detected error bits. Here, the target data may be, for example, data stored in the working memory 125, or data read from the memory 110.

[0063] The error detection and correction circuit 126 may be implemented to decode the data using an error correction code. The error detection and correction circuit 126 may be implemented using various code decoders. For example, a decoder that performs unstructured code decoding or a decoder that performs structured code decoding may be used.

[0064] For example, the error detection and correction circuit 126 can detect error bits in sector units set for each read data. That is, each read data can consist of multiple sectors. A sector can mean a data unit smaller than a page, which is the reading unit of flash memory. The sectors that make up each read data can correspond to each other via addresses.

[0065] The error detection and correction circuit 126 can calculate the bit error rate (BER) and determine whether a sector can be corrected. For example, if the bit error rate BER is higher than a set reference value, the error detection and correction circuit 126 can determine that the sector is uncorrectable or fail. On the other hand, if the bit error rate BER is lower than the reference value, the circuit can determine that the sector can be corrected or pass.

[0066] The error detection and correction circuit 126 can sequentially perform error detection and correction operations for all read data. If a sector included in the read data is correctable, the error detection and correction circuit 126 can omit the error detection and correction operation for that sector for the next read data. In this way, once the error detection and correction operations for all read data are completed, the error detection and correction circuit 126 can detect the last sector that has been determined to be uncorrectable. There may be one or more sectors that have been determined to be uncorrectable. The error detection and correction circuit 126 can transmit information (e.g., address information) about the sector that has been determined to be uncorrectable to the processor 124.

[0067] Bus 127 may be configured to provide channels between components 121, 122, 124, 125, and 126 of the controller 120. Such a bus 127 may, for example, include a control bus for transmitting various control signals, commands, etc., and a data bus for transmitting various data, etc.

[0068] On the other hand, some of the aforementioned components 121, 122, 124, 125, and 126 of the controller 120 may be deleted, or some of the aforementioned components 121, 122, 124, 125, and 126 of the controller 120 may be merged into one. In some cases, one or more other components may be added to the aforementioned components of the controller 120.

[0069] Below, we will describe memory 110 in more detail with reference to Figure 2.

[0070] Figure 2 is a block diagram schematically showing the memory in Figure 1.

[0071] Referring to Figure 2, the memory 110 according to the embodiment of the present disclosure may include a memory cell array 210, an address decoder 220, a read and write circuit 230, a control logic 24, and a voltage generation circuit 250, among others.

[0072] The memory cell array 210 can contain multiple memory blocks BLK1 to BLKz (where z is a natural number greater than or equal to 2).

[0073] Multiple memory blocks BLK1 to BLKz may contain multiple word lines WL and multiple bit lines BL, and multiple memory cells MC may be arranged within them.

[0074] Multiple memory blocks BLK1 to BLKz may be connected to the address decoder 220 via multiple word lines WL. Multiple memory blocks BLK1 to BLKz may be connected to the read and write circuit 230 via multiple bit lines BL.

[0075] Each of the multiple memory blocks BLK1 to BLKz can contain multiple memory cells. For example, the multiple memory cells may be non-volatile memory cells and may consist of non-volatile memory cells having a vertical channel structure.

[0076] The memory cell array 210 may consist of a two-dimensional memory cell array, or, in some cases, a three-dimensional memory cell array.

[0077] On the other hand, each of the multiple memory cells included in the memory cell array 210 can store at least one bit of data. For example, each of the multiple memory cells included in the memory cell array 210 may be a single-level cell (SLC) that stores one bit of data. Another example is that each of the multiple memory cells included in the memory cell array 210 may be a multi-level cell (MLC) that stores two bits of data. Yet another example is that each of the multiple memory cells included in the memory cell array 210 may be a triple-level cell (TLC) that stores three bits of data. Yet another example is that each of the multiple memory cells included in the memory cell array 210 may be a quad-level cell (QLC) that stores four bits of data. Yet another example is that the memory cell array 210 may include multiple memory cells, each storing five or more bits of data.

[0078] In this case, the number of bits of data stored in each of the multiple memory cells can be determined dynamically. For example, a single-level cell that stores 1 bit of data can be changed to a triple-level cell that stores 3 bits of data.

[0079] Referring to Figure 2, the address recorder 220, read and write circuit 230, control logic 240, and voltage generation circuit 250, etc., can operate as peripheral circuits that drive the memory cell array 210.

[0080] The address decoder 220 may be connected to the memory cell array 210 via multiple word lines WL.

[0081] The address decoder 220 may be configured to operate in response to control from the control logic 240.

[0082] The address decoder 220 can receive addresses via input / output buffers within the memory 110. The address decoder 220 may be configured to decode block addresses from the received addresses. The address decoder 220 can select at least one memory block according to the decoded block address.

[0083] The address decoder 220 can receive a read voltage Vread and a pass voltage Vpass from the voltage generation circuit 250.

[0084] The address decoder 220 can apply a read voltage Vread to the selected word line WL within the selected memory block during a read operation, and apply a pass voltage Vpass to the remaining unselected word lines WL.

[0085] During program verification, the address decoder 220 can apply a verification voltage generated by the voltage generation circuit 250 to the selected word line WL within the selected memory block, and apply a pass voltage Vpass to the remaining unselected word lines WL.

[0086] The address decoder 220 may be configured to decode the column address from the received address. The address decoder 220 can transmit the decoded column address to the read and write circuit 230.

[0087] Read and program operations on memory 110 can be performed on a page-by-page basis. The address received when a read or program operation is requested may include one or more of the block address, row address, and column address.

[0088] The address decoder 220 can select one memory block and one word line depending on the block address and row address. The column address can be provided to the read and write circuit 230 by decoding it with the address decoder 220.

[0089] The address decoder 220 may include one or more of the following: a block decoder, a row decoder, a column decoder, and an address buffer.

[0090] The read and write circuit 230 may include multiple page buffers PB. The read and write circuit 230 can operate as a "read circuit" during a read operation of the memory cell array 210 and as a "write circuit" during a write operation.

[0091] The aforementioned read and write circuit 230 is also called a page buffer circuit or data register circuit, which includes multiple page buffers PB. Here, the read and write circuit 230 may include a data buffer that performs data processing functions, and may further include a cache buffer that performs caching functions.

[0092] Multiple page buffers PB can be connected to the memory cell array 210 via multiple bit lines BL. During read and program verification operations, the multiple page buffers PB can continuously supply sensing current to the bit lines BL connected to the memory cells in order to sense the threshold voltage Vth of the memory cells. They can also sense, via sensing nodes, that the amount of current flowing changes according to the program state of the corresponding memory cells and latch it as sensing data.

[0093] The read and write circuit 230 can operate in response to the page buffer control signal output from the control logic 240.

[0094] During a read operation, the read and write circuit 230 senses data from the memory cell, temporarily stores the read data, and then outputs the data DATA to the input / output buffer of the memory 110. In an exemplary embodiment, the read and write circuit 230 may include a column selection circuit and the like in addition to a page buffer PB or page register.

[0095] The control logic 240 can be connected to an address decoder 220, a read and write circuit 230, a voltage generation circuit 250, and the like. The control logic 240 can receive command CMD and control signal CTRL via the input / output buffer of memory 110.

[0096] The control logic 240 may be configured to control the operations of the memory 110 in response to the control signal CTRL. The control logic 240 can output control signals to adjust the precharge potential levels of the sensing nodes of multiple page buffers PB.

[0097] The control logic 240 can control the read and write circuit 230 to perform read operations on the memory cell array 210. The voltage generation circuit 250 can generate the read voltage Vread and pass voltage Vpass used during read operations in response to the voltage generation circuit control signal output from the control logic 240.

[0098] On the other hand, each of the memory blocks of the aforementioned memory 110 may consist of multiple pages corresponding to multiple word lines WL and multiple strings corresponding to multiple bit lines BL.

[0099] A memory block BLK may have multiple word lines WL and multiple bit lines BL arranged in an intersecting manner. For example, each of the multiple word lines WL may be arranged in the row direction, and each of the multiple bit lines BL may be arranged in the column direction. In another example, each of the multiple word lines WL may be arranged in the column direction, and each of the multiple bit lines BL may be arranged in the row direction.

[0100] A memory cell can be defined that is connected to one of several word lines WL and one of several bit lines BL. A transistor may be placed in each memory cell.

[0101] For example, a transistor placed in a memory cell MC may include a drain, source, and gate. The drain (or source) of a transistor may be connected directly to the bit line BL or via another transistor. The source (or drain) of a transistor may be connected directly to the source line (which may be ground) or via another transistor. The gate of a transistor may include a floating gate surrounded by an insulator and a control gate to which a gate voltage is applied from the word line WL.

[0102] Each memory block may have a first selection line (also called a source selection line or drain selection line) located outside the first outermost word line, which is more adjacent to the read and write circuit 230, of the two outermost word lines. A second selection line (also called a drain selection line or source selection line) may be located outside the other second outermost word line.

[0103] In some cases, one or more dummy word lines may be placed between the first outermost word line and the first selection line. Similarly, one or more dummy word lines may be placed between the second outermost word line and the second selection line.

[0104] The aforementioned memory block read and program (write) operations can be performed on a page-by-page basis, while erase operations can be performed on a memory block basis.

[0105] Figure 3 shows a schematic structure of the storage device 100 according to this disclosure.

[0106] Referring to Figure 3, the storage device 100 can include a memory 110 and a controller 120.

[0107] The memory 110 can store data. The storage device 100 can write data requested by the host HOST to the memory 110 and read data requested by the host HOST from the memory 110.

[0108] The controller 120 can control the memory 110 for data input and output. The controller 120 can decide whether or not to activate one or more of several low-power mode delay techniques according to the set power mode. For example, the controller 120 can decide whether or not to activate the first low-power mode delay technique LOW_PWR_DELAY_1, the second low-power mode delay technique LOW_PWR_DELAY_2, and the third low-power mode delay technique LOW_PWR_DELAY_3.

[0109] The controller 120 can maximize performance by preventing entry into low-power mode at points where performance maximization is required (e.g., performance and benchmark measurement intervals). However, unconditionally preventing entry into low-power mode increases power consumption, leading to an earlier point at which performance throttling occurs to reduce heat generation. This can result in a decrease in average performance.

[0110] Therefore, the controller 120 can selectively apply a low-power mode delay technique depending on the power mode to improve performance when performance improvement is needed by delaying entry into low-power mode, and to optimize power consumption when power consumption reduction is needed by entering low-power mode. The low-power mode delay technique is sometimes called a low-power mode delay method or low-power mode delay policy.

[0111] In the embodiments of this disclosure, the power mode may be set as follows:

[0112] For example, the controller 120 can receive configuration information regarding the power mode from the host HOST. Based on the received configuration information, the controller 120 can set the power mode.

[0113] As another example, the controller 120 can set the power mode based on the amount of power consumed by the storage device 100 and the amount of power supplied to the storage device 100. If the amount of power consumed by the storage device 100 is greater than the amount of power supplied to the storage device 100, the controller 120 can change the power mode to reduce power consumption, and conversely, if the power consumption is greater, it can change the power mode to increase power consumption.

[0114] The first low-power mode delay technique, LOW_PWR_DELAY_1, is a technique that determines whether or not to delay entering low-power mode based on the reception history of low-power mode entry requests received from an external source (e.g., a host). This will be explained in detail below in Figures 5 to 7.

[0115] The second low-power mode delay technique, LOW_PWR_DELAY_2, is a technique that determines whether or not there is a delay in entering low-power mode when the storage device 100 satisfies the conditions for entering low-power mode, independently of the host HOST. This will be explained in detail below in Figures 8 and 9.

[0116] The third low-power mode delay technique, LOW_PWR_DELAY_3, is a technique that determines whether or not there is a delay in entering low-power mode based on the history of commands received from the host HOST. This will be explained in detail in Figures 10 and 11 below.

[0117] Figure 4 shows the power modes of the storage device 100 according to this disclosure.

[0118] Referring to Figure 4, the power mode of the storage device 100 can be one of several candidate power modes CAND_PWR_MODE. For example, the power modes of the storage device 100 can be classified into performance mode 1, performance mode 2, standard mode, power saving mode 1, power saving mode 2, etc.

[0119] In this case, the number of low-power mode delay techniques activated for each candidate power mode (CAND_PWR_MODE) may vary depending on the amount of available power corresponding to each candidate power mode. On the other hand, the amount of available power can be determined as the average power available over a set time interval.

[0120] In embodiments of this disclosure, the number of low-power mode delay techniques activated in a candidate power mode may increase as the amount of power available in the candidate power mode increases.

[0121] In other words, if the amount of power available in the first candidate power mode among multiple candidate power modes CAND_PWR_MODE is greater than the amount of power available in the second candidate power mode among multiple candidate power modes CAND_PWR_MODE, then the number of low-power mode delay techniques activated in the first candidate power mode (for example, the first low-power mode delay technique LOW_PWR_DELAY_1, the second low-power mode delay technique LOW_PWR_DELAY_2, and the third low-power mode delay technique LOW_PWR_DELAY_3) may be greater than the number of techniques activated in the second candidate power mode.

[0122] In Figure 4, the amount of power available in a candidate power mode where only the first low-power mode delay technique, LOW_PWR_DELAY_1, is activated is greater than the amount of power available in a candidate power mode where all low-power mode delay techniques are deactivated.

[0123] Furthermore, the amount of power available in a candidate power mode in which both the first low-power mode delay technique LOW_PWR_DELAY_1 and the second low-power mode delay technique LOW_PWR_DELAY_2 are activated is greater than the amount of power available in a candidate power mode in which only the first low-power mode delay technique LOW_PWR_DELAY_1 is activated.

[0124] Furthermore, the amount of power available in a candidate power mode in which the first low-power mode delay technique LOW_PWR_DELAY_1, the second low-power mode delay technique LOW_PWR_DELAY_2, and the third low-power mode delay technique LOW_PWR_DELAY_3 are activated is greater than the amount of power available in a candidate power mode in which the first low-power mode delay technique LOW_PWR_DELAY_1 and the second low-power mode delay technique LOW_PWR_DELAY_2 are activated.

[0125] Figure 5 shows an example of the first low-power mode delay technique LOW_PWR_DELAY_1 according to this disclosure.

[0126] In embodiments of this disclosure, the first low-power mode delay technique LOW_PWR_DELAY_1 may be a technique that increases a short low-power mode cumulative count SLPCC when a low-power mode entry request LPER is received from the host HOST and the time difference between the current time and the previous low-power mode entry time is less than a first threshold time THR1.

[0127] When the host HOST anticipates entering an idle state, it can send a low-power mode entry request LPER to the storage device 100. In this case, the power consumption and response time of the storage device 100 may change depending on the depth of the low-power mode indicated by the low-power mode entry request LPER.

[0128] The deeper the depth of the low-power mode instructed by the low-power mode entry request LPER, the lower the power consumption of the storage device 100, but the greater the response time.

[0129] On the other hand, the shallower the depth of the low-power mode instructed by the low-power mode entry request LPER, the less the response time of the storage device 100 will be, but the more power it will consume.

[0130] In Figure 5, the storage device 100 can enter low-power mode when it first receives a low-power mode entry request (LPER) from the host HOST. At this time, the value of the short low-power mode cumulative count (SLPCC) may be zero.

[0131] Subsequently, when a low-power mode entry request LPER is received from the host HOST, the time difference between the current time and the previous low-power mode entry time may be less than the first threshold time THR1. At this time, the controller 120 of the storage device 100 can increase the value of the short low-power mode cumulative count SLPCC to 1. After that, the storage device 100 can enter low-power mode.

[0132] In embodiments of this disclosure, the first low-power mode delay technique LOW_PWR_DELAY_1 may be a technique in which, when the low-power mode cumulative count SLPCC becomes greater than or equal to the threshold count THR_CNT for a short period of time, the controller 120 of the storage device 100 delays entry into low-power mode by a set delay time DELAY_TIME.

[0133] A large cumulative count (SLPCC) for short low-power modes indicates that the device has entered low-power mode for a short period of time and then returned to it many times. In this case, although the power consumption reduction effect of the storage device 100 is small, it negatively impacts the performance of the storage device 100.

[0134] Therefore, the controller 120 can prevent situations where the system remains in low-power mode for a short time before returning to normal mode by delaying the entry into low-power mode.

[0135] Delaying the entry into low-power mode by the delay time DELAY_TIME means that during the delay time DELAY_TIME, even if the storage device 100 satisfies the conditions for entering low-power mode, it will not enter low-power mode.

[0136] Therefore, even if the storage device 100 receives a low-power mode entry request LPER from the host HOST, it does not immediately enter low-power mode. Instead, it can enter low-power mode after a delay time DELAY_TIME has elapsed.

[0137] On the other hand, even if the storage device 100 is delayed in entering low-power mode, the controller 120 of the storage device 100 can respond to the low-power mode entry request LPER by sending a response message to the host HOST indicating that the storage device 100 has entered low-power mode.

[0138] In embodiments of this disclosure, the aforementioned first threshold time THR1 may be a preset value, or it may be a value determined based on the average of the time differences between low-power mode entry points during a set time interval.

[0139] Similarly, the threshold count THR_CNT may be a preset value, or it may be a value determined based on the average of the short low-power mode cumulative count SLPCC over a set time interval.

[0140] Figure 6 shows another example of the first low-power mode delay technique LOW_PWR_DELAY_1 according to this disclosure.

[0141] In embodiments of this disclosure, the first low-power mode delay technique LOW_PWR_DELAY_1 may be a technique for reducing the value of a short low-power mode cumulative count SLPCC when the time difference between the current time and the immediately preceding low-power mode entry time is greater than or equal to a first threshold time THR1.

[0142] In Figure 6, when the value of the short low-power mode cumulative count SLPCC is N (where N is a natural number), the time difference between the current time and the time of the previous entry into low-power mode may be greater than or equal to the first threshold time THR1. In this case, the controller 120 of the storage device 100 can reduce the value of the short low-power mode cumulative count SLPCC to (N-1).

[0143] Furthermore, in embodiments of this disclosure, the first low-power mode delay technique LOW_PWR_DELAY_1 may be a technique that initializes the value of a short low-power mode cumulative count SLPCC to a preset value (e.g., 0) when the time difference between the current time and the previous low-power mode entry time is greater than or equal to a second threshold time THR2. In this case, the second threshold time THR2 is longer than the first threshold time THR1.

[0144] In Figure 6, when the value of the short low-power mode cumulative count SLPCC is M (where M is a non-negative integer), the time difference between the current time and the previous low-power mode entry time may be greater than or equal to the second threshold time THR2. In this case, the controller 120 of the storage device 100 can initialize the value of the short low-power mode cumulative count SLPCC to zero.

[0145] Figure 7 shows another example of the first low-power mode delay technique LOW_PWR_DELAY_1 according to this disclosure.

[0146] In embodiments of this disclosure, the first low-power mode delay technique LOW_PWR_DELAY_1 may be a technique that increases the delay time DELAY_TIME when the cumulative delay count DELAY_CNT is greater than or equal to the threshold delay count THR_DELAY_CNT. In this case, the cumulative delay count DELAY_CNT may be the number of times the controller 120 has delayed entering low-power mode during a set time interval.

[0147] In Figure 7, when the storage device 100 receives a low-power mode entry request LPER from the host HOST, the controller 120 can delay the entry into low-power mode by a delay time DELAY_TIME.

[0148] As mentioned above, when the time difference between the current time and the previous time of entering low-power mode is less than the first threshold time THR1, and the short low-power mode cumulative count SLPCC is greater than or equal to the threshold count THR_CNT, the controller 120 can delay the entry into low-power mode by the set delay time DELAY_TI.

[0149] At this time, the controller 120 can compare the cumulative delay count DELAY_CNT, which is the number of delays in entering the low-power mode, with the threshold delay count THR_DELAY_CNT. If the cumulative delay count DELAY_CNT is less than the threshold delay count THR_DELAY_CNT, the controller 120 can set the delay time DELAY_TIME to D1.

[0150] Thereafter, when the storage device 100 receives a low-power mode entry request LPER from the host HOST, the controller 120 can delay the entry into low-power mode by a delay time DELAY_TIME D1.

[0151] At this point, the controller 120 can compare the cumulative delay count DELAY_CNT with the threshold delay count THR_DELAY_CNT again. If the cumulative delay count DELAY_CNT is greater than or equal to the threshold delay count THR_DELAY_CNT, the controller 120 can set the delay time DELAY_TIME to D2. In this case, D2 is greater than D1.

[0152] On the other hand, if the low-power mode delay technique is not activated because the low-power mode entry request LPER is not received from the host HOST during the set threshold time, the controller 120 may decrease or initialize the delay time DELAY_TIME.

[0153] Figure 8 shows an example of the second low-power mode delay technique LOW_PWR_DELAY_2 according to this disclosure.

[0154] In embodiments of the present disclosure, the second low-power mode delay technique LOW_PWR_DELAY_2 may be a technique for recording the time interval between the current time and the time immediately preceding the time when the low-power mode entry condition was met, when the storage device 100 autonomously satisfies the low-power mode entry condition LPEC.

[0155] The controller 120 of the storage device 100 can determine that the low-power mode entry condition LPEC has been satisfied in the following cases:

[0156] For example, the controller 120 can determine that the storage device 100 has autonomously met the low-power mode entry condition LPEC when the duration of the idle state is greater than or equal to the set critical idle time. In this case, the fact that the storage device 100 has remained idle can mean that the bus 127 included in the storage device 100 has remained idle (i.e., a state in which no data is being transferred via the bus 127).

[0157] Furthermore, the second low-power mode delay technique, LOW_PWR_DELAY_2, may be a technique that delays entry into low-power mode when the cumulative count CNT is greater than or equal to the threshold entry count THR_CNT. In this case, the cumulative count CNT may be the number of times during the set first time interval that the aforementioned time interval is less than the threshold time interval THR_TI.

[0158] In Figure 8, when the storage device 100 satisfies the low-power mode entry condition LPEC, the controller 120 of the storage device 100 can compare the time interval between the current time and the time immediately preceding when the low-power mode entry condition was met with the threshold time interval THR_TI.

[0159] If the time interval is less than or equal to the threshold time interval THR_TI, the controller 120 of the storage device 100 does not delay entering low-power mode if the cumulative count CNT is less than the threshold entry count THR_CNT. Therefore, the storage device 100 can enter low-power mode immediately when the low-power mode entry condition LPEC is met.

[0160] Subsequently, when the storage device 100 satisfies the low-power mode entry condition LPEC, the controller 120 of the storage device 100 can again compare the time interval between the current time and the time immediately preceding when the low-power mode entry condition was satisfied with the threshold time interval THR_TI.

[0161] If the time interval is less than or equal to the threshold time interval THR_TI, the controller 120 of the storage device 100 delays entering low-power mode if the cumulative count CNT is greater than or equal to the threshold entry count THR_CNT. Therefore, when the low-power mode entry condition LPEC is met, the storage device 100 does not immediately enter low-power mode, but instead enters low-power mode after the delay time DELAY_TIME has elapsed.

[0162] Figure 9 shows another example of the second low-power mode delay technique LOW_PWR_DELAY_2 according to this disclosure.

[0163] In embodiments of the present disclosure, the second low-power mode delay technique LOW_PWR_DELAY_2 may be a technique that increases the threshold idle time THR_IDLE_TIME, which is used to determine whether the storage device 10 autonomously satisfies the low-power mode entry condition LPEC, when the cumulative delay count DELAY_CNT of delaying entry into low-power mode during a set second time interval is greater than or equal to the threshold delay count THR_DELAY_CNT.

[0164] In Figure 9, if, during the set first time interval, the cumulative number of times CNT where the time interval is less than the threshold time interval THR_TI is greater than or equal to the threshold entry number THR_CNT, the controller 120 can delay entry into low power mode by the delay time DELAY_TIME.

[0165] In this case, if the number of times the entry into low-power mode is delayed (DELAY_CNT) is less than the threshold delay count (THR_DELAY_CNT), the controller 120 can maintain the threshold idle time (THR_IDLE_TIME) as is.

[0166] Subsequently, during the first set time interval, if the cumulative number of times CNT in which the time interval is less than the threshold time interval THR_TI is greater than or equal to the threshold number of times THR_CNT, the controller 120 may again delay the entry into low power mode by the delay time DELAY_TIME.

[0167] At this time, if the number of times DELAY_CNT has been delayed in entering low-power mode is greater than or equal to the threshold delay number THR_DELAY_CNT, the controller 120 can increase the threshold idle time THR_IDLE_TIME. The greater the threshold idle time THR_IDLE_TIME, the less likely the storage device 100 is to autonomously satisfy the low-power mode entry condition LPEC.

[0168] On the other hand, if the storage device 100 remains idle for a reference time, the controller 120 can decrease or reset the threshold idle time THR_IDLE_TIME. In this case, the reference time may be longer than the threshold idle time THR_IDLE_TIME.

[0169] Figure 10 shows an example of the third low-power mode delay technique LOW_PWR_DELAY_3 according to this disclosure.

[0170] In embodiments of this disclosure, the third low-power mode delay technique, LOW_PWR_DELAY_3, may be a technique that delays entry into low-power mode by a set delay time, DELAY_TIME, when a read command or write command is received from the host HOST and the host returns from low-power mode.

[0171] If the host HOST sends a data transfer command (e.g., a read command, a write command) to the storage device 100 while the storage device 100 is in low-power mode, the host HOST is likely to continue transferring data transfer commands to the storage device 100 thereafter. Therefore, the storage device 100 can improve its performance by delaying its entry into low-power mode.

[0172] In Figure 10, when the storage device 100 receives a read or write command from the host HOST and returns from low-power mode, the controller 120 of the storage device 100 can delay entering low-power mode during the delay time DELAY_TIME. That is, the storage device 100 will not enter low-power mode even if the conditions for entering low-power mode are met until the delay time DELAY_TIME has elapsed. In this case, the value of the delay time DELAY_TIME may be D1.

[0173] On the other hand, when the controller 120 receives a read command or write command from the host HOST and returns from low-power mode, it can adjust the value of the delay time DELAY_TIME. For example, when the controller 120 receives a read command or write command from the host HOST while the entry into low-power mode has been delayed, it can increase the value of the delay time DELAY_TIME from D1 to D2.

[0174] Figure 11 shows another example of the third low-power mode delay technique LOW_PWR_DELAY_3 as described herein.

[0175] In embodiments of the present disclosure, the third low-power mode delay technique, LOW_PWR_DELAY_3, may be a technique that initializes the delay time DELAY_TIME when the host returns from low-power mode by receiving a command other than a read or write command (e.g., a device configuration command) from the host HOST.

[0176] In Figure 11, when the controller 120 of the storage device 100 receives the remaining commands from the host HOST, it can reduce the value of the delay time DELAY_TIME from D2 to D1.

[0177] Figure 12 is a diagram showing the operation method of the storage device 100 according to this disclosure.

[0178] Referring to Figure 12, the operation method of the storage device 100 may include step S1210 of receiving setting information regarding the power mode.

[0179] For example, the power mode could be one of several candidate power modes, CAND_PWR_MODE.

[0180] In this case, if the amount of power available in the first candidate power mode among the multiple candidate power modes CAND_PWR_MODE is greater than the amount of power available in the second candidate power mode, the number of low-power mode delay techniques activated in the first candidate power mode among the first low-power mode delay technique LOW_PWR_DELAY_1, the second low-power mode delay technique LOW_PWR_DELAY_2, and the third low-power mode delay technique LOW_PWR_DELAY_3 may be greater than the number of low-power mode delay techniques activated in the second candidate power mode.

[0181] The operation method of the storage device 100 may include step S1220 of determining whether or not to activate a plurality of low-power mode delay techniques (for example, a first low-power mode delay technique LOW_PWR_DELAY_1, a second low-power mode delay technique LOW_PWR_DELAY_2, and a third low-power mode delay technique LOW_PWR_DELAY_3) depending on the power mode.

[0182] The first low-power mode delay technique, LOW_PWR_DELAY_1, may be a technique that determines whether or not there is a delay in entering low-power mode based on the reception history of low-power mode entry requests (LPERs) received from an external source (e.g., host).

[0183] As an example, the first low-power mode delay technique, LOW_PWR_DELAY_1, is a technique in which, when a low-power mode entry request is received from the host HOST, if the time difference between the current time and the previous low-power mode entry time is less than a first threshold time THR1, the short low-power mode cumulative count SLPCC is increased, and when the short low-power mode cumulative count SLPCC becomes equal to or greater than the threshold count THR_CNT, the entry into low-power mode is delayed by a set delay time DELAY_TIME.

[0184] In this case, the first low-power mode delay technique, LOW_PWR_DELAY_1, may be a technique that reduces the short low-power mode cumulative count SLPCC when the time difference between the current time and the previous low-power mode entry time is greater than or equal to the first threshold time THR1.

[0185] In this case, the first low-power mode delay technique, LOW_PWR_DELAY_1, may be a technique that increases the delay time DELAY_TIME when the cumulative number of delays DELAY_CNT, which is the number of delays in entering low-power mode during a set time interval, is equal to or greater than the threshold number of delays THR_DELAY_CNT.

[0186] The second low-power mode delay technique, LOW_PWR_DELAY_2, may be a technique for determining whether or not to delay the entry into low-power mode when the storage device 100 satisfies the conditions for entering low-power mode.

[0187] As an example, the second low-power mode delay technique, LOW_PWR_DELAY_2, is a technique in which, when the storage device 100 autonomously satisfies the low-power mode entry conditions, the time interval between the time when the low-power mode entry conditions are met and the time when the previous low-power mode entry conditions were met is recorded, and the entry into low-power mode is delayed when the cumulative number of times CNT, which is the number of times the time interval is less than the critical time interval THR_TI, is equal to or greater than or equal to the critical entry count THR_CNT during the set first time interval.

[0188] In this case, the low-power mode entry condition can be satisfied when the time the storage device 100 has remained in an idle state is greater than or equal to the set threshold idle time THR_IDLE_TIME. The second low-power mode delay technique LOW_PWR_DELAY_2 is a technique that increases the threshold idle time THR_IDLE_TIME when the cumulative delay count DELAY_CNT, which is the number of times the entry into low-power mode has been delayed during the set second time interval, is greater than or equal to the threshold delay count THR_DELAY_CNT.

[0189] A third low-power mode delay technique, LOW_PWR_DELAY_3, may be a technique that determines whether or not to delay entry into low-power mode based on the history of commands received from the host HOST.

[0190] As an example, the third low-power mode delay technique, LOW_PWR_DELAY_3, may be a technique that delays the entry into low-power mode by a set delay time, DELAY_TIME, when the device returns from low-power mode after receiving a read or write command from the host HOST.

[0191] In this case, the third low-power mode delay technique, LOW_PWR_DELAY_3, may be a technique that initializes the delay time DELAY_TIME when the device returns from low-power mode after receiving a command other than read and write commands from the host HOST.

[0192] The above description is merely illustrative of the technical concept of this disclosure, and any person with ordinary skill in the art to which this disclosure belongs could make various modifications and variations without departing from the essential characteristics of this disclosure. Furthermore, the embodiments of this disclosure are for illustrative purposes only, and not to limit the technical concept of this disclosure, and the scope of the technical concept of this disclosure is not limited by such embodiments.

Claims

1. In storage devices, Memory for storing data; and A storage device including a controller that controls the memory for inputting and outputting the aforementioned data and determines whether or not to activate one or more of a plurality of low-power mode delay techniques according to a set power mode.

2. The aforementioned plurality of low-power mode delay techniques include a first low-power mode delay technique, a second low-power mode delay technique, and a third low-power mode delay technique. The first low-power mode delay technique is a technique that determines whether or not to delay entry into low-power mode based on the reception history of low-power mode entry requests received from an external source. The second low-power mode delay technique is a technique for determining whether or not to delay the entry into low-power mode when the storage device satisfies the conditions for entering low-power mode. The storage device according to claim 1, wherein the third low-power mode delay technique is a technique for determining whether or not to delay entry into low-power mode based on the history of commands received from the host.

3. The storage device according to claim 1, wherein the controller receives setting information regarding the power mode from an external source.

4. The aforementioned power mode is one of several candidate power modes. The storage device according to claim 1, wherein, among the plurality of candidate power modes, if the amount of power available in the first candidate power mode is greater than the amount of power available in the second candidate power mode, the number of low-power mode delay techniques activated in the first candidate power mode among the plurality of low-power mode delay techniques is greater than the number of low-power mode delay techniques activated in the second candidate power mode.

5. The first low-power mode delay technique described above is: When a request to enter low power mode is received from an external source, if the time difference between the current time and the previous low power mode entry time is less than a first threshold time, the short low power mode cumulative count is increased. The storage device according to claim 2, wherein when the cumulative count of the short low-power mode exceeds a threshold count, the entry into the low-power mode is delayed by a set delay time.

6. The storage device according to claim 5, wherein the first low-power mode delay technique is a technique for reducing the cumulative count of the short low-power mode when the time difference between the current time and the immediately preceding time of entry into the low-power mode is greater than or equal to the first threshold time.

7. The first low-power mode delay technique is a technique that initializes the short low-power mode cumulative count when the time difference between the current time and the previous low-power mode entry time is greater than or equal to a second threshold time. The storage device according to claim 6, wherein the second threshold time is longer than the first threshold time.

8. The storage device according to claim 5, wherein the first low-power mode delay technique is a technique that increases the delay time when the cumulative number of delays in entering the low-power mode during a set time interval is equal to or greater than a threshold number of delays.

9. The second low-power mode delay technique described above is: When the storage device autonomously satisfies the conditions for entering low power mode, the time interval between the time the low power mode entry conditions are met and the time the previous low power mode entry conditions were met is recorded. The storage device according to claim 2, which is a technique for delaying entry into low-power mode when, during a set first time interval, the cumulative number of times the time interval is less than a threshold time interval is equal to or greater than the number of threshold entry counts.

10. The controller determines that the storage device has autonomously met the conditions for entering low-power mode if the time the storage device has remained idle is equal to or greater than the set critical idle time. The storage device according to claim 9, wherein the second low-power mode delay technique is a technique to increase the threshold idle time when the cumulative delay count, which is the number of times the entry into low-power mode has been delayed during a set second time interval, is equal to or greater than the threshold delay count.

11. The storage device according to claim 2, wherein the third low-power mode delay technique is a technique that delays entry into low-power mode by a set delay time when the device receives a read command or write command from an external source and returns from low-power mode.

12. The storage device according to claim 11, wherein the third low-power mode delay technique is a technique for initializing the delay time when the device returns from low-power mode by receiving a command other than the read command and the write command from the outside.

13. In the operation method of a storage device, A step of receiving setting information regarding the power mode; and A method for operating a storage device, comprising the step of determining whether or not to activate one or more of a plurality of low-power mode delay techniques depending on the power mode.

14. The aforementioned plurality of low-power mode delay techniques include a first low-power mode delay technique, a second low-power mode delay technique, and a third low-power mode delay technique. The first low-power mode delay technique described above is a technique that determines whether or not to delay entry into low-power mode based on the reception history of low-power mode entry requests received from an external source. The second low-power mode delay technique is a method for determining whether or not to delay the entry into low-power mode when the storage device satisfies the conditions for entering low-power mode. The method for operating a storage device according to claim 13, wherein the third low-power mode delay technique is a technique for determining whether or not to delay entering low-power mode based on the history of commands received from the host.

15. The first low-power mode delay technique described above is: When a request to enter low power mode is received from an external source, if the time difference between the current time and the previous low power mode entry time is less than a first threshold time, the short low power mode cumulative count is increased. The method for operating a storage device according to claim 14, wherein when the cumulative count of the short low-power mode exceeds a threshold count, the entry into the low-power mode is delayed by a set delay time.

16. The method for operating a storage device according to claim 15, wherein the first low-power mode delay technique is a technique for reducing the short low-power mode cumulative count when the time difference between the current time and the previous low-power mode entry time is greater than or equal to the first threshold time.

17. The method for operating a storage device according to claim 15, wherein the first low-power mode delay technique is a technique that increases the delay time when the cumulative number of delays in entering the low-power mode during a set time interval is equal to or greater than a threshold number of delays.

18. The second low-power mode delay technique is, When the storage device autonomously satisfies the conditions for entering low power mode, the time interval between the time the conditions for entering low power mode are met and the time the conditions for entering low power mode were met immediately prior to that time is recorded. A method for operating a storage device according to claim 14, wherein, during a set first time interval, if the cumulative number of times the time interval is less than a threshold time interval is equal to or greater than the number of threshold entry counts, the entry into the low-power mode is delayed.

19. The third low-power mode delay technique is a technique that delays the entry into low-power mode by a set delay time when the device receives a read command or write command from an external source and returns from low-power mode, as described in claim 14.

20. In a storage device that processes data, When controlling the low-power mode entry operation of the storage device, The storage device determines whether or not there is a delay in the low-power mode entry operation based on at least one of the following: the history of receiving low-power mode entry requests received from an external source, the history of the storage device entering low-power mode after satisfying the low-power mode entry conditions, and the history of receiving commands received from an external source.

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