Storage device for controlling low-power mode entry delay and its operation method

Abstract

This disclosure provides a storage device and a method for operating the same for controlling low-power mode entry delay. The storage device includes a memory and a controller. The memory stores data, and the controller determines, based on a power mode, whether to activate one or more of a plurality of low-power mode entry techniques among a plurality of low-power mode delay techniques.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0197841, filed on December 27, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure relate to a storage device and a method of operating the same for controlling low-power mode entry delay. Background Technology

[0004] A storage device is a device used to store data according to requests from external devices such as computers, mobile terminals (e.g., smartphones or tablets).

[0005] The storage device may include a memory for storing data and a controller for controlling the memory. The memory may be volatile or non-volatile. The controller may receive commands from an external device (i.e., a host) and execute or control operations according to the received commands to read, write, or erase data in the memory included in the storage device. Summary of the Invention

[0006] Various embodiments of this disclosure can provide a storage device and a method of operating thereof that can improve performance and optimize power consumption by controlling the timing of entering a low-power mode.

[0007] By referring to the specific implementation methods described below, those skilled in the art can more readily understand the embodiments of this disclosure, but the embodiments should not be construed as limited to those described herein.

[0008] Various embodiments of this disclosure may provide a storage device comprising: a memory for storing data; and a controller communicatively coupled to the memory and configured to control the memory to perform at least one of a plurality of low-power mode delay techniques for inputting or outputting data by determining, based on a power mode, whether to activate one or more of them.

[0009] Various embodiments of this disclosure may provide a method of operating a storage device, the method comprising: receiving information about the power mode of the storage device; and determining, based on the power mode, whether to activate one or more of a plurality of low-power mode delay technologies.

[0010] According to various embodiments of the storage device for processing data disclosed herein, when controlling the storage device to enter a low-power mode operation, the storage device may determine whether to delay the low-power mode entry operation based on at least one of the following: the history of receiving low-power mode entry requests received from the outside, the history of the storage device entering low-power mode by satisfying low-power mode entry conditions, and the history of receiving commands received from the outside.

[0011] The effects of this disclosure can be more clearly understood from the description in the claims, but should not be construed as being limited to the foregoing. Attached Figure Description

[0012] This disclosure will be more readily understood from the detailed embodiments and accompanying drawings provided below. These detailed embodiments and accompanying drawings are provided for illustrative purposes only and are not intended to limit this disclosure.

[0013] Figure 1 This is a schematic configuration diagram of a storage device according to an embodiment of the present disclosure.

[0014] Figure 2 It is shown schematically. Figure 1 A block diagram of the memory.

[0015] Figure 3 This is a schematic configuration diagram of a storage device according to the present disclosure.

[0016] Figure 4 This is a diagram illustrating the power mode of a storage device according to the present disclosure.

[0017] Figure 5 This is a diagram illustrating an example of a first low-power mode delay technique according to the present disclosure.

[0018] Figure 6 This is a diagram illustrating another example of a first low-power mode delay technique according to the present disclosure.

[0019] Figure 7 This is a diagram illustrating another example of a first low-power mode delay technique according to the present disclosure.

[0020] Figure 8 This is a diagram illustrating an example of a second low-power mode delay technique according to the present disclosure.

[0021] Figure 9 This is a diagram illustrating another example of a second low-power mode delay technique according to this disclosure.

[0022] Figure 10 This is a diagram illustrating an example of a third low-power mode delay technique according to this disclosure.

[0023] Figure 11This is a diagram illustrating another example of a third low-power mode delay technique according to this disclosure.

[0024] Figure 12 This is a diagram illustrating a method of operating a storage device according to the present disclosure. Detailed Implementation

[0025] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. When assigning reference numerals to components in each drawing, the same components may be assigned the same reference numerals even if shown in different drawings. Details of known techniques or functions may be omitted when it is determined that such omissions would obscure the subject matter of the disclosure.

[0026] In some situations, a storage device can enter a low-power mode to reduce power consumption. However, entering a low-power mode may lead to a degradation in the storage device's performance. Therefore, if improved performance is required, the storage device can delay entering a low-power mode. Various embodiments of the disclosed technology provide the storage device with techniques for controlling the timing of entering a low-power mode, enabling the storage device to improve performance and optimize power consumption.

[0027] Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0028] Figure 1 This is a schematic configuration diagram of a storage device 100 according to an embodiment of the present disclosure.

[0029] Reference Figure 1 The storage device 100 may include a memory 110 for storing data and a controller 120 for controlling the memory 110.

[0030] The memory 110 includes multiple memory blocks and operates in response to control by the controller 120. Operations of the memory 110 may include, for example, read operations, programming operations (also known as "write operations"), and erase operations.

[0031] The memory 110 may include a memory cell array, which includes a plurality of memory cells (also simply referred to as "cells") for storing data.

[0032] For example, memory 110 can be implemented as various types of memory such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Fourth Generation Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), and / or spin-transfer torque random access memory (STT-RAM).

[0033] The memory 110 can be implemented as a three-dimensional array structure. For example, embodiments of this disclosure can be applied to charge-fetch flash memory (CTF) where the charge storage layer is configured by a dielectric layer and to flash memory where the charge storage layer is configured by a conductive floating gate.

[0034] The memory 110 can receive commands and addresses from the controller 120 and can access the region in the memory cell array selected by the address. In other words, the memory 110 can perform operations instructed by commands on the region selected by the address.

[0035] The memory 110 can perform programming, reading, and erasing operations. For example, when performing a programming operation, the memory 110 can program data into a region selected by an address. When performing a reading operation, the memory 110 can read data from the region selected by an address. In an erasing operation, the memory 110 can erase the data stored in the region selected by an address.

[0036] The controller 120 can control write (programming) operations, read operations, erase operations, and background operations on the memory 110. For example, background operations may include at least one of garbage collection (GC) operations, wear leveling (WL) operations, read reclamation (RR) operations, bad block management (BBM) operations, etc.

[0037] In some embodiments, controller 120 may control the operation of memory 110 based on requests from devices located outside storage device 100 (e.g., a host). In some embodiments, controller 120 may control the operation of memory 110 without regard to host requests.

[0038] As a non-limiting example, the host can be a computer, an ultra-mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a storage device configured for a data center, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, an RFID (Radio Frequency Identification) device, and / or a mobile device capable of driving or driving autonomously under human control (e.g., a vehicle, robot, or drone). In some embodiments, the host can be a virtual reality (VR) device that provides 2D or 3D virtual reality images or an augmented reality (AR) device that provides augmented reality images. The host can be any of various electronic devices that require a storage device 100 capable of storing data.

[0039] The host may include at least one operating system (OS). The operating system typically manages and controls the host's functions and operations, and controls the interoperability between the host and storage device 100. Based on the host's mobility, operating systems can be categorized into general-purpose operating systems and mobile operating systems.

[0040] The controller 120 and the host can be separate devices, or they can be integrated into a single device. For ease of explanation, the controller 120 and the host will be described below as separate devices.

[0041] Reference Figure 1 The controller 120 may include a memory interface 122 and a control circuit 123, and may further include a host interface 121.

[0042] Host interface 121 provides an interface for communicating with a host. For example, host interface 121 provides an interface using at least one of the following interface protocols: USB (Universal Serial Bus) protocol, MMC (Multimedia Card) protocol, PCI (Peripheral Component Interconnect) protocol, PCI-E (High-Speed ​​PCI) protocol, ATA (Advanced Technology Attachment) protocol, Serial ATA protocol, Parallel ATA protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Disk Interface) protocol, IDE (Integrated Drive Electronics) protocol, and / or proprietary protocols.

[0043] When a command is received from the host, the control circuit 123 can receive the command through the host interface 121 and can perform operations to process the received command.

[0044] Memory interface 122 can be coupled to memory 110 to provide an interface for communicating with memory 110. That is, memory interface 122 can be configured to provide an interface between memory 110 and controller 120 in response to control of control circuitry 123.

[0045] Control circuit 123 performs general control operations of controller 120 to control the operation of memory 110. For this purpose, for example, control circuit 123 may include at least one of processor 124 and working memory 125, and may optionally include error detection and correction circuitry (ECC circuitry) 126.

[0046] The processor 124 can control the general operation of the controller 120 and can perform logical calculations. The processor 124 can communicate with the host through the host interface 121 and with the memory 110 through the memory interface 122.

[0047] Processor 124 can perform the logical operations required to execute the functions of the Flash Translation Layer (FTL). Processor 124 can translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs) through the Flash Translation Layer. The Flash Translation Layer can receive logical block addresses and translate them into physical block addresses using a mapping table.

[0048] Depending on the mapping unit, there are various address mapping methods in the flash translation layer. Representative address mapping methods include page mapping, block mapping, and hybrid mapping.

[0049] Processor 124 can randomize data received from the host. For example, processor 124 can randomize data received from the host by using a set randomization seed. The randomized data can be provided to memory 110 and can be programmed into the memory cell array of memory 110.

[0050] During a read operation, processor 124 can derandomize data received from memory 110. For example, processor 124 can derandomize data received from memory 110 using a derandomization seed. The derandomized data can then be output to the host.

[0051] Processor 124 can run firmware to control the operation of controller 120. That is, in order to control the general operation of controller 120 and perform logical calculations, processor 124 can run (drive) firmware loaded into working memory 125 at startup. In the following, the operation of storage device 100 according to embodiments of the present disclosure will be described as implementing processor 124, which runs firmware defining the corresponding operations.

[0052] Firmware, which is a program that runs in storage device 100 to drive storage device 100, may include various functional layers. For example, firmware may include binary data in which code for running functional layers is defined.

[0053] For example, the firmware may include at least one of a flash translation layer, a host interface layer (HIL), and a flash interface layer (FIL). The flash translation layer performs the function of translating the logical address requested by the host to the storage device 100 and the physical address of the memory 110. The host interface layer (HIL) is used to analyze the command requested by the host to the storage device 100, which is a storage device, and transmit the command to the flash translation layer. The flash interface layer (FIL) transmits the command indicated by the flash translation layer to the memory 110.

[0054] This firmware can be loaded into working memory 125 from, for example, memory 110 or a separate non-volatile memory (e.g., ROM or NOR flash memory) located outside memory 110. When running a boot operation after power-on, processor 124 may first load all or part of the firmware into working memory 125.

[0055] Processor 124 can execute logical calculations defined in firmware loaded into working memory 125 to control the general operation of controller 120. Processor 124 can store the results of executing the logical calculations defined in the firmware in working memory 125. Processor 124 can control controller 120 based on the results of executing the logical calculations defined in the firmware, causing controller 120 to generate commands or signals. When a portion of the firmware defining the logical calculation to be executed is stored in memory 110 but not loaded into working memory 125, processor 124 can generate an event (e.g., an interrupt) to load the corresponding portion of the firmware from memory 110 into working memory 125.

[0056] The processor 124 can load the metadata required for the driver firmware from the memory 110. The metadata used to manage the data in the memory 110 may include, for example, management information about the user data stored in the memory 110.

[0057] Firmware can be updated during the manufacture of storage device 100 or during operation of storage device 100. Controller 120 can download new firmware from outside storage device 100 and update existing firmware using the new firmware.

[0058] To drive controller 120, working memory 125 may store necessary firmware, program code, commands, and / or data. Working memory 125 may be a volatile memory including at least one of, for example, SRAM (static RAM), DRAM (dynamic RAM), and / or SDRAM (synchronous DRAM). In some embodiments, in addition to working memory 125, controller 120 may also use a separate volatile memory (e.g., SRAM, DRAM) located external to controller 120.

[0059] The error detection and correction circuit 126 can detect and correct error bits in the target data using error correction codes. The target data can be, for example, data stored in the working memory 125 or data read from the memory 110.

[0060] Error detection and correction circuit 126 can decode data using error correction codes. Error detection and correction circuit 126 can be implemented by various code decoders. For example, a decoder performing non-system code decoding or a decoder performing system code decoding can be used.

[0061] For example, when each read data consists of multiple sectors, the error detection and correction circuit 126 can detect error bits in each of the read data on a sector-by-sector basis. A sector can represent a data unit smaller than a page, where a page is the read unit of flash memory. The sectors that make up each read data can be matched with each other using addresses.

[0062] The error detection and correction circuit 126 can calculate the bit error rate (BER) on a sector-by-sector basis and determine whether an error is correctable. For example, when the bit error rate is higher than a reference value, the error detection and correction circuit 126 can determine that the corresponding sector is uncorrectable or has failed. On the other hand, when the bit error rate is lower than the reference value, the error detection and correction circuit 126 can determine that the corresponding sector is correctable or has passed.

[0063] Error detection and correction circuit 126 can sequentially perform error detection and correction operations on all read data. If a sector in the read data is correctable, error detection and correction circuit 126 can omit the error detection and correction operation for the corresponding sector for the next read data. If error detection and correction operations on all read data are completed in this manner, error detection and correction circuit 126 can detect the last uncorrectable sector in the read data. One or more sectors may be determined to be uncorrectable. Error detection and correction circuit 126 can transmit information about the sectors determined to be uncorrectable (e.g., address information) to processor 124.

[0064] Bus 127 can be configured to provide a channel between components 121, 122, 124, 125, and 126 of controller 120. Bus 127 may include, for example, a control bus for transmitting various control signals, commands, etc., a data bus for transmitting various data, etc.

[0065] Some of the components 121, 122, 124, 125, and 126 of the controller 120 may be omitted, or some of the components 121, 122, 124, 125, and 126 of the controller 120 may be integrated into a single component. In addition to the components 121, 122, 124, 125, and 126 of the controller 120, one or more other components may be added.

[0066] In the following text, reference will be made to Figure 2 The memory 110 is described in more detail.

[0067] Figure 2 It is shown schematically. Figure 1 Block diagram of memory 110.

[0068] Reference Figure 2 The memory 110 according to the embodiments of this disclosure may include a memory cell array 210, an address decoder 220, a read and write circuit 230, a control logic 240, and a voltage generation circuit 250.

[0069] The memory cell array 210 may include multiple memory blocks BLK1 to BLKz (where z is a natural number of 2 or greater).

[0070] Multiple word lines (WL) and bit lines (BL) can be set in multiple memory blocks BLK1 to BLKz, and multiple memory cells can be arranged.

[0071] Multiple memory blocks BLK1 to BLKz can be connected to the address decoder 220 via multiple word lines WL. Multiple memory blocks BLK1 to BLKz can be connected to the read and write circuitry 230 via multiple bit lines BL.

[0072] Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. For example, the multiple memory cells may be non-volatile memory cells and may be configured from non-volatile memory cells with a vertical channel structure.

[0073] The memory cell array 210 can be configured as a two-dimensional memory cell array or as a three-dimensional memory cell array.

[0074] Each of the plurality of memory cells included in the memory cell array 210 can store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 can be a single-level cell (SLC) storing one bit of data. In another example, each of the plurality of memory cells included in the memory cell array 210 can be a multi-level cell (MLC) storing two bits of data. In another example, each of the plurality of memory cells included in the memory cell array 210 can be a three-level cell (TLC) storing three bits of data. In another example, each of the plurality of memory cells included in the memory cell array 210 can be a four-level cell (QLC) storing four bits of data. In yet another example, the memory cell array 210 may include a plurality of memory cells, each of which stores five or more bits of data.

[0075] The number of bits of data stored in each of multiple memory cells can be dynamically determined. For example, a single-level cell storing 1 bit of data can be changed to a three-level cell storing 3 bits of data.

[0076] Reference Figure 2 The address decoder 220, read and write circuit 230, control logic 240 and voltage generation circuit 250 can be operated as peripheral circuits to drive the memory cell array 210.

[0077] Address decoder 220 can be connected to memory cell array 210 via multiple word lines WL.

[0078] Address decoder 220 can be configured to operate in response to control logic 240.

[0079] Address decoder 220 can receive addresses through input / output buffers in memory 110. Address decoder 220 can be configured to decode block addresses in the received addresses. Address decoder 220 can select at least one memory block based on the decoded block address.

[0080] Address decoder 220 can receive read voltage Vread and pass voltage Vpass from voltage generation circuit 250.

[0081] During a read operation, the address decoder 220 can apply a read voltage Vread to the selected word line WL in the selected memory block, and can apply a pass voltage Vpass to the remaining unselected word lines WL.

[0082] In the programming verification operation, the address decoder 220 can apply the verification voltage generated in the voltage generation circuit 250 to the selected word line WL in the selected memory block, and can apply the pass voltage Vpass to the remaining unselected word lines WL.

[0083] Address decoder 220 can be configured to decode the column address in the received address. Address decoder 220 can transmit the decoded column address to read and write circuitry 230.

[0084] Read and programming operations on memory 110 can be performed on a page-by-page basis. The address received when requesting a read or programming operation may include at least one of a block address, a row address, and a column address.

[0085] Address decoder 220 can select a memory block and a word line based on the block address and row address. The column address can be decoded by address decoder 220 and provided to read and write circuitry 230.

[0086] Address decoder 220 may include at least one of block decoder, row decoder, column decoder and address buffer.

[0087] The read and write circuitry 230 may include multiple page buffers PB. The read and write circuitry 230 may operate as a read circuit in the read operation of the memory cell array 210 and as a write circuit in the write operation of the memory cell array 210.

[0088] The aforementioned read and write circuit 230 can also be referred to as a page buffer circuit or a data register circuit that includes multiple page buffers PB. The read and write circuit 230 may include a data buffer responsible for data processing functions, and may further include a cache buffer responsible for cache functions.

[0089] Multiple page buffers PB can be connected to the memory cell array 210 via multiple bit lines BL. During read and program verification operations, the multiple page buffers PB can continuously supply sensing current to the bit lines BL connected to the memory cells to sense the threshold voltage (Vth) of the memory cells, and can latch the sensed data by using sensing nodes to sense changes in the amount of current generated according to the programming state of the corresponding memory cells.

[0090] The read and write circuit 230 can operate in response to a page buffer control signal output from the control logic 240.

[0091] During a read operation, the read and write circuit 230 temporarily stores the read data by sensing data in the memory cell, and then outputs the data to the input / output buffer of the memory 110. As an exemplary embodiment, in addition to the page buffer PB or page register, the read and write circuit 230 may also include column select circuitry.

[0092] Control logic 240 can be connected to address decoder 220, read and write circuitry 230, and voltage generation circuitry 250. Control logic 240 can receive commands CMD and control signals CTRL through the input / output buffer of memory 110.

[0093] Control logic 240 can be configured to control the general operation of memory 110 in response to control signal CTRL. Control logic 240 can output control signals for adjusting the precharge potential levels of the sensing nodes of multiple page buffers PB.

[0094] Control logic 240 can control read and write circuit 230 to perform read operations on memory cell array 210. Voltage generation circuit 250 can generate read voltage Vread and pass voltage Vpass used in the read operation in response to voltage generation circuit control signals output from control logic 240.

[0095] Each memory block of the aforementioned memory 110 may consist of multiple pages corresponding to multiple word lines WL and multiple strings corresponding to multiple bit lines BL.

[0096] Within a storage block BLK, multiple word lines (WL) and multiple bit lines (BL) can be configured to intersect each other. For example, each of the multiple word lines (WL) can be configured along the row direction, and each of the multiple bit lines (BL) can be configured along the column direction. In another example, each of the multiple word lines (WL) can be configured along the column direction, and each of the multiple bit lines (BL) can be configured along the row direction.

[0097] A memory cell can be connected to one of multiple word lines (WL) and one of multiple bit lines (BL). A transistor can be placed in each memory cell.

[0098] For example, a transistor disposed in each memory cell may include a drain, a source, and a gate. The drain (or source) of the transistor may be connected directly or via another transistor to the corresponding bit line BL. The source (or drain) of the transistor may be connected directly or via another transistor to the source line (which may be ground). The gate of the transistor may include a floating gate and a control gate, the floating gate being surrounded by a dielectric, and the gate voltage being applied from the word line WL to the control gate.

[0099] In each memory block, a first select line (also referred to as a source select line or drain select line) may be additionally located outside the first outermost word line of the two outermost word lines, closer to the first outermost word line of the read and write circuit 230, and a second select line (also referred to as a drain select line or source select line) may be additionally located outside the second outermost word line of the two outermost word lines.

[0100] At least one additional dummy character line can be set between the first outermost character line and the first selection line. At least one additional dummy character line can also be set between the second outermost character line and the second selection line.

[0101] The read and program (write) operations of the aforementioned storage blocks can be performed on a page-by-page basis, and the erase operation can be performed on a block-by-block basis.

[0102] Figure 3 This is a schematic configuration diagram of a storage device according to the present disclosure.

[0103] Reference Figure 3 The storage device 100 may include a memory 110 and a controller 120.

[0104] The memory 110 can store data. The storage device 100 can write data requested by the host into the memory 110 and read data requested by the host from the memory 110.

[0105] The controller 120 can control the memory 110 to perform data input / output. The controller 120 can determine whether to activate one or more of a plurality of low-power mode delay techniques based on a set power mode. For example, the controller 120 can determine whether to activate a first low-power mode delay technique LOW_PWR_DELAY_1, a second low-power mode delay technique LOW_PWR_DELAY_2, and a third low-power mode delay technique LOW_PWR_DELAY_3. In some embodiments, the controller 120 can store an algorithm for determining the first low-power mode delay technique LOW_PWR_DELAY_1, the second low-power mode delay technique LOW_PWR_DELAY_2, and the third low-power mode delay technique LOW_PWR_DELAY_3, and execute one of the first to third low-power mode delay techniques based on this determination. Reference will be made later in this patent document. Figures 5 to 11Details of the first to third low-power mode delay techniques are described. The controller 120 can maximize performance when it is necessary to maximize performance (e.g., during performance and benchmark measurements) by preventing entry into low-power modes. However, unconditionally disabling entry into low-power modes may increase power consumption and trigger performance throttling to reduce heat generation. This may negatively impact average performance.

[0106] Some embodiments of the disclosed technology enable the controller 120 to selectively apply low-power mode delay techniques based on power modes. For example, if improved performance is required, the controller 120 can delay entering a low-power mode to improve performance. If reduced power consumption is required, the controller 120 can enter a low-power mode to reduce power consumption. Low-power mode delay techniques can also be referred to as low-power mode delay methods, low-power mode delay strategies, etc.

[0107] In embodiments of this disclosure, the power mode can be set in various ways.

[0108] For example, controller 120 can receive power mode setting information from the host. Controller 120 can then set the power mode based on the received setting information.

[0109] In another example, controller 120 can set a power mode based on the power consumed by storage device 100 and the power supplied to storage device 100. If the power consumed by storage device 100 is greater than the power supplied to storage device 100, controller 120 can change the power mode to reduce power consumption, and vice versa, it can change the power mode to increase power consumption.

[0110] The first low-power mode delay technique, LOW_PWR_DELAY_1, is a technique used to determine whether to delay entering low-power mode based on the reception history of low-power mode entry requests received from an external source (e.g., a host). This will be explained below. Figures 5 to 7 Detailed description is provided.

[0111] The second low-power mode delay technology, LOW_PWR_DELAY_2, is a technique used to determine whether to delay entering low-power mode when the storage device 100 meets the low-power mode entry conditions without considering the host. This will be explained below. Figures 8 to 9 Detailed description is provided.

[0112] The third low-power mode delay technique, LOW_PWR_DELAY_3, is used to determine whether to delay entering low-power mode based on the history of commands received from the host. This will be explained below. Figures 10 to 11 Detailed description is provided.

[0113] Figure 4 This is a diagram illustrating the power mode of the storage device 100 according to the present disclosure.

[0114] Reference Figure 4 The power mode of storage device 100 can be one of multiple candidate power modes CAND_PWR_MODE. For example, the power mode of storage device 100 can be divided into performance mode 1, performance mode 2, standard mode, power saving mode 1, and power saving mode 2, etc.

[0115] In this scenario, the number of low-power mode delay techniques activated in each candidate power mode can vary depending on the available power corresponding to each candidate power mode (CAND_PWR_MODE). The available power can be determined as the average power available over a set duration.

[0116] In embodiments of this disclosure, the number of low-power mode delay techniques activated in the candidate power modes can be increased as the available power in the candidate power modes increases.

[0117] When the available power in the first candidate power mode among multiple candidate power modes CAND_PWR_MODE is greater than the available power in the second candidate power mode among multiple candidate power modes CAND_PWR_MODE, the number of low power mode delay techniques activated in the first candidate power mode among multiple low power mode delay techniques (e.g., the first low power mode delay technique LOW_PWR_DELAY_1, the second low power mode delay technique LOW_PWR_DELAY_2, and the third low power mode delay technique LOW_PWR_DELAY_3) can be greater than the number of techniques activated in the second candidate power mode.

[0118] exist Figure 4 In the candidate power mode where only the first low-power mode delay technology LOW_PWR_DELAY_1 is activated, the available power is greater than the available power in the candidate power mode where all low-power mode delay technologies are disabled.

[0119] The available power in the candidate power mode with the first low power mode delay technology LOW_PWR_DELAY_1 and the second low power mode delay technology LOW_PWR_DELAY_2 activated is greater than the available power in the candidate power mode with only the first low power mode delay technology LOW_PWR_DELAY_1 activated.

[0120] The available power in the candidate power modes of activating the first low-power mode delay technology LOW_PWR_DELAY_1, the second low-power mode delay technology LOW_PWR_DELAY_2, and the third low-power mode delay technology LOW_PWR_DELAY_3 is greater than the available power in the candidate power modes of activating the first low-power mode delay technology LOW_PWR_DELAY_1 and the second low-power mode delay technology LOW_PWR_DELAY_2.

[0121] Figure 5 This is a diagram illustrating an example of a first low-power mode delay technique according to the present disclosure.

[0122] In an embodiment according to this disclosure, the first low power mode delay technique LOW_PWR_DELAY_1 may include increasing the short low power mode cumulative count SLPCC when a low power mode entry request LPER is received from the host and the time difference between the current point and the previous low power mode entry point is less than a first threshold time THR1.

[0123] When the host is expected to enter an idle state, it can transmit a Low Power Mode Entry Request (LPER) to the storage device 100. In this case, the power consumption and response time of the storage device 100 can vary depending on the depth of the low power mode indicated by the LPER. The depth of the low power mode can refer to the level of power reduction. If the power reduction is deeper, more aggressive power saving is performed.

[0124] As the depth of transition from low-power mode to low-power mode requiring LPER indication increases or deepens, the power consumption of storage device 100 decreases, but the response time may increase.

[0125] On the other hand, as the depth of transition from low-power mode to low-power mode requesting LPER indication decreases or becomes shallower, the response time of storage device 100 decreases, but power consumption may increase.

[0126] exist Figure 5 In this context, upon initially receiving a Low Power Mode Entry Request (LPER) from the host, storage device 100 may enter low power mode. In this case, the Short Low Power Mode Accumulator (SLPCC) value may be 0.

[0127] Subsequently, after receiving a Low Power Mode Entry Request (LPER), another Low Power Mode Entry Request (LPER) is received from the host. Figure 5In the example shown, the time difference between the current point and the previous low-power mode entry point can be less than a first threshold time THR1. In this case, the controller 120 of the storage device 100 can increment the value of the short low-power mode cumulative count SLPCC to 1. Thereafter, the storage device 100 can enter a low-power mode.

[0128] Figure 5 The storage device 100 is further illustrated by applying a first low-power mode delay technique, LOW_PWR_DELAY_1. In an embodiment, when the short low-power mode cumulative count SLPCC becomes greater than or equal to the threshold count THR_CNT, the controller 120 of the storage device 100 will delay entering low-power mode by a set delay time DELAY_TIME.

[0129] If the short low-power mode cumulative count (SLPCC) is large (e.g., greater than or equal to the threshold count (THR_CNT), this indicates that there have been a sufficient number of cycles in which the device enters a low-power mode for a short period and then exits it. In this case, the effect of reducing the power consumption of the storage device 100 is minimal, but the performance of the storage device 100 is adversely affected.

[0130] Therefore, in the implementation, the controller 120 delays entering the low-power mode, rather than entering the low-power mode for a shorter period of time.

[0131] Delaying entry into low-power mode by using a delay time DELAY_TIME means that even if the conditions for entering low-power mode are met, the storage device 100 will not enter low-power mode during the delay time DELAY_TIME.

[0132] exist Figure 5 In the example shown, if storage device 100 receives a Low Power Mode Entry Request (LPER) from the host, and the time difference between receiving the current LPER and receiving the previous LPER is less than a first threshold time THR1, then controller 120 increments the Short Low Power Mode Accumulator (SLPCC) by 1. Then, if the increment of the SLPCC is greater than the threshold count THR_CNT, it does not immediately enter low power mode. Instead, controller 120 of storage device 100 enters low power mode after a delay time DELAY_TIME.

[0133] In some implementations, even when the storage device 100 delays entering low power mode, the controller 120 of the storage device 100 may, in response to the low power mode entry request LPER, transmit a response message to the host indicating that the storage device 100 has entered low power mode.

[0134] In embodiments of this disclosure, the first threshold time THR1 may be a preset value or a value determined based on the average of the time differences between two consecutive low-power mode entry points during a preset time period.

[0135] Similarly, the threshold count THR_CNT can be a preset value, or it can be a value determined based on the average value of the short low power mode cumulative count SLPCC during a preset time period.

[0136] Figure 6 This is a diagram illustrating another example of the first low-power mode delay technique LOW_PWR_DELAY_1 according to this disclosure.

[0137] In embodiments of this disclosure, the first low-power mode delay technique LOW_PWR_DELAY_1 may include reducing the value of the short low-power mode cumulative count SLPCC when the time difference between the current point and the previous low-power mode entry point is equal to or greater than a first threshold time THR1.

[0138] exist Figure 6 In the event that the value of the Short Low Power Mode Accumulator (SLPCC) is N (where N is a natural number) when the LPER is received, if another LPER is received while the time difference between the current point and the previous low power mode entry point is equal to or greater than the first threshold time THR1, the controller 120 of the storage device 100 may, in response to receiving another LPER, reduce the value of the Short Low Power Mode Accumulator (SLPCC) to (N-1).

[0139] In embodiments of this disclosure, the first low-power mode delay technique LOW_PWR_DELAY_1 may include initializing the value of the short low-power mode cumulative count SLPCC to a preset value (e.g., 0) when the time difference between the current point and the previous low-power mode entry point is greater than or equal to a second threshold time THR2. In this case, the second threshold time THR2 is longer than the first threshold time THR1.

[0140] exist Figure 6 In the case where the value of the short low power mode cumulative count SLPCC is M (M is an integer greater than or equal to 0), if another LPER is received when the time difference between the current point and the previous low power mode entry point is greater than or equal to the second threshold time THR2, the controller 120 of the storage device 100 can initialize the value of the short low power mode cumulative count SLPCC to 0.

[0141] Figure 7 This is a diagram illustrating another example of the first low-power mode delay technique LOW_PWR_DELAY_1 according to this disclosure.

[0142] In embodiments of this disclosure, the first low-power mode delay technique LOW_PWR_DELAY_1 may include increasing the delay time DELAY_TIME when the accumulated delay count DELAY_CNT is greater than or equal to the threshold delay count THR_DELAY_CNT. In this case, the accumulated delay count DELAY_CNT may be the number of times the controller 120 delays entering low-power mode during a set time period.

[0143] exist Figure 7 In the event that the controller 120 of the storage device 100 receives a low-power mode entry request (LPER) from the host, the low-power mode entry can be delayed by a delay time (DELAY_TIME).

[0144] When the time difference between the current point and the previous low-power mode entry point is less than the first threshold time THR1 and the short low-power mode cumulative count SLPCC is greater than or equal to the threshold count THR_CNT, the controller 120 may delay the low-power mode entry by a set delay time DELAY_TIME.

[0145] In this scenario, controller 120 can compare the cumulative delay count DELAY_CNT with the threshold delay count THR_DELAY_CNT, which indicates the number of times the low-power mode has been delayed. When the cumulative delay count DELAY_CNT is less than the threshold delay count THR_DELAY_CNT, controller 120 can set the delay time DELAY_TIME to D1.

[0146] Subsequently, when receiving a low-power mode entry request (LPER) from the host, the controller 120 of the storage device 100 may enter low-power mode with a delay of DELAY_TIME D1.

[0147] In this scenario, controller 120 can again compare the cumulative delay count DELAY_CNT and the threshold delay count THR_DELAY_CNT. When the cumulative delay count DELAY_CNT is greater than or equal to the threshold delay count THR_DELAY_CNT, controller 120 can set the delay time DELAY_TIME to D2. In this case, D2 is greater than D1.

[0148] If the low-power mode delay technology is not activated because a low-power mode entry request (LPER) is not received from the host within a set threshold time, the controller 120 may reduce or initialize the delay time (DELAY_TIME).

[0149] Figure 8This is a diagram illustrating an example of the second low-power mode delay technique LOW_PWR_DELAY_2 according to this disclosure.

[0150] In embodiments of this disclosure, when the storage device 100 itself meets the low power mode entry condition, the second low power mode delay technology LOW_PWR_DELAY_2 may include recording the time interval between the current time point and the previous time point when the storage device 100 met the low power mode entry condition LPEC.

[0151] The controller 120 of storage device 100 can be determined to meet the Low Power Mode Entry Condition (LPEC) under the following conditions.

[0152] For example, if the controller 120 remains idle for a period of time longer than or equal to a set threshold idle time, it can be determined that the storage device 100 meets the Low Power Mode Entry (LPEC) condition. In some embodiments, the storage device 100 remains idle if the bus 127 included in the storage device 100 remains idle (e.g., a state where no data is being transmitted through the bus 127).

[0153] The second low-power mode delay technique, LOW_PWR_DELAY_2, may include delaying entry into low-power mode when the accumulated count CNT is equal to or greater than the threshold entry count THR_CNT. In this case, the accumulated count CNT may be the number of times, during a set first time period, the time interval between the aforementioned current time point and the previous time point of the storage device that satisfies LPEC is less than the threshold time interval THR_TI.

[0154] exist Figure 8 In the process, when the storage device 100 meets the Low Power Mode Entry Condition (LPEC), the controller 120 of the storage device 100 can compare the time interval between the current time point and the previous time point when the Low Power Mode Entry Condition was met with the threshold time interval THR_TI.

[0155] When the time interval is less than or equal to the threshold time interval THR_TI, if the accumulated number of times CNT is less than the threshold number of times THR_CNT, the controller 120 of the storage device 100 will not delay entering the low-power mode. Therefore, when the low-power mode entry condition LPEC is met, the storage device 100 can immediately enter the low-power mode without any delay.

[0156] Subsequently, when the storage device 100 meets the Low Power Mode Entry Condition (LPEC), the controller 120 of the storage device 100 can again compare the time interval between the current time point and the previous time point when the Low Power Mode Entry Condition was met with the threshold time interval THR_TI.

[0157] When the time interval is less than or equal to the threshold time interval THR_TI, if the accumulated number of times CNT is greater than or equal to the threshold number of times THR_CNT, the controller 120 of the storage device 100 delays entering the low-power mode. Therefore, even if the low-power mode entry condition LPEC is met, the storage device 100 will not immediately enter the low-power mode. Instead, the storage device 100 may enter the low-power mode after a delay time DELAY_TIME.

[0158] Figure 9 This is a diagram illustrating another example of the second low-power mode delay technique LOW_PWR_DELAY_2 according to this disclosure.

[0159] In embodiments of this disclosure, the second low-power mode delay technology LOW_PWR_DELAY_2 may include increasing a threshold idle time THR_IDLE_TIME when the cumulative delay count DELAY_CNT is equal to or greater than the threshold delay count THR_DELAY_CNT. The cumulative delay count DELAY_CNT indicates the number of times the device has been delayed into low-power mode during a set second time period. The threshold idle time THR_IDLE_TIME is used to determine whether the storage device 100 itself meets the low-power mode entry condition LPEC.

[0160] exist Figure 9 In the first time interval, when the cumulative number of times the time interval is less than the threshold time interval THR_TI is greater than or equal to the threshold number of times THR_CNT, the controller 120 may delay entering the low power mode by a delay time DELAY_TIME.

[0161] In this case, if the number of times the controller 120 is delayed to enter the low power mode (DELAY_CNT) is less than the threshold delay number (THR_DELAY_CNT), the controller 120 can keep the threshold idle time (THR_IDLE_TIME) unchanged.

[0162] Subsequently, when the cumulative number of times the time interval is less than the threshold time interval THR_TI during the set first time interval is greater than or equal to the threshold number of times THR_CNT, the controller 120 may again delay entering the low power mode by a delay time DELAY_TIME.

[0163] In this case, if the number of delays to enter low-power mode (DELAY_CNT) is greater than or equal to the threshold delay number (THR_DELAY_CNT), the controller 120 may increase the threshold idle time (THR_IDLE_TIME). As the threshold idle time (THR_IDLE_TIME) increases, the probability that the storage device 100 itself satisfies the low-power mode entry condition (LPEC) decreases.

[0164] In some implementations, if the storage device 100 remains idle for a reference time, the controller 120 may decrease or initialize the aforementioned threshold idle time THR_IDLE_TIME. In this case, the reference time may be longer than the threshold idle time THR_IDLE_TIME.

[0165] Figure 10 This is a diagram illustrating an example of the third low-power mode delay technique LOW_PWR_DELAY_3 according to this disclosure.

[0166] In embodiments of this disclosure, the third low-power mode delay technique LOW_PWR_DELAY_3 may include delaying the entry into low-power mode by a set delay time DELAY_TIME when the device is woken from low-power mode by receiving a read command or write command from the host.

[0167] When a host transmits data transfer commands (e.g., read commands, write commands) to a storage device 100 while the storage device 100 is already in low-power mode, the host is more likely to continue transmitting data transfer commands to the storage device 100 thereafter. Therefore, the storage device 100 can improve performance by delaying its entry into low-power mode.

[0168] exist Figure 10 In this configuration, when the storage device 100 is woken from low-power mode by receiving a read command or write command from the host, the controller 120 of the storage device 100 may delay entering low-power mode by a delay time DELAY_TIME. Therefore, even if the storage device 100 meets the low-power mode entry conditions, the storage device 100 will not enter low-power mode until the delay time DELAY_TIME has elapsed. In this case, the value of the delay time DELAY_TIME can be D1.

[0169] When waking from low-power mode by receiving a read or write command from the host, the controller 120 can adjust the value of the delay time DELAY_TIME. For example, when the controller 120 receives a read or write command from the host with a delay before entering low-power mode, the controller 120 can increase the value of the delay time DELAY_TIME from D1 to D2. Figure 10 In the example, the controller starts the delay time DELAY_TIME D2 after the delay time DELAY_TIME D1 expires.

[0170] Figure 11 This is a diagram illustrating another example of the third low-power mode delay technique LOW_PWR_DELAY_3 according to this disclosure.

[0171] In embodiments of this disclosure, the third low-power mode delay technique LOW_PWR_DELAY_3 may include initializing the delay time DELAY_TIME when waking from low-power mode by receiving a command other than a read command or a write command (e.g., a device setup command) from the host.

[0172] exist Figure 11 In the process of receiving further commands from the host, the controller 120 of the storage device 100 can reduce the value of the delay time DELAY_TIME from D2 to D1. Therefore, in situations such as... Figure 11 In the example shown, controller 120 can delay entering low-power mode by DELAY_TIME D1 after receiving other commands from the host.

[0173] Figure 12 This is a diagram illustrating the operation method of the storage device 100 according to the present disclosure.

[0174] Reference Figure 12 The operation method of the storage device 100 may include receiving setting information about the power mode (S1210).

[0175] As an example, the power mode can be one of several candidate power modes, CAND_PWR_MODE.

[0176] In this case, when the available power in the first candidate power mode CAND_PWR_MODE is greater than the available power in the second candidate power mode among multiple candidate power modes, the number of low power mode delay techniques activated in the first candidate power mode among the first low power mode delay techniques LOW_PWR_DELAY_1, the second low power mode delay technique LOW_PWR_DELAY_2, and the third low power mode delay technique LOW_PWR_DELAY_3 can be greater than the number of low power mode delay techniques activated in the second candidate power mode.

[0177] The operation method of the storage device 100 may include determining whether to activate multiple low power mode delay technologies (e.g., a first low power mode delay technology LOW_PWR_DELAY_1, a second low power mode delay technology LOW_PWR_DELAY_2, and a third low power mode delay technology LOW_PWR_DELAY_3) based on the power mode (S1220).

[0178] The first low-power mode delay technique LOW_PWR_DELAY_1 may include determining whether to delay entering low-power mode based on the reception history of the low-power mode entry request LPER received from an external source (e.g., a host).

[0179] For example, when a low-power mode entry request is received from the host, the first low-power mode delay technique LOW_PWR_DELAY_1 can increase the short low-power mode cumulative count SLPCC when the time difference between the current point and the previous low-power mode entry point is less than the first threshold time THR1, and delay the low-power mode entry by the set delay time DELAY_TIME when the short low-power mode cumulative count SLPCC is greater than or equal to the threshold count THR_CNT.

[0180] In this case, the first low-power mode delay technique LOW_PWR_DELAY_1 can reduce the short low-power mode cumulative count SLPCC when the time difference between the current point and the previous low-power mode entry point is greater than or equal to the first threshold time THR1.

[0181] In this case, when the cumulative delay count DELAY_CNT for delaying entry into low power mode within the set time period is greater than or equal to the threshold delay count THR_DELAY_CNT, the first low power mode delay technique LOW_PWR_DELAY_1 can increase the delay time DELAY_TIME.

[0182] The second low-power mode delay technology LOW_PWR_DELAY_2 may include determining whether to delay entering low-power mode when the storage device 100 meets the low-power mode entry conditions.

[0183] For example, the second low-power mode delay technique LOW_PWR_DELAY_2 can record the time interval between the current time when the storage device 100 meets the low-power mode entry condition and the previous time when the low-power mode entry condition was met. When the accumulated count CNT is greater than or equal to the threshold entry count THR_CNT, the low-power mode entry can be delayed. The accumulated count CNT indicates the number of times the time interval is less than the threshold time interval THR_TI during a set first time period.

[0184] In this case, when the storage device 100 is idle for a period of time equal to or greater than a set threshold idle time THR_IDLE_TIME, the low-power mode entry condition can be met. Furthermore, the second low-power mode delay technique LOW_PWR_DELAY_2 may include increasing the threshold idle time THR_IDLE_TIME when the accumulated delay count DELAY_CNT is greater than or equal to the threshold delay count THR_DELAY_CNT, where the accumulated delay count DELAY_CNT is the number of times low-power mode entry is delayed within a set second time period.

[0185] The third low-power mode delay technique, LOW_PWR_DELAY_3, may include determining whether to delay entering low-power mode based on the history of commands received from the host.

[0186] In the example, the third low-power mode delay technique LOW_PWR_DELAY_3 may include delaying the entry into low-power mode by a set delay time DELAY_TIME when the user is woken from low-power mode by receiving a read command or write command from the host.

[0187] In this case, the third low-power mode delay technique LOW_PWR_DELAY_3 may include initializing the delay time DELAY_TIME when waking from low-power mode by receiving commands other than read and write commands from the host.

[0188] Although exemplary embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered merely descriptive and not limiting of the scope of the technology. The technical scope of this disclosure is not limited to the embodiments and the accompanying drawings. The spirit and scope of this disclosure should be interpreted in conjunction with the appended claims and cover all equivalents falling within the scope of the appended claims.

Claims

1. A storage device, comprising: Memory, used to store data; as well as A controller is communicatively connected to the memory and controls the memory to perform at least one of the input or output of the data by determining whether to activate at least one of a plurality of low-power mode delay techniques based on the power mode.

2. The storage device according to claim 1, in, The multiple low-power mode delay technologies include a first low-power mode delay technology, a second low-power mode delay technology, and a third low-power mode delay technology. In response to the activation of the first low-power mode delay technique, the controller determines whether to delay low-power mode entry based on the reception history of low-power mode entry requests received from the host communicating with the controller. In response to the activation of the second low-power mode delay technique, the controller determines whether to delay the low-power mode entry based on whether the storage device meets the low-power mode entry conditions. In response to the activation of the third low-power mode delay technology, the controller determines whether to delay the entry of the low-power mode based on the history of commands received from the host.

3. The storage device according to claim 1, in, The controller receives setting information about the power mode from an external source.

4. The storage device according to claim 1, in, The power mode is one of a plurality of candidate power modes, including a first candidate power mode and a second candidate power mode, and The amount of power available in the first candidate power mode is greater than the amount of power available in the second candidate power mode, and the number of low-power mode delay techniques activated in the first candidate power mode is greater than the number of low-power mode delay techniques activated in the second candidate power mode.

5. The storage device according to claim 2, in, In response to receiving the low-power mode entry request from the host, the first low-power mode delay technology is activated, so that when the controller satisfies the condition that the time difference between the current point and the previous low-power mode entry point is less than a first threshold time, the short low-power mode cumulative count is increased, and when the short low-power mode cumulative count is greater than or equal to the threshold count, the low-power mode entry is delayed by a set delay time.

6. The storage device according to claim 5, in, In response to the activation of the first low-power mode delay technique, the controller further reduces the short low-power mode cumulative count when the time difference between the current point and the previous low-power mode entry point is longer than or equal to the first threshold time.

7. The storage device according to claim 6, in, In response to the activation of the first low-power mode delay technique, the controller further initializes the short low-power mode cumulative count when the time difference between the current point and the previous low-power mode entry point is longer than or equal to a second threshold time. The second threshold time is longer than the first threshold time.

8. The storage device according to claim 5, in, In response to the activation of the first low-power mode delay technology, the controller further increases the delay time when the condition that the cumulative delay count is greater than or equal to the threshold delay count is met, wherein the cumulative delay count indicates the number of times the low-power mode has been delayed during a set time period.

9. The storage device according to claim 2, in, In response to the activation of the second low-power mode delay technique, the controller further records the time interval between the current time when the low-power mode entry condition is met and the previous time when the low-power mode entry condition is met, and The controller further delays entering the low-power mode when the condition that the cumulative number of times is greater than or equal to the threshold number of times it enters is met. The cumulative number of times indicates that the time interval is less than the threshold time interval during a set first time interval.

10. The storage device according to claim 9, in, The controller further determines that the storage device has met the low-power mode entry condition when the storage device has been idle for a period of time greater than or equal to a set threshold idle time. In response to the activation of the second low-power mode delay technology, the controller further increases the threshold idle time when the condition that the cumulative delay count is greater than or equal to the threshold delay count is met. The cumulative delay count indicates the number of times the low-power mode has been delayed during a set second time interval.

11. The storage device according to claim 2, in, In response to the activation of the third low-power mode delay technology, the controller further delays entering the low-power mode by a set delay time after waking up from the low-power mode by receiving a read command or write command from the host.

12. The storage device according to claim 11, in, In response to the activation of the third low-power mode delay technology, the controller further initializes the delay time when waking up from the low-power mode by receiving commands from the host other than the read command and the write command.

13. A method of operating a storage device, comprising: Receive information about the power mode of the storage device; as well as Based on the power mode, determine whether to activate at least one of a plurality of low-power mode delay techniques.

14. The method of operating a storage device according to claim 13, in, The multiple low-power mode delay technologies include a first low-power mode delay technology, a second low-power mode delay technology, and a third low-power mode delay technology. In response to the activation of the first low-power mode delay technique, the method further includes determining whether to delay low-power mode entry based on the reception history of low-power mode entry requests received from a host communicatively connected to the storage device, and In response to the activation of the second low-power mode delay technique, the method further includes determining whether to delay the low-power mode entry based on whether the storage device meets the low-power mode entry conditions, and In response to the activation of the third low-power mode delay technique, the method further includes determining whether to delay the entry of the low-power mode based on the history of commands received from the host.

15. The method of operating a storage device according to claim 14, in, In response to receiving the low-power mode entry request from the host, the method further includes incrementing the short low-power mode cumulative count when the time difference between the current point and the previous low-power mode entry point is less than a first threshold time, and delaying the low-power mode entry by a set delay time when the short low-power mode cumulative count is greater than or equal to the threshold count.

16. The method of operating a storage device according to claim 15, in, In response to the activation of the first low-power mode delay technique, the method further includes reducing the short low-power mode cumulative count when the time difference between the current point and the previous low-power mode entry point is greater than or equal to the first threshold time.

17. The method of operating a storage device according to claim 15, in, In response to the activation of the first low-power mode delay technique, the method further includes increasing the delay time when the condition that the cumulative delay count is greater than or equal to a threshold delay count is met, wherein the cumulative delay count indicates the number of times the low-power mode has been delayed during a set time period.

18. The method of operating a storage device according to claim 14, in, In response to the activation of the second low-power mode delay technique, the method further includes recording the time interval between the current time when the low-power mode entry condition is met and the previous time when the low-power mode entry condition is met, and delaying entry into the low-power mode when the condition that the cumulative number is greater than or equal to a threshold entry number is met, the cumulative number indicating the number of times the time interval is less than the threshold time interval during a set first time interval.

19. The method of operating a storage device according to claim 14, in, In response to the activation of the third low-power mode delay technology, the method further includes delaying the entry into the low-power mode by a set delay time after waking from the low-power mode by receiving a read command or a write command from the host.

20. A storage device for processing data, in, The storage device determines whether to delay entering the low-power mode based on at least one of the following: a history of receiving low-power mode entry requests from the outside, a history of entering the low-power mode by satisfying low-power mode entry conditions when no low-power mode entry request is received, and a history of receiving commands from the outside.

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