substrate structure

The substrate structure addresses warpage issues by using a coreless base with alternating layers of varying thermal expansion coefficients and bonding layers to form compressive stress, enhancing structural reliability and conductive through-hole density for high-density circuits.

JP2026116662APending Publication Date: 2026-07-10UNIMICRON TECH CORP
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Patent Information

Authority / Receiving Office
JP ยท JP
Patent Type
Applications
Current Assignee / Owner
UNIMICRON TECH CORP
Filing Date
2025-06-13
Publication Date
2026-07-10

AI Technical Summary

Technical Problem

The warpage of high-density integrated circuit substrates and circuit boards due to thermal expansion mismatch between layers, leading to reduced structural reliability and limited conductive through-hole density, is addressed by incorporating a coreless base with alternating dielectric and conductive pattern layers having different thermal expansion coefficients, and using bonding layers to connect these layers, thereby forming compressive stress to suppress warping.

Method used

A substrate structure comprising a coreless base with alternating dielectric and conductive pattern layers, where the thermal expansion coefficient of the build-up structure layers is smaller than that of the coreless base, and bonding layers are used to connect these layers, allowing for increased wiring density and improved structural reliability.

Benefits of technology

The substrate structure achieves superior structural reliability by suppressing warpage through compressive stress, enabling higher conductive through-hole density and improved flatness, suitable for high-density circuit applications.

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Abstract

To provide a substrate structure with excellent structural reliability. [Solution] The substrate structure of the present invention includes a coreless base and a first build-up structure layer. The coreless base includes at least one first dielectric layer and at least one first conductive pattern layer. The first build-up structure layer is provided on the coreless base and includes at least one second dielectric layer and at least one second conductive pattern layer. The thermal expansion coefficient of at least one second dielectric layer is smaller than the thermal expansion coefficient of at least one first dielectric layer. The at least one second conductive pattern layer is electrically connected to at least one first conductive pattern layer.
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