Light-emitting display device

Abstract

To provide a light-emitting display device that improves the extraction efficiency of light emitted from a light-emitting layer. [Solution] The light-emitting display device according to the embodiment of this specification includes a substrate containing a plurality of pixels, a pixel drive line arranged on the substrate in a first direction, a gate line arranged on the substrate in a second direction intersecting the first direction, an auxiliary line superimposed on the pixel drive line, a pixel circuit connected to the pixel drive line, an overcoat layer covering the pixel circuit, a groove superimposed on the auxiliary line, and a light-emitting layer arranged on the overcoat layer and connected to the pixel circuit.

Description

Technical Field

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[0001] This specification relates to a light-emitting display device.

Background Art

[0002] A light-emitting display device is a self-emitting display device. Different from a liquid crystal display device, it does not require a separate light source, so it can be manufactured to be lightweight and thin, and the display device can be miniaturized. In addition, the light-emitting display device is not only advantageous in terms of power consumption due to low-voltage driving, but also excellent in hue arrangement, response speed, viewing angle, and brightness contrast ratio, and has been in the spotlight as a next-generation display device.

[0003] The light-emitting display device displays an image by the light emission of a light-emitting element layer including a light-emitting element interposed between two electrodes. The light generated by the light emission of the light-emitting element is emitted to the outside through a substrate or the like.

[0004] On the other hand, in the light-emitting display device, due to total reflection or the like between a plurality of layers arranged inside the display panel or at an interface, a part of the light emitted from the light-emitting element layer may not be emitted to the outside. Therefore, the light extraction efficiency of the light-emitting display device may decrease.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The inventors of this specification recognized the above problems and invented a light-emitting display device with a new structure in which the light extraction efficiency can be improved through many experiments.

[0006] The problem to be solved by the examples in this specification is to provide a light-emitting display device with improved extraction efficiency (light extraction efficiency) of the light emitted from the light-emitting element layer.

[0007] The problem to be solved by the examples in this specification is to provide a light-emitting display device that can reduce the overall power consumption and be driven with low power by improving the light extraction efficiency.

[0008] The problems addressed by the embodiments described herein are not limited to those mentioned above, and other problems not mentioned will be readily apparent to those skilled in the art from the following description. [Means for solving the problem]

[0009] The light-emitting display device according to the embodiments of this specification may include a substrate containing a plurality of pixels, pixel drive lines arranged on the substrate in a first direction, gate lines arranged on the substrate in a second direction intersecting the first direction, auxiliary lines superimposed on the pixel drive lines, pixel circuits connected to the pixel drive lines, an overcoat layer covering the pixel circuits, grooves superimposed on the auxiliary lines, and a light-emitting layer disposed on the overcoat layer and connected to the pixel circuits.

[0010] In addition to the technical problems of the present invention mentioned above, other features and advantages of the present invention may also be described below, and such descriptions and explanations will be clearly understandable to those who have ordinary skill in the art to which the present invention pertains. [Effects of the Invention]

[0011] According to one or more embodiments of this specification, the light-emitting display device includes auxiliary lines superimposed on the pixel drive lines, thereby enabling the formation of grooves between each subpixel by a subsequently placed overcoat layer without the need for an additional masking process. This allows for control of the direction of light reflection toward adjacent subpixels, thereby improving the light extraction efficiency of the light-emitting display device.

[0012] According to one or more embodiments of this specification, the light-emitting display device includes auxiliary lines and grooves superimposed on the pixel drive lines, enabling light extraction even in non-light-emitting areas. Therefore, compared to a display device without auxiliary lines and grooves, it can have equivalent or even higher luminous efficiency at lower power consumption, thus reducing overall power consumption.

[0013] According to one or more embodiments of this specification, the light-emitting display device includes auxiliary lines and grooves superimposed on the pixel drive lines, thereby enabling all light that would otherwise be lost due to the waveguide and light that would otherwise be lost due to total internal reflection within the substrate to be emitted to the outside. This maximizes the light extraction efficiency.

[0014] According to one or more embodiments of this specification, the light-emitting display device can separate color filters configured in adjacent subpixels by including auxiliary lines and grooves superimposed on the pixel drive lines. This prevents light leakage and color mixing between subpixels.

[0015] According to one or more embodiments of this specification, a light-emitting device can include auxiliary lines superimposed on the pixel drive lines to form grooves between each subpixel without the need for additional masking steps (e.g., halftone masking steps). Thus, the light extraction efficiency of the light-emitting device can be improved without increasing the manufacturing process and costs.

[0016] According to one or more embodiments of this specification, the resistance of the pixel drive line can be reduced by including auxiliary lines electrically connected to the pixel drive line in the light-emitting display device.

[0017] The aforementioned problem to be solved, means of solving the problem, and effects do not specify essential features of the claims. The claims are not limited to what is described in the detailed description of the invention. [Brief explanation of the drawing]

[0018] [Figure 1] This figure schematically shows a light-emitting device according to the embodiments described herein. [Figure 2] This figure shows an example of the pixel arrangement structure shown in Figure 1. [Figure 3] Figure 2 shows a cross-sectional view of the line I-I'. [Figure 4] This is a cross-sectional view showing an example of region A as shown in Figure 2. [Figure 5] It is a cross-sectional view showing an example of the B region shown in FIG. 2. [Figure 6] It is a diagram showing another example of the pixel arrangement structure shown in FIG. 1. [Figure 7] It is a cross-sectional view of the line II-II' shown in FIG. 6. [Figure 8] It is a cross-sectional view showing an example of the C region shown in FIG. 7. [Figure 9] It is a cross-sectional view showing another example of the C region shown in FIG. 7. [Figure 10] It is a cross-sectional view showing another example of the B region shown in FIG. 2. [Figure 11] It is a cross-sectional view showing another example of the B region shown in FIG. 2. [Figure 12A] It is a diagram showing a method of manufacturing a light-emitting display device according to an embodiment of the present specification. [Figure 12B] It is a diagram showing a method of manufacturing a light-emitting display device according to an embodiment of the present specification. [Figure 12C] It is a diagram showing a method of manufacturing a light-emitting display device according to an embodiment of the present specification. [Figure 12D] It is a diagram showing a method of manufacturing a light-emitting display device according to an embodiment of the present specification. [Figure 12E] It is a diagram showing a method of manufacturing a light-emitting display device according to an embodiment of the present specification. [Figure 12F] It is a diagram showing a method of manufacturing a light-emitting display device according to an embodiment of the present specification. [Figure 13A] It is a diagram showing a method of manufacturing a light-emitting display device according to an embodiment of the present specification. [Figure 13B] It is a diagram showing a method of manufacturing a light-emitting display device according to an embodiment of the present specification. [Figure 13C] It is a diagram showing a method of manufacturing a light-emitting display device according to an embodiment of the present specification. [Figure 13D] It is a diagram showing a method of manufacturing a light-emitting display device according to an embodiment of the present specification. [Figure 13E] It is a diagram showing a method of manufacturing a light-emitting display device according to an embodiment of the present specification.

Embodiments for Carrying Out the Invention

[0019] The advantages and features of this specification, as well as the methods for achieving them, will become apparent upon reference to the various examples described below in detail with reference to the accompanying drawings. However, this specification is not limited to the examples disclosed below, but is arranged in a variety of different forms, and the examples herein are provided to complete the disclosure herein and to fully inform those who are ordinary skill in the art to which the technical concept herein pertains, and the technical concept herein is defined solely by the claims.

[0020] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings illustrating examples in this specification are illustrative, and this specification is not limited to those depicted. The same reference numerals throughout the specification indicate the same components. Furthermore, in describing examples in this specification, if it is determined that a specific description of related known technology would unnecessarily obscure the gist of this specification, such detailed description is omitted.

[0021] When using words such as "includes," "possesses," and "becomes" as used herein, other parts may be added unless "only" is used. When a component is expressed singularly, it includes cases where it includes multiple components unless otherwise explicitly stated.

[0022] In interpreting the constituent elements, even if there is no separate explicit description, it should be interpreted as including a margin of error.

[0023] When describing the relative positions of two parts, for example, using phrases like "on top of," "above," "below," or "next to," one or more other parts can be located between the two parts, unless "immediately" or "directly" is used.

[0024] When describing temporal relationships, for example, when describing sequential relationships using phrases like "after," "following," "next," or "before," it can include non-continuous events unless "immediately" or "directly" is used.

[0025] The terms "first," "second," etc., are used to describe various components, but these components are not limited to these terms. These terms are used simply to distinguish one component from others. Therefore, the first component mentioned below may also be the second component within the technical concepts of this specification.

[0026] The term "at least one" must be understood to include all possible combinations of one or more related items. For example, "at least one of items 1, 2, and 3" could mean not just each of items 1, 2, or 3 individually, but all possible combinations of two or more items from items 1, 2, and 3.

[0027] The technical features of each of the various examples described herein can be combined or combined in part or in whole, enabling a variety of technical interdependencies and drives, and each embodiment can be implemented independently of the others or together in a related manner.

[0028] Hereinafter, preferred examples of light-emitting devices according to this specification will be described in detail with reference to the accompanying drawings. When assigning reference numerals to the components in each figure, the same reference numeral will be used for the same component, even if it is shown in different figures, for example. Furthermore, the scale of the components shown in the accompanying drawings is different from the actual scale for the sake of explanation and is not limited to the scale shown in the drawings.

[0029] Figure 1 is a schematic diagram showing a light-emitting device according to an embodiment of this specification.

[0030] Referring to Figure 1, an embodiment of this specification (first embodiment) of the light-emitting display device may include a display panel 10, a control circuit 30, a data drive circuit 50, and a gate drive circuit 70.

[0031] The display panel 10 may include a display area (or active area) AA defined on the substrate and a non-display area (or inactive area) IA surrounding the display area AA.

[0032] A display area (or active area) AA defined on the substrate may include multiple pixels 12. Multiple pixels 12 can be defined by pixel drive lines PDL and gate lines GL. The pixel drive line PDL may include multiple pixel power lines PL, multiple data lines DL, and multiple reference power lines RL.

[0033] Multiple pixels 12 may include multiple subpixels 12a, 12b, 12c arranged in a region defined by n gate lines GL and m data lines DL. Each of the n gate lines GL extends long in a first direction X and can be separated from each other in a second direction Y that crosses the first direction X. Each of the m data lines DL extends long in the second direction Y and can be separated from each other in the first direction X.

[0034] Multiple pixel power lines PL and multiple reference power lines RL may be arranged alongside the data line DL. Each of the n gate lines GL may include an intersection that crosses each of the m data lines DL, multiple pixel power lines PL, and multiple reference power lines RL. Each intersection of the n gate lines GL may include at least one slit or opening to minimize the overlap area with other lines.

[0035] Each of the multiple subpixels 12a, 12b, and 12c can display a color image corresponding to the gate signal supplied from the adjacent gate line GL and the data voltage supplied from the adjacent data line DL. For example, each of the multiple subpixels 12a, 12b, and 12c may be arranged adjacent to each other in the first direction (longitudinal direction) X of the gate line GL.

[0036] According to embodiments of this specification, each of the plurality of subpixels 12a, 12b, 12c may include a pixel circuit located in the circuit region (or non-emitting region) of the subpixel area, and a light-emitting layer located in the aperture region (or light-emitting region) of the subpixel area and electrically connected to the pixel circuit. For example, the pixel circuit may include at least two transistors and at least one capacitor. The light-emitting layer may include an autoluminescent element that emits light itself in response to a data signal provided by the pixel circuit to display an image.

[0037] Each of the multiple subpixels 12a, 12b, and 12c can be defined as the smallest unit area that actually emits light. For example, at least three adjacent pixels can constitute a single pixel (or unit pixel) 12 for color display of an image.

[0038] For example, one pixel 12 may include first to third subpixels 12a, 12b, and 12c arranged adjacent to each other in the longitudinal direction of the gate line GL. For example, the first subpixel 12a may be a red subpixel or a first-color subpixel. The second subpixel 12b may be a green subpixel or a second-color subpixel. The third subpixel 12c may be a blue subpixel or a third-color subpixel. The light-emitting layers arranged in each of the first to third subpixels 12a, 12b, and 12c may individually emit light of different colors or emit white light in common.

[0039] The control circuit 30 can generate pixel-specific data signals corresponding to each of the multiple sub-pixels 12a, 12b, and 12c in response to the video signal. In one example, the control circuit 30 can calculate red pixel data, green pixel data, and blue pixel data based on the video signal, i.e., the red input data, green input data, and blue input data of each pixel 12. The control circuit 30 can then align the calculated red pixel data, green pixel data, and blue pixel data to match the pixel array structure and supply them to the data driving circuit 50.

[0040] The control circuit 30 can drive the data drive circuit 50 and the gate drive circuit 70 in display mode or sensing mode. Based on a timing synchronization signal, the control circuit 30 can generate data control signals and gate control signals, respectively, to drive the data drive circuit 50 and the gate drive circuit 70 in display mode or sensing mode. The control circuit 30 can provide the data control signal to the data drive circuit 50 and the gate control signal to the gate drive circuit 70. For example, sensing mode (or externally compensated drive) may be performed during the pre-shipment inspection process of the light-emitting display device, during the initial drive of the display panel 10, when the light-emitting display device is powered on, when the light-emitting display device is powered off, when the display panel 10 is powered off after a long period of operation, or during blank periods of frames set in real time or periodically.

[0041] Depending on the sensing mode, the control circuit 30 can store pixel-specific sensing data provided by the data driving circuit 50 in the storage circuit. In display mode, the control circuit 30 can correct the pixel data supplied to each sub-pixel 12a, 12b, and 12c based on the sensing data stored in the storage circuit and provide it to the data driving circuit 50. For example, the pixel-specific sensing data may include information on the time-dependent changes of the drive transistor and the light-emitting element. Therefore, in sensing mode, the control circuit 30 can sense the characteristic values ​​(e.g., threshold voltage or mobility) of the drive transistors arranged in each sub-pixel 12a, 12b, and 12c, and based on this, correct the pixel data supplied to each sub-pixel 12a, 12b, and 12c, thereby minimizing or suppressing image quality degradation due to characteristic value deviations of drive transistors in multiple sub-pixels.

[0042] The data driving circuit 50 may be individually connected to each of the m data lines DL arranged on the display panel 10. The data driving circuit 50 can receive pixel-specific data signals and data control signals provided by the control circuit 30 and can receive multiple reference gamma voltages provided by the power supply circuit.

[0043] In display mode, the data driving circuit 50 converts digital pixel-specific data signals into analog pixel-specific data voltages using a data control signal and multiple reference gamma voltages. In display mode, the data driving circuit 50 can supply the converted pixel-specific data voltages to the corresponding data line DL and generate reference voltages synchronized with the data voltages, which can then supply to multiple reference power lines RL.

[0044] In sensing mode, the data driving circuit 50 converts a digital sensing data signal into a sensing data voltage based on a data control signal and multiple reference gamma voltages, and supplies it to the corresponding sub-pixels 12a, 12b, and 12c via the corresponding data line DL. In sensing mode, the data driving circuit 50 senses the characteristic values ​​of the drive transistors located in the corresponding sub-pixels 12a, 12b, and 12c via each of the multiple reference power supply lines RL. The data driving circuit 50 can provide the pixel-specific sensing data sensed in sensing mode to the control circuit 30. For example, the data driving circuit 50 can sequentially sense the first to third sub-pixels 12a, 12b, and 12c that constitute the pixel 12.

[0045] The gate drive circuit 70 may be individually connected to each of the n gate lines GL provided on the display panel 10. Based on the gate control signal supplied from the control circuit 30, the gate drive circuit 70 can generate a gate signal in a predetermined procedure and supply it to the corresponding gate line GL.

[0046] According to embodiments of this specification, the gate drive circuit 70 may be integrated on one side edge and / or both side edges of the substrate by the manufacturing process of the thin-film transistor and connected one-to-one with a plurality of gate lines GL. According to other embodiments of this specification, the gate drive circuit 70 may be composed of an integrated circuit and mounted on the substrate, or mounted on a flexible circuit film and connected one-to-one with a plurality of gate lines GL.

[0047] Figure 2 shows an example of the pixel arrangement structure shown in Figure 1 (first embodiment).

[0048] Referring to Figure 2, the light-emitting display device according to the embodiment of this specification may include a plurality of pixels 12, a pixel drive line PDL, a gate line GL, an auxiliary line SL, and a pixel circuit PC.

[0049] According to embodiments of this specification, a light-emitting display device may include a plurality of pixels 12. For example, two adjacent pixels 12-1 and 12-2 may include a pixel drive line PDL. Two adjacent pixels 12-1 and 12-2 may include a plurality of data lines DL, a plurality of pixel power lines PL, and a plurality of reference power lines RL. Two adjacent pixels 12-1 and 12-2 may include first to sixth data lines DL1 to DL6, first and second pixel power lines PL1 and PL2, and first and second reference power lines RL1 and RL2. The pixel drive line PDL may be arranged on the substrate in a first direction X. The gate line GL may be arranged on the substrate in a second direction Y intersecting the first direction X.

[0050] Therefore, for the sake of explanation, the embodiments of this specification will be described below using two adjacent pixels 12-1 and 12-2 as an example. For example, the two adjacent pixels may be the first pixel 12-1 and the second pixel 12-2.

[0051] Any one of the multiple pixels 12 or the first pixel 12-1 may include multiple sub-pixel regions SPA1 to SPA3 arranged in a first direction X and a second direction Y that crosses the first direction X, and a pixel drive line PDL that extends long in the second direction Y and is arranged in the multiple sub-pixel regions SPA1 to SPA3. Each of the multiple sub-pixel regions SPA1 to SPA3 or the multiple sub-pixels 12a, 12b, 12c may overlap all or part of at least one pixel drive line PDL adjacent to the first direction X. As another example, each of the multiple sub-pixel regions SPA1 to SPA3 or the multiple sub-pixels 12a, 12b, 12c may be arranged between at least two pixel drive lines PDL adjacent to the first direction X. The pixel drive line PDL driving the first pixel 12-1 may be the first to third data lines DL1 to DL3, the first pixel power line PL1, and the first reference power line RL1.

[0052] One adjacent pixel among the multiple pixels 12, or a second pixel 12-2, may include multiple subpixel regions SPA4 to SPA6 arranged in a first direction X and a second direction Y that crosses the first direction X, and a pixel drive line PDL that extends long in the second direction Y and is arranged in the multiple subpixel regions SPA4 to SPA6. Each of the multiple subpixel regions SPA4 to SPA6 or the multiple subpixels 12d, 12e, 12f may overlap all or part of at least one pixel drive line PDL adjacent to the first direction X among the pixel drive line PDL. As another example, each of the multiple subpixel regions SPA4 to SPA6 or the multiple subpixels 12d, 12e, 12f may be arranged between at least two pixel drive lines PDL adjacent to the first direction X among the pixel drive line PDL. The pixel drive line PDL that drives the second pixel 12-2 may be the fourth to sixth data lines DL4 to DL6, the second pixel power line PL2, and the second reference power line RL2.

[0053] Multiple pixel power lines PL1 and PL2 can be spaced apart from each other in a first direction X on the substrate. Multiple data lines DL1 to DL6 may be arranged between the multiple pixel power lines PL1 and PL2 in the first direction X. Multiple reference power lines RL1 and RL2 may be arranged between the multiple data lines DL1 to DL6 in the first direction X.

[0054] The first pixel 12-1 of two adjacent pixels 12 can contain multiple sub-pixel regions SPA1 to SPA3.

[0055] The first subpixel region SPA1 among the multiple subpixel regions SPA1 to SPA3 may be positioned between the first pixel power line PL1 among the multiple pixel power lines PL and the first data line DL1 among the multiple data lines DL. For example, the first pixel power line PL1 may be an odd-numbered pixel power line among the multiple pixel power lines PL.

[0056] The second subpixel region SPA2 among the multiple subpixel regions SPA1 to SPA3 may be positioned between the second data line DL2 among the multiple data lines DL and the first reference power line RL1 among the multiple reference power lines RL. For example, the first data line DL1 and the second data line DL2 among the multiple data lines DL may be positioned adjacent to each other. For example, the first reference power line RL1 may be an odd-numbered reference power line among the multiple reference power lines RL.

[0057] The third subpixel region SPA3 among the multiple subpixel regions SPA1 to SPA3 may be positioned between the first reference power line RL1 among the multiple reference power lines RL and the third data line DL3 among the multiple data lines DL.

[0058] The second pixel 12-2 of two adjacent pixels 12 can contain multiple subpixel regions SPA4 to SPA6.

[0059] The fourth subpixel region SPA4 of the multiple subpixel regions SPA4 to SPA6 may be positioned between the fourth data line DL4 of the multiple data lines DL and the second reference power line RL2 of the multiple reference power lines RL. For example, the third data line DL3 and the fourth data line DL4 of the multiple data lines DL may be positioned adjacent to each other. For example, the second reference power line RL2 may be an even-numbered reference power line of the multiple reference power lines RL.

[0060] The fifth subpixel region SPA5 among the multiple subpixel regions SPA4 to SPA6 may be positioned between the second reference power line RL2 among the multiple reference power lines RL and the fifth data line DL5 among the multiple data lines DL.

[0061] The sixth subpixel region SPA6 among the multiple subpixel regions SPA4 to SPA6 may be positioned between the sixth data line DL6 among the multiple data lines DL and the second pixel power line PL2 among the multiple pixel power lines PL. For example, the fifth data line DL5 and the sixth data line DL6 among the multiple data lines DL may be positioned adjacent to each other. For example, the second pixel power line PL2 may be an even-numbered pixel power line among the multiple pixel power lines PL.

[0062] Each of the multiple subpixel regions SPA1 to SPA6 can be divided into a first region A1 and a second region A2 based on the second direction Y.

[0063] The first region (or light-emitting region) A1 is positioned on the upper side with respect to the second direction Y, and does not necessarily overlap with the gate line GL. Each of the first regions A1 of the multiple sub-pixel regions SPA1 to SPA6 may have the same size or may have different sizes.

[0064] Multiple subpixel regions SPA1 to SPA6 may include an light-emitting portion EP and a non-light-emitting portion NEP located in the first region A1. Each of the light-emitting portion EP and the non-light-emitting portion NEP may be configured to correspond to each of the multiple subpixel regions SPA1 to SPA6.

[0065] Multiple light-emitting units EP of each pixel 12-1, 12-2 may be superimposed on the light-emitting layer. The light-emitting layer arranged in each light-emitting unit EP of multiple sub-pixel regions SPA1 to SPA6 may include an anode electrode AE, a light-emitting layer, and a cathode electrode. Multiple light-emitting units EP of each pixel 12-1, 12-2 may include a first light-emitting unit EPr, a second light-emitting unit EPg, and a third light-emitting unit EPb.

[0066] Multiple non-emitting parts (NEPs) of each pixel 12-1, 12-2 may be superimposed on the pixel drive line PDL. Multiple non-emitting parts (NEPs) of each pixel 12-1, 12-2 may also be superimposed on the pixel power line PL, data line DL, and reference power line RL of the corresponding pixel. Multiple non-emitting parts (NEPs) may be arranged between each light-emitting part EP.

[0067] In the first pixel 12-1, the first light-emitting unit EPr may be located in the first sub-pixel region SPA1, the second light-emitting unit EPg may be located in the second sub-pixel region SPA2, and the third light-emitting unit EPb may be located in the third sub-pixel region SPA3.

[0068] In the second pixel 12-2, the first light-emitting unit EPr may be located in the fourth sub-pixel region SPA4, the second light-emitting unit EPg may be located in the fifth sub-pixel region SPA5, and the third light-emitting unit EPb may be located in the sixth sub-pixel region SPA6.

[0069] The second region (or circuit region) A2 is located on the lower side with respect to the second direction Y and may overlap with the gate line GL. The second region A2 of each of the multiple subpixel regions SPA1 to SPA6 may, but are not limited to, have substantially the same size.

[0070] According to embodiments of this specification, the light-emitting display device may include a pixel circuit PC. The pixel circuit PC may be located in or superimposed on the second region (or circuit region) A2 of each of the multiple sub-pixel regions SPA1 to SPA6. The pixel circuit PC may be connected to a pixel drive line PDL and a gate line GL. Each pixel circuit PC of the multiple sub-pixel regions SPA1 to SPA6 may include a gate line GL, a pixel power line PL, a data line DL, and a reference power line RL.

[0071] The gate line GL may be positioned adjacent to the first region A1 of the second region A2 of SPA6, which comprises multiple subpixel regions SPA1 to SPA6.

[0072] Each pixel circuit PC of multiple sub-pixel regions SPA1 to SPA6 may include a first switching transistor Tsw1, a second switching transistor Tsw2, a drive transistor Tdr, and a storage capacitor Cst. Each of the transistors Tsw1, Tsw2, and Tdr in the pixel circuit PC may be composed of a thin-film transistor TFT. For example, at least one of the thin-film transistors Tsw1, Tsw2, and Tdr may be an amorphous silicon (a-Si) TFT, a polysilicon (poly-Si) TFT, an oxide (Oxide) TFT, or an organic (Organic) TFT. For example, in the pixel circuit PC, some of the first switching transistor Tsw1, the second switching transistor Tsw2, and the drive transistor Tdr may be thin-film transistors including a semiconductor layer (or active layer) made of LTPS (low-temperature poly-Si) which has excellent response characteristics. For example, the remaining components of the first switching transistor Tsw1, the second switching transistor Tsw2, and the drive transistor Tdr, excluding a portion of them, may be thin-film transistors containing a semiconductor layer (or active layer) made of an oxide with excellent off-current characteristics.

[0073] The first switching transistor Tsw1 may include a gate electrode GE, a first source / drain electrode SDE1 connected to an adjacent data line DL, and a second source / drain electrode SDE2 connected to the gate electrode GE of the drive transistor Tdr. The gate electrode GE of the first switching transistor Tsw1 may be a portion of the gate line GL. The first switching transistor Tsw1 can turn on in response to a first gate signal supplied to the gate line GL and supply a data voltage from the adjacent data line DL to the gate electrode GE of the drive transistor Tdr.

[0074] For example, the first source / drain electrode SDE1 of the first switching transistor Tsw1 located in the first sub-pixel region SPA1 may be connected to the first data line DL1 via the 1-1 contact hole CH1-1, and the first source / drain electrode SDE1 of the first switching transistor Tsw1 located in the second sub-pixel region SPA2 may be connected to the second data line DL2 via the 1-2 contact hole CH1-2. For example, the first source / drain electrode SDE1 of the first switching transistor Tsw1 located in the third sub-pixel region SPA3 may be connected to the third data line DL3 via the 1-3 contact hole CH1-3, and the first source / drain electrode SDE1 of the first switching transistor Tsw1 located in the fourth sub-pixel region SPA4 may be connected to the fourth data line DL4 via the 1-4 contact hole CH1-4. For example, the first source / drain electrode SDE1 of the first switching transistor Tsw1 located in the fifth sub-pixel region SPA5 may be connected to the fifth data line DL5 via the first-to-fifth contact holes CH1-5, and the first source / drain electrode SDE1 of the first switching transistor Tsw1 located in the sixth sub-pixel region SPA6 may be connected to the sixth data line DL6 via the first-to-sixth contact holes CH1-6.

[0075] The second switching transistor Tsw2 may include a gate electrode GE connected to the gate line GL, a first source / drain electrode SDE1 connected to the source electrode of the drive transistor Tdr, and a second source / drain electrode SDE2 connected to an adjacent reference power line RL. In display mode, such a second switching transistor Tsw2 can supply a reference voltage to the source electrode SE of the drive transistor Tdr in response to a gate signal supplied to the gate line GL. In sensing mode, the second switching transistor Tsw2 can turn on in response to a gate signal supplied to the gate line GL and supply the current output from the drive transistor Tdr to the adjacent reference power line RL, or connect the source electrode SE of the drive transistor Tdr to the adjacent reference power line RL. In each of the multiple sub-pixel regions SPA1 to SPA6, the gate electrode GE of the second switching transistor Tsw2 may be part of the gate line GL.

[0076] The second source / drain electrode SDE2 of the second switching transistor Tsw2 may be electrically connected to the reference power line RL via the reference coupling line RCL and the second contact holes CH2-1 and CH2-2. The reference coupling line RCL may be positioned alongside the gate line GL and positioned to pass through the reference power line RL, and may be electrically connected to the reference power line RL via the second contact holes CH2-1 and CH2-2.

[0077] For example, the second source / drain electrode SDE2 of a second switching transistor Tsw2 located in the first to third sub-pixel regions SPA1 to SPA3 may be connected to the first reference power line RL1 via the second-first contact hole CH2-1. For example, the second source / drain electrode SDE2 of a second switching transistor Tsw2 located in the fourth to sixth sub-pixel regions SPA4 to SPA6 may be connected to the second reference power line RL2 via the second-second contact hole CH2-2.

[0078] A storage capacitor Cst is formed between the gate electrode GE and source electrode SE of the drive transistor Tdr. For example, the storage capacitor Cst may include a first capacitor electrode consisting of the gate electrode GE of the drive transistor Tdr, a second capacitor electrode consisting of the source electrode of the drive transistor Tdr, and a dielectric layer formed in the superposition region of the first and second capacitor electrodes. Such a storage capacitor Cst can charge the voltage difference between the gate electrode GE and source electrode SE of the drive transistor Tdr, and then switch the drive transistor Tdr using the charged voltage.

[0079] The drive transistor Tdr may include a gate electrode GE connected to the second source / drain electrode SDE2 of the first switching transistor Tsw1, a source electrode SE connected to the first source / drain electrode SDE1 of the second switching transistor Tsw2, and a drain electrode DE connected to the pixel power line PL. The drive transistor Tdr may be electrically connected to the light-emitting element layer. The source electrode SE and drain electrode DE of the drive transistor Tdr may be located on the same layer as multiple data lines DL, the pixel power line PL, and the reference power line RL. The gate electrode GE of the drive transistor Tdr may be located on the same layer as the gate line GL. The drive transistor Tdr controls the amount of current flowing from the pixel power line PL to the light-emitting element layer by being turned on by the voltage of the storage capacitor Cst.

[0080] The drain electrode DE of the drive transistor Tdr located in the first and second sub-pixel regions SPA1 and SP2 of the multiple sub-pixel regions SPA1 to SPA6 may be connected to the first pixel power line PL1 via the internal power line IPL. The drain electrode DE of the drive transistor Tdr located in the first and second sub-pixel regions SPA1 and SP2 of the multiple sub-pixel regions SPA1 to SPA6 may be a protruding region that extends beyond the internal power line IPL. The drain electrode DE of the drive transistor Tdr located in the third to sixth sub-pixel regions SPA3 to SP6 of the multiple sub-pixel regions SPA1 to SPA6 may be connected to the second pixel power line PL2 via the internal power line IPL. The drain electrode DE of the drive transistor Tdr located in the third to sixth sub-pixel regions SPA3 to SP6 of the multiple sub-pixel regions SPA1 to SPA6 may be a protruding region that extends beyond the internal power line IPL.

[0081] According to embodiments of this specification, the light-emitting display device may include an auxiliary line SL. The auxiliary line SL may be superimposed on a pixel drive line PDL. The auxiliary line SL may be superimposed on one or more of a plurality of pixel power lines PL, a plurality of data lines DL, and a plurality of reference power lines RL.

[0082] Two adjacent data lines DL may be located between two adjacent subpixels 12a to 12f. An auxiliary line SL may overlap one or more of the two adjacent data lines.

[0083] Adjacent first data line DL1 and second data line DL2 among multiple data lines DL may be positioned between the first subpixel 12a and the second subpixel 12b among multiple subpixels 12a to 12f. The auxiliary line SL may superimpose one or more of the first data line DL1 and the second data line DL2. For example, the auxiliary line SL may superimpose the second data line DL2 among the first data line DL1 and the second data line DL2. As another example, the auxiliary line SL may superimpose the first data line DL1 among the first data line DL1 and the second data line DL2.

[0084] The adjacent third data line DL3 and fourth data line DL4 among the multiple data lines DL may be positioned between the third subpixel 12c and fourth subpixel 12d among the multiple subpixels 12a to 12f. The auxiliary line SL may overlap with one or more of the third data line DL3 and fourth data line DL4. For example, the auxiliary line SL may overlap with the fourth data line DL4 among the third data line DL3 and fourth data line DL4. As another example, the auxiliary line SL may overlap with the third data line DL3 among the third data line DL3 and fourth data line DL4.

[0085] The adjacent fifth data line DL5 and sixth data line DL6 among the multiple data lines DL may be positioned between the fifth subpixel 12e and the sixth subpixel 12f among the multiple subpixels 12a to 12f. The auxiliary line SL may overlap one or more of the fifth data line DL5 and the sixth data line DL6. For example, the auxiliary line SL may overlap the sixth data line DL6 among the fifth data line DL5 and the sixth data line DL6. As another example, the auxiliary line SL may overlap the fifth data line DL5 among the fifth data line DL5 and the sixth data line DL6.

[0086] Each of the auxiliary line SL and the multiple data lines DL may be electrically connected via the third-first contact hole CH3-1. According to the embodiments herein, the electrical connection of the auxiliary line SL and the multiple data lines DL can reduce the resistance of each of the multiple data lines DL.

[0087] Multiple pixel power lines PL may be configured for each of the multiple pixels. An auxiliary line SL may be superimposed on each of the multiple pixel power lines PL. An auxiliary line SL may be placed above each of the multiple pixel power lines PL. An auxiliary line SL may be placed above the first pixel power line PL1. The first pixel power line PL1 may be superimposed on the auxiliary line SL. An auxiliary line SL may be placed above the second pixel power line PL2. The second pixel power line PL2 may be superimposed on the auxiliary line SL.

[0088] The pixel power line PL and the auxiliary line SL positioned on the pixel power line PL may be electrically connected via the third-third contact hole CH3-2. According to the embodiments herein, the electrical connection of the auxiliary line SL and the pixel power line PL can reduce the resistance of each of the multiple pixel power lines PL.

[0089] Multiple reference power lines RL may be configured for each of multiple pixels. An auxiliary line SL may be superimposed on each of the multiple reference power lines RL. An auxiliary line SL may be placed above each of the multiple reference power lines RL. An auxiliary line SL may be placed above the first reference power line RL1. The first reference power line RL1 may be superimposed on the auxiliary line SL. An auxiliary line SL may be placed above the second reference power line RL2. The second reference power line RL2 may be superimposed on the auxiliary line SL.

[0090] The reference power line RL and the auxiliary line SL positioned on the reference power line RL may be electrically connected via the third-third contact hole CH3-3. According to the embodiments herein, the electrical connection of the auxiliary line SL and the reference power line RL can reduce the resistance of each of the multiple reference power lines RL.

[0091] According to the embodiments of this specification, auxiliary lines SL are arranged on the pixel drive line PDL, and the resistance of the pixel drive line PDL can be reduced by electrically connecting the auxiliary lines SL arranged on the pixel drive line PDL to each of the pixel drive lines PDL.

[0092] The auxiliary line SL may be located in the same layer as the gate electrode GE and gate line GL. The auxiliary line SL may contain the same material as the gate electrode GE and gate line GL and be constructed using the same masking process. Therefore, the light-emitting device can place the auxiliary line SL on the pixel drive line PDL without a separate masking process.

[0093] According to the embodiments of this specification, the source / drain electrodes of the pixel drive line PDL and transistors Tsw1, Tsw2, and Tdr may be arranged on the substrate. A buffer layer may be arranged on the source / drain electrodes of the pixel drive line PDL and transistors Tsw1, Tsw2, and Tdr. The semiconductor layer has a source region, a drain region, and a channel region, and the semiconductor channel region may be covered with an insulating layer. The gate line GL, gate electrode GE, and auxiliary line SL may each be arranged on an insulating layer. The auxiliary line SL can separate the color filter layer arranged after the auxiliary line SL for each pixel and create grooves in the overcoat layer. The source / drain electrodes of the pixel drive line PDL and transistors Tsw1, Tsw2, and Tdr, the gate line GL, gate electrode GE, and auxiliary line SL may be covered with a passivation layer and an overcoat layer. In the first region A1, a color filter layer may be formed between the passivation layer and the overcoat layer. A light-emitting layer including an anode electrode AE ​​connected to transistors Tsw1, Tsw2, and Tdr may be formed on the overcoat layer. The configuration and effects of the auxiliary lines and grooves of such light-emitting devices according to the embodiments of this specification will be described in detail below with reference to Figures 3 to 5.

[0094] Figure 3 is a cross-sectional view along the line I-I' shown in Figure 2. Figure 4 is a cross-sectional view showing an example of area A shown in Figure 2. Figure 5 is a cross-sectional view showing an example of area B shown in Figure 2. These show the cross-section of a single pixel in the light-emitting display device according to the embodiments of this specification described with reference to Figures 1 and 2. Therefore, substantially the same components are denoted by the same reference numerals below, and redundant descriptions are either briefly described or omitted.

[0095] Referring to Figures 3 to 5, the light-emitting display device according to the embodiment of this specification may include a substrate 100, a pixel drive line PDL, a buffer layer 110, an insulating layer 130, an auxiliary line SL, a passivation layer 120, a color filter layer CFL, an overcoat layer 140, a groove 145, and a light-emitting element layer EDL.

[0096] The substrate 100 contains transistors and may be a transistor array substrate, a lower substrate, a base substrate, or a first substrate. The substrate 100 may be a transparent glass substrate or a transparent plastic substrate.

[0097] The substrate 100 may include a plurality of pixels 12. Each of the plurality of pixels 12 may include a plurality of subpixels 12a, 12b, and 12c. The plurality of subpixels 12a, 12b, and 12c may be a first subpixel 12a, a second subpixel 12b, and a third subpixel 12c.

[0098] Each of the multiple subpixels 12a, 12b, and 12c may include an light-emitting part EP and a non-light-emitting part NEP. The light-emitting part EP may be superimposed on the light-emitting element layer EDL. The non-light-emitting part NEP may be superimposed on the pixel drive line PDL. For example, in the first subpixel region SPA1, the non-light-emitting part NEP may be superimposed on the first pixel power line PL1 and the first data line DL1. In the second subpixel region SPA2, the non-light-emitting part NEP may be superimposed on the second data line DL2 and the first reference power line RL1. In the third subpixel region SPA3, the non-light-emitting part NEP may be superimposed on the first reference power line RL1 and the third data line DL3.

[0099] In a single pixel 12-1, the pixel drive line PDL may include a pixel power line PL1, a plurality of data lines DL, and a reference power line RL1. The pixel power line PL1, the plurality of data lines DL, and the reference power line RL1 may be arranged in a first direction X on the substrate 100. For example, in a single pixel 12-1, the pixel power line PL1 and the reference power line RL1 may be arranged spaced apart from each other. In a single pixel 12-1, the plurality of data lines DL may be arranged between the pixel power line PL1 and the reference power line RL1.

[0100] The pixel power line PL1, the multiple data lines DL, and the reference power line RL1 may be arranged on the same layer. The pixel power line PL1, the multiple data lines DL, and the reference power line RL1 may contain the same material and be formed by the same process. For example, the pixel power line PL1, the multiple data lines DL, and the reference power line RL1 may contain molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), tungsten (W), or compounds or alloys thereof, and may be configured to have a single layer or a multilayer structure of two or more layers of the said metal or alloy. For example, the pixel power line PL1, the multiple data lines DL, and the reference power line RL1 may be configured to have a multilayer structure of two or more layers, such as Cu / MoTi. For example, the pixel power line PL1, the multiple data lines DL, and the reference power line RL1 may be configured to have a multilayer structure of two or more layers containing a low-reflectivity material such as tungsten(W) oxide.

[0101] The buffer layer 110 may be formed on the substrate 100. The buffer layer 110 may be placed on the light-emitting portion EP and the non-light-emitting portion NEP of the substrate 100, respectively.

[0102] According to one embodiment of this specification, the buffer layer 110 may be configured over the entire surface of the light-emitting section EP. The buffer layer 110 can cover the pixel drive line PDL located in the non-light-emitting section NEP. The buffer layer 110 can cover the entire surface of the pixel drive line PDL that does not overlap with the auxiliary line SL. The buffer layer 110 can cover the upper surface of the pixel drive line PDL that overlaps with the auxiliary line SL. The buffer layer 110 can cover the upper surface of the first data line DL1 which does not have an auxiliary line SL. The buffer layer 110 can cover the upper surface of the second data line DL2 which has an auxiliary line SL configured on its upper surface.

[0103] Therefore, a separation region SA, in which the buffer layer 110 is not present, may be placed between the first data line DL1, which does not have an auxiliary line SL on its upper surface, and the second data line DL2, which has an auxiliary line SL on its upper surface. The separation region SA may be a region on the upper surface of the substrate 100 in which the buffer layer 110 is not present. The separation region SA may be a region in contact with the color filter layer CFL, which will be described later.

[0104] The buffer layer 110 can prevent substances contained in the substrate 100 from diffusing into the active layer of the transistor during high-temperature processes in the manufacturing process of thin-film transistors. For example, the buffer layer 110 can contain inorganic materials such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0105] The insulating layer 130 may be placed in the non-light-emitting section NEP. The insulating layer 130 may be placed between the auxiliary line SL and the pixel drive line PDL. The insulating layer 130 may be placed between the buffer layer 110 and the auxiliary line SL. The insulating layer 130 may be configured as an island below the auxiliary line SL. The insulating layer 130 may be placed in the same layer as the gate insulating layer, which is configured as an island below the gate electrode. The insulating layer 130 may contain the same material as the gate insulating layer and be formed in the same process.

[0106] The buffer layer 110 and the insulating layer 130 may have a width smaller than the pixel drive line PDL. The buffer layer 110 and the insulating layer 130 may have a width smaller than the underside of the pixel drive line PDL. The buffer layer 110 and the insulating layer 130 may have a width smaller than the auxiliary line SL. The buffer layer 110 and the insulating layer 130 may have a width smaller than the underside of the auxiliary line SL.

[0107] According to one embodiment of this specification, by having the buffer layer 110 and the insulating layer 130 have a width smaller than the auxiliary line SL, the buffer layer 110, the insulating layer 130, and the auxiliary line SL may have an undercut shape. Therefore, in subsequent steps, the color filters CFr, CFg, and CFb formed on each subpixel can be easily separated. For example, the color filters CFr, CFg, and CFb of adjacent color filter layers CFL can be separated from each other by the auxiliary line SL. The color filters CFr, CFg, and CFb of adjacent color filter layers CFL do not need to be in contact with each other by the auxiliary line SL.

[0108] The auxiliary line SL may be arranged on the substrate 100 in a first direction X. The auxiliary line SL may be arranged on the pixel drive line PDL. The auxiliary line SL may be superimposed on the pixel drive line PDL. The auxiliary line SL may be superimposed on one or more of the multiple data lines DL, pixel power line PL, and reference power line RL. The auxiliary line SL may be superimposed on one of the multiple data lines DL, data line DL2, the first pixel power line PL1, and the first reference power line RL1, respectively. For example, there may be multiple auxiliary lines SL, and each of the multiple auxiliary lines SL may be superimposed on one of the multiple data lines DL, data line DL2, the first pixel power line PL1, and the first reference power line RL1, respectively. Therefore, the auxiliary line SL may be arranged between each sub-pixel region SPA1 to SPA3.

[0109] The auxiliary line SL may have the same width as the pixel drive line PDL. For example, the width of the auxiliary line SL placed on the first pixel power line PL1 may be the same as the width of the first pixel power line PL1. The width W1 of the auxiliary line SL placed on the second data line DL2 may be the same as the width W2 of the second data line DL2. The width W1 of the auxiliary line SL placed on the first reference power line RL1 may be the same as the width W3 of the first reference power line RL1.

[0110] The auxiliary line SL may have the same shape as the pixel drive line PDL. For example, the auxiliary line SL and the pixel drive line PDL may have an inclined surface where the width of the top surface is smaller than the width of the bottom surface and the sides are sloped. For example, the auxiliary line SL and the pixel drive line PDL may have a tapered shape.

[0111] According to one embodiment of this specification, the light-emitting display device includes auxiliary lines SL and pixel drive lines PDL having the same width and tapered shape, so that a subsequently placed color filter layer CFL can easily come into contact with the respective sides of the auxiliary lines SL and pixel drive lines PDL, and the ends of the color filter layer CFL may be configured to have inclined surfaces.

[0112] Furthermore, according to one embodiment of this specification, the light-emitting device may include an auxiliary line SL and a pixel driving line PDL having the same width and tapered shape. Therefore, when light emitted from the light-emitting layer EL is reflected by the cathode electrode CE and propagates downward, the light does not propagate to the adjacent pixel region, but is re-reflected by the side of the auxiliary line SL and emitted to the corresponding pixel region. Thus, the light extraction efficiency of the light-emitting device can be improved.

[0113] The passivation layer 120 may be placed on the buffer layer 110. The passivation layer 120 can cover the pixel drive line PDL that does not overlap with the auxiliary line SL. The passivation layer 120 can cover the first data line DL that does not overlap with the auxiliary line SL. The passivation layer 120 does not have to be configured above the auxiliary line SL. The passivation layer 120 can be separated from the auxiliary line SL. The passivation layer 120 does not have to be configured above the second data line DL2, the first pixel power line PL1, and the first reference power line RL1 that overlap with the auxiliary line SL. The passivation layer 120 does not have to be configured in the separation region SA on the substrate 100. The passivation layer 120 may be placed in each of the multiple sub-pixel regions SPA1 to SPA3 with the auxiliary line SL in between. Thus, the end of the subsequently configured color filter layer CFL can cover the separation region SA.

[0114] The color filter layer CFL may be placed between the substrate 100 and the overcoat layer 140. The color filter layer CFL may be interposed between the passivation layer 120 and the overcoat layer 140. The color filter layer CFL may be placed superimposed on the respective light-emitting parts EPr, EPb, and EPg of the multiple subpixel regions SPA1 to SPA3. The color filter layer CFL may have a size larger than the respective light-emitting parts EPr, EPb, and EPg of the multiple subpixel regions SPA1 to SPA3. Therefore, both ends of the color filter layer CFL may be placed in the non-light-emitting parts NEP.

[0115] The color filter layer CFL may include a red color filter CFr superimposed on the red light-emitting portion EPr of the first subpixel region SPA1, a green color filter CFg superimposed on the green light-emitting portion EPg of the second subpixel region SPA2, and a blue color filter CFb superimposed on the blue light-emitting portion EPb of the third subpixel region SPA3.

[0116] Each of the red color filter CFr, green color filter CFg, and blue color filter CFb may be larger or wider than the corresponding light-emitting units EPr, EPg, and EPb. For example, each of the red color filter CFr, green color filter CFg, and blue color filter CFb may be configured to be larger or wider than the light-emitting units EPr, EPg, and EPb in order to prevent light leakage from other adjacent subpixel regions.

[0117] According to one embodiment of this specification, the respective ends of the red color filter CFr, green color filter CFg, and blue color filter CFb can cover the sides of the pixel drive line PDL and the auxiliary line SL adjacent to each other, with the corresponding light-emitting units EPr, EPg, and EPb in between. Thus, the color filters CFr, CFg, and CFb, each located in each sub-pixel region SPA1 to SPA3, can be separated by the auxiliary line SL.

[0118] One end of the red color filter CFr can cover the side of the first pixel power line PL1 and the side of the auxiliary line SL located on the first pixel power line PL1. The other end of the red color filter CFr can cover the side of the second data line DL and the side of the auxiliary line SL located on the second data line DL.

[0119] One end of the green color filter CFg can cover the side of the second data line DL and the side of the auxiliary line SL located on the second data line DL. The other end of the green color filter CFg can cover the side of the first reference power line RL1 and the side of the auxiliary line SL located on the first reference power line RL1.

[0120] One end of the blue color filter CFb can cover the side of the first reference power line RL1 and the side of the auxiliary line SL located on the first reference power line RL1. The other end of the blue color filter CFb can cover the side of the fourth data line DL4 of an adjacent pixel and the side of the auxiliary line SL located on the fourth data line DL4.

[0121] Each of the red color filter CFr, green color filter CFg, and blue color filter CFb can cover the separation region SA between the passivation layer 120 and the pixel drive line PDL, which are separated from each other. Thus, the ends of each of the red color filter CFr, green color filter CFg, and blue color filter CFb can partially contact the upper surface of the substrate 100. Furthermore, the ends of each of the red color filter CFr, green color filter CFg, and blue color filter CFb may have inclined surfaces CFr-A, CFg-A, and CFb-A, respectively.

[0122] The auxiliary line SL and the pixel drive line PDL can protrude in the direction of the color filter layer CFL beyond the buffer layer 110 and the insulating layer 130, which are positioned between the auxiliary line SL and the pixel drive line PDL.

[0123] For example, the end of the first pixel power line PL1 adjacent to the red color filter CFr, and the end of the auxiliary line SL positioned on the first pixel power line PL1, may include protrusions that project in the direction of the red color filter CFr.

[0124] The second data line DL2 adjacent to the red color filter CFr and the green color filter CFg, and each end of the auxiliary line SL positioned on the second data line DL2, may include a protrusion DL2a projecting in the direction of the red color filter CFr and the green color filter CFg.

[0125] The first reference power line RL1 adjacent to the green color filter CFg and the blue color filter CFb, and the auxiliary line SL positioned on the first reference power line RL1, may each include protrusions RL1a and SLla projecting in the direction of the green color filter CFg and the blue color filter CFb.

[0126] Therefore, the auxiliary line SL and the pixel drive line PDL may have an undercut shape. Thus, each of the red color filter CFr, green color filter CFg, and blue color filter CFb can be inserted into the sides of the insulating layer 130 and buffer layer 110 between the auxiliary line SL and the pixel drive line PDL. Thus, each of the ends of the red color filter CFr, green color filter CFg, and blue color filter CFb has an inclined surface and can be easily separated across the auxiliary line SL. Furthermore, the overcoat layer 140, described later, may be arranged along the shape of the inclined surface formed on each of the red color filter CFr, green color filter CFg, and blue color filter CFb.

[0127] According to one embodiment of this specification, each of the red color filter CFr, green color filter CFg, and blue color filter CFb may include quantum dots having a size that re-emits light in response to light emitted from the light-emitting element layer EDL towards the substrate 100, emitting light of the hue set for the subpixel. In this case, the red color filter CFr may further include a long-wavelength absorbing material (or dye) that does not contain red quantum dots or absorbs at least a portion of the long-wavelength light, such that the transmittance (or emission rate) for light in the long-wavelength region is reduced. For example, the long-wavelength absorbing material can reduce the transmittance (or emission rate) for light in the long-wavelength region and increase the color temperature by absorbing wavelengths of 620 nm to 700 nm.

[0128] The overcoat layer 140 may be formed on the substrate 100. The overcoat layer 140 can cover the passivation layer 120 and the color filter layer CFL. The overcoat layer 140 can cover the pixel drive line PDL and the auxiliary line SL. The overcoat layer 140 may cover the pixel circuit including transistors and may be formed on the pixel circuit. The overcoat layer 140 may be formed along the shape of the upper surface of the color filter layer CFL and the auxiliary line SL. The overcoat layer 140 may be formed along the upper surface of the color filter layer CFL located in the light-emitting section EP and along the inclined surfaces CFr-A, CFg-A, and CFb-A of the color filter layer CFL located in the non-light-emitting section NEP. Therefore, the groove 145 may be formed on the upper part of the auxiliary line SL located in the non-light-emitting section NEP.

[0129] The groove 145 may be located in the non-emitting portion NEP of the substrate 100. The groove 145 may overlap with the edge of the color filter layer CFL and the auxiliary line SL. The groove 145 is made up of the overcoat layer 140 and may have a shape that is recessed from the upper surface to the lower surface of the overcoat layer 140. The groove 145 may be formed along the edge of the color filter layer CFL and the auxiliary line SL. Thus, the groove 145 may include at least two or more inclined portions 145a, 145b and connecting portions 145c that connect at least two or more inclined portions. One or more of the at least two or more inclined portions 145a, 145b may overlap with the edge of adjacent color filters CFr, CFg, CFb.

[0130] According to one embodiment of this specification, the groove 145 may include a first inclined portion 145a, a second inclined portion 145b, and a first connecting portion 145c.

[0131] In the first sub-pixel region SPA1 and the second sub-pixel region SPA2, the first inclined portion 145a may be superimposed on the red color filter CFr. For example, the red color filter CFr may be configured to fill the separation region SA between the passivation layer 120 and the second data line DL2, and to cover one side of the second data line DL2 and the auxiliary line SL. Thus, the red color filter CFr may have an inclined surface CFr-A superimposed on the separation region SA between the passivation layer 120 and the second data line DL2. Since the overcoat layer 140 is configured along the color filter layer CFL and the auxiliary line SL, the first inclined portion 145a of the groove 145 may be configured to correspond to the inclined surface CFr-A of the red color filter CFr.

[0132] In the first sub-pixel region SPA1 and the second sub-pixel region SPA2, the second inclined portion 145b may be superimposed on the green color filter CFg. For example, the green color filter CFg may be configured to fill the separation region SA between the passivation layer 120 and the second data line DL2, and to cover the other sides of the second data line DL2 and the auxiliary line SL. Thus, the green color filter CFg may have an inclined surface CFg-A superimposed on the separation region SA between the passivation layer 120 and the second data line DL2. Since the overcoat layer 140 is configured along the color filter layer CFL and the auxiliary line SL, the second inclined portion 145b may be configured to correspond to the inclined surface CFg-A of the green color filter CFg.

[0133] In the first sub-pixel region SPA1 and the second sub-pixel region SPA2, the first connecting portion 145c can connect the first inclined portion 145a and the second inclined portion 145b. The first connecting portion 145c may also be superimposed on the auxiliary line SL. The first connecting portion 145c may also be superimposed on the pixel drive line PDL or the second data line DL2.

[0134] In the second sub-pixel region SPA2 and the third sub-pixel region SPA3, the first inclined portion 145a may be superimposed on the green color filter CFg. For example, the green color filter CFg may be configured to fill the separation region SA between the passivation layer 120 and the first reference power line RL1, and to cover one side of the first reference power line RL1 and the auxiliary line SL. Thus, the green color filter CFg may have an inclined surface CFg-A superimposed on the separation region SA between the passivation layer 120 and the first reference power line RL1. Since the overcoat layer 140 is configured along the color filter layer CFL and the auxiliary line SL, the first inclined portion 145a may be configured to correspond to the inclined surface CFg-A of the green color filter CFg.

[0135] In the second sub-pixel region SPA2 and the third sub-pixel region SPA3, the second inclined portion 145b may be superimposed on the blue color filter CFb. For example, the blue color filter CFb may be configured to fill the separation region SA between the passivation layer 120 and the first reference power line RL1, and to cover the other sides of the first reference power line RL1 and the auxiliary line SL. Thus, the blue color filter CFb may have an inclined surface CFb-A superimposed on the separation region SA between the passivation layer 120 and the first reference power line RL1. Since the overcoat layer 140 is configured along the color filter layer CFL and the auxiliary line SL, the second inclined portion 145b may be configured to correspond to the inclined surface CFb-A of the blue color filter CFb.

[0136] In the second sub-pixel region SPA2 and the third sub-pixel region SPA3, the first connecting portion 145c can connect the first inclined portion 145a and the second inclined portion 145b. The first connecting portion 145c may also be superimposed on the auxiliary line SL. The first connecting portion 145c may also be superimposed on the pixel drive line PDL or the first reference power supply line RL1.

[0137] According to one embodiment of this specification, the groove 145 may be formed along the shape of the color filter layer CFL and the auxiliary line SL without using a separate masking process (or halftone masking process). Subsequently, the cathode electrode formed along the groove 145 allows the light-emitting device of this specification to have a mirror structure that can improve the light extraction efficiency of the light-emitting device without increasing the manufacturing process and cost.

[0138] The light-emitting element layer EDL may be placed on the overcoat layer 140. The light-emitting element layer EDL may be configured in each light-emitting section EP of a plurality of sub-pixel regions SPA1 to SPA3. The light-emitting element layer EDL may be connected to the pixel circuit. The light-emitting element layer EDL may include an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE.

[0139] The anode electrode AE ​​may be individually arranged on the overcoat layer 140 on the substrate 100, corresponding to each light-emitting portion EP of the multiple subpixel regions SPA1 to SPA3. For example, the anode electrode AE ​​may have a size and shape corresponding to each light-emitting portion EP of the multiple subpixel regions SPA1 to SPA3. The anode electrode AE ​​may be made of a transparent conductive material such as TCO (Transparent Conductive Oxide) so that light emitted from the light-emitting layer EL can be transmitted to the outside.

[0140] The anode electrode AE ​​can directly contact the uppermost surface of the overcoat layer 140. For example, the anode electrode AE ​​may be configured to have a shape corresponding to the surface shape (morphology) of the overcoat layer 140. For example, each anode electrode AE ​​of a plurality of sub-pixel regions SPA1 to SPA3 may include an extension that extends toward the corresponding pixel circuit. The extension of the anode electrode AE ​​may be electrically connected to the source or drain electrode of the drive transistor of the corresponding pixel circuit via electrode contact holes located in the overcoat layer 140 and the passivation layer 120. Thus, each anode electrode AE ​​of a plurality of sub-pixel regions SPA1 to SPA3 can individually receive data current from the drive transistor of the corresponding pixel circuit.

[0141] The anode electrode AE ​​can be separated from the groove 145. The groove 145 does not necessarily have to contain the anode electrode AE. Therefore, the light emitted from the light-emitting layer EL can be easily reflected by the cathode electrode CE and emitted downwards.

[0142] The light-emitting layer EL of the light-emitting element layer EDL may be formed over the entire surface of the first to third sub-pixel regions SPA1 to SPA3. The light-emitting layer EL may be formed on the anode electrode AE, the overcoat layer 140, and the groove 145, which are arranged in each of the first to third sub-pixel regions SPA1 to SPA3.

[0143] The light-emitting layer (EL) may be an organic light-emitting element, a quantum dot light-emitting element, an inorganic light-emitting element, or a microlight-emitting diode element. For example, a light-emitting layer (EL) made of an organic light-emitting element may include a hole functional layer disposed on the anode electrode, an organic light-emitting layer disposed on the hole functional layer, and an electronic functional layer disposed on the organic light-emitting layer.

[0144] According to the embodiments of this specification, the light-emitting layers EL located in each of the first to third subpixel regions SPA1 to SPA3 may be arranged to emit light of different hues. For example, the light-emitting layer EL of the first subpixel region SPA1 may include a red organic light-emitting layer, the light-emitting layer EL of the second subpixel region SPA2 may include a green organic light-emitting layer, and the light-emitting layer EL of the third subpixel region SPA3 may include a blue organic light-emitting layer.

[0145] In other examples, the light-emitting layers EL located in each of the first to third subpixel regions SPA1 to SPA3 may be located in a common layer that emits white light. For example, the light-emitting layers EL located in each of the first to third subpixel regions SPA1 to SPA3 may include a first organic light-emitting layer and the second organic light-emitting layer, or may include the first organic light-emitting layer, the second organic light-emitting layer and the third organic light-emitting layer. In this case, the light-emitting layers EL can be in direct contact with the anode electrodes AE located in each of the first to third subpixel regions SPA1 to SPA3.

[0146] Additionally, the light-emitting layers EL located in each of the first to third subpixel regions SPA1 to SPA3 may further include quantum dot light-emitting layers to be converted into quantum dot light-emitting elements or to improve color reproduction.

[0147] The cathode electrode CE of the light-emitting element layer EDL may be arranged across the entire display area of ​​the substrate 100 so as to be in direct contact with the light-emitting layer EL. In one example, the cathode electrode CE may include a highly reflective metallic material to reflect the light emitted from the light-emitting layer EL and incident toward the substrate 100.

[0148] The light-emitting layer EL and the cathode electrode CE may be superimposed on the groove 145. The light-emitting layer EL and the cathode electrode CE may be configured to follow the shape of the groove 145. Therefore, the light-emitting layer EL and the cathode electrode CE superimposed on the groove 145 may have at least two inclined portions and connecting portions that connect at least two inclined portions. For example, a portion of the light emitted from the light-emitting layer EL may be primary reflected by the cathode electrode CE superimposed on the groove 145. A portion of the light primary reflected by the cathode electrode CE can pass through the color filter layer CFL and be emitted towards the substrate 100. The remaining portion of the light primary reflected by the cathode electrode CE may be secondary reflected by the auxiliary line SL. The light secondary reflected by the auxiliary line SL has its optical path changed and can pass through the color filter layer CFL and be emitted towards the substrate 100.

[0149] According to one embodiment of this specification, the light-emitting display device includes an auxiliary line SL superimposed on a pixel drive line PDL, thereby enabling the formation of grooves 145 between each subpixel without the need for an additional masking process. This allows for the control of the reflection direction of light emitted from a subpixel toward an adjacent subpixel, thereby improving the light extraction efficiency of the light-emitting display device.

[0150] According to one embodiment of this specification, the light-emitting display device includes an auxiliary line SL and a groove 145 superimposed on the pixel drive line PDL, enabling light extraction even in non-light-emitting areas. Therefore, it can have equivalent or even higher luminous efficiency at lower power consumption compared to a display device without the auxiliary line and groove. Thus, overall power consumption can be reduced.

[0151] According to one embodiment of this specification, the light-emitting display device includes an auxiliary line SL superimposed on the pixel drive line PDL and a groove 145, thereby enabling all light that would otherwise be lost due to the waveguide and light that would otherwise be lost due to total internal reflection within the substrate to be emitted to the outside. Thus, the light extraction efficiency can be maximized.

[0152] According to one or more embodiments of this specification, the light-emitting display device includes an auxiliary line SL superimposed on the pixel drive line PDL and a groove 145, thereby enabling the formation of grooves between each subpixel without the need for an additional masking process (e.g., a halftone masking process). Thus, the light extraction efficiency of the light-emitting display device can be improved without increasing the manufacturing process and costs.

[0153] According to the embodiments herein, the display panel 10 may further include an encapsulation layer 160. The encapsulation layer 160 may be formed on the display area of ​​the substrate 100 so as to cover the cathode electrode CE. The encapsulation layer 160 can protect the thin-film transistor and the light-emitting layer EL from external impacts and prevent oxygen and / or moisture, as well as foreign matter (particles), from penetrating the light-emitting layer EDL. For example, the encapsulation layer 160 may include at least one inorganic film. For example, the encapsulation layer 160 may further include at least one organic film. For example, the encapsulation layer 160 may include, but is not limited to, a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

[0154] Selectively, the sealing layer 160 may be replaced with a filler material that surrounds the entire pixel. In this case, the display panel 10 according to the embodiments herein may further include a sealing substrate 170 that is attached to the substrate 100 via the filler material. The sealing substrate 170 may be made of a plastic, glass, or metal material. For example, the filler material may, but is not limited to, a getter material that absorbs oxygen and / or moisture.

[0155] Figure 6 shows another example (second embodiment) of the pixel arrangement structure shown in Figure 1. Figure 7 is a cross-sectional view of line II-II' shown in Figure 2. Figure 8 is a cross-sectional view showing an example of region C shown in Figure 7. In this example, in the light-emitting display device shown in Figures 1 to 5, auxiliary lines are connected to each of several adjacent data lines. Therefore, in the following description, only the auxiliary lines and related configurations will be described, and the remaining configurations will be given the same reference numerals as in Figures 1 to 5, and redundant explanations will be simplified or omitted.

[0156] Referring to Figures 6 to 8, the light-emitting display device according to this specification may include an auxiliary line SL. The auxiliary line SL may be superimposed on a pixel drive line PDL. Two adjacent data lines among a plurality of data lines DL may be configured between two adjacent subpixels among a plurality of subpixels 12a, 12b, and 12c. The auxiliary line SL may be superimposed on two adjacent data lines DL. The auxiliary line SL may be superimposed on the first data line DL1 to the sixth data line DL6, respectively. The auxiliary line SL may be superimposed on adjacent pixel power lines PL and reference power lines RL, respectively. The auxiliary line SL may be positioned above each of the pixel power lines PL and reference power lines RL.

[0157] According to the embodiments of this specification, the buffer layer 110 can cover the pixel drive line PDL. The buffer layer 110 may be placed between the pixel drive line PDL and the auxiliary line SL. The buffer layer 110 may be placed on top of the pixel drive line PDL that is superimposed on the auxiliary line SL. The buffer layer 110 may be placed on top of the first data line DL1, the second data line DL2, the first pixel power line PL1, and the first reference power line RL1. The buffer layer 110 may be placed between the first data line DL1 and the second data line DL2 which are adjacent to each other. The buffer layer 110 can cover one side of the first data line DL1 and the second data line DL2 which are adjacent to each other. The buffer layer 110 does not have to be configured on the other side of the first data line DL1 and the second data line DL2 which are adjacent to the color filter layer CFL. Therefore, a separation region SA in which the buffer layer 110 is not formed may be placed on the substrate 100. The separation region SA may be covered with a color filter layer CFL, as described later.

[0158] The auxiliary line SL may be positioned on the substrate 100 in a first direction X. The auxiliary line SL may be positioned on the pixel drive line PDL. The auxiliary line SL may be superimposed on the pixel drive line PDL. The auxiliary line SL may be superimposed on multiple data lines DL, pixel power line PL, and reference power line RL.

[0159] The passivation layer 120 may be placed on the buffer layer 110. The passivation layer 120 may be placed between adjacent first data line DL1 and second data line DL2. The passivation layer 120 can cover the sides of adjacent insulating layers 130. The passivation layer 120 can cover the sides and parts of the top surfaces of adjacent auxiliary lines SL. The passivation layer 120 does not have to be placed in the separation region SA formed on the top surface of the substrate 100.

[0160] According to this example, the respective ends of the red color filter CFr, the green color filter CFg, and the blue color filter CFb can cover the sides of the pixel drive line PDL and the auxiliary line SL that are adjacent to each other, flanking the corresponding light-emitting units EPr, EPg, and EPb.

[0161] For example, one end of the red color filter CFr can cover the side of the first pixel power line PL1 and the side of the auxiliary line SL located on the first pixel power line PL1. The other end of the red color filter CFr can cover the side of the first data line DL1 and the side of the auxiliary line SL located on the first data line DL1.

[0162] For example, one end of the green color filter CFg can cover the side of the second data line DL2 and the side of the auxiliary line SL located on the second data line DL2. The other end of the green color filter CFg can cover the side of the first reference power line RL1 and the side of the auxiliary line SL located on the first reference power line RL1.

[0163] For example, one end of the blue color filter CFb can cover the side of the first reference power line RL1 and the side of the auxiliary line SL located on the first reference power line RL1. The other end of the blue color filter CFb can cover the side of the third data line DL3 of an adjacent pixel and the side of the auxiliary line SL located on the third data line DL3.

[0164] Each of the red color filter CFr, green color filter CFg, and blue color filter CFb can cover the separation region SA between the passivation layer 120 and the pixel drive line PDL, which are separated from each other. Therefore, each of the red color filter CFr, green color filter CFg, and blue color filter CFb can be in partial contact with the upper surface of the substrate 100. Thus, each of the color filters CFr, CFg, and CFb located in each sub-pixel region SPA1 to SPA3 can be separated by the pixel drive line PDL and the auxiliary line SL.

[0165] According to one embodiment of this specification, the auxiliary line SL and the pixel drive line PDL can protrude in the direction of the color filter layer CFL beyond the buffer layer 110 and the insulating layer 130 positioned between the auxiliary line SL and the pixel drive line PDL.

[0166] The ends of the first data line DL1 adjacent to the red color filter CFr and the auxiliary line SL positioned on the first data line DL1 can protrude in the direction of the red color filter CFr. The ends of the second data line DL2 adjacent to the green color filter CFg and the auxiliary line SL positioned on the second data line DL2 can protrude in the direction of the green color filter CFg.

[0167] According to this example, the groove 145 may include first to fourth inclined portions 145a to 145d and first to third connecting portions 145e to 145g.

[0168] In the first sub-pixel region SPA1 and the second sub-pixel region SPA2, the first inclined portion 145a may be superimposed on a red color filter CFr. The first inclined portion 145a can correspond to the inclined surface CFr-A of the red color filter CFr. The second inclined portion 145b may be superimposed on a green color filter CFg. The second inclined portion 145b can correspond to the inclined surface CFg-A of the green color filter CFg. The third and fourth inclined portions 145c and 145d can correspond to the inclined surfaces of the passivation layer 120 positioned between the adjacent first data line DL1 and second data line DL2. The first connecting portion 145e connects the first inclined portion 145a and the third inclined portion 145c, the second connecting portion 145f connects the third inclined portion 145c and the fourth inclined portion 145d, and the third connecting portion 145g can connect the fourth inclined portion 145d and the second inclined portion 145b.

[0169] According to this example, the groove 145 can be formed along the shape of the color filter layer CFL and the auxiliary line SL without using a separate masking process (or halftone masking process).

[0170] The cathode electrode CE may be superimposed on the groove 145. The cathode electrode CE may be configured to follow the shape of the groove 145. Therefore, the cathode electrode CE superimposed on the groove 145 may include four inclined portions and three connecting portions.

[0171] The light-emitting device according to the second embodiment of this specification can have the same effects as the light-emitting device according to the first embodiment of this specification.

[0172] According to the second embodiment of this specification, an auxiliary line SL may be configured for each of the multiple data lines DL, and a buffer layer 110 and a passivation layer 120 may be placed between adjacent data lines DL. This reduces the step difference between the multiple data lines DL during the subsequent process of forming the overcoat layer 140. Furthermore, the inclined surface of the groove 145 can be increased during the process of forming the overcoat layer 140, and the reflective surface of the cathode electrode CE corresponding to the inclined surface of the groove 145 can be increased during the process of forming the cathode electrode CE. This allows all light that would otherwise be lost due to the waveguide and light that would otherwise be lost due to total internal reflection within the substrate to be emitted to the outside. This maximizes the light extraction efficiency.

[0173] Figure 9 is a cross-sectional view showing another example of region C shown in Figure 7. In this example, the width of the auxiliary lines of the light-emitting display device shown in Figures 6 to 8 has been changed. Therefore, in the following description, only the auxiliary lines and related components will be described, and the remaining components will be given the same reference numerals as in Figures 6 to 8, with redundant explanations being simplified or omitted.

[0174] Referring to Figure 9, the light-emitting display device according to this example may include an auxiliary line SL. The auxiliary line SL may have a different width from the pixel drive line PDL. The width W1 of the auxiliary line SL may be smaller than the width W2 of the pixel drive line PDL. For example, the width W1 of each auxiliary line SL arranged on multiple data lines DL may be smaller than the width W2 of each of the multiple data lines DL. Therefore, the sides of the auxiliary line SL and pixel drive line PDL according to this example may have a gentler slope than the sides of the auxiliary line SL and pixel drive line PDL described with reference to Figures 6 to 8.

[0175] The color filter layer CFL can be formed along the sides of the auxiliary line SL and the pixel drive line PDL. For example, the ends of the red color filter CFr and the green color filter CFg can cover the sides of the pixel drive line PDL and the auxiliary line SL adjacent to each other, with the corresponding light-emitting units EPr and EPg in between.

[0176] According to this example, the light-emitting display device can be configured such that the slope of the color filter layer CFL covering the sides of the pixel drive line PDL and the auxiliary line SL is gentle by configuring the width W1 of the auxiliary line SL to be smaller than the width W2 of the pixel drive line PDL. Therefore, the shape of the groove 145 and cathode electrode CE that are subsequently placed can be changed. For example, the angle of the inclined surface of the groove 145 can be made gentle, and the angle of the reflective surface of the cathode electrode CE can be made gentle.

[0177] According to this example, by configuring the width W1 of the auxiliary line SL to be smaller than the width W2 of the pixel drive line PDL, the angle of the inclined surface of the groove 145 and the reflective surface of the cathode electrode CE can be adjusted, thereby further improving the light extraction efficiency of the light emitted from the light-emitting layer EL.

[0178] Figure 10 is a cross-sectional view showing another example of area B shown in Figure 2. In this example, the shapes of the pixel drive lines and auxiliary lines of the light-emitting display device shown in Figures 2 to 5 have been changed. Therefore, in the following description, only the shapes of the pixel drive lines and auxiliary lines and related configurations will be described, and the remaining configurations will be given the same reference numerals as in Figures 6 to 8, with redundant explanations being simplified or omitted.

[0179] Referring to Figure 10, according to this example, the auxiliary line SL may have the same shape as the pixel drive line PDL. For example, the auxiliary line SL and the pixel drive line PDL may have vertical surfaces, where the width of the top surface is the same as the width of the bottom surface and the sides are vertical. For example, the cross-sections of the auxiliary line SL and the pixel drive line PDL may each be rectangular.

[0180] Therefore, in the light-emitting display device according to this specification, since the sides of the auxiliary line SL and the pixel drive line PDL have vertical surfaces, when light emitted from the light-emitting layer EL is reflected by the cathode electrode CE and propagates downward, the emitted light does not propagate to an adjacent pixel area, but is re-reflected by any one of the sides of the auxiliary line SL and the pixel drive line PDL, and can be emitted from the pixel area corresponding to the light-emitting layer EL that emitted the light.

[0181] Furthermore, in the light-emitting display device according to this specification, since the sides of the auxiliary line SL and the pixel drive line PDL are perpendicular, a portion of the light reflected by the cathode electrode CE can be reflected by the auxiliary line SL and emitted toward the substrate 100, and the remaining light from the other path can be reflected by the side of the pixel drive line PDL and emitted toward the substrate 100, thereby further improving the light extraction efficiency. For example, in the light-emitting display device according to this specification, since the sides of the auxiliary line SL and the pixel drive line PDL are perpendicular, a portion of the light reflected by the cathode electrode CE can be fully reflected by the side of the auxiliary line SL and the side of the pixel drive line PDL and emitted toward the substrate 100, thereby further improving the light extraction efficiency.

[0182] Figure 11 is a cross-sectional view showing another example of area B shown in Figure 2. In this example, the shape of the color filter layer of the light-emitting device shown in Figures 2 to 5 has been changed. Therefore, in the following description, only the shape of the color filter layer and related configurations will be described, and the remaining configurations will be given the same reference numerals as in Figures 6 to 8, and redundant explanations will be simplified or omitted.

[0183] Referring to Figure 11, the light-emitting device according to this embodiment of the specification may include a color filter layer CFL. The color filter layer CFL may include a red color filter CFr, a green color filter CFg, and a blue color filter CFb. For convenience of explanation, the light-emitting device according to this embodiment of the specification will be described below using the green color filter CFg and the blue color filter CFb as examples. As another example, the configuration according to the embodiment of the specification can also be applied to the red color filter CFr and the green color filter CFg.

[0184] In this example, the color filter layer CFL can be in contact with the pixel drive line PDL and separated from the auxiliary line SL. The ends of the color filter layer CFL can cover the sides of the pixel drive lines PDL that are adjacent to each other, sandwiching the corresponding light-emitting units EPg and EPb. The ends of the color filter layer CFL do not have to be located on the sides of the auxiliary line SL. For example, the green color filter CFg of the second sub-pixel region SPA2 can be in contact with the pixel drive line PDL and separated from the auxiliary line SL. The green color filter CFg of the second sub-pixel region SPA2 can be in contact with the first reference power line RL1 and separated from the auxiliary line SL. For example, the blue color filter CFb of the third sub-pixel region SPA3 can be in contact with the pixel drive line PDL and separated from the auxiliary line SL. The blue color filter CFb of the third sub-pixel region SPA3 can be in contact with the first reference power line RL1 and separated from the auxiliary line SL.

[0185] According to this example, by adjusting the exposure during the process of forming the color filter layer CFL, the edges of the color filter layer CFL can be formed so as not to contact the side surface of the auxiliary line SL. For example, in the masking process, the exposure can be increased to engrave the color filter layer CFL. In this case, by increasing the exposure, the edges of the color filter layer CFL can be formed so as not to contact the side surface of the auxiliary line SL.

[0186] According to the embodiments of this specification, since the edges of the color filter layer CFL do not contact the side surfaces of the auxiliary line SL, the lengths of the inclined surfaces CFg-A and CFb-A of the color filter layer CFL can be increased. Therefore, the shapes of the grooves 145 and cathode electrodes CE that are subsequently placed may be aligned with the inclined surfaces CFg-A and CFb-A of the color filter layer CFL. For example, the inclined surface of the grooves 145 can be increased along the inclined surfaces CFg-A and CFb-A of the color filter layer CFL. For example, the inclined surface of the cathode electrodes CE that are subsequently placed can be increased.

[0187] According to this example, by separating the color filter layer CFL from the auxiliary line SL, the length of the inclined surfaces CFg-A, CFb-A, and groove 145 of the color filter layer CFL can be increased. Therefore, the light extraction efficiency of the light emitted from the light-emitting layer EL can be further improved.

[0188] Figures 12A to 12F show the method for manufacturing a light-emitting device according to the embodiments of this specification. These illustrate the method for manufacturing a light-emitting device described with reference to Figures 1 to 5. In Figures 12A to 12F, the manufacturing methods for areas A and B are the same, so for the sake of explanation, the manufacturing method described herein will be explained using area B as an example. In the following description, the same reference numerals as in Figures 1 to 5 will be used, and redundant explanations will be simplified or omitted.

[0189] As shown in Figure 12A, a pixel drive line PDL can be patterned on the substrate 100, and a buffer layer 110 can be formed over the entire surface of the substrate 100. An insulating layer 130 can be patterned on the buffer layer 110, and an auxiliary line SL can be patterned on the insulating layer 130. Here, the auxiliary line SL and the pixel drive line PDL can be formed to have the same shape and width. Next, a passivation layer 120 can be formed over the entire surface of the substrate 100, covering the pixel drive line PDL, the buffer layer 110, the insulating layer 130, and the auxiliary line SL.

[0190] As shown in Figure 12B, in the passivation layer 120, photoresist can be placed in the area excluding the region overlapping with the pixel drive line PDL and auxiliary line SL, and the separation region SA.

[0191] As shown in Figure 12C, the buffer layer 110, the insulating layer 130, and the passivation layer 120 can be patterned using exposure and etching processes. Here, by allowing the etching solution to penetrate beneath the pixel drive line PDL and the auxiliary line SL, an undercut shape can be formed on the sides where the width of the pixel drive line PDL and the auxiliary line SL is greater than the width of the buffer layer 110 and the insulating layer 130.

[0192] As shown in Figure 12D, a color filter material can be applied to the entire surface of the substrate, a mask for exposure can be placed, and the exposure and etching processes can be carried out. The color filter material can be applied along the steps of the substructure. During the exposure process, the diffraction of light generated at the edges of the mask can cause the edges of the color filter to have an inclined surface. For example, the shape and length of the edges of the color filter can be controlled by adjusting the exposure amount. For example, if the exposure amount is high, the etching amount at the edges of the color filter increases, so that the edges of the color filter layer CFL do not come into contact with the side surface of the auxiliary line SL.

[0193] Referring to Figure 12E, a color filter layer (CFL) can be formed in each subpixel region using the method shown in Figure 12D.

[0194] Referring to Figure 12F, an overcoat layer 140, a light-emitting element layer EDL, a sealing layer 160, and a sealing substrate 170 can be sequentially formed over the entire surface. Here, a step may be formed in the overcoat layer 140 by the color filter layer CFL and the auxiliary line SL. A groove 145 may be formed at the edge of the color filter layer CFL and in the portion overlapping with the auxiliary line SL. In the light-emitting element layer EDL, the light-emitting layer EL and the cathode electrode CE may be configured over the entire surface of the substrate 100. Therefore, the light-emitting layer EL and the cathode electrode CE may be formed so that they have an inclined surface in the non-light-emitting portion NEP that follows the shape of the groove 145.

[0195] According to the embodiments of this specification, the method for manufacturing a light-emitting device, by including an auxiliary line, allows for the configuration of grooves with inclined surfaces and cathode electrodes between each subpixel without the need for an additional masking step (e.g., a halftone masking step). Therefore, the light extraction efficiency of the light-emitting device can be improved without increasing the manufacturing process and costs.

[0196] Figures 13A to 13E show a method for manufacturing a light-emitting device according to the embodiments of this specification. This illustrates the method for manufacturing a light-emitting device described with reference to Figures 6 to 8. In Figures 13A to 13E, the manufacturing method for area B is the same as in Figures 12A to 12F, so the manufacturing method described herein will be explained below using area A as an example. In the following description, the same reference numerals as in Figures 6 to 8 will be used, and redundant explanations will be simplified or omitted.

[0197] The process of forming the pixel drive line PDL, buffer layer 110, insulating layer 130, auxiliary line SL, and passivation layer 120 on the substrate 100 is the same as in Figure 12A.

[0198] As shown in Figure 13A, photoresist can be placed in the passivation layer 120 in the area excluding the region overlapping with the pixel drive line PDL and auxiliary line SL, and the separation region SA. Here, photoresist can also be placed between adjacent auxiliary lines SL. The photoresist may be placed so as to cover a portion of the upper surface of adjacent auxiliary lines SL.

[0199] As shown in Figure 13B, the buffer layer 110, the insulating layer 130, and the passivation layer 120 can be patterned using exposure and etching processes. Here, the etching solution can penetrate beneath the pixel drive line PDL and the auxiliary line SL. Therefore, it is possible to form undercut side surfaces in which the width of the pixel drive line PDL and the auxiliary line SL is greater than the width of the buffer layer 110 and the insulating layer 130.

[0200] As shown in Figure 13C, a color filter material can be applied to the entire surface of the substrate, and a mask for exposure can be placed to perform the exposure and etching processes. The color filter material can be applied along the steps of the substructure. Due to the diffraction of light generated at the edges of the mask during the exposure process, the edges of the color filter can have an inclined surface.

[0201] Referring to Figure 13D, a color filter layer (CFL) can be formed in each subpixel region using the method shown in Figure 12C.

[0202] Referring to Figure 13E, an overcoat layer 140, a light-emitting element layer EDL, a sealing layer 160, and a sealing substrate 170 can be formed over the entire surface. Here, a step may be formed in the overcoat layer 140 by the color filter layer CFL and the auxiliary line SL. A groove 145 may be formed at the edge of the color filter layer CFL and in the portion overlapping with the auxiliary line SL. In the light-emitting element layer EDL, the light-emitting layer EL and the cathode electrode CE can be configured over the entire surface of the substrate 100. Therefore, the light-emitting layer EL and the cathode electrode CE can be formed to have an inclined surface in the non-light-emitting portion NEP that follows the shape of the groove 145.

[0203] According to the embodiments of this specification, the method for manufacturing a light-emitting device, by including an auxiliary line, allows for the configuration of grooves with inclined surfaces and cathode electrodes between each subpixel without the need for an additional masking step (e.g., a halftone masking step). Therefore, the light extraction efficiency of the light-emitting device can be improved without increasing the manufacturing process and costs.

[0204] The light-emitting display device according to this specification can be described as follows.

[0205] According to some embodiments of this specification, a light-emitting display device may include a substrate containing a plurality of pixels, pixel drive lines arranged on the substrate in a first direction, gate lines arranged on the substrate in a second direction intersecting the first direction, auxiliary lines superimposed on the pixel drive lines, pixel circuits connected to the pixel drive lines, an overcoat layer covering the pixel circuits, grooves superimposed on the auxiliary lines, and a light-emitting layer disposed on the overcoat layer and connected to the pixel circuits.

[0206] According to some embodiments of this specification, each of a plurality of pixels may include a plurality of subpixels, each of which may include a light-emitting portion superimposed on a light-emitting layer, a non-light-emitting portion superimposed on a pixel drive line, and a circuit region superimposed on a pixel circuit.

[0207] According to some embodiments of this specification, a pixel drive line may include a plurality of pixel power lines spaced apart from each other in a first direction on a substrate, a plurality of data lines positioned between the plurality of pixel power lines in the first direction, and a plurality of reference power lines positioned between the plurality of data lines in the first direction. An auxiliary line may be superimposed on one or more of the plurality of pixel power lines, the plurality of data lines, and the plurality of reference power lines.

[0208] According to some embodiments of this specification, two adjacent data lines among a plurality of data lines are configured between two adjacent subpixels among a plurality of subpixels, and auxiliary lines may overlap one or more of the two adjacent data lines.

[0209] According to some embodiments of this specification, two adjacent data lines among a plurality of data lines are configured between two adjacent subpixels among a plurality of subpixels, and the plurality of pixel power lines may be configured for each of the plurality of pixels. The auxiliary lines may be configured to overlap one or more of the two adjacent data lines and to overlap each of the plurality of pixel power lines.

[0210] According to some embodiments of this specification, two adjacent data lines among a plurality of data lines are configured between two adjacent subpixels among a plurality of subpixels, and a plurality of reference power lines may be configured for each of the plurality of pixels. An auxiliary line may be configured to overlap one or more of the two adjacent data lines and to overlap each of the plurality of reference power lines.

[0211] According to some embodiments of this specification, auxiliary lines may be located in the same layer as gate lines and may contain the same material as gate lines.

[0212] According to some embodiments of this specification, a pixel circuit includes a drive transistor electrically connected to a light-emitting layer, the drive transistor includes source and drain electrodes located in the same layer as a plurality of data lines and a gate electrode located in the same layer as the gate line, and auxiliary lines located in the same layer as the gate electrode and may include the same material as the gate electrode.

[0213] According to some embodiments of this specification, the auxiliary lines may have the same width as the pixel drive lines.

[0214] According to some embodiments of this specification, the auxiliary lines may have a different width from the pixel drive lines.

[0215] According to some embodiments of this specification, the width of the upper surface of the auxiliary line and the pixel drive line is smaller than the width of the lower surface, and the sides of the auxiliary line and the pixel drive line may be inclined.

[0216] According to some embodiments of this specification, the width of the upper surface of the auxiliary line and the pixel drive line is the same as the width of the lower surface, and the sides of the auxiliary line and the pixel drive line may be vertical.

[0217] According to some embodiments of this specification, the groove may be made up of the overcoat layer and have a shape that is recessed from the upper surface to the lower surface of the overcoat layer.

[0218] According to some embodiments of this specification, the following may be further included: a buffer layer disposed in the light-emitting and non-light-emitting portions respectively and covering the pixel drive lines on the substrate; an insulating layer disposed between the pixel drive lines and auxiliary lines; a passivation layer disposed on the buffer layer disposed in the light-emitting portion; and a color filter disposed between the passivation layer and the overcoat layer and disposed in each of a plurality of subpixels.

[0219] According to some embodiments of this specification, the pixel drive lines and auxiliary lines can protrude in the direction of the adjacent color filter.

[0220] According to some embodiments of this specification, adjacent color filters can be separated from each other by an auxiliary line.

[0221] According to some embodiments of this specification, each of the color filters can cover the sides of adjacent pixel drive lines and auxiliary lines.

[0222] According to some embodiments of this specification, each of the color filters can cover the sides of adjacent pixel drive lines and be separated from auxiliary lines.

[0223] According to some embodiments of this specification, the groove includes at least two or more inclined portions and connecting portions that connect at least two or more inclined portions, and one or more of the at least two or more inclined portions may overlap with the edges of adjacent color filters.

[0224] According to some embodiments of this specification, the light-emitting layer may include an anode electrode disposed on an overcoat layer, a light-emitting layer disposed on the anode electrode, and a cathode electrode disposed on the light-emitting layer. The anode electrode may be spaced away from the groove, and the light-emitting layer and the cathode electrode may be arranged along the shape of the groove.

[0225] The light-emitting display devices described herein can be applied to all electronic devices, including display devices. For example, the light-emitting display devices described herein can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, electronic organizers, e-books, PMPs (portable multimedia players), PDAs (personal digital assistants), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation systems, vehicle navigation systems, vehicle display devices, televisions, wallpaper display devices, signage devices, game consoles, notebook PCs, monitors, cameras, camcorders, and home appliances.

[0226] The features, structures, and effects described in the various examples of this specification described above are included in at least one example of this specification, and are not necessarily limited to just one example. Furthermore, the features, structures, and effects exemplified in at least one example of this specification can be combined or modified in other examples and implemented by a person with ordinary skill in the art to which the technical concept of this specification belongs. Accordingly, the content related to such combinations and modifications should be interpreted as being included in the technical scope or scope of rights of this specification.

[0227] The present invention described above is not limited by the embodiments and accompanying drawings, and it will be apparent to those with ordinary skill in the art to which the present invention pertains that various substitutions, modifications, and alterations are possible without departing from the technical matters of the present invention. Accordingly, the scope of the present invention is determined by the claims described below, and all forms of modification or alteration derived from the meaning, scope, and equivalent concepts of the claims should be interpreted as being included within the scope of the present invention. [Explanation of symbols]

[0228] 10 Display Panel 12 pixels 12a First subpixel 12b Second subpixel 12c Third subpixel 12d 4th subpixel 12e Fifth subpixel 12f 6th subpixel 100 circuit boards 110 buffer layers 120 Passivation Layers 130 Insulating layer 140 Overcoat Layer 145 Groove 160 sealing layer 170 Sealing substrate PDL Pixel Drive Line DL Dataline PL pixel power line RL Reference Power Line SL auxiliary line EDL light-emitting diode layer AE anode electrode EL light-emitting layer CE cathode electrode SPA1, SPA2, SPA3, SPA4: 1st to 4th subpixel regions

Claims

1. A substrate containing multiple pixels, A pixel drive line arranged in a first direction on the substrate, A gate line is arranged on the substrate in a second direction intersecting the first direction, The aforementioned pixel drive line and the auxiliary line superimposed thereon, A pixel circuit connected to the aforementioned pixel drive line, An overcoat layer covering the aforementioned pixel circuit, The groove portion overlapping the aforementioned auxiliary line, A light-emitting element layer disposed on the overcoat layer and connected to the pixel circuit, A light-emitting display device, including a light-emitting display device.

2. Each of the aforementioned multiple pixels includes multiple subpixels, Each of the aforementioned subpixels is A light-emitting portion superimposed on the light-emitting layer, A non-light-emitting section superimposed on the aforementioned pixel drive line, The circuit region superimposed on the aforementioned pixel circuit, The light-emitting display device according to claim 1, including the above.

3. The aforementioned pixel drive line is A plurality of pixel power lines spaced apart from each other in the first direction are provided on the substrate, A plurality of data lines arranged between the plurality of pixel power lines in the first direction, A plurality of reference power lines arranged between the plurality of data lines in the first direction, Includes, The auxiliary line overlaps with one or more of the plurality of pixel power lines, the plurality of data lines, and the plurality of reference power lines. The light-emitting display device according to claim 1.

4. Two adjacent data lines among the plurality of data lines are configured between two adjacent subpixels among the plurality of subpixels, The auxiliary line overlaps with one or more of the two adjacent data lines. The light-emitting display device according to claim 3.

5. Two adjacent data lines among the plurality of data lines are configured between two adjacent subpixels among the plurality of subpixels, The plurality of pixel power lines are configured for each of the plurality of pixels, The auxiliary line is configured to overlap with one or more of the two adjacent data lines and with each of the plurality of pixel power lines. The light-emitting display device according to claim 3.

6. Two adjacent data lines among the plurality of data lines are configured between two adjacent subpixels among the plurality of subpixels, The aforementioned plurality of reference power lines are configured for each of the plurality of pixels, The auxiliary line is configured to overlap with one or more of the two adjacent data lines and with each of the multiple reference power lines. The light-emitting display device according to claim 3.

7. The light-emitting display device according to claim 1, wherein the auxiliary line is arranged in the same layer as the gate line and contains the same material as the gate line.

8. The pixel circuit includes a drive transistor electrically connected to the light-emitting layer. The aforementioned drive transistor is Source and drain electrodes arranged in the same layer as the aforementioned plurality of data lines, A gate electrode arranged in the same layer as the aforementioned gate line, Includes, The auxiliary line is located in the same layer as the gate electrode and contains the same material as the gate electrode. The light-emitting display device according to claim 3.

9. The light-emitting display device according to claim 1, wherein the auxiliary line has the same width as the pixel driving line.

10. The light-emitting display device according to claim 1, wherein the auxiliary line has a different width from the pixel driving line.

11. The light-emitting display device according to claim 1, wherein the width of the upper surface of the auxiliary line and the pixel drive line is smaller than the width of the lower surface, and the sides of the auxiliary line and the pixel drive line are inclined.

12. The light-emitting display device according to claim 1, wherein the width of the upper surface of the auxiliary line and the pixel drive line is the same as the width of the lower surface, and the sides of the auxiliary line and the pixel drive line are vertical.

13. The light-emitting display device according to claim 1, wherein the groove is formed in the overcoat layer and has a shape that is recessed from the upper surface to the lower surface of the overcoat layer.

14. A buffer layer is provided in each of the light-emitting and non-light-emitting sections, covering the pixel drive line on the substrate, An insulating layer disposed between the pixel drive line and the auxiliary line, A passivation layer is disposed on the buffer layer disposed on the light-emitting section, A color filter is placed between the passivation layer and the overcoat layer, and is positioned in each of the plurality of subpixels. The light-emitting display device according to claim 2, further comprising:

15. The light-emitting display device according to claim 14, wherein the pixel drive line and the auxiliary line protrude in the direction of the adjacent color filter.

16. The light-emitting display device according to claim 14, wherein adjacent color filters among the color filters are separated from each other by the auxiliary line.

17. The light-emitting display device according to claim 14, wherein each of the color filters covers the side surface of an adjacent pixel drive line and the side surface of an auxiliary line.

18. The light-emitting display device according to claim 14, wherein each of the color filters covers the side surface of an adjacent pixel drive line and is separated from the auxiliary line.

19. The groove portion is At least two or more inclined sections, A connecting portion that connects at least two or more of the aforementioned inclined portions, Includes, One or more of the two or more inclined portions overlap with the edge of an adjacent color filter. The light-emitting display device according to claim 14.

20. The light-emitting layer is an anode electrode disposed on the overcoat layer, A light-emitting layer disposed on the anode electrode, A cathode electrode disposed on the light-emitting layer, Includes, The anode electrode is separated from the groove, The light-emitting layer and the cathode electrode are arranged along the shape of the groove. The light-emitting display device according to claim 1.

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