Indication device

Abstract

To reduce the non-display area of ​​the circuit board included in the display device. [Solution] A display device according to one embodiment of this specification includes a circuit film electrically connected to at least one side of a non-display area of ​​a substrate, the circuit film superimposed on the non-display area and including a plurality of first via holes penetrating the circuit film, a portion of the plurality of first via holes being included in a first group, the remaining portion of the plurality of first via holes being included in a second group, the plurality of first via holes included in the first group and the second group being arranged in a direction between a first direction and a second direction intersecting the first direction, the first group and the second group being arranged alternately in the first direction, the alignment direction of the plurality of first via holes included in the first group being the same as one another, and the alignment direction of the plurality of first via holes included in the second group being the same as one another.

Description

Technical Field

[0001] This specification relates to a display device, and more particularly to a display device having a structure capable of reducing the width of a non-display area.

Background Art

[0002] In recent years, with the advent of the full-scale information age, the development of display devices for visually representing electrical information signals has been rapidly progressing. Research has been continued to reduce the width of the bezel area and improve the aesthetic quality of display devices.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The problem to be solved by this specification is to provide a display device capable of reducing production energy by reducing the non-display area of a substrate included in the display device.

[0004] The problems of this specification are not limited to the problems mentioned above, and other problems not mentioned may be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0005] A display device according to an embodiment of this specification includes a circuit film electrically connected to at least one side of a non-display area of a substrate. The circuit film overlaps the non-display area and includes a plurality of first via holes penetrating the circuit film. A part of the plurality of first via holes is included in a first group, and the remaining part of the plurality of first via holes is included in a second group. The plurality of first via holes included in each of the first group and the second group are arranged in a direction between a first direction and a second direction intersecting the first direction. The first group and the second group are alternately arranged in the first direction. The alignment directions of the plurality of first via holes included in the first group are the same as each other, and the alignment directions of the plurality of first via holes included in the second group are the same as each other.

[0006] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0007] According to the embodiments of this specification, by using a circuit film having a structure that can reduce the area in which the substrate and circuit film of the display device are superimposed, the size of the substrate can be reduced, and the process of forming the substrate from the base substrate can be optimized.

[0008] According to the embodiments described herein, a circuit film can be made lighter by arranging multiple via holes in a circuit film having a limited area.

[0009] The effects described herein are not limited to those exemplified above, and a wider variety of effects are included within this specification. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic plan view of a display device according to one embodiment of this specification. [Figure 2] This figure schematically shows the cross-sectional structure obtained by cutting along line ab in Figure 1. [Figure 3] This figure schematically shows the upper surface structure of the circuit film of a display device according to one embodiment of this specification. [Figure 4] This figure schematically shows the back structure of the circuit film of a display device according to one embodiment of this specification. [Figure 5] This is a plan view showing a structure in which a substrate and a circuit film are connected in a display device according to one embodiment of this specification. [Figure 6] This is a cross-sectional view along line A-A' in Figure 5. [Figure 7] This is a cross-sectional view along line B-B' in Figure 5. [Figure 8] This is a cross-sectional view along line C-C' in Figure 5. [Figure 9]It is a cross-sectional view taken along D-D' of FIG. 5. [Figure 10] It is a plan view schematically showing a display device according to another embodiment of the present specification. [Figure 11] It is a view schematically showing a cross-sectional structure cut along c-d of FIG. 10. [Figure 12] It is a view schematically showing an upper surface structure of a circuit film of a display device according to another embodiment of the present specification. [Figure 13] It is a view schematically showing a back surface structure of a circuit film of a display device according to another embodiment of the present specification. [Figure 14] It is a plan view showing a structure in which a substrate and a circuit film of a display device according to another embodiment of the present specification are connected. [Figure 15] It is a cross-sectional view taken along E-E' of FIG. 14. [Figure 16] It is a cross-sectional view taken along F-F' of FIG. 14. [Figure 17] It is a cross-sectional view taken along G-G' of FIG. 14. [Figure 18] It is a cross-sectional view taken along H-H' of FIG. 14. [Figure 19] It is a plan view schematically showing a display device according to still another embodiment of the present specification. [Figure 20] It is a plan view schematically showing a circuit film of FIG. 19. [Figure 21] It is a view schematically showing a cross-sectional structure cut along e-f of FIG. 19. [Figure 22] It is a plan view showing a structure in which a substrate and a circuit film of a display device according to still another embodiment of the present specification are connected. [Figure 23] It is a cross-sectional view taken along I-I' of FIG. 22. [Figure 24] It is a cross-sectional view taken along J-J' of FIG. 22. [Figure 25] It is a cross-sectional view taken along K-K' of FIG. 2.. [Figure 26] It is a cross-sectional view taken along L-L' of FIG. 22. [Figure 27]It is a plan view schematically showing a display device according to another embodiment of the present specification. [Figure 28] It is a plan view schematically showing the circuit film of FIG. 27. [Figure 29] It is a view schematically showing a cross-sectional structure cut along g-h of FIG. 27. [Figure 30] It is a plan view showing a structure in which a substrate and a circuit film of a display device according to another embodiment of the present specification are connected. [Figure 31] It is a cross-sectional view along M-M' of FIG. 30. [Figure 32] It is a cross-sectional view along N-N' of FIG. 30. [Figure 33] It is a cross-sectional view along O-O' of FIG. 30. [Figure 34] It is a cross-sectional view along P-P' of FIG. 30. [Figure 35] It is a plan view schematically showing a display device according to another embodiment of the present specification. [Figure 36] It is a plan view schematically showing the circuit film of FIG. 35. <* [Figure 37] It is a view schematically showing a cross-sectional structure cut along i-j of FIG. 35. [Figure 38] It is a plan view showing a structure in which a substrate and a circuit film of a display device according to another embodiment of the present specification are connected. [Figure 39] It is a cross-sectional view along Q-Q' of FIG. 38. [Figure 40] It is a cross-sectional view along R-R' of FIG. 38. [Figure 41] It is a cross-sectional view along S-S' of FIG. 38. [Figure 42] It is a cross-sectional view along T-T' of FIG. 38. [Figure 43] It is a plan view schematically showing a display device according to another embodiment of the present specification. [[ID=SO]] [Figure 44] It is a plan view schematically showing the circuit film of FIG. 43. [[ID=5S]] [Figure 45] It is a view schematically showing a cross-sectional structure cut along k-l of FIG. 43. [Figure 46] This is a plan view showing a structure in which a substrate and a circuit film are connected in another embodiment of the display device according to this specification. [Figure 47] This is a cross-sectional view along line U-U' in Figure 46. [Figure 48] This is a cross-sectional view along line V-V' in Figure 46. [Figure 49] This is a cross-sectional view along line W-W' in Figure 46. [Figure 50] This is a cross-sectional view along line X-X' in Figure 46. [Modes for carrying out the invention]

[0011] The advantages and features of this specification, and the methods for achieving them, will become clearer with reference to the examples described below in detail with the accompanying drawings. However, this specification is not limited to the examples disclosed below, but can be embodied in a variety of different forms, and these examples are provided merely to make the disclosure of this specification complete and to fully inform a person with ordinary skill in the art to which this specification belongs.

[0012] The shapes, areas, proportions, angles, numbers, etc. disclosed in the drawings illustrating the embodiments of this specification are illustrative and the specification is not limited to those illustrated. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing this specification, if it is determined that a specific explanation of related prior art would unnecessarily obscure the gist of this specification, such detailed explanation will be omitted. Where "includes," "has," "is made," etc., are used in this specification, other parts may be added unless "only" is used. When a component is expressed singularly, it includes cases where it includes multiple components unless otherwise explicitly stated.

[0013] When interpreting the constituent elements, they shall be interpreted as including a margin of error, even if not explicitly stated otherwise.

[0014] When describing a spatial relationship, for example, when describing the positional relationship between two parts using phrases like "on top," "above," "below," or "next to," it is acceptable for one or more other parts to be located between the two parts, as long as "immediately" or "directly" is not used.

[0015] When an element or layer is referred to as "on" another element or layer, this includes cases where another layer or other element is interposed immediately above or between the other element.

[0016] Furthermore, while terms such as "first," "second," etc., are used to describe a variety of components, these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0017] Throughout the specification, the same reference numeral refers to the same component.

[0018] The area and thickness of each component shown in the drawings are provided for illustrative purposes only, and this specification is not necessarily limited to the area and thickness of the components shown.

[0019] The features of each of the various embodiments described herein can be combined or combined with one another, either partially or as a whole, enabling a variety of technically diverse interoperability and drive, and each embodiment may be implemented independently of the others or together in relation to one another.

[0020] In the following, this specification will be described with reference to the drawings.

[0021] Figure 1 is a schematic plan view of a display device according to one embodiment of this specification. Figure 2 is a schematic diagram showing a cross-sectional structure cut along ab in Figure 1. Figure 3 is a schematic diagram showing the top surface structure of the circuit film of a display device according to one embodiment of this specification. Figure 4 is a schematic diagram showing the back surface structure of the circuit film of a display device according to one embodiment of this specification.

[0022] Referring to Figures 1 to 4, a display device 100 according to one embodiment of this specification may include a display panel 110 and a circuit film 160. The display panel 110 may include a display area AA and a non-display area NA surrounding the display area AA. Multiple subpixels SP may be arranged in the display area AA. An organic light-emitting element 107 may be arranged in each subpixel SP.

[0023] Furthermore, the display panel 110 may include a substrate 110a, on which a cover window 108 superimposed with the entirety of multiple subpixels SP may be arranged. The substrate 110a may also include a display area AA and a non-display area NA in the same area as the display panel 110.

[0024] A gate drive circuit 130 may be placed in a portion of the non-display area NA. For example, the gate drive circuit 130 may be placed on two sides of the display panel 110. However, it is not limited to this, and the gate drive circuit 130 may not be placed inside the display panel 110, or it may be placed on only one side of the display panel 110.

[0025] A circuit film 160 may be connected to a portion of the non-display area NA of the display panel 110. The circuit film 160 may be electrically connected to at least one side of the non-display area NA surrounding the display area AA of the substrate 110a.

[0026] However, for the sake of clarity, the following explanation will focus on a configuration in which the source driver integrated circuit 180 is mounted on the circuit film 160. The circuit film 160 is not limited to this configuration and may be any film on which a general integrated circuit is mounted.

[0027] The circuit film 160 may be superimposed on the non-display area NA of the substrate 110a. The circuit film 160 may also be superimposed on at least a portion of the multiplexer circuit 121 located in the non-display area NA of the display panel 110. The multiplexer circuit 121 may include a multiplexer (MUX) that receives inputs of a high potential voltage (e.g., integrated circuit drive voltage (AVDDH)) and a low potential voltage (e.g., ground voltage (GND)). The circuit film 160 may be located on one side of the non-display area NA. Such a circuit film 160 may be located in an area where the gate drive circuit 130 is not located.

[0028] Multiple first signal lines 171, multiple second signal lines 172, and multiple third signal lines 173 may be arranged on the circuit film 160. A source driver integrated circuit 180 may also be mounted on the circuit film 160.

[0029] Furthermore, a printed circuit 190 can be connected to one side of the circuit film 160.

[0030] Multiple fourth signal lines 174 and multiple fifth signal lines 175 may be arranged on the back of the circuit film 160. Specifically, the first signal line 171 may be electrically connected to the fourth signal line 174 located on the back of the circuit film 160 through a first via hole 165 located within the circuit film 160. The first via hole 165 may be formed through the circuit film 160.

[0031] The fourth signal line 174 can be electrically connected to the first routing line 111 located on the substrate 110a of the display device 100. For example, the fourth signal line 174 and the first routing line 111 can be electrically connected by electrically connecting the first pad 101 connected to the first routing line 111 and the first connection pad 161 connected to the fourth signal line 174. The fourth signal line 174 can be connected to the first pad 101 through the first connection pad 161.

[0032] Furthermore, the second signal line 172 can be electrically connected to a fifth signal line 175 located on the back of the circuit film 160 through a second via hole 165a located within the circuit film 160. The second via hole 165a may be located in an intermediate region of the circuit film and may be located further away from the display area AA than the first via hole 165.

[0033] The fifth signal line 175 can be electrically connected to the second routing line 112 located on the substrate 110a of the display device 100. For example, the fifth signal line 175 and the second routing line 112 can be electrically connected by electrically connecting the second pad 102 connected to the second routing line 112 and the second connection pad 162 connected to the fifth signal line 175. The fifth signal line 175 can also be connected to the second pad 102 through the second connection pad 162.

[0034] On the other hand, although the first routing line 111 and the second routing line 112, which are arranged on the substrate 110a, appear to be in contact in cross-section, the first routing line 111 and the second routing line 112 can actually be arranged at a distance from each other.

[0035] Referring to Figures 1 to 4, a first electrode pattern layer 181a may be placed on a portion of the upper surface of a plurality of first signal lines 171, a second electrode pattern layer 182a may be placed on a portion of the upper surface of a plurality of second signal lines 172, and a third electrode pattern layer 183a may be placed on a portion of the upper surface of a plurality of third signal lines 173.

[0036] A first connection layer 181 electrically connected to the source driver integrated circuit 180 is arranged on the first electrode pattern layer 181a, a second connection layer 182 electrically connected to the source driver integrated circuit 180 is arranged on the second electrode pattern layer 182a, and a third connection layer 183 electrically connected to the source driver integrated circuit 180 may be arranged on the third electrode pattern layer 183a.

[0037] Furthermore, a third connection pad 191 may be placed on a portion of the upper surface of the third signal line 173. A printed circuit 190 may be connected to the third connection pad 191. The line width of such a third signal line 173 may be wider than the line width of the first signal line 171, but is not limited to this.

[0038] Specifically, the first signal line 171 can be electrically connected to the source driver integrated circuit 180 and can be electrically connected to the fourth signal line 174. The second signal line 172 can be electrically connected to the source driver integrated circuit 180 and can be electrically connected to the fifth signal line 175. The third signal line 173 can be electrically connected to the source driver integrated circuit 180 and can be electrically connected to the printed circuit 190.

[0039] Multiple signal lines are arranged on a single circuit film 160, and an efficient signal line arrangement design is necessary to enable the operation of the display device 100. Therefore, multiple signal lines can be arranged on both the top and back surfaces of the circuit film 160 of the display device 100.

[0040] However, each of the multiple first signal lines 171 located on the upper surface of the circuit film 160 must be electrically connected to each of the multiple fourth signal lines 174, and each of the multiple second signal lines 172 must be connected to each of the multiple fifth signal lines 175.

[0041] In one embodiment of this specification, the display device 100 may have a circuit film 160 that includes a plurality of via holes 165, 165a for the electrical connection of different signal lines.

[0042] Specifically, the first signal line 171 located on the upper surface of the circuit film 160 and the fourth signal line 174 located on the back surface of the circuit film 160 can be electrically connected through a first via hole 165 formed to penetrate the circuit film 160.

[0043] For the electrical connection between the first signal line 171 and the fourth signal line 174, the first via hole 165 may be filled with a conductive material. The conductive material may consist of, for example, a single metal or an alloy containing multiple metals.

[0044] The first via hole 165 can be superimposed on the first signal line 171 and the fourth signal line 174. Furthermore, the second signal line 172, located on the upper surface of the circuit film 160, and the fifth signal line 175, located on the back surface of the circuit film 160, can be electrically connected through the second via hole 165a, which is formed to penetrate the circuit film 160.

[0045] For the electrical connection between the second signal line 172 and the fifth signal line 175, the second via hole 165a may be filled with a conductive material. The conductive material may consist of a single metal or an alloy containing multiple metals.

[0046] The second via hole 165a can be superimposed on the second signal line 172 and the fifth signal line 175. In this way, the first signal line 171 and the fourth signal line 174 are connected through the first via hole 165, and the second signal line 172 and the fifth signal line 175 are connected through the second via hole 165a. This has the effect of simplifying the process because it is not necessary to form a separate electrode layer to connect each signal line.

[0047] Furthermore, the area of ​​the circuit film 160 can be efficiently utilized because the first via hole 165 is superimposed on the first signal line 171 and the fourth signal line 174, and the second via hole 165a is superimposed on the second signal line 172 and the fifth signal line 175. In particular, when the display device 100 is a mobile device or the like, the size of the substrate 110a of the display device 100 is small, and the area of ​​the circuit film 160 connected to one side of the substrate 110a can also be small.

[0048] The multiple first via holes 165 and multiple second via holes 165a provided in the circuit film 160 of the display device 100 according to one embodiment of this specification can efficiently connect multiple signal lines even if the area of ​​the circuit film 160 is small.

[0049] Multiple first via holes 165 can be arranged in multiple groups G1 and G2 within the circuit film 160. For example, multiple first via holes 165 can include a first group G1 and a second group G2. Some of the multiple first via holes 165 may be included in the first group G1, and the remaining portion of the multiple first via holes 165 may be included in the second group G2. Each of the first group G1 and the second group G2 may contain multiple first via holes 165.

[0050] Multiple first via holes 165 included in the first group G1 may be arranged in a direction between a first direction DR1 and a second direction DR2 which intersects the first direction DR1. Here, the first direction DR1 is the direction perpendicular to the direction in which one first signal line 171 extends, and the second direction DR2 may be the direction in which one first signal line 171 extends.

[0051] Each of the multiple first beer holes 165 included in the first group G1 can be arranged so as not to overlap with each other with respect to the first direction DR1 and the second direction DR2.

[0052] Multiple first via holes 165 included in the second group G2 may be arranged in the same manner as multiple first via holes 165 included in the first group G1. For example, multiple first via holes 165 included in the second group G2 may be arranged in a direction that intersects the first direction DR1 and the second direction DR2.

[0053] Each of the multiple first beer holes 165 included in the second group G2 may be arranged so as not to overlap with each other with respect to the first direction DR1 and the second direction DR2.

[0054] The arrangement of multiple first via holes 165 included in the first group G1 and the arrangement of multiple first via holes 165 included in the second group G2 may be identical to each other. Furthermore, one of the multiple first via holes 165 included in the first group G1 may be superimposed on one of the multiple first via holes 165 included in the second group G2 in the first direction DR1.

[0055] For example, the first beer hall 165 located in the first row of the first group G1 and the first beer hall 165 located in the first row of the second group G2 may be arranged so as to overlap each other with respect to the first direction DR1, and the first beer hall 165 located in the second row of the first group G1 and the first beer hall 165 located in the second row of the second group G2 may be arranged so as to overlap each other with respect to the first direction DR1. Here, the first row and the second row may be aligned with respect to the first direction DR1.

[0056] The distance with respect to the first direction DR1 between the first beer hall 165 located in one row of the first group G1 and the first beer hall 165 located in one row of the second group G2, and the distance with respect to the first direction DR1 between the first beer hall 165 located in two rows of the first group G1 and the first beer hall 165 located in two rows of the second group G2, may be the same.

[0057] Furthermore, the circuit film 160 has multiple first groups G1 and multiple second groups G2, each containing multiple first via holes 165, and these multiple first groups G1 and multiple second groups G2 can be arranged in a first direction DR1. By arranging the multiple first via holes 165 on the circuit film 160 in a regular manner, the first width W1 of the area occupied by the multiple first via holes 165 on the circuit film 160 can be reduced. Here, the first width W1 may represent the straight-line distance in the first direction DR1 from the first via hole 165 closest to the display area AA to the first via hole 165 closest to the first connection pad 161.

[0058] For example, the first width W1 can be reduced to 0.7 times the width of the non-display area NA where the circuit film 160 is placed relative to the first direction DR1. To give another example, if the width of the non-display area NA where the circuit film 160 is placed relative to the first direction DR1 is 4 mm, the first width W1 can be reduced to 2.8 mm or less.

[0059] Multiple first via holes 165 may be positioned between the display area AA of the display panel 110 and the source driver integrated circuit 180. Multiple first via holes 165 may be positioned so as to overlap with a portion of the non-display area NA of the substrate 110a. The larger the area occupied by the circuit film 160 by the multiple first via holes 165, the larger the area in which the non-display area NA of the substrate 110a and the circuit film 160 overlap.

[0060] In this case, the area of ​​the non-display region NA of the substrate 110a becomes larger, and the size of the substrate 110a itself may increase. Consequently, there is a problem in that the size of the non-display region NA or bezel of the display device 100 becomes larger, which may increase the manufacturing cost of the display device 100.

[0061] However, in one embodiment of this specification, the display device 100 can reduce the first width W1 of the circuit film 160 superimposed on the non-display area NA of the substrate 110a by arranging a plurality of first via holes 165 in a plurality of groups G1, G2.

[0062] Therefore, the manufacturing cost of the display device 100 can be reduced. Specifically, a substrate 110a used in one display device 100 can be manufactured by cutting a large-area master substrate. Here, the larger the size of the substrate 110a used in one display device 100, the fewer substrates 110a can be obtained through the master substrate. In this case, the manufacturing cost of the display device 100 will increase. In one embodiment of this specification, the width of the non-display area NA of the substrate 110a can be reduced by reducing the first width W1 of the circuit film 160 superimposed on the non-display area NA of the substrate 110a, and thereby the number of substrates 110a obtained through the master substrate can also be increased.

[0063] On the other hand, as shown in Figure 3, at least some of the multiple first signal lines 171 arranged on the upper surface of the circuit film 160 may include multiple signal sublines.

[0064] If the first signal line 171 includes multiple signal sublines, the first signal line 171 may include a first signal subline 171a and a second signal subline 171b connected to the first signal subline 171a. The first signal subline 171a may be positioned closer to the display area AA than the second signal subline 171b. The first signal subline 171a and the second signal subline 171b may be electrically connected through a connection area 178. A pad may be placed in the connection area 178.

[0065] If the first signal line 171 includes multiple signal sublines, the first via hole 165 can be connected to the first signal subline 171a. That is, the first signal subline 171a can be electrically connected to the fourth signal line 174 through the first via hole 165. Also, if the first signal line 171 includes multiple signal sublines, the second via hole 165a can be connected to the second signal subline 171b. That is, the second signal subline 171b can be connected to the first electrode pattern layer 181a. However, the structure of the first signal line 171 is not limited to this, and the first signal line 171 may be a single line without including multiple signal sublines.

[0066] Referring to Figure 4, the back surface of the circuit film 160 may include a plurality of first signal lines 171 and a plurality of fourth signal lines 174 connected through a first via hole 165, and a plurality of second signal lines 172 and a plurality of fifth signal lines 175 connected through a second via hole 165a.

[0067] As multiple signal lines are arranged on the top and back surfaces of the circuit film 160, it is necessary to test whether each signal line is functioning correctly.

[0068] Therefore, before connecting to the substrate 110a of the display device 100, a first test pattern 185 can be connected to each of the multiple fourth signal lines 174 located on the back of the circuit film 160, and a second test pattern 186 can be connected to each of the multiple fifth signal lines 175 to test whether each signal line is functioning correctly. The multiple first test patterns 185 and multiple second test patterns 186 that are electrically connected to the fourth signal lines 174 and fifth signal lines 175 located on the circuit film 160 can be removed after the inspection is complete.

[0069] After inspecting the circuit film 160, the first connection pad 161 connected to the fourth signal line 174 can be placed on the first pad 101 located on the substrate 110a, and the second connection pad 162 connected to the fifth signal line 175 can be placed on the second pad 102 located on the substrate 110a. Through this, the normally functioning circuit film 160 can be electrically connected to the first pad 101 and the second pad 102 located on the substrate 110a to configure the display device 100.

[0070] Each of the at least one first pad 101 and at least one first connection pad 161 may be positioned closer to the display area AA than at least one second pad 102 and at least one second connection pad 162.

[0071] Figure 5 is a plan view showing a structure in which a substrate and a circuit film are connected in a display device according to one embodiment of this specification. Figure 6 is a cross-sectional view taken along line A-A' in Figure 5. Figure 7 is a cross-sectional view taken along line B-B' in Figure 5. Figure 8 is a cross-sectional view taken along line C-C' in Figure 5. Figure 9 is a cross-sectional view taken along line D-D' in Figure 5.

[0072] Referring to Figures 5 to 9, a circuit film 160 may be placed on a portion of the upper surface of the substrate 110a of the display device 100. Multiple fourth signal lines 174 and multiple fifth signal lines 175 may be placed on the back surface of the circuit film 160.

[0073] Each of the multiple fourth signal lines 174 can be connected to the first via hole 165.

[0074] At least one of the multiple first via holes 165 can be superimposed on the first pad 101. Since the multiple first via holes 165, each of which serves to connect the multiple fourth signal lines 174 to the multiple first signal lines 171, are arranged inside the circuit film 160, the multiple first via holes 165 can be superimposed on numerous components, thereby efficiently utilizing the limited area of ​​the circuit film 160. However, this is not limited to the above, and the multiple first via holes 165 do not necessarily have to be superimposed on the first pad 101.

[0075] Multiple first via holes 165 may be arranged on the substrate 110a of the display device 100. Specifically, referring to Figures 5 and 6, a circuit film 160 may be arranged on the substrate 110a.

[0076] Multiple first signal lines 171 and a first protective layer 166 disposed on the circuit film 160 and the first signal lines 171 may be arranged on the upper surface of the circuit film 160. The first protective layer 166 may include an organic insulating material. Although not shown in the drawings, the first protective layer 166 may include open areas that expose a portion of the upper surface of the first signal lines 171. For example, the first protective layer 166 may include open areas in the region where the first signal lines 171 are connected to the source driver integrated circuit 180.

[0077] On the back of the circuit film 160, a plurality of fourth signal lines 174 and a second protective layer 167 may be arranged on the back of the fourth signal lines 174 and the circuit film 160. The second protective layer 167 may contain an organic insulating material.

[0078] At least one first signal line 171 can be electrically connected to a fourth signal line 174 by a first via hole 165 that penetrates the circuit film 160.

[0079] Referring to Figure 5, each of the multiple fourth signal lines 174 may have a width in the region 174a that overlaps with the first via hole 165 that is greater than the width of the region that does not overlap with the first via hole 165. Here, the width of the fourth signal line 174 represents the length with respect to the first direction DR1. Through this, the margin necessary to form the first via hole 165 can be secured.

[0080] Referring to Figures 5 and 7, each of the multiple fourth signal lines 174 can be connected to a first connection pad 161. Each of the multiple first connection pads 161 can be connected to a multiple first pad 101 located on the upper surface of the substrate 110a of the display device 100.

[0081] Specifically, the second protective layer 167 located on the back of the circuit film 160 may include a first open region 167a for connecting the fourth signal line 174 and the first pad 101.

[0082] The first open region 167a may overlap with a plurality of first connection pads 161. That is, a portion of the back and sides of each of the plurality of first connection pads 161 may be configured not to overlap with the second protective layer 167. In order for each of the plurality of first connection pads 161 to be directly connected to the first pad 101, at least a portion of the plurality of first connection pads 161 must be in contact with the first pad 101.

[0083] Such multiple first connection pads 161 are arranged spaced apart from each other, but the distance between them may be short. In this case, it may be difficult to form a first open region 167a in the second protective layer 167 that corresponds to each of the multiple first connection pads 161. For example, at least one of the multiple first connection pads 161 and the first open region 167a formed to correspond to them in the second protective layer 167 may not be in the same position, and therefore at least one first connection pad 161 may not be connected to the first pad 101. In one embodiment of the display device 100 according to this specification, the circuit film 160 of the second protective layer 167 is arranged so that the first open region 167a of the second protective layer 167 overlaps with the multiple first connection pads 161, thereby enabling each of the multiple first connection pads 161 to be stably connected to the first pad 101.

[0084] Referring to Figures 5 and 8, each of the multiple fifth signal lines 175 can be connected to a second connection pad 162. Each of the multiple second connection pads 162 can be connected to a multiple second pad 102 located on the upper surface of the substrate 110a of the display device 100.

[0085] Specifically, the second protective layer 167, positioned on the surface of the second connection pad 162 and the back of the circuit film 160, may include a second open area 167b for connecting the second connection pad 162 and the second pad 102. The second open area 167b may overlap with multiple second connection pads 162. That is, a portion of the back and sides of each of the multiple second connection pads 162 may be configured not to overlap with the second protective layer 167.

[0086] For each of the multiple second connection pads 162 to be directly connected to the second pad 102, at least a portion of the multiple second connection pads 162 must be in contact with the second pad 102. By arranging the second open region 167b of the second protective layer 167 located on the back of the circuit film 160 to overlap with the multiple second connection pads 162, each of the multiple second connection pads 162 can be stably connected to the second pad 102.

[0087] In at least a portion of the area where the second connection pad 162 is in contact with the second pad 102, there may be areas where the fifth signal line 175 and other signal lines do not overlap. In areas where the second connection pad 162 and the first signal line 171 located on the upper surface of the circuit film 160 do not overlap, the first protective layer 166 may be located on the upper surface of the circuit film 160.

[0088] Referring also to Figures 5 and 9, the back and sides of the fifth signal line 175 may be surrounded by the second protective layer 167 in at least a portion of the area where the fifth signal line 175 does not contact the second pad 102. The fifth signal line 175 may also include areas that do not overlap with other signal lines. In this case, the first protective layer 166 may be placed on the upper surface of the circuit film 160.

[0089] Referring to Figures 5, 7, and 8, a structure is shown in which a portion of the first connection pad 161 of each of the multiple fourth signal lines 174 is superimposed on a portion of the first pad 101, and a portion of each of the multiple fifth signal lines 175 is superimposed on a portion of the second pad 102, but the structure is not limited to this.

[0090] For example, each of the first connection pads 161 of the multiple fourth signal lines 174 and each of the multiple first pads 101 may be completely superimposed, and each of the second connection pads 162 of the multiple fifth signal lines 175 and each of the multiple second pads 102 may be completely superimposed.

[0091] Furthermore, although Figure 6 only shows the multiple first pads 101 and multiple second pads 102 arranged on the substrate 110a, each of the multiple first pads 101 can be connected to a multiple first routing line 111, and each of the multiple second pads 102 can be connected to a multiple second routing line 112.

[0092] Thus, the display device 100 according to one embodiment of this specification can reduce the width W1 of the circuit film 160 superimposed on the non-display area NA of the substrate 100a by arranging a plurality of first via holes 165 in a plurality of groups G1, G2.

[0093] Figure 10 is a schematic plan view of a display device according to another embodiment of this specification. Figure 11 is a schematic diagram showing a cross-sectional structure cut along cd in Figure 10. Figure 12 is a schematic diagram showing the top surface structure of the circuit film of a display device according to another embodiment of this specification. Figure 13 is a schematic diagram showing the back surface structure of the circuit film of a display device according to another embodiment of this specification.

[0094] The display devices 200 in Figures 10 to 13 differ from the display devices 200 in Figures 1 to 4 only in the arrangement of the multiple first via holes 265; the other components are substantially the same, so redundant explanations will be omitted.

[0095] Referring to Figures 10 to 13, the multiple first via holes 265 of the display device 200 may be arranged in multiple groups G3, G4 within the circuit film 260. For example, the multiple first via holes 265 may include a third group G3 and a fourth group G4. Each of the third group G3 and the fourth group G4 may contain multiple first via holes 265.

[0096] Multiple first via holes 265 included in the third group G3 may be arranged in a direction between the first direction DR1 and the second direction DR2. Multiple first via holes 265 included in the fourth group G4 may be arranged in a direction between the first direction DR1 and the second direction DR2.

[0097] One of the multiple first beer halls 265 included in the third group G3 may be included in the fourth group G4. Except for the one first beer hall 265 included in both the third group G3 and the fourth group G4, the orientation in which the multiple first beer halls 265 included in the third group G3 are arranged and the orientation in which the multiple first beer halls 265 included in the fourth group G4 are arranged may differ from each other.

[0098] For example, with the exception of one first via hole 265 included in the third group G3 and the fourth group G4, the directions in which the multiple first via holes 265 included in the third group G3 are arranged and the directions in which the multiple first via holes 265 included in the fourth group G4 are arranged may intersect with each other. One of the multiple first via holes 265 included in the third group G3 may overlap with one of the multiple first via holes 265 included in the fourth group G4 in the first direction DR1.

[0099] For example, the first beer hall 265 located in the first row of the third group G3 and the first beer hall 265 located in the first row of the fourth group G4 may be arranged so as to overlap each other with respect to the first direction DR1, and the first beer hall 265 located in the second row of the third group G3 and the first beer hall 265 located in the second row of the fourth group G4 may be arranged so as to overlap each other with respect to the first direction DR1. Here, the first row and the second row may be aligned with respect to the first direction DR1.

[0100] The distance with respect to the first direction DR1 between the first beer hall 265 located in one row of the third group G3 and the first beer hall 265 located in one row of the fourth group G4, and the distance with respect to the first direction DR1 between the first beer hall 265 located in two rows of the third group G3 and the first beer hall 265 located in two rows of the fourth group G4, may be different from each other.

[0101] For example, the distance with respect to the first direction DR1 between the first beer hall 265 located in one row of the third group G3 and the first beer hall 265 located in one row of the fourth group G4 may be wider than the distance with respect to the first direction DR1 between the first beer hall 265 located in two rows of the third group G3 and the first beer hall 265 located in two rows of the fourth group G4.

[0102] Two adjacent third groups G3 and two adjacent fourth groups G4 may form a W shape on the plane.

[0103] The circuit film 260 may have multiple third groups G3 and multiple fourth groups G4, each containing multiple first via holes 265, arranged alternately with respect to each other and aligned in the first direction DR1.

[0104] In this way, by arranging the multiple first via holes 265 placed on the circuit film 260 in a regular manner, the second width W2 of the area occupied by the multiple first via holes 265 on the circuit film 260 can be reduced. Here, the second width W2 may represent the straight-line distance in the first direction DR1 from the first via hole 265 that is closest to the display area AA to the first via hole 265 that is closest to the first connection pad 161.

[0105] For example, the second width W2 can be reduced to 0.37 to 0.38 times the width of the non-display area NA where the circuit film 260 is placed relative to the first direction DR1. To give another example, if the width of the non-display area NA where the circuit film 260 is placed relative to the first direction DR1 is 4 mm, the first width W1 can be reduced to 1.5 mm or less.

[0106] In other embodiments of this specification, the display device can reduce the width of the non-display area NA of the substrate 110a by reducing the second width W2 of the circuit film 160 superimposed on the non-display area NA of the substrate 110a, thereby increasing the number of substrates 110a obtained through the master substrate.

[0107] On the other hand, a display panel 110 containing multiple organic light-emitting elements 107 may be placed on a portion of the substrate 110a, and a cover window 108 that covers the display panel 110 may be placed thereon. As the second width W2 of the circuit film 260 increases, the area in which the circuit film 260 overlaps with the substrate 110a increases, which can cause interference such as the circuit film 260 coming into contact with the cover window 108, potentially damaging the circuit film 260.

[0108] In other embodiments of this specification, the display device 200 has a W-shaped arrangement of at least some of the multiple first via holes 265, which reduces the second width W2 of the circuit film 260 superimposed on the non-display area NA of the substrate 110a. This not only reduces the size of the non-display area NA of the substrate 110a, but also reduces interference between the circuit film 260 and the cover window 108.

[0109] Figure 14 is a plan view showing a structure in which a substrate and a circuit film are connected in a display device according to another embodiment of this specification. Figure 15 is a cross-sectional view along line E-E' in Figure 14. Figure 16 is a cross-sectional view along line F-F' in Figure 14. Figure 17 is a cross-sectional view along line G-G' in Figure 14. Figure 18 is a cross-sectional view along line H-H' in Figure 14.

[0110] The display device 200 in Figures 14 to 18 differs from the display device 100 in Figures 6 to 10 only in the arrangement of the multiple first via holes 265; the other components are substantially the same, so redundant explanations are omitted.

[0111] Referring to Figures 14 to 18, the multiple first via holes 265 arranged on the back surface of the circuit film 260 are arranged in multiple W-shapes on a plane, which can result in a larger number of first via holes 265 arranged on the circuit film 260 per unit area compared to the multiple first via holes 165 provided within the circuit film 260 of the display device 200. In this way, by diversifying the arrangement of the multiple first via holes 265, the size of the area in which the substrate 110a of the display device 200 and the circuit film 260 overlap can be adjusted.

[0112] Furthermore, since the second protective layer 167, which is positioned on the rear surface of the circuit film 260, includes a first open region 167a in some areas, the first connection pad 161 of the fourth signal line 174 and the first pad 101 positioned on the substrate 110a can easily make contact. In addition, since the first open region 167a of the second protective layer 167 is superimposed on multiple first connection pads 161, the process of forming the first open region 167a can be simplified while simultaneously improving process reliability.

[0113] The second protective layer 167, positioned on the back of the circuit film 260, includes a second open region 167b in some areas, allowing the second connection pad 162 of the fifth signal line 175 and the second pad 102 positioned on the substrate 110a to easily make contact. Furthermore, the superimposition of the second open region 167b of the second protective layer 167 with multiple second connection pads 162 simplifies the process of forming the second open region 167b while simultaneously improving process reliability.

[0114] Figure 19 is a schematic plan view of a display device according to another embodiment of this specification. Figure 20 is a schematic plan view of the circuit film of Figure 19. Figure 21 is a schematic diagram showing a cross-sectional structure cut along ef of Figure 19.

[0115] The display device 300 in Figures 19 to 21 differs from the display device 100 in Figures 1 and 2 only in the position of the circuit film 160, the connection position between the circuit film 160 and the substrate 110a, the configuration for electrically connecting the circuit film 160 and the substrate 110a, and the position of the fifth signal line 375 arranged on the circuit film 160. Since the other components are substantially the same, redundant explanations will be omitted.

[0116] Referring to Figures 19 to 21, the circuit film 360 of the display device 300 may be a film on which the source driver integrated circuit (SDIC) 180 is mounted, or a printed circuit board on which the timing controller 140 is mounted. If the circuit film 160 is a printed circuit board, the source driver integrated circuit 180 may be located in the non-display area NA of the substrate 110a.

[0117] Specifically, a portion of the circuit film 360 may be placed beneath the substrate 110a. An integrated circuit 180 may be mounted on the circuit film 360, and at least a portion of the integrated circuit 180 does not need to be superimposed on the substrate 110a.

[0118] Multiple first signal lines 171, multiple second signal lines 172, multiple third signal lines 173, and multiple fifth signal lines 375 may be arranged on the upper surface of the circuit film 360. Multiple fourth signal lines 374 may be arranged on the back surface of the circuit film 360.

[0119] Each of the multiple first signal lines 171 and each of the multiple fourth signal lines 374 can be electrically connected through a first via hole 365. Each of the multiple first signal lines 171 can be electrically connected to a multiple first pad 101 located on the upper surface of the substrate 110a.

[0120] Specifically, the substrate 110a may be provided with multiple third via holes 301 that penetrate the substrate 110a in the region where it overlaps with the multiple first pads 101. Each of the multiple third via holes 301 may be filled with a conductive material.

[0121] Each of the multiple fifth signal lines 375 can be electrically connected to a plurality of second pads 102 located on the upper surface of the substrate 110a. Specifically, the substrate 110a may be provided with a plurality of fourth via holes 302 that penetrate the substrate 110a in a region overlapping with the plurality of second pads 102. Each of the plurality of fourth via holes 302 may be filled with a conductive material.

[0122] Although not shown in Figures 19 to 21, each of the multiple fifth signal lines 375 can be electrically connected to each of the multiple fourth signal lines 174 located on the back of the circuit film 360 through multiple via holes located within the circuit film 360.

[0123] Alternatively, each of the multiple second signal lines 172 may be electrically connected to each of the multiple fourth signal lines 174 located on the back of the circuit film 360 through multiple via holes located within the circuit film 360.

[0124] A fourth electrode pattern layer 381a may be placed on a portion of the upper surface of the multiple fifth signal lines 375. A first connection layer 181, electrically connected to the source driver integrated circuit 180, may be placed on the fourth electrode pattern layer 381a.

[0125] Specifically, the first signal line 171 is electrically connected to the first pad 101 located on the substrate 110a and can be electrically connected to the fourth signal line 174. Furthermore, the fifth signal line 575 is electrically connected to the second pad 102 located on the substrate 110a and can be electrically connected to the source driver integrated circuit 180.

[0126] On the other hand, although not shown in Figures 19 to 21, the first pad 101 may be connected to a first routing line that is located on the substrate 110a and electrically connected to a data line located in the display area AA. The second pad 102 may be connected to a second routing line that is located on the substrate 110a and electrically connected to another data line located in the display area AA. Multiple first signal lines 171 and multiple fifth signal lines 375 located on the upper surface of the circuit film 360 may be electrically connected to the first pad 101 and the second pad 102 on the back surface of the substrate 110a by multiple third via holes 301 and multiple fourth via holes 304 provided within the substrate 110a.

[0127] Therefore, some of the multiple signal lines and multiple first via holes 365 arranged on the circuit film 360 can be superimposed on a portion of the display area AA.

[0128] Another embodiment of the display device 300 according to this specification includes a source driver integrated circuit 180 mounted on a circuit film 360, wherein a first signal line 171 may be electrically connected to a third via hole 301, and a fifth signal line 375 may be electrically connected to a fourth via hole 302. The fifth signal line 375 may also be electrically connected to the source driver integrated circuit 180. Furthermore, each of the plurality of third via holes 301 and the plurality of fourth via holes 302 may be located further away from the display area AA than the plurality of first via holes 365.

[0129] Multiple first via holes 365 can be arranged in multiple groups G1 and G2 within the circuit film 360. For example, multiple first via holes 365 may include a first group G1 and a second group G2, and the first group G1 and the second group G2 may be arranged with the same regularity as the arrangement of multiple first via holes 165 described in Figures 1 to 4.

[0130] When the circuit film 360 is placed on the upper surface of the substrate 110a, it may be placed in the non-display area NA. If the circuit film 360 is placed up to the display area AA, defects may occur, in particular, interference may occur between the cover window 108, which is placed up to the entire display area AA and part of the non-display area NA, and the circuit film 360.

[0131] In another embodiment of the display device 300 described herein, the circuit film 360 is electrically connected on the back surface of the substrate 110a. Therefore, even if the circuit film 360 is arranged to overlap with the cover window 108, the occurrence of defects due to interference between the circuit film 360 and the cover window 108 is suppressed.

[0132] Furthermore, since the circuit film 360 is connected to the back of the substrate 110a through a plurality of third via holes 301 and a plurality of fourth via holes 302, the circuit film 360 does not obscure the display area AA even when it is superimposed on it. This makes it possible to reduce the width of the side surface of the substrate 110a that is connected to the circuit film 360. Here, the width of the side surface of the substrate 110a that is connected to the circuit film 360 represents the shortest length from the display area AA to the end of the substrate 110a in the second direction DR2.

[0133] For example, the minimum width of the third width W3 on the side where the substrate 110a is connected to the circuit film 360 may be the width of the multiple first pads 101, multiple second pads 102, and multiple routing wires. In other words, since there is no longer an area on the upper surface of the substrate 110a where the circuit film 360 must be placed, the width W3 on the side where the substrate 110a is connected to the circuit film 360 can be reduced. Consequently, this has the effect of reducing the width of the non-display area NA or bezel area of ​​the display device 300.

[0134] Furthermore, by positioning the circuit film 360 below the substrate 110a and reducing the area where the multiple first via holes 365 located within the circuit film 360 are situated, the area in which the circuit film 360 protrudes outside the substrate 110a of the display device 300 can be reduced. Therefore, it is not necessary to bend the circuit film 360 to reduce the area it occupies outside the substrate 100a, thus eliminating stress on the circuit film 360 caused by bending.

[0135] Figure 22 is a plan view showing a structure in which a substrate and a circuit film are connected in a display device according to another embodiment of this specification. Figure 23 is a cross-sectional view along line I-I' in Figure 22. Figure 24 is a cross-sectional view along line J-J' in Figure 22. Figure 25 is a cross-sectional view along line K-K' in Figure 22. Figure 26 is a cross-sectional view along line L-L' in Figure 22.

[0136] Referring to Figures 22 to 26, a circuit film 360 may be placed on a portion of the back surface of the substrate 110a of the display device 300.

[0137] Multiple first signal lines 171 and multiple fifth signal lines 375 may be arranged on the upper surface of the circuit film 360. Each of the multiple first signal lines 171 may be connected to a first via hole 365. Multiple first via holes 365 may be located at the bottom of the substrate 110a of the display device 100.

[0138] Multiple first via holes 365 electrically connect the first signal line 171 and the fourth signal line 174, and at least a portion of each of the multiple first signal line 171, the multiple fourth signal line 174, and the multiple first via holes 365 can be superimposed on the display area AA.

[0139] The design further includes a plurality of third via holes 301 and a plurality of fourth via holes 302 that penetrate the substrate 110a in a non-display area NA, and may further include a plurality of first pads 101 and a plurality of fourth via holes 302 and a plurality of second pads 102 disposed on the substrate 110a. At least one of the plurality of first via holes 365 may overlap with the first pad 101.

[0140] Specifically, referring to Figures 22 and 23, a circuit film 360 may be placed on the lower part of the substrate 110a. A plurality of first signal lines 171 and a first protective layer 166 placed on the first signal lines 171 and the circuit film 360 may be placed on the upper surface of the circuit film 360.

[0141] On the back of the circuit film 360, a plurality of fourth signal lines 174 and a second protective layer 167 may be arranged on the back of the fourth signal lines 174 and the circuit film 360.

[0142] At least one first signal line 171 can be electrically connected to a fourth signal line 174 by a first via hole 365 that penetrates the circuit film 360.

[0143] Referring to Figures 22 and 24, each of the multiple first sub-pads 101a can be connected to a plurality of first pads 101 located on the substrate 110a through a plurality of third via holes 301 located within the substrate 110a of the display device 300.

[0144] Specifically, the first protective layer 166 positioned on the upper surface of the circuit film 360 may include a third open region 166c for connecting the first sub-pad 101a positioned on the first signal line 171 to the third via hole 301. The third open region 166c may overlap with multiple first sub-pads 101a. That is, a portion of the upper and side surfaces of each of the multiple first sub-pads 101a may be configured not to overlap with the first protective layer 166.

[0145] Furthermore, the third open region 166c may be superimposed on the third connection pads 363 of multiple first signal lines 171.

[0146] Referring to Figures 22 and 25, each of the multiple fifth signal lines 375 may be connected to a second sub-pad 102a. Each of the second sub-pads 102a may be connected to a multiple second pad 102 located on the substrate 110a through a multiple fourth via hole 302 located within the substrate 110a of the display device 300. The first protective layer 166 located on the upper surface of the circuit film 360 may include a fourth open area 166d for connecting the second sub-pads 102a located on the fifth signal lines 375 to the fourth via hole 302.

[0147] The fourth open area 166d may overlap with a plurality of second sub-pads 102a. That is, the top surface and part of the side of each of the plurality of second sub-pads 102a may be configured so as not to overlap with the first protective layer 166. In addition, the fourth open area 166d may overlap with a plurality of second connection pads 362 of the fifth signal lines 375.

[0148] Since each of the second connection pads 362 and the multiple second sub-pads 102a of the multiple fifth signal lines 375 are electrically connected to the second pad 102, at least a portion of the second connection pads 362 and the multiple second sub-pads 102a of the fifth signal lines 375 can be in contact with the fourth via hole 302.

[0149] In another embodiment of the display device 300 described herein, the fourth open area 166d of the first protective layer 166, which is located on the upper surface of the circuit film 360, is arranged to overlap with a plurality of second connection pads 362, so that each of the plurality of second connection pads 362 can be stably connected to the second pad 102 through the fourth via hole 302.

[0150] Furthermore, referring to Figures 22 and 26, in at least a portion of the area where the fifth signal line 375 does not overlap with the fourth via hole 302, the top and sides of the fifth signal line 375 may be surrounded by the first protective layer 166.

[0151] Furthermore, the second sub-pad 102a may include a region in which the fifth signal line 375 does not overlap with other signal lines, at least in a portion of the area where the second sub-pad 102a does not contact the fourth via hole 302. For example, the fifth signal line 375 may be configured not to overlap with the fourth signal line 174, which is located on the back of the circuit film 360. In this case, the second protective layer 167 may be located on the back of the circuit film 360.

[0152] Referring to Figures 22, 24, and 25, a structure is shown in which a portion of the third connection pad 363 of each of the multiple first signal lines 171 is superimposed on a portion of the first pad 101, and a portion of each of the multiple fifth signal lines 175 is superimposed on a portion of the second pad 102, but the structure is not limited to this.

[0153] In this way, the circuit film 360 is placed on the back surface of the substrate 110a, and the multiple first pads 101 and multiple second pads 102 placed on the top surface of the substrate 110a are electrically connected to the signal lines of the circuit film 360 through the multiple third via holes 301 and multiple fourth via holes 302 provided within the substrate 110a. As a result, the circuit film 360 does not need to be connected to the top surface of the substrate 110a in the non-display area NA, which has the effect of reducing the size of the non-display area NA.

[0154] In another embodiment of the display device 300 described herein, the circuit film 360 is electrically connected on the back surface of the substrate 110a, so there is no need to consider interference between the circuit film 360 and the cover window 108 positioned on the upper surface of the substrate 110a. In other words, even if the circuit film 360 is positioned so as to overlap with the cover window 108, the occurrence of defects due to interference between the circuit film 360 and the cover window 108 is suppressed.

[0155] Furthermore, since the circuit film 360 of the display device 300 is electrically connected to the back surface of the substrate 110a through the third via hole 301 and the fourth via hole 302 of the substrate 110a, it can also be superimposed on the display area AA of the display device 300. In other words, the circuit film 360 does not have to be placed only in the non-display area NA of the display device 300, so the degree of freedom in the position where the circuit film 360 is placed can be increased.

[0156] Figure 27 is a schematic plan view of a display device according to another embodiment of this specification. Figure 28 is a schematic plan view of the circuit film of Figure 27. Figure 29 is a schematic diagram showing a cross-sectional structure cut along gh of Figure 27.

[0157] The display device 400 in Figures 27 to 29 differs from the display device 300 in Figures 19 to 21 only in the arrangement of the multiple first via holes 265 and the placement of a heat sink 410 at the bottom of the substrate 110a; the other components are substantially the same, so redundant explanations will be omitted.

[0158] Referring to Figures 27 to 29, a circuit film 460 is connected to a portion of the back surface of the non-display area NA of the substrate 110a of the display device 400 through a plurality of third via holes 301 and a plurality of fourth via holes 302, and a first via hole 465 located in a portion of the circuit film 460 may be located at the bottom of the substrate 110a.

[0159] Multiple first via holes 465 may be arranged in multiple groups G3, G4 within the circuit film 460. For example, multiple first via holes 465 may include a third group G3 and a fourth group G4. Each of the third group G3 and the fourth group G4 may contain multiple first via holes 465.

[0160] Two adjacent third groups G3 and two adjacent fourth groups G4 may be arranged in a W-shape on the plane. The arrangement of multiple first via holes 465 in Figures 27 to 29 may be substantially identical to the arrangement of multiple first via holes 265 included in the display device 200 in Figures 11 to 19.

[0161] On the other hand, if the display device 400 is a small display device such as a mobile device, the number and area of ​​the circuit film 460 connected to the substrate 110a of the display device 400 will also be smaller. Therefore, the area for connecting the multiple signal lines arranged on the top and back surfaces of the circuit film 460 may also be narrower. In another embodiment of the display device 400 described herein, the third group G3 and the fourth group G4 of the multiple first via holes 465 arranged within the circuit film 460 are arranged alternately with each other, thereby enabling efficient arrangement of multiple first via holes 465 within the circuit film 460.

[0162] Furthermore, since the circuit film 460 is connected on the back of the substrate 110a through multiple third via holes 301 and multiple fourth via holes 304, the circuit film 460 will not obscure the display area AA even when it is superimposed on it.

[0163] Therefore, the fourth width W4 of the side surface where the substrate 110a is connected to the circuit film 460 can be reduced. Consequently, there is an effect of reducing the width of the non-display area NA or bezel area of ​​the display device 400.

[0164] A heat sink 410 may be further positioned below the substrate 110a.

[0165] The heat sink 410 may overlap at least a portion of the display area AA and can play a role in controlling the amount of heat generated when the display device is driven so that it does not affect the display device 400. Such a heat sink 410 may be separated from the circuit film 460 located below the substrate 110a.

[0166] In particular, by arranging the third group G3 and the fourth group G4 of the multiple first via holes 465 arranged within the circuit film 460 alternately, the area in which the multiple first via holes 465 are arranged can be reduced, thereby preventing interference with the heat sink 410, which is arranged to overlap with at least a portion of the display area AA. Therefore, it is possible to prevent malfunctions of the display device 400 due to interference between the circuit film 460 and the heat sink 410. Furthermore, by arranging the circuit film 460 at the bottom of the substrate 110a and reducing the area in which the multiple first via holes 465 arranged within the circuit film 460 are located, the area in which the circuit film 460 protrudes outside the substrate 110a of the display device 400 can be reduced. Therefore, it is not necessary to bend the circuit film 460 to reduce the area in which it occupies outside the substrate 100a, thus eliminating stress on the circuit film 460 due to bending.

[0167] Figure 30 is a plan view showing a structure in which a substrate and a circuit film are connected in a display device according to another embodiment of this specification. Figure 31 is a cross-sectional view taken along line M-M' in Figure 30. Figure 32 is a cross-sectional view taken along line N-N' in Figure 30. Figure 33 is a cross-sectional view taken along line O-O' in Figure 30. Figure 34 is a cross-sectional view taken along line P-P' in Figure 30.

[0168] The display devices 400 in Figures 30 to 34 are substantially identical to the display devices 300 in Figures 22 to 26, except for the arrangement of the multiple first via holes 465; therefore, redundant explanations are omitted.

[0169] Referring to Figures 30 to 34, the multiple first via holes 465 of the display device 400 may be located at the bottom of the substrate 110a of the display device 400.

[0170] By arranging multiple first via holes 465 in multiple W-shapes on a plane, the number of first via holes 465 placed on the circuit film 460 per unit area can be increased. This has the effect of reducing the size of the display device 400, and even if the size of the circuit film 460 is reduced as a result, multiple first via holes 465 can be efficiently arranged.

[0171] Furthermore, since the circuit film 460 of the display device 400 is electrically connected to the back surface of the substrate 110a through the third via hole 301 and the fourth via hole 302 of the substrate 110a, it can also be superimposed on the display area AA of the display device 400. In other words, the circuit film 460 does not have to be placed only in the non-display area NA of the display device 400, so the degree of freedom in the position where the circuit film 460 is placed can be increased.

[0172] Figure 35 is a schematic plan view of a display device according to another embodiment of this specification. Figure 36 is a schematic plan view of the circuit film of Figure 35. Figure 37 is a schematic diagram showing a cross-sectional structure cut along ij of Figure 35.

[0173] The display device 500 shown in Figures 35 to 37 differs from the display device 100 described in Figures 2 to 5 only in that the circuit film 560 is electrically connected on the back of the substrate 110a and the circuit film 560 is inverted vertically at the bottom of the substrate 100a. Since the other components are substantially the same, redundant explanations will be omitted.

[0174] Referring to Figures 36 to 38, the display device 500 may include a display panel 110 and a circuit film 560.

[0175] A circuit film 560 can be connected to a portion of the back surface of the non-display area NA of the substrate 110a of the display device 500.

[0176] The entire circuit film 560, positioned beneath the substrate 110a, can be superimposed on the substrate 110a. Therefore, on a plane, the circuit film 560 may be hidden and invisible from the substrate 110a.

[0177] Furthermore, in the case of another embodiment of the display device 500 described herein, in which a source driver integrated circuit 180 is mounted on a circuit film 560 and a printed circuit 190 is connected to one side of the circuit film 560, the printed circuit 190 connected to the circuit film 560 is also located below the substrate 110a, and the entire printed circuit 190 can be superimposed on the substrate 110a.

[0178] The source driver integrated circuit 180 and printed circuit 190 mounted on the circuit film 560 can be superimposed on the display area AA. However, the circuit film 560 may be a printed circuit board on which the timing controller 140 is mounted.

[0179] Multiple fourth signal lines 174 and multiple fifth signal lines 175 may be arranged on the upper surface of the circuit film 560. Multiple first signal lines 171, multiple second signal lines 172, multiple third signal lines 173 and a source driver integrated circuit 180 may be arranged on the back surface of the circuit film 560.

[0180] Each of the multiple first signal lines 171 and each of the multiple fourth signal lines 174 can be electrically connected through a plurality of first via holes 565 provided in the circuit film 560.

[0181] Multiple first via holes 565 can be arranged in multiple groups G1 and G2 within the circuit film 560. For example, multiple first via holes 565 may include a first group G1 and a second group G2, and the first group G1 and the second group G2 may be arranged with the same regularity as the arrangement of multiple first via holes 165 in Figures 2 to 5.

[0182] These multiple first via holes 565 can be superimposed on the non-display area NA of the substrate 110a. In addition, multiple second signal lines 172 located on the back of the circuit film 560 can be electrically connected to a fifth signal line 175 located on the top surface of the circuit film 160 through second via holes 565a located within the circuit film 160.

[0183] At least a portion of the second beer hall 565a may be positioned to overlap with the display area AA.

[0184] Each of the multiple fourth signal lines 174 arranged on the upper surface of the circuit film 560 can be electrically connected to a multiple second pad 102 arranged on the substrate 110a through a multiple third via hole 601 provided in the substrate 110a.

[0185] Furthermore, each of the multiple fifth signal lines 175 arranged on the upper surface of the circuit film 560 can be electrically connected to a plurality of first pads 101 arranged on the substrate 110a through a plurality of fourth via holes 602 provided in the substrate 110a. Specifically, a first connection pad 561 may be arranged on a portion of the upper surface of each of the plurality of fourth signal lines 174.

[0186] Multiple first connection pads 561 can contact multiple third via holes 601 provided in the non-display area NA of the substrate 110a. Each of the multiple third via holes 601 can contact multiple second pads 102 located in the non-display area NA of the substrate 110a. In addition, a second connection pad 562 may be located on a portion of the upper surface of each of the multiple fifth signal lines 175.

[0187] Multiple second connection pads 562 can contact multiple fourth via holes 602 provided in the non-display area NA of the substrate 110a. Each of the multiple fourth via holes 602 can contact multiple first pads 101 located in the non-display area NA of the substrate 110a.

[0188] That is, it may further include a plurality of first pads 101 and a plurality of second pads 102 arranged on the substrate 110a in a non-display area NA, and a source driver integrated circuit 180 mounted on the circuit film 560. A portion of each of the plurality of first signal lines 171 and a plurality of second signal lines 172 may be electrically connected to the source driver integrated circuit 180, a fourth signal line 174 may be connected to the second pad 102, and a fifth signal line 175 may be connected to the first pad 101.

[0189] Each of the at least one second connection pad 562 and each of the at least one first pad 101 may be positioned closer to display area AA than the at least one first connection pad 561 and each of the at least one second pad 102. For example, each of the at least one first pad 101 may be positioned even closer to display area AA than the at least one second pad 102.

[0190] The multiple first via holes 565 can be positioned further away from the display area AA than the multiple third via holes 601 and multiple fourth via holes 602 provided within the substrate 110a.

[0191] Furthermore, multiple third via holes 601 and multiple fourth via holes 602 may be arranged between multiple first via holes 565 and multiple second via holes 565a. At least a portion of the multiple second via holes 565a may overlap with the display area AA.

[0192] Furthermore, at least a portion of each of the first signal line 171, the second signal line 172, and the fifth signal line 175 may be arranged to overlap with the display area AA.

[0193] Furthermore, multiple third beer halls 601 and multiple fourth beer halls 602 may be arranged between multiple first beer halls 565 and cover windows 108.

[0194] In another embodiment of the display device 500 described herein, the circuit film 560 is electrically connected on the back surface of the substrate 110a through a plurality of third via holes 601 and a plurality of fourth via holes 602. Therefore, even if the circuit film 560 is arranged to overlap with the cover window 108, the occurrence of defects due to interference between the circuit film 560 and the cover window 108 is suppressed.

[0195] Furthermore, since the circuit film 560 is connected on the back of the substrate 110a through multiple third via holes 301 and multiple fourth via holes 302, the circuit film 560 will not obscure the display area AA even when it is superimposed on it.

[0196] In particular, by arranging the entire circuit film 560 to overlap with the substrate 110a, the non-display area NA of the substrate 110a only requires the area where the multiple first pads 101, multiple second pads 102, and multiple routing wires electrically connected to the multiple first pads 101 and multiple second pads 102 are arranged.

[0197] Therefore, the width of the side surface to which the substrate 110a is connected to the circuit film 560 can be reduced. Here, the width of the side surface to which the substrate 110a is connected to the circuit film 560 means the shortest length from the display area AA to the end of the substrate 110a with respect to the second direction DR2. In other words, since there is no longer an area that the circuit film 560 must be placed on the upper surface of the substrate 110a, the fifth width W5 of the side surface to which the substrate 110a is connected to the circuit film 560 can be reduced.

[0198] In addition, by arranging the entire circuit film 560 to overlap with the substrate 110a, areas other than the display area AA and non-display area NA of the display panel 110 become unnecessary. Therefore, this has the effect of allowing the display device 100 to be formed in a simple manner.

[0199] Furthermore, by positioning the circuit film 560 at the bottom of the substrate 110a and reducing the area where the multiple first via holes 565 located within the circuit film 560 are situated, the area in which the circuit film 560 protrudes outside the substrate 110a of the display device 500 can be reduced. Therefore, it is not necessary to bend the circuit film 560 to reduce the area it occupies outside the substrate 100a, thus eliminating stress on the circuit film 560 caused by bending.

[0200] Figure 38 is a plan view showing a structure in which a substrate and a circuit film are connected in a display device according to another embodiment of this specification. Figure 39 is a cross-sectional view along Q-Q' in Figure 38. Figure 40 is a cross-sectional view along R-R' in Figure 38. Figure 41 is a cross-sectional view along S-S' in Figure 38. Figure 42 is a cross-sectional view along T-T' in Figure 38.

[0201] The display device 500 in Figures 38 to 42 has a structure in which the circuit film 560 is electrically connected on the back of the substrate 110a and the circuit film 560 is inverted vertically at the bottom of the substrate 100a, compared to the display device 100 in Figures 6 to 10. The only difference is the arrangement of the multiple second via holes 565a. Since the other components are substantially the same, redundant explanations will be omitted.

[0202] Referring to Figures 38 to 42, the substrate 110a of the display device 500 and the entire circuit film 560 can be superimposed.

[0203] Multiple fourth signal lines 174, multiple fifth signal lines 175, multiple first connection pads 561, multiple second connection pads 562, and a second protective layer 167 may be arranged on the upper surface of the circuit film 560. Multiple first signal lines 171, multiple second signal lines 172, and a first protective layer 166 may be arranged on the back surface of the circuit film 560.

[0204] Furthermore, multiple first via holes 565 and multiple second via holes 565a may be arranged within the circuit film 560.

[0205] Multiple fourth signal lines 174 may be located further away from display area AA than multiple fifth signal lines 175. For example, multiple fourth signal lines 174 may overlap with non-display area NA. At least a portion of the multiple fifth signal lines 175 may overlap with display area AA, and the remaining portion may overlap with non-display area NA.

[0206] Each of the multiple fifth signal lines 175 can be connected to a second via hole 565a. At least one of the multiple second via holes 565a can be superimposed on a second pad 102. And at least one of the multiple first via holes 565 can be superimposed on a first pad 101.

[0207] Since multiple second via holes 565a, each serving to connect multiple fifth signal lines 175 to multiple second signal lines 172, are arranged inside the circuit film 560, multiple second via holes 565a can be superimposed on numerous other components, thereby efficiently utilizing the limited area of ​​the circuit film 560.

[0208] Furthermore, each of the multiple fourth signal lines 174 can be connected to a first via hole 565. At least one of the multiple first via holes 565 can be superimposed on a second pad 102. Since the multiple first via holes 565, which serve to connect each of the multiple fourth signal lines 174 to the multiple first signal lines 171, are arranged inside the circuit film 560, the multiple first via holes 565 can be superimposed on numerous components, thereby allowing for more efficient use of the limited area of ​​the circuit film 560.

[0209] In addition, at least some of the multiple fifth signal lines 175 and the multiple second via holes 565a can also be superimposed on the source driver integrated circuit 180.

[0210] Referring to Figures 38 and 39, a circuit film 560 may be placed below the substrate 110a. The second signal line 172 and the fifth signal line 175 may be electrically connected through a second via hole 565a that penetrates the circuit film 560.

[0211] Furthermore, at least one second signal line 172, at least one fifth signal line 175, and at least one second via hole 565a can be superimposed on the display area AA.

[0212] Referring to Figures 38 and 40, each of the multiple fifth signal lines 175 can be connected to a second sub-pad 102a. Each of the multiple second sub-pads 102a can be connected to a multiple first pad 101 located on the substrate 110a through a multiple fourth via hole 602 located within the substrate 110a of the display device 500.

[0213] Specifically, the second protective layer 167 positioned on the upper surface of the circuit film 560 may include a fifth open region 167e for connecting the second sub-pad 102a positioned on the fifth signal line 175 to the fourth via hole 602. The fifth open region 167e may be superimposed on multiple second sub-pads 102a.

[0214] Furthermore, the fifth open region 167e may be superimposed on the second connection pads 562 of multiple fifth signal lines 175.

[0215] Referring to Figures 38 and 41, each of the multiple fourth signal lines 174 can be connected to a first sub-pad 101a. Each of the first sub-pads 101a can be connected to a multiple second pad 102 located on the substrate 110a through a multiple third via hole 601 located within the substrate 110a of the display device 500.

[0216] Specifically, the second protective layer 167 positioned on the upper surface of the circuit film 560 may include a sixth open area 167f for connecting the first sub-pad 101a positioned on the fourth signal line 174 with the third via hole 601.

[0217] The sixth open region 167f may overlap with a plurality of first sub-pads 101a. That is, the top surface and a portion of the side of each of the plurality of first sub-pads 101a may be configured so as not to overlap with the second protective layer 167. Also, the sixth open region 167f may overlap with a plurality of first connection pads 561 of the fourth signal lines 174. That is, the top surface and a portion of the side of each of the first connection pads 561 of the plurality of fourth signal lines 174 may be configured so as not to overlap with the second protective layer 167.

[0218] In another embodiment of the display device 500 described herein, the sixth open area 167f of the second protective layer 167, which is located on the upper surface of the circuit film 560, is arranged to overlap with a plurality of first connection pads 561, so that each of the plurality of first connection pads 561 can be stably connected to the second pad 102 through the third via hole 601.

[0219] In at least a portion of the area where the first connection pad 561 is in contact with the third via hole 601, there may be an area where the fourth signal line 174 and other signal lines do not overlap. In the area where the first connection pad 561 and the first signal line 171 located on the back of the circuit film 560 do not overlap, the first protective layer 166 may be located on the back of the circuit film 560.

[0220] Furthermore, referring to Figures 38 and 42, in at least a portion of the area where the fourth signal line 174 does not overlap with the third via hole 601, the top and sides of the fourth signal line 174 may be surrounded by the second protective layer 167.

[0221] Furthermore, the first sub-pad 101a may include a region in which the fourth signal line 174 does not overlap with other signal lines, at least in a portion of the area where the first sub-pad 101a does not contact the third via hole 301. For example, the fourth signal line 174 may be configured not to overlap with the first signal line 171 located on the back of the circuit film 560. In this case, the first protective layer 166 may be located on the back of the circuit film 560.

[0222] In this way, the circuit film 560 is placed on the back surface of the substrate 110a, and the multiple first pads 101 and multiple second pads 102 placed on the top surface of the substrate 110a are electrically connected to the signal lines of the circuit film 560 through the multiple third via holes 601 and multiple fourth via holes 602 provided within the substrate 110a. As a result, the circuit film 360 does not need to be connected to the top surface of the substrate 110a in the non-display area NA, which has the effect of reducing the size of the non-display area NA.

[0223] Furthermore, since the circuit film 560 of the display device 500 is electrically connected to the back surface of the substrate 110a through the third via hole 601 and the fourth via hole 602 of the substrate 110a, it can also be superimposed on the display area AA of the display device 300, thereby improving the degree of freedom in the position where the circuit film 560 is placed.

[0224] Figure 43 is a schematic plan view of a display device according to another embodiment of this specification. Figure 44 is a schematic plan view of the circuit film of Figure 43. Figure 45 is a schematic diagram showing the cross-sectional structure of Figure 43 cut along kl.

[0225] The display device 600 in Figures 43 to 45 differs from the display device 500 in Figures 35 to 37 only in the arrangement of the multiple first via holes 665 and the multiple second via holes 665a; the other components are substantially the same, so redundant explanations are omitted.

[0226] Referring to Figures 43 to 45, a circuit film 460 is connected to a portion of the back surface of the non-display area NA of the substrate 110a of the display device 600 through a plurality of third via holes 301 and a plurality of fourth via holes 302, and a first via hole 665 located in a portion of the circuit film 460 may be located at the bottom of the substrate 110a.

[0227] Multiple first via holes 665 may be arranged in multiple groups G3, G4 within the circuit film 660. For example, multiple first via holes 665 may include a third group G3 and a fourth group G4.

[0228] The arrangement of the multiple first via holes 665 included in the third group G3 and the fourth group G4 may be the same as the arrangement of the multiple first via holes 465 described in Figures 27 to 29.

[0229] The circuit film 660 is connected on the back of the substrate 110a through multiple third via holes 301 and multiple fourth via holes 304, so that even when the circuit film 660 is superimposed on the display area AA, the circuit film 660 does not obscure the display area AA.

[0230] Therefore, the sixth width W6 of the side surface where the substrate 110a is connected to the circuit film 660 can be reduced. Consequently, there is an effect of reducing the width of the non-display area NA or bezel area of ​​the display device 600.

[0231] Multiple second via holes 665a formed through the circuit film 660 can be arranged in the same manner as the multiple first via holes 665, thereby allowing multiple second via holes 665a to be efficiently arranged within the limited area of ​​the circuit film 660 without consuming a large area.

[0232] Furthermore, by positioning the circuit film 660 below the substrate 110a and reducing the area where the multiple first via holes 665 and multiple second via holes 665a located within the circuit film 660 are situated, the area in which the circuit film 660 protrudes outside the substrate 110a of the display device 600 can be reduced. Therefore, it is not necessary to bend the circuit film 660 to reduce the area it occupies outside the substrate 100a, thus eliminating stress on the circuit film 660 caused by bending.

[0233] Figure 46 is a plan view showing a structure in which a substrate and a circuit film are connected in a display device according to another embodiment of this specification. Figure 47 is a cross-sectional view along line U-U' in Figure 46. Figure 48 is a cross-sectional view along line V-V' in Figure 46. Figure 49 is a cross-sectional view along line W-W' in Figure 46. Figure 50 is a cross-sectional view along line X-X' in Figure 46.

[0234] The display device 600 in Figures 46 to 50 is substantially identical to the display device 500 in Figures 38 to 42, except for the arrangement of the multiple first via holes 665 and the multiple second via holes 665a; therefore, redundant explanations are omitted.

[0235] Referring to Figures 46 to 50, a circuit film 660 can be connected to a portion of the back surface of the substrate 110a of the display device 600 through a plurality of third via holes 301 and a plurality of fourth via holes 302 provided within the substrate 110a.

[0236] By arranging multiple first via holes 665 in multiple W-shapes on a plane, the number of first via holes 665 placed on the circuit film 660 per unit display area can be increased. This has the effect of reducing the size of the display device 600, and even if the size of the circuit film 660 is reduced as a result, multiple first via holes 665 can be efficiently arranged.

[0237] Furthermore, each of the multiple fifth signal lines 175 located on the upper surface of the circuit film 660 and the multiple second signal lines 172 located on the back surface of the circuit film 660 can be electrically connected through the second via hole 665a.

[0238] Multiple second via holes 665a may be arranged on the lower part of the substrate 110a of the display device 600. By arranging multiple second via holes 665a in multiple W shapes on a plane, the number of second via holes 665a arranged on the circuit film 660 per unit area can be increased. Through this, the size of the display device 600 can be reduced, and even if the size of the circuit film 660 is reduced as a result, multiple second via holes 665a can be efficiently arranged.

[0239] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to these embodiments and can be modified and implemented in various ways within the scope of the technical concept of this specification. Accordingly, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

Claims

1. A substrate including a display area and a non-display area, and A circuit film electrically connected to at least one side of the non-display area of ​​the substrate. Includes, The circuit film is superimposed on the non-display area and includes a plurality of first via holes that penetrate the circuit film. Some of the aforementioned multiple first beer halls are included in the first group, The remaining portion of the aforementioned first beer halls is included in the second group. The plurality of first via holes included in the first group and the second group, respectively, are arranged in a direction between the first direction and the second direction intersecting the first direction. The first group and the second group are arranged alternately in the first direction, The alignment direction of the multiple first beer halls included in the first group is the same for all of them. The alignment direction of the multiple first beer halls included in the second group is the same for all of them. Display device.

2. The circuit film is placed on the substrate, The circuit film further includes a plurality of first signal lines, a plurality of second signal lines, and a plurality of third signal lines arranged on its upper surface. The circuit film further includes a plurality of fourth signal lines and a plurality of fifth signal lines arranged on the back surface. The first via hole electrically connects the first signal line and the fourth signal line. The display device according to claim 1.

3. The circuit film further includes a plurality of second via holes that electrically connect the second signal line and the fifth signal line and penetrate the circuit film. The second via hole is located in the non-display area and is positioned further away from the display area than the first via hole. The display device according to claim 2.

4. The non-display area includes a plurality of first pads and a plurality of second pads arranged on the substrate, The integrated circuit mounted on the circuit film and It further includes, A portion of the first signal line and a portion of the second signal line are electrically connected to the integrated circuit. The fourth signal line is connected to the first pad, and the fifth signal line is connected to the second pad. The display device according to claim 2.

5. The display device according to claim 4, wherein at least one of the plurality of first pads is positioned closer to the display area than at least one of the plurality of second pads.

6. The display device according to claim 1, wherein the circuit film is disposed below the substrate.

7. The substrate further includes a cover window disposed on the substrate and positioned in the entire display area and a portion of the non-display area, A portion of the circuit film is superimposed on a portion of the cover window. The display device according to claim 6.

8. The circuit film further includes a plurality of first signal lines, a plurality of second signal lines, a plurality of third signal lines, and a plurality of fifth signal lines arranged on its upper surface. The circuit film further includes a plurality of fourth signal lines arranged on the back, The first via hole electrically connects the first signal line and the fourth signal line. At least a portion of each of the plurality of first signal lines, the plurality of fourth signal lines, and the plurality of first via holes is superimposed on the display area. The display device according to claim 6.

9. The aforementioned non-display area includes a plurality of third via holes and a plurality of fourth via holes that penetrate the substrate, The plurality of third via holes and the plurality of first pads arranged on the substrate, The plurality of fourth via holes and the plurality of second pads arranged on the substrate It further includes, At least one of the plurality of first via holes is superimposed on the first pad. The display device according to claim 8.

10. The circuit film further includes an integrated circuit mounted on the said circuit film, The first signal line is electrically connected to the third via hole, The fifth signal line is electrically connected to the fourth via hole, The fifth signal line is electrically connected to the integrated circuit, Each of the aforementioned plurality of third beer halls and plurality of fourth beer halls is positioned further from the display area than the plurality of first beer halls. The display device according to claim 9.

11. The substrate further includes a heat sink positioned below it and superimposed on at least a portion of the display area, The circuit film is separated from the heat sink. The display device according to claim 6.

12. The display device according to claim 6, wherein the entire circuit film is superimposed on the substrate.

13. The aforementioned circuit film is Multiple first signal lines, multiple second signal lines, and multiple third signal lines are located on the rear, Multiple fourth signal lines and fifth signal lines are arranged on the upper surface, The second signal line and the fifth signal line are electrically connected, and a plurality of second via holes penetrate the circuit film. It further includes, The first via hole electrically connects the first signal line and the fourth signal line. At least a portion of the plurality of second beer halls is superimposed on the display area. The display device according to claim 12.

14. The display device according to claim 13, wherein at least a portion of each of the first signal line, the second signal line, and the fifth signal line is superimposed on the display area.

15. The non-display area includes a plurality of first pads and a plurality of second pads arranged on the substrate, The integrated circuit mounted on the circuit film and It further includes, A portion of the first signal line and a portion of the second signal line are electrically connected to the integrated circuit. The fourth signal line is connected to the first pad, and the fifth signal line is connected to the second pad. At least one of the plurality of first beer holes is superimposed on the second pad. The display device according to claim 13.

16. The display device according to claim 15, wherein at least one of the plurality of first pads is positioned closer to the display area than at least one of the plurality of second pads.

17. The non-display region further includes a plurality of third via holes and a plurality of fourth via holes that penetrate the substrate, The display device according to claim 15, wherein the plurality of first via holes are arranged at a position further away from the display area than the plurality of third via holes and the plurality of fourth via holes.

18. The arrangement direction of the plurality of first via holes included in the first group is the same as the arrangement direction of the plurality of first via holes included in the second group, or The display device according to claim 1, wherein the arrangement direction of the plurality of first via holes included in the first group is different from the arrangement direction of the plurality of first via holes included in the second group.

19. The display device according to claim 18, wherein the arrangement direction of the plurality of first via holes included in the first group intersects with the arrangement direction of the plurality of first via holes included in the second group in any one of the plurality of first via holes included in the first group.

20. The aforementioned circuit film is Multiple signal lines located on at least one of the top or back surfaces, The first protective layer disposed on the upper surface, The second protective layer located on the back surface and Furthermore, The first protective layer includes an opening region that exposes at least a portion of the plurality of signal lines arranged on the upper surface of the circuit film, or The second protective layer includes an opening region that exposes at least a portion of the plurality of signal lines arranged on the back surface of the circuit film. The display device according to claim 1.

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