Display devices and personal digital assistants

Abstract

Reduces parasitic capacitance in the wiring of the display device. High resolution and high frame rate are both possible. To provide a standing display device. To provide a high-definition display device. [Solution] The semiconductor device applied to the display device has a first wiring and a transistor between them. A resin layer 1, a first insulating layer between the first resin layer and the transistor, and the transistor Between the second wiring, there is a second resin layer, and between the second resin layer and the transistor, there is a second insulating layer It has a margin layer. The first insulating layer and the second insulating layer have an inorganic insulating film containing nitrogen. Furthermore, the first resin layer and the second resin layer are thicker than the first insulating layer and the second insulating layer, respectively. The dielectric constant is low, and the thickness is between 5 and 100 times the original thickness.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same. Regarding the device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the technical field is semiconductor devices, display devices, light-emitting devices, energy storage devices, and memory devices. Electronic equipment, lighting equipment, input devices, input / output devices, methods for driving them, or methods for manufacturing them. Laws can be cited as one example. Semiconductor devices function by utilizing semiconductor properties. This refers to all devices that can do so. [Background technology]

[0003] In recent years, there has been a demand for high-resolution display devices. For example, home television equipment (tele In a TV (also called a television receiver), the resolution is full HD (19 pixels). While 20x1080 resolution is currently the mainstream, 4K (3840x21 pixels) is expected to become more common in the future. 60), or high resolution such as 8K (7680 x 4320 pixels), It is expected that resolution will continue to increase.

[0004] Furthermore, mobile phones, smartphones, tablet devices, and laptop PCs are also available. In information terminal equipment, the display panels used in the display sections of the devices are also becoming higher resolution. ru.

[0005] As a semiconductor material applicable to transistors used in display devices, metal oxides are used. Oxide semiconductors are attracting attention. For example, Patent Document 1 describes stacking multiple oxide semiconductor layers. The oxide semiconductor layers are layered, and among the plurality of oxide semiconductor layers, the oxide semiconductor layer that forms the channel is indium and By including gallium and having a higher proportion of indium than gallium, A semiconductor device with enhanced field effect mobility has been disclosed. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2014-7399 [Overview of the project] [Problems that the invention aims to solve]

[0007] In display devices of the same screen size, higher resolution results in higher pixel density, therefore wiring The parasitic capacitance between them increases. Furthermore, the higher the resolution, the more wires a single wire crosses. As it increases, the parasitic capacitance increases accordingly. If the parasitic capacitance of the wiring is large, the time constant of the wiring becomes As the size increases, it becomes difficult to display images at high frame rates.

[0008] One aspect of the present invention aims to provide a display device in which the parasitic capacitance of the wiring is reduced. One aspect of the present invention provides a display device that achieves both high resolution and a high frame rate. One objective of the present invention is to provide a high-resolution display device. This is one aspect of the present invention. One aspect of the present invention provides a highly reliable display device or semiconductor device. This will be one of the challenges.

[0009] One aspect of the present invention relates to a semiconductor device, display device, display module, and having a novel configuration. One of the objectives of this invention is to provide electronic devices and the like. One aspect of this invention is the above-mentioned display device. Another object of the present invention is to provide a method for manufacturing a semiconductor device with high yield. One aspect of the present invention aims to at least reduce at least one of the problems of the prior art.

[0010] Note that the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily need to solve all of these problems. Other problems can be extracted from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention is a semiconductor device having a first wiring, a second wiring, and a transistor. The semiconductor device has a first resin layer between the first wiring and the transistor. The semiconductor device has a first insulating layer between the first resin layer and the transistor. The semiconductor device has a second resin layer between the transistor and the second wiring. The semiconductor device has a second insulating layer between the second resin layer and the transistor. The first insulating layer and the second insulating layer have an inorganic insulating film containing nitrogen. The first resin layer and the second resin layer each have a lower dielectric constant than the first insulating layer and the second insulating layer, respectively. Also, the first resin layer and the second resin layer each have a thickness that is 5 times or more and 100 times or less that of the first insulating layer and the second insulating layer, respectively.

[0012] Preferably, the first resin layer and the second resin layer contain the same material and have the same thickness. Or, preferably, the thickness of the second resin layer is 80% or more and 120% or less of the thickness of the first resin layer. Further, preferably, the first resin layer and the second resin layer are formed by the same film-forming method using the same material. ​​​​​​​​​​

[0013] Furthermore, the first insulating layer and the second insulating layer contain the same material and have equal thickness to each other. Preferably, the thickness of the second insulating layer is 80% or more of the thickness of the first insulating layer. It is preferable that it be 0% or less. Furthermore, the first insulating layer and the second insulating layer are made of the same material. It is preferable that the film is formed using the same film formation method as used.

[0014] Furthermore, in the above, the transistor comprises a first gate electrode, a second gate electrode, and It is preferable to have a gate insulating layer, a second gate insulating layer, and a semiconductor layer. In this case, the first gate insulating layer is located between the semiconductor layer and the first gate electrode. The gate insulating layer is located between the semiconductor layer and the second gate electrode. The second gate electrode has a region that overlaps with it via a semiconductor layer. The first gate electrode has a region that overlaps with it via a semiconductor layer. In the openings provided in the insulating layer and the first resin layer, the first wiring is electrically connected. It can be done.

[0015] Furthermore, in the above, the second wiring is provided in the openings of the second resin layer and the second insulating layer. In this section, it is preferable to electrically connect it to the semiconductor layer.

[0016] Alternatively, in the above, the transistor has a first between the second resin layer and the second insulating layer It is preferable to have electrodes. Furthermore, the first electrode is an opening provided in the second insulating layer In this case, it is preferable to electrically connect to a part of the semiconductor layer. Also, the second wiring is In the opening provided in the second resin layer, it is preferable that it be electrically connected to the first electrode. It's nice.

[0017] Furthermore, in any of the above, the second gate electrode is the first gate insulating layer and the second gate An opening provided in the insulating layer is electrically connected to the first gate electrode. preferable.

[0018] Furthermore, in any of the above, the semiconductor layer may be made of either indium or zinc. It is preferable that both and oxygen are included. In this case, the semiconductor layer is indium, gallium The semiconductor layer contains indium and zinc, and the atomic ratio of indium is more than twice that of gallium. Furthermore, it is more preferable that the atomic ratio of zinc is at least twice that of gallium.

[0019] Furthermore, in any of the above, the first resin layer and the second resin layer are acrylic, Alternatively, it is preferable to include polyimide.

[0020] Furthermore, one aspect of the present invention comprises any of the above-mentioned semiconductor devices, a pixel electrode, and a source driving circuit. The display device has a gate drive circuit and a pixel electrode and a transient It is preferable to have a third resin layer between the starter and the starter. Also, the first wiring is source drive. The second wire is electrically connected to the circuit, and it is preferable that the second wire be electrically connected to the gate drive circuit. It seems so.

[0021] Furthermore, it is preferable to have an organic EL element in the above. The primary electrode is preferably an electrode of an organic EL element.

[0022] Furthermore, one aspect of the present invention comprises any of the above-mentioned display devices, a connector or integrated circuit, It is a display module that has [a certain feature].

[0023] Furthermore, one aspect of the present invention includes the above-mentioned display module, an antenna, a battery, a housing, and a camera. It has at least one of the following: a speaker, microphone, touch sensor, and control button. It is an electronic device. [Effects of the Invention]

[0024] According to one aspect of the present invention, a display device with reduced parasitic capacitance in the wiring can be provided. This allows us to provide a display device that achieves both high resolution and a high frame rate. We can provide a fine display device. Or, we can provide a highly reliable display device or semiconductor device. ru.

[0025] According to one aspect of the present invention, a semiconductor device, a display device, and a display module having a novel configuration , or can provide electronic devices, etc. Or, can yield the above-mentioned display devices or semiconductor devices. A method for manufacturing can be provided that is more efficient. According to one aspect of the present invention, the problems of the prior art are reduced. At the very least, it can reduce the severity by at least one.

[0026] Furthermore, the description of these effects does not preclude the existence of other effects. One embodiment does not necessarily have to possess all of these effects. Furthermore, other effects may be considered. This information can be extracted from descriptions such as specifications, drawings, and claims. [Brief explanation of the drawing]

[0027] [Figure 1] Figures 1A to 1C show examples of semiconductor device configurations. [Figure 2] Figures 2A and 2B show examples of semiconductor device configurations. [Figure 3] Figures 3A and 3B show examples of semiconductor device configurations. [Figure 4]Figures 4A to 4F illustrate examples of methods for manufacturing semiconductor devices. [Figure 5] Figures 5A to 5D illustrate examples of methods for manufacturing semiconductor devices. [Figure 6] Figures 6A to 6C illustrate examples of methods for manufacturing semiconductor devices. [Figure 7] Figures 7A and 7B illustrate examples of semiconductor device manufacturing methods. [Figure 8] Figures 8A and 8B illustrate examples of methods for manufacturing semiconductor devices. [Figure 9] Figures 9A to 9C show examples of display device configurations. [Figure 10] Figures 10A to 10C show examples of pixel configurations. [Figure 11] Figure 11 shows an example of a display device configuration. [Figure 12] Figure 12 shows an example of a display device configuration. [Figure 13] Figures 13A to 13F show examples of the configuration of electronic equipment. [Figure 14] Figures 14A and 14B show examples of the configuration of a display module. [Figure 15] Figures 15A and 15B show examples of electronic device configurations. [Figure 16] Figures 16A to 16E show examples of electronic device configurations. [Figure 17] Figures 17A to 17G show examples of electronic device configurations. [Figure 18] Figures 18A to 18D show examples of the configuration of electronic equipment. [Modes for carrying out the invention]

[0028] The embodiments will be described below with reference to the drawings. However, many embodiments are described. It can be implemented in different ways, without deviating from its purpose and scope. Those skilled in the art will readily understand that the form and details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents described in the following embodiments.

[0029] In the configuration of the invention described below, the same part or part having a similar function is The same reference numerals are used consistently across different drawings, and explanations of their repetition are omitted. When referring to the function of [this], the hatch pattern is the same, and sometimes no specific symbol is assigned.

[0030] In each figure described herein, the size, layer thickness, or area of ​​each component is not specified. This may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. I can't.

[0031] In this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion of constituent elements. This is added for the purpose of providing a numerical limit, and is not intended to limit the number of items.

[0032] A transistor is a type of semiconductor device that has the function of amplifying current or voltage, and conducting electricity. Alternatively, switching operations that control non-conductivity can be implemented. The transistor is an IGFET (Insulated Gate Field Efficient). (ct Transistor) and Thin Film Transistor (TFT) Includes (ransistor).

[0033] Furthermore, the "source" and "drain" functions are used when transistors with different polarities are employed. Or, they may be reversed when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" are to be used interchangeably. It is assumed that this is possible.

[0034] Furthermore, in this specification, the terms "membrane" and "layer" are interchangeable. It is possible to replace them. For example, the terms "conductive layer" or "insulating layer" are replaced with "conductive film". In some cases, the terms "insulating film" or "insulating film" can be used interchangeably.

[0035] In this specification, a display panel, which is one form of a display device, displays an image or the like on its display surface. It has the function of (powering). Therefore, the display panel is one form of an output device.

[0036] Furthermore, in this specification, the substrate of the display panel may be, for example, FPC (Flexible Printed Circuit). (inted Circuit) or TCP (Tape Carrier Packa A connector such as a ge is attached, or the circuit board has a COG (Chip On A display panel module or display module is a device on which an IC is mounted using a glass or similar method. It may be called a display panel, or simply a display board.

[0037] (Embodiment 1) In this embodiment, a semiconductor device, a method for manufacturing the same, and a display device, etc., according to one aspect of the present invention are described. I will explain this in particular. In this embodiment, as an example of a semiconductor device, a channel is formed This section describes transistors that use oxide semiconductors in their semiconductor layers.

[0038] [Example Configuration] [Configuration Example 1] Figure 1A shows a schematic top view of a semiconductor device including transistor 100. Figure 1B shows... Figure 1A shows a cross-sectional view along the dashed line A1-A2, and Figure 1C shows the same point shown in Figure 1A. This corresponds to the cross-sectional view along the dashed line B1-B2. Note that in Figure 1A, some of the components (G The diagram omits the insulating layer, etc. Also, Figure 1B shows the channel length of transistor 100. Figure 1C shows a cross-sectional view including a cross-section in the channel width direction.

[0039] The transistor 100 is provided on the substrate 102 and has a conductive layer 106, an insulating layer 103a, and an insulating layer Edge layer 103b, semiconductor layer 108, insulating layer 110, metal oxide layer 114, and conductive layer 112 It has the following features. A resin layer 131 is provided between the transistor 100 and the substrate 102. A resin layer 132 is provided on the transistor 100. The resin layer 131 and the transistor An insulating layer 104 is provided between the transistor 100 and the resin. Insulating layers 116 and 118 are laminated between layer 132 and the other layer.

[0040] In transistor 100, a portion of the conductive layer 106 and a portion of the conductive layer 112 are It functions as a gate electrode. Also, a part of the insulating layer 103a, a part of the insulating layer 103b, and A portion of the insulating layer 110 functions as a gate insulating layer.

[0041] A conductive layer 130, which functions as wiring, is provided between the substrate 102 and the resin layer 131. Furthermore, a conductive layer 120a and a conductive layer 120b are provided on the resin layer 132. At least one of the conductive layer 120a and conductive layer 120b functions as a wire.

[0042] Furthermore, the resin layer 133 covers the resin layer 132, the conductive layer 120a, and the conductive layer 120b. It is provided. Furthermore, a conductive layer 150 is provided on the resin layer 133. Conductive layer 15 0 can be used, for example, as a pixel electrode of a display element. Alternatively, the conductive layer 150 is It may also be used as wiring. The conductive layer 150 is provided in the opening 144 of the resin layer 133. It is electrically connected to the conductive layer 120b.

[0043] The insulating layer 104 contains impurities such as water or hydrogen in the resin layer 131, which can affect the transistor 100. It functions as a barrier film that prevents diffusion into the resin layer 1. Similarly, the insulating layer 116 also functions as a barrier film that prevents diffusion into the resin layer 1. This prevents impurities such as water or hydrogen contained in 32 from diffusing into transistor 100. It functions as a barrier film. In this way, the transistor 100 is separated by the insulating layer 104 and the insulating layer 11 By using a configuration that encloses it with 6, the structure is such that the top and bottom of the transistor 100 are sandwiched between resin layers. This also enables the creation of highly reliable semiconductor devices.

[0044] Insulating layers 104 and 116 use an inorganic insulating film that is resistant to the diffusion of water or hydrogen. This is possible. For example, silicon nitride, silicon oxide nitride, silicon oxide nitride, aluminum nitride Insulating films containing nitrides, such as aluminum oxide or aluminum nitride, can be suitably used. In particular, silicon nitride blocks either hydrogen or oxygen, or both. Because it has properties, hydrogen diffuses from the outside to the semiconductor layer 108 and from the semiconductor layer 108 to the outside. This prevents both oxygen desorption and the resulting transistor, enabling the creation of highly reliable transistors.

[0045] Organic resins can be used for resin layers 131 and 132. In particular, acrylic Alternatively, polyimide is preferable. Furthermore, materials that can be used in the resin layer 131 This is not limited to the above, and chemically or thermally stable materials can be used.

[0046] The resin layers 131 and 132 preferably function as planarizing films. For example, The film is preferably formed by a coating method such as pin coating or slit coating. The resin layer 131 functions as a planarizing film, so that the transistor 100 is more efficient than the substrate 1 The effect of the step caused by the conductive layer 130 located on the 02 side is suppressed, and the surface of the transistor 100 to be formed This allows the surface to be made flat, reducing variations in the electrical characteristics of the transistor 100. Also, the resin layer 1 32 functions as a planarization film, suppressing the effect of the step caused by transistor 100. The surfaces of conductive layer 120a and conductive layer 120b can be made flat, and these processing defects can be reduced. Furthermore, the surface on which the conductive layer 150, which can be used as a pixel electrode, is formed can be flattened. Therefore, variations in the electrical and optical characteristics of display elements using the conductive layer 150 as a pixel electrode It can reduce the amount of noise.

[0047] It is preferable that the resin layer 131 and the resin layer 132 each have low dielectric constants. Specifically, , an organic insulating layer with a dielectric constant lower than either or both of insulating layers 104 and 116 It is preferable to use an edge material. In particular, resin layer 131 and resin layer 132 are insulating layer 104 It is preferable that the dielectric constant is lower than that of both the insulating layer 116 and the dielectric constant of the insulating layer 116.

[0048] Furthermore, it is preferable that the resin layer 131 and the resin layer 132 each be formed to be thick. For example, resin layer 131 and resin layer 132 are either insulating layer 104 or insulating layer 116, respectively. It is preferable that the resin layer 131 and resin layer 132 be thicker than one or both. In particular, the resin layer 131 and resin layer 132 are It is preferable that the resin layer 1 is thicker than both the insulating layer 104 and the insulating layer 116. Specifically, the resin layer 1 31 and the resin layer 132 each have a thickness of at least 5 times that of the insulating layer 104 or the insulating layer 116. The thickness can be 00 times or less, or 5 times or more but 50 times or less, or 5 times or more but 30 times or less. Yes, it is possible. A more specific example would be insulating layer 104 and insulating layer 116 with a thickness of 50 nm or more and 300 nm. The thickness of the resin layer 131 and resin layer 132 shall be less than or equal to nm, and the thickness of the resin layer 131 and resin layer 132 shall be between 500 nm and 20 μm. Preferably, the thickness can be between 1 μm and 10 μm.

[0049] On the left side of Figure 1B, the cross-section of the conductive layer 130 and conductive layer 120a shown in Figure 1A is visible. It shows the surface.

[0050] Between the conductive layer 130 and the conductive layer 120a, there is at least a resin layer 131 and a resin layer 132 The resin layers 131 and 132 are formed with low dielectric constant and are thick. Because it is a layer, at the intersection of conductive layer 130 and conductive layer 120a, The capacity can be made extremely small. This allows for high resolution, high definition, and high frame rate. This makes it possible to create a display device that can be driven at a frame rate.

[0051] Because parasitic capacitance between wires can be reduced, the number of pixels connected to a single wire can be increased. This enables the creation of high-resolution display devices. The resolution is Full HD ("2K resolution"). Also known as "2K1K" or "2K", Ultra High Definition ("4K resolution") Also known as "4K2K" or "4K") or Super Hi-Vision ("8K") Achieving a resolution equivalent to "8K4K" or "8K" (also known as "resolution") It is possible.

[0052] Furthermore, because the parasitic capacitance between wires is small, the increase in the wiring time constant can be suppressed even when the resolution is increased. Therefore, a high-definition display device can be realized. The resolution can be, for example, 400 ppi or higher, 500 ppi or higher, preferably 1000 ppi or higher, more preferably 2000 ppi or higher Furthermore, it must be 3000 ppi or higher, and 10000 ppi or lower, 7500 ppi or lower, Alternatively, a high-definition display device with a resolution of 6000 ppi or less can be realized. Furthermore, even for display devices with a resolution of less than 400 ppi, the above configuration can be applied to... This is preferable because it can reduce raw data size. For example, if the screen diagonal size is 50 inches The above configuration is also suitable for large display devices of 60 inches or more, or 70 inches or more. It can be used appropriately.

[0053] Furthermore, the time constant of the wiring can be reduced, thus reducing the time required for charging and discharging the wiring (for example, the time required for the pixels). This reduces the writing time, making it possible to operate at a high frame rate. For example, 60Hz, 120Hz, 180Hz, and even 240Hz operation can be expected. can.

[0054] Furthermore, resin layer 131 and resin layer 132 contain the same material and have equal thickness. Preferably, the thickness of the resin layer 132 is 80% or more of the thickness of the resin layer 131. It is preferable that it be 0% or less. Furthermore, the resin layer 131 and the resin layer 132 are made of the same material. It is preferable that the film is formed using the same film formation method as used.

[0055] A pair of resin layers 131 and 132 sandwiching the transistor 100 are formed from the same material, and Furthermore, by making the thickness approximately the same, the stress can be made approximately the same. This allows the transistor Because the stress can be made to be roughly the same on the top and bottom of the Zista 100, extreme stress differences do not occur, and therefore As a result, film peeling during the process can be suppressed. Also, transient Because the stress applied to transistor 100 from above and below can be made uniform, the electrical characteristics of transistor 100 This can reduce the variability.

[0056] Furthermore, the insulating layer 104 and the insulating layer 116 also contain the same material and have different thicknesses relative to each other. It is preferable that they are equal. Alternatively, the thickness of the insulating layer 116 is 80% or less of the thickness of the insulating layer 104. It is preferable that the upper limit is 120% or less. Furthermore, insulating layer 104 and insulating layer 116 are the same It is preferable to form the film using the same film-forming method with the same material. Not only can peeling be suppressed more effectively, but the variation in the electrical characteristics of transistor 100 It can be reduced.

[0057] The conductive layer 106 is provided on the insulating layer 104. The insulating layer 103a covers the conductive layer 106. The insulating layer 103b is provided on the insulating layer 103a. Island-shaped semiconductor layer 10 8 is provided on the insulating layer 103b and superimposed on a part of the conductive layer 106. Insulating layer 110, gold The oxide layer 114 and the conductive layer 112 are arranged in this order on the semiconductor layer 108 and the insulating layer 103b. It is provided in a laminated manner and has a portion that overlaps with the semiconductor layer 108 and the conductive layer 106. 116 consists of an insulating layer 103a, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, and The insulating layer 118 is provided covering the conductive layer 112. The insulating layer 118 is provided on top of the insulating layer 116.

[0058] The semiconductor layer 108 consists of a region superimposed on the conductive layer 112 and a pair of low-resistance regions flanking that region. It has 108n. The region of the semiconductor layer 108 that overlaps with the conductive layer 112 is transistor 1 It functions as a channel formation region of 00. On the other hand, the pair of low-resistance regions 108n are transient It functions as the source and drain area of ​​Sta100.

[0059] For the insulating layer 103a located on the conductive layer 106 side, it is preferable to use an insulating film containing nitrogen. On the other hand, an insulating film containing oxygen is used for the insulating layer 103b that is in contact with the semiconductor layer 108. This is preferable. In addition, insulating layer 103a and insulating layer 103b are each plasma CVD coated. It is preferable to use a device that allows for continuous film formation without exposure to the atmosphere.

[0060] Examples of insulating layers 103a include silicon nitride film, silicon nitride oxide film, and aluminum nitride film. Insulating films containing nitrogen, such as um film or hafnium nitride film, can be used.

[0061] As for the insulating layer 103b that is in contact with the semiconductor layer 108, impurities such as water are adsorbed on its surface. It is preferable to have a dense insulating film that is resistant to water or It is preferable to use an insulating film in which impurities such as hydrogen have been reduced.

[0062] Examples of insulating layer 103b include silicon oxide film, silicon oxide nitride film, silicon oxide nitride film. Recon film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide um film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, oxide An insulating layer containing one or more cerium films and neodymium oxide films can be used. In particular, acid It is preferable to use a silicon oxide film or a silicon oxide nitride film.

[0063] The insulating layer 103b in contact with the semiconductor layer 108 preferably has an oxide insulating film. The insulating layer 103b has regions that contain an excess of oxygen compared to the stoichiometric composition. It is preferable. In other words, the insulating layer 103b has an insulating film that can release oxygen. For example, forming the insulating layer 103b under an oxygen atmosphere, and the insulating layer 103b after film formation. For this, heat treatment is performed under an oxygen atmosphere, and after the deposition of the insulating layer 110, under an oxygen atmosphere, Plasma treatment or similar processes, or an oxide film (for example) applied to the insulating layer 103b in an oxygen atmosphere. By forming a metal oxide film (which becomes the semiconductor layer 108) in the insulating layer 103b, It is also possible to supply oxygen. In addition, in each of the above oxygen supply processes, instead of oxygen, Alternatively, in addition to oxygen, an oxidizing gas (such as nitrous oxide or ozone) may be used. .

[0064] The semiconductor layer 108 contains a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor properties. The semiconductor layer 108 preferably contains at least indium and oxygen. The presence of indium oxide in 108 can increase its carrier mobility. For example, A transistor that can carry a larger current than one made of amorphous silicon. This can be achieved.

[0065] The region of the semiconductor layer 108 that overlaps with the conductive layer 112 functions as a channel formation region. Furthermore, the semiconductor layer 108 has a pair of low-resistance regions 108n flanking the channel formation region. This is preferable. The low-resistance region 108n is a region with a higher carrier concentration than the channel-forming region. It is a region that functions as both a source region and a drain region.

[0066] The low-resistance region 108n is a region with lower resistance and higher carrier concentration than the channel-forming region. This can also be referred to as a region with high oxygen deficiency, a region with high hydrogen concentration, or a region with high impurity concentration. I can say that.

[0067] Here, the composition of the semiconductor layer 108 will be described. The semiconductor layer 108 is at least It is preferable that the semiconductor layer 108 contains a metal oxide containing zinc and oxygen. In addition, it may also contain zinc. Furthermore, the semiconductor layer 108 may contain gallium. stomach.

[0068] Typical semiconductor layers 108 include indium oxide and indium zinc oxide (In -Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, IGZO and (Also written as) can be used. In addition, indium tin oxide (In-Sn oxide) can be used. Other materials such as silicon-containing indium tin oxide can also be used.

[0069] Here, the composition of the semiconductor layer 108 is determined by the electrical characteristics and reliability of the transistor 100, etc. This has a significant impact. For example, by increasing the indium content in semiconductor layer 108, This improves carrier mobility and enables the realization of transistors with high field-effect mobility.

[0070] Here, as one of the indicators for evaluating the reliability of a transistor, an electric field is applied to the gate. Gate bias stress test (GBT) There is an SS Test. Among them, the gate is used with respect to the source potential and drain potential. A test in which a positive potential is applied and maintained at a high temperature is called PBTS (Positive Voltage Test). (Temperature Stress) test, with a negative potential applied to the gate, The test of holding at high temperatures is called NBTS (Negative Bias Temperature Test). This is called the e-stress test. It is also called a PB test, which is performed under the illumination of light such as white LED light. The TS trial and the NBTS trial were conducted using PBTIS (Positive Bias Test). mperature Illumination Stress) test, NBTIS(N egative Bias Temperature Illumination St This is called a (RESS) test.

[0071] In particular, in n-type transistors using oxide semiconductors, the transistor is in the ON state. When the gate is set to a state where current is flowing, a positive potential is applied to it, therefore in PBTS testing... The fluctuation in key voltage is one of the important factors to consider as an indicator of transistor reliability. This is the result.

[0072] Here, the composition of the semiconductor layer 108 is either gallium-free or gallium-free. By using a metal oxide film with low volts, the fluctuation in threshold voltage during PBTS testing can be reduced. It is possible to do so. Also, if gallium is included, the composition of the semiconductor layer 108 is as follows: It is preferable to have a gallium content that is lower than the um content. This ensures reliability This makes it possible to create high-performance transistors.

[0073] More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer 108, the atoms of In A metal oxide film with a numerical ratio higher than the atomic ratio of Ga can be applied to the semiconductor layer 108. It is possible to use a metal oxide film in which the atomic ratio of Zn is higher than that of Ga. , more preferable. In other words, the atomic ratio of the metal elements is In > Ga and Zn > Ga. It is preferable to apply the filling metal oxide film to the semiconductor layer 108.

[0074] For example, in semiconductor layer 108, the atomic ratio of metal elements is In:Ga:Zn=2:1: 3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn =4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, I n:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6: A metal oxide film with a ratio of 1:6, In:Ga:Zn=5:2:5, or close to these values ​​is used. It is possible to be there.

[0075] Alternatively, as the semiconductor layer 108, a metal oxide with an atomic ratio of metal elements within the above range may be used. It is preferable that the film is formed by sputtering using a GET. The composition of the semiconductor layer 108 after film formation may deviate from the composition of the metal oxide target. .

[0076] Alternatively, a gallium-free metal oxide film may be applied to the semiconductor layer 108. For example, In this case, an In-Zn oxide can be applied to the semiconductor layer 108. By increasing the ratio of the number of In atoms to the number of metal elements contained in the transistor, The field effect mobility can be increased. On the other hand, the number of atoms of the metal element contained in the metal oxide By increasing the atomic ratio of Zn, a highly crystalline metal oxide film is formed, The fluctuations in the electrical characteristics of the zista are suppressed, and reliability can be improved. Also, the semiconductor layer 10 Even if a gallium and zinc-free metal oxide film, such as indium oxide, is applied to 8... Good. By using a metal oxide film that contains no gallium at all, especially in PBTS testing... The fluctuation in the threshold voltage can be made extremely small.

[0077] For example, oxides such as indium oxide, indium zinc oxide, and indium tin oxide. The film can be used as the semiconductor layer 108.

[0078] Although gallium was explained as a representative example here, the element M (M is) can be used instead of gallium. Aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium Selected from luminous, neodymium, hafnium, tantalum, tungsten, or magnesium. The above description can also be applied when using one or more types. In particular, M is gallium, a It is preferable to use one or more species selected from luminium, yttrium, or tin. It's nice.

[0079] It is preferable to use a crystalline metal oxide film for the semiconductor layer 108. For example, CAAC (c-axis aligned crystal) structure, polycrystalline structure, which will be described later. A metal oxide film having a microcrystalline structure can be used. By using the film in the semiconductor layer 108, the defect level density in the semiconductor layer 108 can be reduced. This enables the creation of highly reliable semiconductor devices.

[0080] The higher the crystallinity of the semiconductor layer 108, the lower the defect level density in the film. On the other hand, By using a metal oxide film with low crystallinity, transistors can conduct large currents. This can be achieved.

[0081] When forming a metal oxide film by sputtering, the higher the substrate temperature (stage temperature) during film formation, the higher the crystallinity of the metal oxide film that can be formed. Also, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during film formation (also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film that can be formed. The low-resistance region 108n of the semiconductor layer 108 is a region containing impurity elements. Examples of such impurity elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, or noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable to contain boron or phosphorus. Also, two or more of these elements may be included. The low-resistance region 108n preferably contains a region where the impurity concentration is 1×10 atoms / cm

[0082] or more, 1×1 0 atoms / cm or less, preferably 5×10 atoms / cm

[0083] or more, 5× 19 atoms / cm 3 or less, more preferably 1×10 0 23 atoms / cm 3 or more 19 atoms / cm 3 and 1×10 0 22 atoms / cm 3 or less. 20 atoms / cm 3 The concentration of impurities contained in the low-resistance region 108n can be measured by, for example, secondary ion mass spectrometry (SIM S:Secondary Ion Mass Spectrometry), or X-ray 22 atoms / cm 3 The concentration of impurities contained in the low-resistance region 108n can be measured by, for example, secondary ion mass spectrometry (SIMS:Secondary Ion Mass Spectrometry), or X-ray

[0084] S:Secondary Ion Mass Spectrometry), or X-ray S:Secondary Ion Mass Spectrometry), or X-ray Photoelectron spectroscopy (XPS:X-ray Photoelectron Spectrosc) Analysis can be performed using analytical methods such as opy. When using XPS analysis, the surface side Alternatively, by combining ion sputtering from the back side with XPS analysis, the depth direction can be determined. The concentration distribution can be determined.

[0085] The conductive layer 112, the metal oxide layer 114, and the insulating layer 110 have roughly the same top surface shape. It is processed to do so.

[0086] In this specification, "approximately matching top surface shape" means that there is a small difference between the stacked layers. This refers to the overlapping of parts of the outlines. For example, the upper layer and the lower layer may have the same mask pattern. , or including cases where part of it is processed with the same mask pattern. However, strictly speaking, ring The walls do not overlap, and the upper layer is located inside the lower layer, or the upper layer is located outside the lower layer. In some cases, the top surface shape is described as "approximately identical."

[0087] As an insulating film that can be used for the insulating layer 110, refer to the description of the insulating layer 103b above. It is possible.

[0088] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 is in the insulating layer 110. It functions as a barrier film that prevents the contained oxygen from diffusing to the conductive layer 112. The oxide layer 114 allows hydrogen or water contained in the conductive layer 112 to diffuse towards the insulating layer 110. It also functions as a barrier film to prevent this. The metal oxide layer 114 is, for example, at least an insulating layer. It is preferable to use a material that is less permeable to oxygen and hydrogen than 110.

[0089] The metal oxide layer 114 attracts oxygen such as aluminum or copper to the conductive layer 112. Even when using inexpensive metal materials, oxygen diffuses from the insulating layer 110 to the conductive layer 112. This can prevent this from happening. Also, even if the conductive layer 112 contains hydrogen, the conductive layer 1 This prevents hydrogen from diffusing from 12 to the semiconductor layer 108 via the insulating layer 110. As a result, the carrier density in the channel formation region of the semiconductor layer 108 is made extremely low. It can be done this way.

[0090] As the metal oxide layer 114, an insulating material or a conductive material can be used. If the metal oxide layer 114 has insulating properties, the metal oxide layer 114 is part of the gate insulating layer. It functions as follows. On the other hand, if the metal oxide layer 114 is conductive, the metal oxide layer 1 14 functions as part of the gate electrode.

[0091] As the metal oxide layer 114, an insulating material with a higher dielectric constant than silicon oxide is used. This is preferred. In particular, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminum film is preferred. Using a film or similar material is preferable because it allows for a reduction in the driving voltage.

[0092] For example, the metal oxide layer 114 may be indium oxide or indium tin oxide (ITO). or conductive oxides such as silicon-containing indium tin oxide (ITSO) It can also be used. Conductive oxides containing indium are particularly preferred due to their high conductivity. .

[0093] Furthermore, the metal oxide layer 114 may contain one or more of the same elements as the semiconductor layer 108. It is preferable to use a material. In particular, an oxide semiconductor material applicable to the semiconductor layer 108 is preferable. It is preferable to use the same material as the semiconductor layer 108 as the metal oxide layer 114. By applying a metal oxide film formed using a puttering target, the equipment can be standardized. This is preferable because it allows for this.

[0094] Furthermore, the metal oxide layer 114 is preferably formed using a sputtering apparatus. When forming an oxide film using a sputtering apparatus, the film is formed in an atmosphere containing oxygen gas. This allows for the appropriate addition of oxygen to the insulating layer 110 or the semiconductor layer 108.

[0095] The insulating layer 116 is provided in contact with the upper surface of the low-resistance region 108n. It is preferable that the insulating layer 11 has the function of reducing the resistance of the resistive region 108n. 6. By heating during or after the deposition of the insulating layer 116, a low-resistance region 1 An insulating film that can supply impurities into O8n can be used. Alternatively, an insulating layer By heating during or after film formation of 116, oxygen vacancies are created in the low-resistance region 108n. An insulating film capable of producing this can be used. Alternatively, when forming the insulating layer 116 By heating after film formation, an insulating film can be used to impart strain to the low-resistance region 108n. A border film can be used.

[0096] For example, as an insulating layer 116, a source for supplying impurities to the low-resistance region 108n is used. An insulating film capable of this can be used. In this case, the insulating layer 116 releases hydrogen upon heating. It is preferable that the film is such that an insulating layer 116 is formed in contact with the semiconductor layer 108. By doing so, impurities such as hydrogen are supplied to the low-resistance region 108n, and the low-resistance region 108n is reduced to low resistance It can be made resistant.

[0097] The insulating layer 116 is made of a gas that contains impurity elements such as hydrogen, which is used as the film-forming gas during film formation. It is preferable that the film is formed using [a specific method]. Furthermore, the lower the film formation temperature of the insulating layer 116, This allows for the effective supply of many impurity elements to the semiconductor layer 108. The film temperature is, for example, 200°C to 500°C, preferably 220°C to 450°C. More preferably, the temperature can be between 230°C and 400°C.

[0098] Furthermore, by forming the insulating layer 116 under reduced pressure and heating, the semiconductor layer 108 This can promote the desorption of oxygen from the region with low resistance of 10⁸n. By supplying impurities such as hydrogen to the formed semiconductor layer 108, a low-resistance region 108 is created. The carrier density in n increases, making it possible to more effectively reduce the resistance of the low-resistance region 108n. can.

[0099] Examples of insulating layer 116 include silicon nitride, silicon nitride oxide, and silicon oxide nitride. Preferably, an insulating film containing a nitride, such as aluminum nitride or aluminum oxide nitride, is used. This is possible. In particular, silicon nitride has blocking properties for hydrogen or oxygen. Therefore, both hydrogen diffusion from the outside to the semiconductor layer and oxygen desorption from the semiconductor layer to the outside are necessary. This can be prevented, and highly reliable transistors can be realized. Alternatively, silicon oxide, oxide Insulating films containing oxides such as aluminum and hafnium oxide can also be used.

[0100] The insulating layer 118 functions as a protective layer to protect the transistor 100. Insulating layer 110 For example, inorganic insulating materials such as oxides or nitrides can be used. Specific examples include silicon oxide, silicon oxide nitride, silicon nitride, and silicon oxide nitride. Aluminum oxide, aluminum nitride oxide, aluminum nitride, hafnium oxide, haf Inorganic insulating materials such as nium aluminate can be used.

[0101] Furthermore, it is not necessary to provide either the insulating layer 116 or the insulating layer 118. The stacking order of layer 116 and the insulating layer 118 may be changed.

[0102] A portion of the conductive layer 120a and conductive layer 120b provided on the resin layer 132 is a transistor It is electrically connected to the low-resistance region 108n of TA100 and serves as either the source electrode or the drain electrode. It can also be said that it functions in this way. Conductive layer 120a and conductive layer 120b are each made of resin layer 132, Through the openings 141a or 141b provided in the insulating layer 118 and the insulating layer 116 This then electrically connects to the low-resistance region 108n.

[0103] Furthermore, here, conductive layer 112, conductive layer 106, and conductive layer 130 are electrically An example of a connection is shown. The conductive layer 112 is connected to the metal oxide layer 114 and the insulating layer 110. In the opening 142 provided in the insulating layer 103b and the insulating layer 103a, the conductive layer 106 It is electrically connected to the insulating layer 104 and the resin layer 131. The opening 143 is electrically connected to the conductive layer 130.

[0104] In this example, both gate electrodes of the pair are electrically connected to the conductive layer 130. However, either one may be electrically connected to the conductive layer 130. For example, conductive layer When 130 and the conductive layer 112 are electrically connected without the conductive layer 106, the conductive layer 106 The conductive layer 130 and the conductive layer 106 are connected via an intermediate electrode formed by processing the same conductive film. An electrical connection is sufficient. Alternatively, the connection can extend from the metal oxide layer 114 to the upper surface of the conductive layer 130. An opening may be formed to directly connect the conductive layer 112 and the conductive layer 130.

[0105] Furthermore, by not providing the conductive layer 106 below the semiconductor layer 108, one of the gates It may also be a transistor that has only one gate (also called a single-gate transistor). In this case, the transistor has its gate above the semiconductor layer 108 where the channel is formed. This can be made into a so-called top-gate type transistor. For example, in Figure 1C The right edge of the conductive layer 106 is positioned between the opening 142 and the semiconductor layer 108. By forming this structure, a single-gate transistor can be realized.

[0106] [Configuration Example 2] Figures 2A and 2B show an example with some configuration differences from the above example 1. The configuration shown in B differs primarily in the shape of the insulating layer 110.

[0107] The insulating layer 110 is provided to cover the upper surface of the insulating layer 103b and the upper and side surfaces of the semiconductor layer 108. The insulating layer 110 is present not only in the channel formation region of the semiconductor layer 108, but also in the low-resistance region. It is provided in contact with the upper surface of region 108n.

[0108] The low-resistance region 108n forms an insulating layer 110, a metal oxide layer 114, and a conductive layer 112. After that, the conductive layer 112 is used as a mask to supply impurities and other substances through the insulating layer 110. It can be formed by, for example, plasma treatment, plasma ion doping, and The aforementioned impurity elements are implanted into the semiconductor layer 10 via the insulating layer 110 by methods such as ion implantation. It can be supplied to 8.

[0109] By configuring the insulating layer 110 in this way, the insulating layer near the edge of the conductive layer 112 This improves the coverage of 116, thereby increasing reliability and manufacturing yield. It is possible.

[0110] [Configuration Example 3] The configuration shown in Figure 3A has conductive layer 121a and conductive layer 121b, which is equivalent to the above configuration example 1. It differs primarily from the above.

[0111] The conductive layer 120a is electrically connected to the low-resistance region 108n via the conductive layer 121a. Furthermore, the conductive layer 120b has electrical connections with the low-resistance region 108n via the conductive layer 121b. It is connected to the following: Therefore, conductive layer 121a and conductive layer 121b are connected to the relay wiring. It can also be said that...

[0112] The conductive layer 121a and the conductive layer 121b are provided between the insulating layer 118 and the resin layer 132. The conductive layer 121a and the conductive layer 121b are the insulating layer 118 and the insulating layer 116, respectively. An opening is provided in the structure, which is electrically connected to the low-resistance region 108n.

[0113] The conductive layer 120a and the conductive layer 120b are connected at an opening in the resin layer 132. They are electrically connected to conductive layer 121a and conductive layer 121b, respectively.

[0114] Thus, conductive layers 121a and 121b, which function as relay wiring, are placed in an insulating layer 1 By placing it between 18 and the resin layer 132, it is not necessary to form a deep contact hole. Therefore, the manufacturing yield can be increased. For example, a resin layer 132 containing resin, When opening the insulating layer 118 and insulating layer 116, which include an inorganic insulating film, in a series of steps, Not only are the constraints on processing conditions stricter, but the semiconductor layer 108 located at the bottom of the opening disappears. Problems may occur, such as the opening diameter becoming larger.

[0115] Furthermore, in Figure 3A, at the connection between conductive layer 120a and conductive layer 121a, resin layer 132 The opening provided in and the openings provided in the insulating layer 118 and insulating layer 116 are mutual An example of overlapping is shown. Also, as in the connection between conductive layer 120b and conductive layer 121b, The two openings can also be offset so that they do not overlap.

[0116] Figure 3B shows the configuration illustrated in Configuration Example 2 above, with conductive layers 121a and 121b applied. This is an example of the case where the conductive layer 121a and conductive layer 121b are insulated by the insulating layer 118, respectively. In the openings provided in the edge layer 116 and the insulating layer 110, the low-resistance region 108n and the electrical They are directly connected.

[0117] [Example of manufacturing method] The following describes an example of a method for manufacturing the semiconductor device exemplified above, with reference to the drawings. Here, we will explain using the semiconductor device illustrated in Configuration Example 2, Figure 2A, and Figure 2B as an example. .

[0118] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices are produced by sputtering. Chemical vapor deposition (CVD) method Vacuum deposition, pulsed laser deposition (PLD) tion) method, Atomic Layer Deposition (ALD) method It can be formed using methods such as the CVD method. CVD methods include plasma chemical vapor deposition (PE This includes methods such as CVD (Plasma-Enhanced CVD) or thermal CVD. Furthermore, one of the thermal CVD methods is metal-organic chemical vapor deposition (MOCVD). There is also the anic CVD method.

[0119] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices are spin-coated. Dip, spray coating, inkjet, dispensing, screen printing, offset Printing, doctor's knife, slit coat, roll coat, curtain coat, knife coat It can be formed by methods such as those listed above.

[0120] Furthermore, when processing the thin films that make up semiconductor devices, photolithography and other methods are used. It can be processed using nanoimprint lithography, sandblasting, and lift-off. Thin films may be processed using methods such as the F method. Alternatively, a shielding mask such as a metal mask may be used. Island-like thin films may be directly formed by a film-forming method.

[0121] There are two main methods of photolithography. One is to process the image... A resist mask is formed on a thin film, and the thin film is processed by etching or the like, and the resist This is a method for removing the mask. Another method is to deposit a photosensitive thin film and then expose it to light. This method involves developing the film and then processing it into a desired shape.

[0122] In photolithography, the light used for exposure is, for example, the i-line (wavelength 365 nm). Using g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof This can be done by using ultraviolet light, KrF laser light, or ArF laser light, etc. It is also possible to perform exposure using immersion lithography. Furthermore, the light used for exposure and Then, extreme ultraviolet (EUV) light or X-rays It may be used. Also, an electron beam can be used instead of the light used for exposure. Extreme Using ultraviolet light, X-rays, or electron beams is preferable because it allows for extremely fine processing. Furthermore, when exposure is performed by scanning a beam such as an electron beam, photomass The "ku" is unnecessary.

[0123] Thin film etching methods include dry etching, wet etching, and sandblasting. Laws and other regulations can be used.

[0124] Figures 4A to 8B show the steps in the manufacturing process of the semiconductor device illustrated in Configuration Example 2. The cross-sections in the channel length direction and the channel width direction are shown side by side.

[0125] [Formation of conductive layer 130] A conductive film is formed on the substrate 102, and this is processed by etching to function as wiring. A conductive layer 130 is formed (Figure 4A).

[0126] At this time, the resin layer 131 that is formed later functions as a planarizing film, and the coverage is extremely high. Therefore, the conductive layer 130 does not need to be tapered. Also, the conductive layer 130 can be made thicker. Therefore, the wiring resistance of the wiring to which the conductive layer 130 is applied can be reduced.

[0127] Furthermore, by using a conductive film containing copper as the conductive film that forms the conductive layer 106, the wiring resistance can be reduced. It can be made smaller. For example, when applied to a large display device or when used as a display device with high resolution, it is preferable to use a conductive film containing copper. Also, even when a conductive film containing copper is used for the conductive layer 106, since the diffusion of copper to the semiconductor layer 108 side is suppressed by the insulating layer 103a, a highly reliable transistor can be realized.

[0128] 〔Formation of Resin Layer 131〕 Subsequently, a resin layer 131 covering the substrate 102 and the conductive layer 130 is formed (Fig. 4B).

[0129] The resin layer 131 is formed, for example, by a method such as spin coating, dipping, spray coating, inkjet, dispenser, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, knife coating, etc., using a mixed material of a resin precursor and a solvent on a support substrate. Then, by performing a heat treatment, while removing the solvent and the like, the material is cured to form a resin layer 131 containing an organic resin.

[0130] Typically, polyimide can be used as the organic resin that can be used for the resin layer 131. Polyimide is preferable because of its excellent heat resistance. In addition, acrylic, epoxy, polyamide, polyimide amide, siloxane, benzocyclobutene-based resin, phenol resin, etc. can be used.

[0131] For example, when using polyimide, a resin precursor that forms an imide bond by dehydration can be used. Or, a material containing soluble polyimide may be used.

[0132] ​​​​​​​​​​The organic resin used in the resin layer 131 can be either a photosensitive or non-photosensitive resin. Good. Photosensitive polyimide is a suitable material for use in planarization films of display panels, etc. Therefore, forming apparatus and materials can be shared. For this reason, the configuration of one aspect of the present invention can be implemented. It does not require any new equipment or materials to achieve this. Furthermore, it does not use photosensitive resin materials. By applying exposure and development processes, for example, an opening can be formed, or an opening can be formed. The essential parts can be removed. Furthermore, by optimizing the exposure method and exposure conditions, This also makes it possible to form uneven shapes on the surface. For example, multiple exposure technology or half-tap exposure. Exposure techniques using a black mask or gray tone mask can be employed.

[0133] [Formation of insulating layer 104] Next, an insulating layer 104 is formed on the resin layer 131 (Figure 4C). The insulating layer 104 is made of PE It can be formed using methods such as CVD, ALD, and sputtering.

[0134] [Formation of opening 143] Next, a resist mask is formed on the insulating layer 104, and a portion of the insulating layer 104 is etched. By removing it, an opening is formed in the insulating layer 104. Subsequently, the insulating layer 104 is hard To use as a mask, an opening is formed in a part of the resin layer 131 that reaches the conductive layer 130. Then, an opening 143 is formed (Figure 4D).

[0135] In this way, by using the insulating layer 104 as a hard mask, the diameter of the opening 143 can be reduced. It can be cut. At this time, the resist mask used for processing the insulating layer 104 is an insulating mask. It is preferable to remove layer 104 after etching. Also, the resin layer 131 is dry etched Etching by a ting is preferable. For example, ashing treatment using plasma can be used for etching.

[0136] As a method different from the above, the opening 143 may be formed using the following method . First, a photosensitive material is used for the resin layer 131, and exposure and development are performed to form a resin layer 131 having an opening overlapping with the conductive layer 130 . Subsequently, after forming the insulating layer 104, the portion overlapping with the opening of the resin layer 131 is removed by etching to form the opening 143 . In this method, the process of etching the thick resin layer 131 can be omitted .

[0137] 〔Formation of conductive layer 106〕 Subsequently, a conductive film is formed covering the insulating layer 104 and the opening 143, and this is processed by etching to form a conductive layer 106 that functions as a gate electrode (FIG. 4E).

[0138] At this time, as shown in FIG. 4E, it is preferable to process so that the end portion of the conductive layer 106 has a tapered shape . Thereby, the step coverage of the insulating layer 103a to be formed next can be improved .

[0139] Also, by using a conductive film containing copper as the conductive film to be the conductive layer 106, the wiring resistance can be reduced.

[0140] 〔Formation of insulating layer 103a and insulating layer 103b〕 Subsequently, the insulating layer 103a and the insulating layer 103b are formed covering the insulating layer 104 and the conductive layer 106 (FIG. 4F). The insulating layer 103a and the insulating layer 103b can be formed using the PECVD method, the ALD method , or the sputtering method or the like.

[0141] Here, insulating layer 103a and insulating layer 103b are formed by laminating them. In particular, insulating layer 10 3a and the insulating layer 103b are preferably formed by the PECVD method.

[0142] After forming the insulating layer 103b, a process is performed to supply oxygen to the insulating layer 103b. Alternatively, plasma treatment or heat treatment can be performed under an oxygen atmosphere. Alternatively, by plasma ion doping or ion implantation, the insulating layer 103b Oxygen may be supplied to it.

[0143] [Formation of semiconductor layer 108] Next, a metal oxide film is formed on the insulating layer 103b, and a portion of it is etched. This forms island-like semiconductor layers 108 (Figure 5A).

[0144] The metal oxide film is formed by a sputtering method using a metal oxide target. It is preferable.

[0145] The metal oxide film is preferably a dense film with as few defects as possible. Oxide films are high-purity films in which impurities such as hydrogen or water are reduced as much as possible. Preferably. In particular, it is preferable to use a crystalline metal oxide film.

[0146] Furthermore, when forming a metal oxide film, oxygen gas and an inert gas (for example, helium gas) are used. It may also be mixed with argon gas, xenon gas, etc. Furthermore, a metal oxide film is formed. The higher the proportion of oxygen gas in the total film-forming gas (hereinafter also called the oxygen flow rate ratio), the better. This improves the crystallinity of the metal oxide film, enabling the realization of highly reliable transistors. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and the higher the on-current. It can be represented as a transistor.

[0147] When depositing a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film. This can be done. On the other hand, the lower the substrate temperature, the lower the crystallinity and the higher the electrical conductivity of the metal. It can form an oxide film.

[0148] For depositing the metal oxide film, the substrate temperature should be between room temperature and 250°C, preferably at room temperature. The substrate temperature should be 200°C or lower, more preferably between room temperature and 140°C. If the substrate temperature is set to above room temperature but below 140°C, productivity will increase, which is preferable. By forming a metal oxide film at room temperature or without intentional heating, This allows for lower crystallinity.

[0149] Furthermore, before forming the metal oxide film, water or hydrogen adsorbed on the surface of the insulating layer 103b, Among the treatments for removing organic matter and the treatment for supplying oxygen into the insulating layer 103b, It is preferable to perform at least one of the following: For example, in a reduced pressure atmosphere at a temperature of 70°C to 200°C. Heat treatment can be performed at the following temperatures. Alternatively, plasma in an oxygen-containing atmosphere. The process may be carried out under an atmosphere containing an oxidizing gas such as nitrous oxide (N2O). Oxygen may be supplied to the insulating layer 103b by plasma treatment. Plasma treatment including acid effectively removes organic matter from the surface of the insulating layer 103b. The material can be supplied. After such processing, the surface of the insulating layer 103b is exposed to the atmosphere. It is preferable to continuously form metal oxide films without interruption.

[0150] Furthermore, if the semiconductor layer 108 is a stacked structure in which multiple metal oxide films are stacked, After forming the metal oxide film, the surface is continuously exposed to the atmosphere. It is preferable to form the following metal oxide film.

[0151] Metal oxide films can be processed using either wet etching or dry etching methods. Either one or both may be used. In this case, the insulating layer 103 does not overlap with the semiconductor layer 108. In some cases, a portion of b may be etched and become thinner. For example, if the insulating layer 103b is etched... This can cause the layer to disappear, potentially exposing the surface of the insulating layer 103a.

[0152] Here, after the metal oxide film is formed, or after the metal oxide film is processed into the semiconductor layer 108 Heat treatment is preferable. Heat treatment is performed to create a metal oxide film or semiconductor layer 108 It can remove hydrogen or water contained within or adsorbed on the surface. The process improves the film quality of the metal oxide film or semiconductor layer 108 (for example, by reducing defects). (This can sometimes lead to improved crystallinity, etc.)

[0153] Furthermore, heat treatment causes the metal oxide film or semiconductor layer 108 to be converted from the insulating layer 103b by acid It is also possible to supply the raw material. In this case, heat treatment is performed before processing into semiconductor layer 108. That is preferable.

[0154] The heat treatment temperature is typically 150°C or higher but below the strain point of the substrate, or 200°C or higher but below 5°C. The temperature must be below 00°C, or between 250°C and 450°C, or between 300°C and 450°C. It is possible.

[0155] The heat treatment can be carried out in an atmosphere containing a noble gas or nitrogen. After heating with gas, it may be heated in an oxygen-containing atmosphere. Alternatively, it may be heated in a dry air atmosphere. It is also preferable that the atmosphere during the above heat treatment contains as little hydrogen, water, etc. as possible. The heat treatment is carried out in an electric furnace or RTA (Rapid Thermal Annealing). al) Equipment can be used. By using an RTA device, the heat treatment time can be shortened. It is possible.

[0156] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) In some cases, such as in the film deposition process, this heat treatment can be carried out in conjunction with other processes.

[0157] [Formation of insulating layer 110] Next, the insulating layer 110 is formed by covering the insulating layer 103b and the semiconductor layer 108.

[0158] The insulating layer 110 is preferably formed by the PECVD method.

[0159] Furthermore, before forming the insulating layer 110, the surface of the semiconductor layer 108 is subjected to plasma treatment. This is preferable. The plasma treatment removes water and other impurities adsorbed on the surface of the semiconductor layer 108. Pure matter can be reduced. Therefore, at the interface between the semiconductor layer 108 and the insulating layer 110 Because impurities can be reduced, highly reliable transistors can be realized. In particular, semiconductor layer 1 Between the formation of 08 and the deposition of the insulating layer 110, the surface of the semiconductor layer 108 is exposed to the atmosphere. In some cases, this is preferable. Examples of plasma treatments include oxygen, ozone, nitrogen, and nitrous oxide. This can be carried out in an atmosphere such as argon. Furthermore, the plasma treatment and the formation of the insulating layer 110 The membrane is preferably formed continuously without exposure to the atmosphere.

[0160] Here, it is preferable to perform a heat treatment after forming the insulating layer 110. This allows for the removal of hydrogen or water contained in or adsorbed on the insulating layer 110. This also reduces defects in the insulating layer 110.

[0161] The conditions for heat treatment can be applied as described above.

[0162] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) In some cases, such as in the film deposition process, this heat treatment can be carried out in conjunction with other processes.

[0163] [Formation of metal oxide film 114f] Next, a metal oxide film 114f is formed on the insulating layer 110 (Figure 5B).

[0164] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. It is preferable to form it by sputtering in an oxygen-containing atmosphere. Oxygen can be supplied to the insulating layer 110 during the formation of the metal oxide film 114f. Oxygen may be supplied to the semiconductor layer 108 during the formation of the oxide film 114f.

[0165] The metal oxide film 114f is made of an oxide containing the same metal oxide as in the case of the semiconductor layer 108. When formed by a sputtering method using a target, the semiconductor layer 108 is described above. The reference can be used.

[0166] For example, as a film deposition condition for metal oxide film 114f, oxygen is used as the deposition gas, and the metal target... A metal oxide film may be formed by a reactive sputtering method using a metal target. For example, if aluminum is used as the base material, an aluminum oxide film is formed. It is possible.

[0167] When forming the metal oxide film 114f, the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus is The higher the ratio of oxygen flow rate (oxygen flow rate ratio), or the higher the oxygen partial pressure in the deposition chamber, the more insulating layer 1 The amount of oxygen supplied to 10 can be increased. The oxygen flow rate ratio or oxygen partial pressure can be, for example, 5 0% to 100%, preferably 65% ​​to 100%, more preferably 80% or more The oxygen flow rate ratio should be 100% or less, more preferably 90% to 100%. In particular, the oxygen flow rate ratio should be 1 It is preferable to set the oxygen partial pressure in the deposition chamber to 00% and bring it as close to 100% as possible.

[0168] In this way, a metal oxide film 114f is formed by sputtering in an oxygen-containing atmosphere. By doing so, when the metal oxide film 114f is formed, oxygen is supplied to the insulating layer 110. In both cases, it is possible to prevent oxygen from detaching from the insulating layer 110. As a result, the insulating layer 1 A very large amount of oxygen can be trapped in a 10.

[0169] It is preferable to perform a heat treatment after the formation of the metal oxide film 114f. By performing the heat treatment, The oxygen contained in the insulating layer 110 can be supplied to the semiconductor layer 108. When 114f is heated while covering the insulating layer 110, acid is released from the insulating layer 110 to the outside. This prevents the element from being detached and allows for a large supply of oxygen to the semiconductor layer 108. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced, enabling the realization of highly reliable transistors.

[0170] The conditions for heat treatment can be applied as described above.

[0171] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) In some cases, such as in the film deposition process, this heat treatment can be carried out in conjunction with other processes.

[0172] Furthermore, after the formation of the metal oxide film 114f, or after the heat treatment, the metal oxide film 114 You may remove f.

[0173] [Formation of opening 142] Next, the metal oxide film 114f, insulating layer 110, insulating layer 103b, and insulating layer 103a By etching a portion of it, an opening 142 that reaches the conductive layer 106 is formed (Figure 5C). This allows the conductive layer 106 and the conductive layer 112 to be formed later to be separated through the opening 142. It can be electrically connected.

[0174] [Formation of conductive layer 112 and metal oxide layer 114] Next, a conductive film 112f, which will become the conductive layer 112, is formed on the metal oxide film 114f. Figure 5D).

[0175] It is preferable to use a low-resistance metal or alloy material as the conductive film 112f. The conductive film 112f is a material that does not easily release hydrogen, and is also a material that does not easily diffuse hydrogen. It is preferable to use [a specific material]. Furthermore, it is preferable to use a material that is resistant to oxidation as the conductive film 112f. It is preferable.

[0176] For example, the conductive film 112f is produced using a sputtering target containing a metal or alloy. It is preferable to deposit the film by the puttering method.

[0177] For example, the conductive film 112f is a conductive film that is resistant to oxidation and hydrogen diffusion, and has low resistance. It is preferable to form a laminated film by stacking a conductive film.

[0178] Next, by etching a portion of the conductive film 112f and the metal oxide film 114f, A conductive film 112f and a metal oxide film 114 are formed. It is preferable to process each of f using the same resist mask. Alternatively, etching The conductive layer 112 after etching is used as a hard mask to etch the metal oxide film 114f. That's fine.

[0179] As etching of the conductive film 112f and the metal oxide film 114f, particularly wet etching It is preferable to use the G method.

[0180] This results in the formation of a conductive layer 112 and a metal oxide layer 114 with substantially matching upper surface shapes. It is possible.

[0181] In this way, without etching the insulating layer 110, the top and side surfaces of the semiconductor layer 108, and By having a structure in which an insulating layer 103b is covered, when etching the conductive film 112f, etc., This prevents the conductive layer 108, insulating layer 103b, etc. from being etched and becoming thin. ru.

[0182] [Processing of supplying impurity elements] Next, using the conductive layer 112 as a mask, impurities are introduced into the semiconductor layer 108 via the insulating layer 110. The process involves supplying (adding or injecting) element 140 (Figure 6A). By forming a low-resistance region 108n in the region of the semiconductor layer 108 that is not covered by the conductive layer 112, This can be done. At this time, in the region of the semiconductor layer 108 that overlaps with the conductive layer 112, impurity element 14 To minimize the supply of zeros, the materials and thickness of the conductive layer 112 and other components that act as a mask are carefully controlled. It is preferable to consider this when determining the conditions for the supply treatment of impurity element 140. In the region of the semiconductor layer 108 that overlaps with the conductive layer 112, a channel with a sufficiently reduced impurity concentration is formed. A formation region can be created.

[0183] The supply of impurity element 140 is preferably by plasma ion doping or ion implantation. These methods can be used to obtain a depth-direction concentration profile, and to accelerate ions. It can be controlled with high precision by adjusting voltage and dose. Plasma ion doping By using this method, productivity can be increased. Also, ion implantation using mass separation can be used. By using this method, the purity of the supplied impurity elements can be increased.

[0184] In the supply process of impurity element 140, at the interface between the semiconductor layer 108 and the insulating layer 110, This refers to the portion of the semiconductor layer 108 that is close to the interface, or the portion of the insulating layer 110 that is close to the interface. However, it is preferable to control the processing conditions so that the highest concentration is achieved. This process supplies both the semiconductor layer 108 and the insulating layer 110 with an optimal concentration of impurity element 140. It is possible.

[0185] The 140 impurity elements are hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, Examples include aluminum, magnesium, silicon, or noble gases. Typical examples include helium, neon, argon, krypton, and xenon. In particular, boron, phosphorus, aluminum, magnesium, or silicon are preferred. It's nice.

[0186] As the raw material gas for impurity element 140, a gas containing the above-mentioned impurity element can be used. When supplying boron, typically B2H6 gas or BF3 gas is used. This is possible. Furthermore, when supplying phosphorus, pH3 gas can typically be used. Alternatively, a mixed gas obtained by diluting these source gases with a noble gas may be used.

[0187] Other raw material gases include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and noble gases can be used. Furthermore, the ion source is not limited to gases; solids or liquids that have been heated and vaporized can also be used. That's fine.

[0188] The addition of impurity element 140 affects the composition, density, and thickness of the insulating layer 110 and the semiconductor layer 108. By taking these factors into consideration, it is possible to control the system by setting conditions such as acceleration voltage or dose amount. Cut.

[0189] For example, by ion implantation or plasma ion doping, boron or phosphorus is added. If you do so, the dose should be, for example, 1 × 10⁻⁶ 13 ions / cm 2 The above 1 x 10 17 ions / cm 2 The following is preferably 1 × 10 14 ions / cm 2 The above 5 x 10 16ions / c m 2 More preferably 1 × 10 15 ions / cm 2 The above 3 x 10 16 ions / c m 2 The following range is possible.

[0190] Furthermore, the method of supplying impurity element 140 is not limited to this; for example, thermal diffusion by heating. Processing using or plasma processing may also be used. In the case of plasma processing, Plasma is generated in a gas atmosphere containing impurity elements, and plasma processing is performed. Therefore, impurity elements can be added. The apparatus for generating the above plasma is: Dry etching equipment, ashing equipment, plasma CVD equipment, high-density plasma CVD equipment Placement, etc., can be used.

[0191] In one aspect of the present invention, impurity elements 140 are supplied to the semiconductor layer 108 via the insulating layer 110. Therefore, even if the semiconductor layer 108 has crystalline properties, impurities The damage to the semiconductor layer 108 during the supply of element 140 is reduced, and its crystallinity is not impaired. This can suppress the occurrence of this problem. Therefore, the decrease in crystallinity can increase electrical resistance. It is suitable in such cases.

[0192] [Formation of insulating layer 116 and insulating layer 118] Next, the insulating layer 110, the metal oxide layer 114, and the conductive layer 112 are covered by the insulating layer 11 Forming layers 6 and 118 (Figure 6B).

[0193] When insulating layers 116 and 118 are formed by plasma CVD, the film deposition temperature is high. If this is excessive, impurities contained in the low-resistance region 108n, etc., will form channel formation regions in the semiconductor layer 108. There is a risk of diffusion to the surrounding area including the region. Also, the electrical resistance in the low-resistance region 108n will increase. There is a risk that this may happen. Therefore, the film formation temperature of insulating layer 116 and insulating layer 118 is set accordingly. You should make your decision after considering these factors.

[0194] For example, the film deposition temperature for insulating layer 116 and insulating layer 118 is, for example, 150°C or higher. Below 0°C, preferably between 180°C and 360°C, more preferably between 200°C and 250°C The following is preferable: By forming the insulating layer 116 and insulating layer 118 at a low temperature. Therefore, even transistors with short channel lengths can be given good electrical characteristics.

[0195] Furthermore, after the formation of the insulating layer 116 and the insulating layer 118, a heat treatment may be performed. In some cases, the low-resistance region 108n can be made to have even lower resistance in a more stable manner. Yes. For example, by heat treatment, impurity element 140 diffuses appropriately and locally. A low-resistance region 108n can be formed, which is homogenized and has an ideal concentration gradient of impurity elements. Furthermore, if the heat treatment temperature is too high (for example, above 500°C), the impurity element 140 will be affected. It may diffuse into the Nellum formation region, potentially leading to a deterioration of the transistor's electrical characteristics and reliability. be.

[0196] The conditions for heat treatment can be applied as described above.

[0197] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) For example, if there is a film formation process, it may be possible to combine it with the heat treatment.

[0198] [Formation of resin layer 132] Next, a resin layer 132 having an opening is formed on the insulating layer 118 (Figure 6C).

[0199] The material that can be used for resin layer 132 can be referred to in the description of resin layer 131 above. Here, a photosensitive material is used, and by exposure and development, a resin layer 1 with an opening is formed. Forms 32.

[0200] [Formation of openings 141a and 141b] Next, in the region overlapping with the opening of the resin layer 132, the insulating layer 118, insulating layer 116, And by etching a portion of the insulating layer 110, an opening 1 reaches a low-resistance region 108n. Forms 41a and opening 141b (Figure 7A).

[0201] Here, the resin layer 132 is used as an etching mask, and the insulating layer 118 and insulating layer 116 The portion of the insulating layer 110 located within the opening of the resin layer 132 is etched.

[0202] In addition, as a method different from the above, the following method can be used to open the opening 141a and the opening 14 1b may be formed. First, before forming the resin layer 132, resin A mask is formed, and openings are made in advance in the insulating layer 118, insulating layer 116, and insulating layer 110. Form. Subsequently, exposure and development are performed using a photosensitive material to form a tree with an opening. A lipid layer 132 is formed. This creates openings 141a and 141b. It is possible.

[0203] [Formation of conductive layer 120a and conductive layer 120b] Next, a conductive film is applied to the resin layer 132 so as to cover the openings 141a and 141b. By forming a film and processing the conductive film into a desired shape, conductive layer 120a and conductive layer 120b are formed. It forms (Figure 7B).

[0204] By following the above steps, a semiconductor device equipped with a transistor can be manufactured.

[0205] [Formation of resin layer 133] Next, the conductive layer 120a, conductive layer 120b, and resin layer 132 are covered, and the opening 144 A resin layer 133 having the above characteristics is formed (Figure 8A).

[0206] For details regarding resin layer 133, refer to the descriptions of resin layer 131 and resin layer 132.

[0207] [Formation of conductive layer 150] Next, a conductive film is formed on the resin layer 133 so as to cover the opening 144, and the conductive film is The conductive layer 150 is formed by processing it into the desired shape (Figure 8B).

[0208] The above is an explanation of an example of the manufacturing method.

[0209] [Components of semiconductor devices] The following describes the components included in the semiconductor device of this embodiment.

[0210] 〔substrate〕 There are no major restrictions on the material of the substrate 102, but it should at least be able to withstand subsequent heat treatment. It must have heat resistance. For example, a single material made of silicon or silicon carbide. Crystalline semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SO Substrate 102 includes substrates such as I substrate, glass substrate, ceramic substrate, quartz substrate, and sapphire substrate. It may also be used as follows. Furthermore, a substrate on which semiconductor elements are provided may be referred to as substrate 102 and It may be used in this way.

[0211] Furthermore, a flexible substrate is used as the substrate 102, and a semiconductor device is formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the semiconductor device. The release layer is After partially or completely completing the semiconductor device on top of it, it is separated from the substrate 102 and placed on another substrate It can be used for reproduction. In this case, the semiconductor device is a substrate with poor heat resistance or It can also be mounted on flexible substrates.

[0212] [Conductive layer] Conductive layer 112, conductive layer 106, conductive layer 120a, conductive layer 120b, conductive layer 121a, conductive The conductive layer 121b, conductive layer 130, and conductive layer 150, etc., are made of chromium, copper, aluminum, gold, Silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, Metal elements selected from the Baltic, or alloys containing the aforementioned metal elements, or the aforementioned gold These can be formed using alloys or other combinations of group elements.

[0213] Furthermore, the conductive layer contains In-Sn oxide, In-W oxide, In-W-Zn oxide, and In -Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, Oxide conductors such as in-Ga-Zn oxide or metal oxide films can also be applied.

[0214] [Semiconductor layer] If the semiconductor layer 108 is In-M-Zn oxide, then to deposit the In-M-Zn oxide film... The atomic ratio of metal elements in the sputtering target used is In:M:Zn=1: 1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Z n=1:3:4, In:M:Zn=1:3:6, In:M:Zn=2:2:1, In:M :Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In :M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1: 6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6: Examples include 1:6 and In:M:Zn=5:2:5.

[0215] Furthermore, a target containing a polycrystalline oxide is used as the sputtering target. This is preferable because it facilitates the formation of a crystalline semiconductor layer 108. The atomic ratio of semiconductor layer 108 is the original number of metal elements contained in the sputtering target mentioned above. This includes variations of plus or minus 40% in the number of particles. For example, sputtering used for semiconductor layer 108. When the composition of the ring target is In:Ga:Zn=4:2:4.1 [atomic ratio], The composition of the semiconductor layer 108 is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. There are cases where this occurs.

[0216] Note that when the atomic ratio is stated as In:Ga:Zn=4:2:3 or close to it, In When we set the ratio to 4, this includes the case where Ga is between 1 and 3, and Zn is between 2 and 4. Furthermore, when stating that the atomic ratio is In:Ga:Zn = 5:1:6 or close to it, When n is set to 5, Ga is greater than 0.1 and less than or equal to 2, and Zn is between 5 and 7. This includes cases where the atomic ratio is In:Ga:Zn = 1:1:1 or close to it. When listing, if In is set to 1, Ga must be greater than 0.1 and less than or equal to 2, and Zn must be 0. This includes cases where the value is greater than 1 and less than or equal to 2.

[0217] Furthermore, the semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or less. As shown above, by using metal oxides with a wider energy gap than silicon... This allows for a reduction in the transistor's off-current.

[0218] Furthermore, it is preferable that the semiconductor layer 108 has a non-single-crystal structure. A non-single-crystal structure is, for example, This includes the CAAC structure, polycrystalline structure, microcrystalline structure, or amorphous structure described later. Non-single crystal structure In construction, amorphous structures have the highest defect level density, while CAAC structures have the highest defect level density. low.

[0219] The following explains CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0220] A CAAC structure is a structure that has multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). It is one of the crystalline structures of thin films, in which each nanocrystal has its c-axis oriented in a specific direction, and its a-axis and The b-axis does not have orientation, and the nanocrystals are continuously connected to each other without forming grain boundaries. This crystal structure has the following characteristics. In particular, thin films with a CAAC structure have each nanocrystal The c-axis is oriented in the thickness direction of the thin film, the normal direction of the surface to be formed, or the normal direction of the surface of the thin film. It has the characteristic of being inexpensive.

[0221] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. It is a conductor. On the other hand, CAAC-OS does not allow for the identification of clear grain boundaries, It can be said that a decrease in electron mobility caused by grain boundaries is less likely to occur in oxide semiconductors. Crystallinity may decrease due to the inclusion of impurities, the formation of defects, etc., therefore CAAC-OS It can also be described as an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, CAAC Oxide semiconductors containing -OS have stable physical properties. Therefore, CAAC-OS is Oxide semiconductors are highly heat-resistant and reliable.

[0222] In crystallography, the three axes a, b, and c constitute the unit cell (crystal). Regarding the axis, it is common to take a unit cell with a specific axis as the c-axis. Especially in layered structures In crystals with a structure, the two axes parallel to the plane direction of the layer are defined as the a-axis and the b-axis, and the axis intersecting the layer is defined as the axis intersecting the layer. It is common to use the c-axis. A typical example of a crystal having such a layered structure is... There is graphite, which is classified as a hexagonal crystal system, and the a-axis and b-axis of its unit cell are parallel to the cleavage plane. The row is oriented, and the c-axis is perpendicular to the cleavage plane. For example, the layered structure of YbFe2O4 type crystal structure. InGaZnO4 crystals can be classified as hexagonal, and their unit cell a-axis and The b-axis is parallel to the plane direction of the layer, and the c-axis is perpendicular to the layer (i.e., the a-axis and b-axis).

[0223] Oxide semiconductor films with a microcrystalline structure (microcrystalline oxide semiconductor films) can be observed using TEM. In some cases, the crystalline portion cannot be clearly identified. The crystalline portion is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, with microcrystals between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor film having a certain nanocrystal (nc) is called nc-OS (Nanocrystalline Oxide Semiconductor) film Furthermore, in nc-OS films, grain boundaries can be clearly observed, for example, in TEM observation images. It may not be possible.

[0224] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions between 1 nm and 10 nm). The atomic arrangement has periodicity in the region of 3 nm or less. In addition, the nc-OS film is different There is no regularity in the crystal orientation between the crystalline regions. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. There are cases where this occurs. For example, XRD using X-rays with a diameter larger than that of the crystalline region on an nc-OS film. When structural analysis is performed using the apparatus, the out-of-plane method analyzes the crystal planes. The indicated peak is not detected. Also, the probe diameter is larger than that of the crystalline region in the nc-OS film. Electron diffraction (also called limited-field electron diffraction) using electron beams (for example, 50 nm or longer). When this is done, a diffraction pattern resembling a halo pattern is observed. On the other hand, when applied to an nc-OS film... Furthermore, the probe diameter should be close to or smaller than the size of the crystal (for example, 1 nm to 30 nm). When electron diffraction (also called nanobeam electron diffraction) is performed using the electron beam shown below, a circle is drawn. A ring-shaped region of high brightness was observed, and within this ring-shaped region, multiple spots were observed. A retched object may be observed.

[0225] nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, nc-O The S film shows no regularity in crystal orientation between different crystalline regions. Therefore, the nc-OS film is Compared to CAAC-OS films, nc-OS films have a higher defect level density. Therefore, nc-OS films are CAAC- Compared to OS films, it may have a higher carrier density and higher electron mobility. Therefore, nc Transistors using OS films may exhibit high field-effect mobility.

[0226] Compared to CAAC-OS films, nc-OS films require a lower oxygen flow rate ratio during deposition. It can be formed by [method]. In addition, compared to CAAC-OS films, nc-OS films have [processing time] It can also be formed by lowering the substrate temperature. For example, the nc-OS film can be formed by lowering the substrate temperature. A state where the temperature is set to a relatively low temperature (for example, below 130°C), or a state where the substrate is not heated. However, because it can form thin films, it is suitable for use with large glass substrates or resin substrates. This allows for increased productivity.

[0227] An example of a metal oxide crystal structure is described. In-Ga-Zn oxide target ( Using In:Ga:Zn=4:2:4.1 (atomic ratio), the substrate temperature was set to 100°C or higher. At temperatures below 30°C, metal oxides formed by sputtering are nc(nano C Either a crystalline structure (rystal) or a CAAC structure, or a mixture of both. It is easy to form such a structure. On the other hand, metal oxides formed with the substrate temperature at room temperature (RT) It readily adopts an nc crystal structure. Note that room temperature (RT) here refers to the substrate being intentionally cooled. This includes the temperature when not heated.

[0228] [Composition of metal oxides] Hereinafter, CAC(C) that can be used in the transistor disclosed in one aspect of the present invention will be described. This document describes the configuration of a loud-Aligned Composite (Loud) OS.

[0229] Note that CAAC (c-axis aligned crystal) is an example of a crystal structure. This represents CAC (Cloud-Aligned Composite), which is a function or material. This shows an example of the composition of the ingredients.

[0230] CAC-OS or CAC-metal oxide is a material in which some parts are conductive. It has both electrical and insulating properties in some parts of the material, and the material as a whole has semiconductor properties. Furthermore, CAC-OS or CAC-metal oxide is used to activate the transistor. When used in layers, the conductive function is the function of allowing electrons (or holes) that act as carriers to flow. In other words, the insulating function is the function of preventing the flow of electrons, which act as carriers. Conductive function and insulating function By making the functions of sex and other functions work complementaryly, a switching function (On / O) is created. The function of ff (fastening) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, the respective functions are separated. By doing so, the functions of both can be maximized.

[0231] Furthermore, CAC-OS or CAC-metal oxide provides conductive and insulating properties. It has conductive regions. The conductive regions have the conductive function described above, and the insulating regions have the insulating function described above. It has the function of being conductive. Furthermore, within the material, the conductive region and the insulating region are separated by nanoparticles. In some cases, they are separated by a bell. Also, conductive regions and insulating regions are located within the material. It may be unevenly distributed. Also, the conductive region appears blurred around the edges and connected in a cloud-like manner when observed. There are cases where this can happen.

[0232] Furthermore, in CAC-OS or CAC-metal oxide, the conductive region and The insulating region is defined as 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material in sizes smaller than m.

[0233] Furthermore, CAC-OS or CAC-metal oxide have different band gaps. It is composed of components having [a certain characteristic]. For example, CAC-OS or CAC-metal ox The ide consists of a component with a wide gap due to the insulating region and a component with a wide gap due to the conductive region. It consists of a component having a narrow gap. In this configuration, when the carrier is flowing... In components with a narrow gap, the carrier mainly flows. The component with a gap acts complementaryly with the component with a wide gap, and the component with a narrow gap In conjunction with the components that perform this action, carriers also flow to components with a wide gap. Therefore, the above CAC-OS or CAC-metal oxide in the channel formation region of the transistor When used in this way, a high current driving force, i.e., a large on-current, is required in the transistor's on state. Furthermore, high field-effect mobility can be obtained.

[0234] In other words, CAC-OS or CAC-metal oxide is a matrix composite Material (matrix composite), or metal matrix composite material (metal It can also be called a matrix composite.

[0235] The above is an explanation of the composition of metal oxides.

[0236] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be combined with other configuration examples or drawings as appropriate.

[0237] (Embodiment 2) In this embodiment, an example of a display device having the semiconductor device illustrated in the previous embodiment is provided. I will explain.

[0238] Figure 9A shows a schematic top view of the display device 10 illustrated below. The display device 10 has a pixel section 11, circuit 12, circuit 13, terminal section 15a, terminal section 15b, wiring 16a, wiring 16b, and It has wiring 16c. Also, Figure 9A shows an example where IC17 is mounted on the display device 10. This indicates that.

[0239] The pixel unit 11 has multiple pixels and has the function of displaying an image.

[0240] Circuit 12 and IC 17 output a signal to drive each pixel in the pixel section 11. It has the function of doing so. For example, circuit 12 is a circuit that functions as a gate drive circuit. For example, IC17 is a circuit that functions as a source drive circuit. In Figure 9A, the pixel section 11 is This example shows two circuits 12 flanking each other, and six ICs 17 mounted on top of each other. Furthermore, even if an IC that functions as a gate drive circuit is implemented and circuit 12 is not provided, That's good. Alternatively, a source drive circuit may be provided, and IC17 may not be implemented.

[0241] Note that integrated circuits such as ICs, or FPCs (Flexible Printed Cables) A form in which connectors such as rcuit are implemented can also be called a display module. Furthermore, a form in which connectors or integrated circuits are not mounted is called a display panel. It can also be done this way.

[0242] Circuit 13 has the function of distributing one of the signals input from IC 17 to two or more wires. This is a circuit (for example, a demultiplexer circuit). By providing circuit 13, IC1 The number of signals output by 7 can be reduced, and the number of terminals on IC17 can be reduced. This can reduce the number of items. In particular, it enables the creation of extremely high-resolution display devices such as 4K or 8K. In some cases, providing circuit 13 is particularly effective. Circuit 13 can be omitted if it is not needed. That's fine.

[0243] Terminal sections 15a and 15b are provided with multiple terminals, and connectors such as FPCs are available. Alternatively, other integrated circuits such as ICs can be connected. Each terminal of terminal section 15a is a multiple It is electrically connected to circuit 12 via one of the wires 16a. Each terminal of terminal section 15b is IC17 is electrically connected via one of the multiple wires 16b. Furthermore, IC17 has Each of the multiple output terminals is electrically connected to the circuit 13 via one of the multiple wires 16c. It can be done.

[0244] Figure 9B is a schematic top view showing an example of the arrangement method of pixel electrodes in the pixel section 11. Section 11 has multiple pixel units 20. Figure 9B shows four pixel units 20. The pixel unit 20 is composed of pixels 21a and 21b. Pixel 21a has pixel electrode 31a, pixel electrode 32a, and pixel electrode 33a. Pixel 21b It has pixel electrodes 31b, 32b, and 33b. Each pixel electrode is located behind It functions as an electrode of the display element described above. Also, the display area 22 of one sub-pixel is that sub-pixel It is located inside the pixel electrodes.

[0245] The six pixel electrodes of the pixel unit 20 are arranged in a matrix of two vertically and three horizontally. Here, pixel electrode 31a, pixel electrode 32a, and pixel electrode 33a are respectively It can be used as an electrode for a display element that exhibits different colors. Also, the pixel electrode 31b is the same as the pixel electrode 3 1a, pixel electrode 32b is pixel electrode 32a, pixel electrode 33b is pixel electrode 33a, and These can be used as electrodes for display elements that exhibit the same color. Note that here, three types of pixel electrodes are used. Although the poles are explicitly shown to be the same size, they may be different sizes. The size of the display area 22 on the pixel electrode may be varied.

[0246] For the sake of simplicity, the pixel electrode 31a is a display element that exhibits red (R). The electrode is denoted with the sign R. Similarly, the pixel electrode 32a is a display element that exhibits green (G). The electrode is denoted with the sign G, and the pixel electrode 33a is the electrode of the display element that exhibits blue (B). The pixels are labeled with symbols. Note that the pixel arrangement shown in Figure 9B, etc., is just one example and is not limited to this. R, G, and B can be interchanged with each other. Also, the pixel arrangement shown in Figure 9B, etc. You may also use a pixel array in which the columns are flipped horizontally or vertically.

[0247] Note that the arrangement method of the display elements is not limited to the above; for example, a rectangular shape could be arranged within a single square. The three display elements may be arranged in a so-called stripe arrangement. Alternatively, the same shape may be used. A grid made up of tiled triangles is used, and one of the three display elements is placed at the vertices of this grid, a so-called D It may also be a Ruta array.

[0248] [Example of pixel circuit configuration] The following describes an example of the pixel circuit of the pixel unit 20. Figure 9C shows the pixel An example of the circuit diagram for unit 20 is shown. The pixel unit 20 has wiring 51a and wiring 51b and Wirings 52a to 52d and wirings 53a to 53c are connected. Each pixel unit 20 has four wires (wires 52a, etc.) that function as signal lines connected to it. This shows an example of what happens when it continues.

[0249] Pixel 21a has sub-pixels 71a, 72a, and 73a. Pixel 21b It has sub-pixels 71b, 72b, and 73b. Each sub-pixel has a pixel Path (pixel circuit 41a, pixel circuit 41b, pixel circuit 42a, pixel circuit 42b, pixel circuit 43 It has a (or pixel circuit 43b) and a display element 60. For example, sub-pixel 71a has a pixel circuit 4 It has 1a and a display element 60. Here, as the display element 60, it is a light-emitting element such as an organic EL element. This shows the case where a child is used.

[0250] Each pixel circuit also includes transistor 61, transistor 62, and capacitive element 63. It has, for example, in the pixel circuit 41a, the gate of transistor 61 is connected to wiring 51 a is electrically connected, and either the source or the drain is electrically connected to wiring 52a, source Alternatively, the other drain may be electrically connected to the gate of transistor 62 and one electrode of capacitive element 63. They are connected in a specific way. Transistor 62 has either its source or drain connected to one of the display elements 60. One electrode is electrically connected to the other electrode, and the other of the source or drain is the other electrode of the capacitive element 63, and It is electrically connected to wiring 53a. The other electrode of the display element 60 is given a potential V1. It is electrically connected to the wiring. Note that other pixel circuits are shown in Figure 9C. The wiring to which the gate of transistor 61 is connected, and one of the source or drain of transistor 61. Except for the wiring to which one side connects, and the wiring to which the other electrode of the capacitive element 63 connects, the pixels It has the same configuration as circuit 41a.

[0251] In Figure 9C, transistor 61 functions as a selector transistor. The transistor 62 is connected in series with the display element 60 and controls the current flowing through the display element 60. It has a function. In Figure 9C, transistor 61 functions as a selection transistor, One electrode (pixel electrode) of the display element 60 is electrically connected via the transistor 62. It can be said that the capacitive element 63 is connected to the gate of transistor 62. It has the function of maintaining the potential of the node being treated. Note that when transistor 61 is in the off state When the leakage current and the leakage current through the gate of transistor 62 are extremely small. In this case, it is not necessary to intentionally provide the capacitive element 63.

[0252] Here, as shown in Figure 9C, the transistors 62 are electrically connected to the first It is preferable to have a configuration that has a gate and a second gate. By using this configuration, the current that transistor 62 can supply can be increased. In particular, in high-definition display devices, the size of the transistor 62, especially the channel width, This is preferable because it allows the current to be increased without increasing its size.

[0253] Furthermore, of the pair of electrodes of the display element 60, the electrode that is electrically connected to the transistor 62 is This corresponds to the above-mentioned pixel electrode (for example, pixel electrode 31a, etc.). Here, in Figure 9C, the display element The configuration uses 60 transistors 62 with the electrode electrically connected to it as the cathode and the electrode on the opposite side as the anode. This shows that transistor 62 is an n-channel type transistor. This is particularly effective when transistor 62 is ON, by wiring 53a Since the applied potential becomes the source potential, variations in the electrical resistance of the display element 60, and electricity The current flowing through transistor 62 can be kept constant regardless of fluctuations in resistance.

[0254] Furthermore, the electrode on the side of the display element 60 facing the transistor 62 is designated as the anode, and the electrode on the opposite side is designated as the cathode. This configuration is also possible. By using this configuration, the other electrode of the display element 60 is supplied A fixed potential lower than the potential applied to wiring 53a, etc., can be used for the potential V1. Furthermore, the potential V1 may also be a common potential or ground potential, or a potential that is common to other circuits. Using this method is preferable because it simplifies the circuit configuration.

[0255] In this context, the transistors in the pixel circuit are n-channel type transistors. While examples of its use have been shown, a p-channel transistor may also be used.

[0256] [Example of pixel layout] The following describes an example of the layout of the pixel unit 20.

[0257] Figures 10A and 10B show an example of a single subpixel layout. To simplify the explanation, an example before the pixel electrodes are formed is shown. Also, Figure 10B is a reference to Figure 10A. The wiring 52 etc. in Figure 10A is shown with dashed lines. The sub-pixel shown in Figure 10A is transistor 61, It has a transistor 62 and a capacitive element 63. The transistor 62 has two semiconductor layers sandwiched between them. It is a transistor with two gates.

[0258] Transistors 61 and 62 are the transistors exemplified in Embodiment 1. It can be used.

[0259] In Figure 10A, etc., the same hatching pattern is applied to a pattern formed by processing the same conductive film. It is indicated by a circle. The lowest conductive layer (conductive layer 130) is used for wiring 51 A conductive layer (conductive layer 106a, conductive layer 106b) is formed after this. These are used to form relay wiring and one of the gates of transistor 62. The conductive layer formed after this (conductive layer 112a, conductive layer 112b, etc.) The gate of sta 61 and the other gate of transistor 62 are formed. Conductive layers formed later (conductive layer 121a, conductive layer 121b, conductive layer 121c, conductive Layers 121d, etc., provide the source and drain electrodes of each transistor, as well as capacitive elements. One of the electrodes, etc., of 63 is formed. A conductive layer (conductive layer 12) is formed later. Wiring 52, wiring 53, and relay wiring are provided by conductive layer 120b, conductive layer 120c, etc. (0a, conductive layer 120b, conductive layer 120c, etc.) These are formed. A portion of the wiring 53 functions as the other electrode of the capacitive element 63. The conductive layer 120c serves as a relay wiring connecting the transistor 62 and the pixel electrode 31, etc. It is capable of. Also, transistor 61 has a semiconductor layer 108a, and transistor 62 is semiconductor It has layer 108b.

[0260] Figure 10C shows one of the layouts of the pixel unit 20 using the subpixels exemplified in Figure 10A. An example is shown. Figure 10C also clearly shows each pixel electrode and the display area 22.

[0261] Here, there are three sub-pixels electrically connected to wiring 51a, and wiring 51b is electrically connected The three subpixels shown are each symmetrical. Subpixels of the same color are arranged in a zigzag pattern in the direction of extension, such as 52a, and these subpixels When configured to connect to a single wire that functions as a signal line, the length of the wire within the sub-pixel is Because the pixels can be aligned, variations in brightness between sub-pixels can be suppressed.

[0262] Furthermore, the display area 22 of the three sub-pixels that are electrically connected to the wiring 51a, and the wiring 51b and the The three sub-pixel display areas 22 that are electrically connected are arranged in the direction of extension of the wiring 51a, with a pitch of sorts. They may also be arranged so that they are offset by half a distance. This can achieve a so-called delta arrangement. ru.

[0263] The above is an explanation of an example of pixel layout.

[0264] The display device illustrated in this embodiment makes it possible to realize an extremely high-resolution display device. It can also provide a display device with improved display quality. Furthermore, it can provide a display device with improved viewing angle characteristics. We can provide a display device. Furthermore, we can provide a display device with an increased aperture ratio.

[0265] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be combined with other configuration examples or drawings as appropriate.

[0266] (Embodiment 3) This embodiment describes an example of a cross-sectional configuration of a display device according to one aspect of the present invention.

[0267] [Cross-sectional configuration example 1] Figure 11 shows a schematic cross-sectional view of the display panel 700. Figure 11 shows the pixel section 702 and This shows a cross-section including the gate driver circuit section 706 and the FPC terminal section 708. Pixel Section 702 includes transistors 750 and 754, and a capacitive element 790. The gate driver circuit section 706 includes a transistor 752.

[0268] Transistors 750, 752, and 754 are provided in Embodiment 1 The transistor exemplified above can be applied.

[0269] Transistors 750, 752, and 754 have channels that form This transistor uses an oxide semiconductor in the semiconductor layer it forms. However, it is not limited to this. First, the semiconductor layer contains silicon (amorphous silicon, polycrystalline silicon, or single-crystal silicon) It is also possible to apply transistors using (converters) or organic semiconductors.

[0270] The transistor used in this embodiment is made of an oxide that has been purified to suppress the formation of oxygen vacancies. It has a semiconductor film. The transistor can significantly reduce the off-current. Therefore, Pixels to which such transistors are applied can have a longer retention time for electrical signals such as image signals, and the image The writing interval for image signals, etc., can also be set to be longer. Therefore, the frequency of refresh operations can be reduced. Therefore, power consumption can be reduced.

[0271] Furthermore, the transistor used in this embodiment is capable of obtaining a relatively high field-effect mobility. Therefore, high-speed operation is possible. For example, a transistor capable of such high-speed operation can be used to display... By using it in the panel, the switching transistors in the pixel section and the drive circuit used in the drive circuit section are used. IBA transistors can be formed on the same substrate, that is, on a silicon wafer, etc. A configuration that does not require a more formed drive circuit is also possible, reducing the number of components in the display device. This is possible. Furthermore, by using transistors capable of high-speed driving in the pixel section, This allows us to provide high-quality images.

[0272] Capacitive element 790 is made from the same film as the first gate electrode of transistor 750. A lower electrode formed by processing a metal oxide film identical to the semiconductor layer, and an upper electrode formed by processing the same metal oxide film as the semiconductor layer. The upper electrode has the same characteristics as the source and drain regions of transistor 750. The resistance has been reduced. Also, between the lower electrode and the upper electrode, the first of transistor 750 A portion of the insulating film, which functions as the gate insulating layer, is provided. That is, the capacitive element 790 is It has a multilayer structure in which an insulating film, which functions as a dielectric film, is sandwiched between a pair of electrodes. Furthermore, the upper electrode was processed with the same film as the source and drain electrodes of transistor 750. The resulting wiring is connected.

[0273] The display panel 700 has a support substrate 745 and a support substrate 740. The support substrate 740 can be, for example, a glass substrate or a flexible plastic substrate. A substrate having the following properties can be used.

[0274] Transistor 750, transistor 752, transistor 754, and capacitive element 790 These are provided on the insulating layer 744. The support substrate 745 and the insulating layer 744 are connected by an adhesive layer 742 It is bonded together by [something].

[0275] The conductive layer 720 is provided on the insulating layer 744. The resin layer 722 is provided on the insulating layer 744 and the conductive layer 720. The insulating layer 723 is provided covering the electrical layer 720. The insulating layer 723 is provided covering the resin layer 722.

[0276] Transistor 750, transistor 752, transistor 754, and capacitive element 790 These are provided on the insulating layer 723.

[0277] Transistors 750, 752, and 754 are each the first gate A conductive layer 791 that functions as a gate electrode, and an insulating layer 792 that functions as a first gate insulating layer. , semiconductor layer 793, insulating layer 794 which functions as a second gate insulating layer, and second gate It has conductive layers 795 that function as electrodes, etc. Also, transistors 750 and 7 52. An insulating layer 726 is provided covering the transistor 754.

[0278] A resin layer 724 is provided on the insulating layer 726, and a conductive layer 725, etc., is provided on the resin layer 724. It is possible.

[0279] Furthermore, the conductive layer 721, which is formed by processing the same conductive film as the conductive layer 791, is the insulating layer 72 3 and the openings provided in the resin layer 722 are electrically connected to the conductive layer 720. ru.

[0280] A portion of the conductive layer 720 functions as a gate wire. A portion of the conductive layer 725 functions as a source wire. It functions as follows: Part of the conductive layer 720 and part of the conductive layer 725 are at least the resin layer 722 And it is superimposed via a resin layer 724.

[0281] Also, transistors 750, 752, 754, and capacitive elements An insulating layer 770, which functions as a planarization film, is provided on 790.

[0282] The pixel unit 702 includes transistors 750 and 754, and a gate driver. The transistors 752 in the circuit section 706 use transistors with different structures. This is also a good option. For example, you could apply a top-gate transistor to one of them and a bob to the other. A configuration using a Tomgate-type transistor is also acceptable.

[0283] The FPC terminal section 708 includes wiring 760, part of which functions as a connecting electrode, and an anisotropic conductive film 78. It has 0 and FPC716. Wiring 760 is connected to FPC71 via an anisotropic conductive film 780. It is electrically connected to the terminals of 6. Here, wiring 760 is connected to transistor 750, etc. The source electrode and drain electrode are formed of the same conductive film.

[0284] The display panel 700 also includes a light-emitting element 782, a colored layer 736, a light-shielding layer 738, and the like.

[0285] The light-emitting element 782 has a conductive layer 772, an EL layer 786, and a conductive layer 788. 772 is electrically connected to the source or drain electrode of transistor 750. The conductive layer 772 is provided on the insulating layer 770 and functions as a pixel electrode. An insulating layer 730 is provided covering the end of layer 772, and E is applied to the insulating layer 730 and the conductive layer 772. The L layer 786 and the conductive layer 788 are laminated together.

[0286] The conductive layer 772 can be made of a material that is reflective to visible light. For example, Materials containing aluminum, silver, etc. can be used. In addition, the conductive layer 788 may contain visible Materials that are translucent to light can be used. For example, indium, zinc, tin It is preferable to use an oxide material containing such materials. Therefore, the light-emitting element 782 is on the opposite side from the surface to be formed. This is a top-emission type light-emitting element that emits light towards the support substrate 740 side.

[0287] The EL layer 786 contains organic compounds or inorganic compounds such as quantum dots. 86 contains a light-emitting material that emits white light when an electric current flows through it.

[0288] Examples of light-emitting materials include fluorescent materials, phosphorescent materials, and thermally activated delayed fluorescence (A ctivated delayed fluorescence (TADF) materials, inorganic Compounds (such as quantum dot materials) can be used. The materials that can be used include colloidal quantum dot materials, alloy quantum dot materials, and core-shell type quantum dot materials. Examples include quantum dot materials and core-type quantum dot materials.

[0289] The light-shielding layer 738 and the colored layer 736 are provided on one side of the insulating layer 746. 736 is positioned to overlap with the light-emitting element 782. Also, the light-shielding layer 738 is located at the pixel In section 702, it is provided in an area that does not overlap with the light-emitting element 782. Also, the light-shielding layer 73 8 may also be provided on top of the gate driver circuit section 706, etc.

[0290] The support substrate 740 is bonded to the other side of the insulating layer 746 by an adhesive layer 747. Furthermore, the support substrate 740 and the support substrate 745 are bonded together by the sealing layer 732. ru.

[0291] Here, the EL layer 786 of the light-emitting element 782 is a light-emitting material that exhibits white light emission. This is applied. The white light emitted by the light-emitting element 782 is colored by the colored layer 736. The light is then emitted to the outside. The EL layer 786 is provided across pixels exhibiting different colors. A colored layer 7 that transmits either red (R), green (G), or blue (B) is placed in part 702. By arranging the pixels with 36 in a matrix, the display panel 700 is full color. It is possible to display -.

[0292] Furthermore, a conductive film having transparency and reflectivity may be used as the conductive layer 788. This enables the realization of a microcavity structure between conductive layer 772 and conductive layer 788. Furthermore, it is possible to configure it to intensify and emit light of a specific wavelength. Also, in this case, the conductive layer 7 An optical adjustment layer is placed between 72 and the conductive layer 788 to adjust the optical distance, and the optical adjustment By varying the thickness of the layer between pixels of different colors, the light emitted from each pixel... A configuration that enhances color purity is also acceptable.

[0293] Furthermore, the EL layer 786 is formed in an island-like pattern for each pixel or in a striped pattern for each row of pixels, i.e., color separation. When formed by this method, the colored layer 736 and the optical adjustment layer described above are at least It is also possible to omit one of the components. In that case, use a shadow mask such as a metal mask. The EL layer 786 may be fabricated separately by vacuum deposition, or by photolithography. The EL layer 786 may be processed into island-like or striped patterns.

[0294] Here, insulating layer 744 and insulating layer 746 each function as a barrier film with low moisture permeability. It is preferable to use an inorganic insulating film. Between such insulating layer 744 and insulating layer 746 By having the light-emitting element 782 and the transistor 750 etc. sandwiched in between, these This suppresses degradation and enables the creation of highly reliable display panels.

[0295] The display panel 700A shown in Figure 12 has a protective layer 749 instead of a support substrate 740. .

[0296] The protective layer 749 is bonded to the sealing layer 732. The protective layer 749 is made of glass. A substrate or resin film can be used. In addition, the protective layer 749 can be polarized. Optical components such as plates (including circular polarizers) and scattering plates, input devices such as touch sensor panels, Alternatively, a configuration in which two or more of these are stacked may be applied.

[0297] Furthermore, the EL layer 786 of the light-emitting element 782 has islands on the insulating layer 730 and the conductive layer 772. It is arranged in a certain manner. The EL layer 786 is made so that the light-emitting color differs for each sub-pixel. Therefore, color display can be achieved without using the colored layer 736.

[0298] Furthermore, a protective layer 741 is provided covering the light-emitting element 782. The protective layer 741 emits light. The element 782 has a function to prevent impurities such as water from diffusing into it. The protective layer 741 is conductive. Insulating layer 741a, insulating layer 741b, and insulating layer 741c are laminated in this order from the layer 788 side. It has a laminated structure. At this time, the insulating layer 741a and insulating layer 741c are filled with water, etc. An inorganic insulating film with high barrier properties against impurities is used, and the insulating layer 741b functions as a planarization film. It is preferable to use organic insulating films. Furthermore, the protective layer 741 is gate dry It is preferable that the circuit section 706 also extends to the circuit section.

[0299] Furthermore, in Figure 12, a conductive layer 761 is provided on the protective layer 741. 61 can be used as wiring or an electrode, etc.

[0300] Furthermore, the conductive layer 761 is used when a touch sensor is installed on top of the display panel 700A. This is a static noise mechanism to prevent electrical noise generated when driving the pixels from being transmitted to the touch sensor. It can function as an electrical shielding film. At this time, a predetermined constant potential is applied to the conductive layer 761. It should be configured in a way that is achievable.

[0301] Alternatively, the conductive layer 761 can be used, for example, as an electrode for a touch sensor. This allows the display panel 700A to function as a touch panel. For example, The electrode layer 761 can be used as an electrode or wiring for a capacitive touch sensor. At this time, the conductive layer 761 is connected to the wiring or electrodes to which the detection circuit is connected, or to the sensor. It can be used as wiring or electrodes to which signals are input. By integrating the touch sensor onto the child 782, the number of parts can be reduced, and the manufacturing cost of electronic devices, etc. This can reduce strikes.

[0302] The conductive layer 761 is preferably provided in a portion that does not overlap with the light-emitting element 782. The conductive layer 761 can be provided in a position that overlaps with the insulating layer 730. As layer 761, there is no need to use a transparent conductive film with relatively low conductivity, and a highly conductive metal is used instead. Alternatively, alloys or other materials can be used, which can increase the sensitivity of the sensor.

[0303] Furthermore, the types of touch sensors that can be constructed using the conductive layer 761 include electrostatic Not limited to capacitive methods, but also include resistive, surface acoustic wave, infrared, optical, and pressure-sensitive methods. Various methods can be used. Alternatively, two or more of these can be combined. stomach.

[0304] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be combined with other configuration examples or drawings as appropriate.

[0305] (Embodiment 4) In this embodiment, as an example of an electronic device according to one aspect of the present invention, a display device is applied to a Let's look at an example of a head-mounted display.

[0306] Figures 13A and 13B show the external appearance of the head-mounted display 8300. .

[0307] The head-mounted display 8300 consists of a housing 8301, a display unit 8302, and control buttons. It has 8303 and a band-shaped fastener 8304.

[0308] Operation button 8303 has functions such as a power button. In addition to operation button 8303 It may have buttons.

[0309] Furthermore, as shown in Figure 13C, there is a lens 8 between the display unit 8302 and the user's eye position. It may have 305. The lens 8305 allows the user to magnify the display unit 8302. Because it can be seen, the sense of realism is enhanced. At this time, as shown in Figure 13C, diopter adjustment It may have a dial 8306 for changing the position of the lens for the node.

[0310] A display device according to one aspect of the present invention can be applied to the display unit 8302. Because the display device has extremely high resolution, it can be magnified using lens 8305 as shown in Figure 13C. Even if it's not a big deal, it displays a more realistic image without the user being able to see the individual pixels. It is possible.

[0311] Figures 13A to 13C show an example where there is one display unit 8302. By adopting such a configuration, the number of parts can be reduced.

[0312] The display unit 8302 has two regions, left and right, each containing an image for the right eye and an image for the left eye. Images can be displayed side by side. This allows for the display of stereoscopic images using binocular parallax. It is possible.

[0313] Furthermore, even if a single image visible to both eyes is displayed across the entire area of ​​the display unit 8302, Good. This makes it possible to display a panoramic image across both edges of the field of view, It feels more real.

[0314] Here, the head-mounted display 8300 adjusts to the size of the user's head, or the size of their eyes. The mechanism has a mechanism that changes the curvature of the display unit 8302 to an appropriate value depending on the position, etc. Preferred. For example, operating the dial 8307 for adjusting the curvature of the display unit 8302. Therefore, the user may adjust the curvature of the display unit 8302 themselves. Alternatively, the housing 8301 Sensors that detect the size of the user's head or the position of their eyes (e.g., cameras, contact sensors) A sensor (such as a contact sensor or a non-contact sensor) is provided, and a display unit 8302 is provided based on the sensor's detection data. It may have a mechanism for adjusting the curvature.

[0315] Furthermore, when using lens 8305, the curvature of the display unit 8302 is synchronized with the curvature of lens 8 It is preferable to have a mechanism for adjusting the position and angle of 305. Alternatively, dial 830 6 may have a function to adjust the angle of the lens.

[0316] Figures 13E and 13F show a drive unit 8308 that controls the curvature of the display unit 8302. An example is shown. The drive unit 8308 is fixed to at least a portion of the display unit 8302. The drive unit 8308 is affected by deformation or movement of the part that is fixed to the display unit 8302. It has a function to deform the display unit 8302.

[0317] Figure 13E shows a user 8310 with a relatively large head size wearing the housing 8301. This is a schematic diagram of the case where the display unit 8302 has a relatively small curvature. The drive unit 8308 adjusts the radius of curvature to be large.

[0318] On the other hand, Figure 13F shows that user 83 has a smaller head size compared to user 8310. 11 indicates that the housing 8301 is installed. Also, user 8311 is Compared to the 8310, the distance between the eyes is narrower. In this case, the shape of the display unit 8302 is The drive unit 8308 adjusts the curvature of the indicator part 8302 so that it becomes larger (the radius of curvature becomes smaller). It is arranged. Figure 13F shows the position and shape of the display unit 8302 in Figure 13E with dashed lines. ru.

[0319] In this way, the head-mounted display 8300 adjusts the curvature of the display unit 8302. By having such a mechanism, it is possible to provide optimal display to a wide range of users, regardless of age or gender. .

[0320] Furthermore, the curvature of the display unit 8302 is changed according to the content to be displayed on the display unit 8302. By doing so, it is possible to give the user a high level of realism. For example, the music displayed on the 8302 display unit By making the rate vibrate, shaking can be expressed. In this way, in scenes within content It is possible to create a variety of effects and provide users with a new experience. Furthermore, by linking this with the vibration module installed in the housing 8301, it becomes even more precise. This enables a display that conveys a strong sense of the context.

[0321] The head-mounted display 8300 has two display units 8, as shown in Figure 13D. It may have 302.

[0322] Having two display units 8302 allows the user to view one display unit per eye. This allows for high resolution even when performing 3D displays using parallax. It can display images. Furthermore, the display unit 8302 is an arc roughly centered on the user's eyes. It is curved in a specific shape. This ensures that the distance from the user's eye to the display surface of the display unit remains constant. Therefore, users can see more natural images. In addition, the brightness and color of the light from the display unit Even in cases where the degree changes depending on the viewing angle, the normal direction of the display surface of the display unit. Because the user's eyes are positioned there, the effect can be practically ignored, making it more realistic. It can display images that evoke a sense of atmosphere.

[0323] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be combined with other configuration examples or drawings as appropriate.

[0324] (Embodiment 5) In this embodiment, a display module that can be manufactured using one aspect of the present invention is provided. I will explain.

[0325] The display module 6000 shown in Figure 14A consists of an upper cover 6001 and a lower cover 6002 Between them are the display device 6006, frame 6009, and print, with the FPC6005 connected. It has a circuit board 6010 and a battery 6011.

[0326] For example, a display device manufactured using one aspect of the present invention may be used in the display device 6006. This is possible. The display device 6006 enables the realization of an extremely low-power display module. It is possible.

[0327] The upper cover 6001 and the lower cover 6002 are sized to fit the display device 6006. The shape and dimensions can be changed as appropriate.

[0328] The display device 6006 may also have the functionality of a touch panel.

[0329] Frame 6009 is determined by the protection function of the display device 6006 and the operation of the printed circuit board 6010. It may also have functions such as blocking electromagnetic waves generated, or functioning as a heat sink.

[0330] Printed circuit board 6010 is a power supply circuit and a signal for outputting video signals and clock signals. It includes a processing circuit, a battery control circuit, and the like.

[0331] Figure 14B is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. ru.

[0332] The display module 6000 includes a light-emitting section 6015 and a receiver provided on the printed circuit board 6010. It has a light-emitting section 6016. It is also surrounded by an upper cover 6001 and a lower cover 6002. The region has a pair of light guides (light guide 6017a, light guide 6017b).

[0333] The display device 6006 has a frame 6009 in between which it connects the printed circuit board 6010 and the battery. It is installed overlapping with Lee 6011. The display device 6006 and frame 6009 are light guide units. 6017a is fixed to the light guide section 6017b.

[0334] Light 6018 emitted from the light-emitting unit 6015 is directed by the light guide unit 6017a to the display device 600. It passes through the upper part of 6, through the light guide part 6017b, and reaches the light receiving part 6016. For example, a finger or Touch operation is detected when light 6018 is blocked by an object being detected, such as a stylus. It is possible.

[0335] Multiple light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. Multiple light-receiving units 6016 are provided at positions opposite to the light-emitting unit 6015. This allows for... Information about the location where the operation was performed can be obtained.

[0336] The light-emitting section 6015 can use a light source such as an LED element, and in particular, infrared light It is preferable to use a light source that emits light. The light receiving unit 6016 receives the light emitted by the light emitting unit 6015. A photoelectric element that converts light into an electrical signal can be used. Preferably, one that can receive infrared light. A photodiode can be used.

[0337] The light-emitting section 6015 and the light-emitting section 6015 are separated by the light-transmitting light-emitting section 6017a and light-transmitting section 6017b. The light receiving unit 6016 can be positioned below the display device 6006, and ambient light can be received by the light receiving unit 601 Reaching 6 can suppress the malfunction of the touch sensor. In particular, it absorbs visible light and infrared light. Using a resin that allows light to pass through can more effectively suppress malfunctions in touch sensors.

[0338] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0339] (Embodiment 6) This embodiment describes an example of an electronic device to which a display device according to one aspect of the present invention can be applied. I will reveal it.

[0340] The electronic device 6500 shown in Figure 15A is a portable device that can be used as a smartphone. It is a news terminal device.

[0341] The electronic device 6500 consists of a housing 6501, a display unit 6502, a power button 6503, and a button 6 It includes 504, speaker 6505, microphone 6506, camera 6507, and light source 6508, etc. The display unit 6502 is equipped with a touch panel function.

[0342] A display device according to one aspect of the present invention can be applied to the display unit 6502.

[0343] Figure 15B is a schematic cross-sectional view of the housing 6501, including the end on the microphone 6506 side.

[0344] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and the housing 650 Within the space surrounded by 1 and protective member 6510, display panel 6511, optical member 6512, The touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged. Yes, they are.

[0345] The protective member 6510 includes a display panel 6511, an optical member 6512, and a touch sensor panel. Nel 6513 is fixed by an adhesive layer (not shown).

[0346] Furthermore, in the area outside the display unit 6502, a portion of the display panel 6511 is folded back. It is done. Furthermore, the FPC6515 is connected to the folded portion. IC6516 is mounted on the 6515. Also, the FPC6515 is printed circuit board 6 It is connected to the terminal provided at 517.

[0347] A flexible display panel according to one aspect of the present invention is applied to the display panel 6511. This makes it possible to create extremely lightweight electronic devices. Also, the display panel 651 Because it is extremely thin, it allows for a reduction in the thickness of electronic devices while incorporating a large-capacity 6518 battery. It is also possible to fold back a portion of the display panel 6511 and place an FPC on the back of the pixel area. By positioning the connection point with 6515, it is possible to realize electronic devices with narrow bezels.

[0348] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0349] (Embodiment 7) In this embodiment, an electronic device equipped with a display device manufactured using one aspect of the present invention is provided. I will explain.

[0350] The electronic device described below is equipped with a display device according to one embodiment of the present invention in its display unit. Therefore, it is an electronic device that achieves high resolution. Also, high resolution and a large screen It can be made into an electronic device that is compatible with both systems.

[0351] One aspect of the present invention relates to a display device, an antenna, a battery, a housing, a camera, a speaker, and a microphone. It has at least one of the following: a touch sensor and an operation button.

[0352] An electronic device according to one aspect of the present invention may have a secondary battery and uses contactless power transmission. It is preferable that the secondary battery can be recharged.

[0353] Examples of secondary batteries include lithium polymer batteries (lithium-ion batteries) that use a gel-like electrolyte. Lithium-ion secondary batteries such as polymer batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic Examples include radical batteries, lead-acid batteries, air-based rechargeable batteries, nickel-zinc batteries, and silver-zinc batteries. ru.

[0354] An electronic device according to one aspect of the present invention may have an antenna. The antenna receives a signal. This allows the display unit to show images, information, etc. Also, the electronic device acts as an antenna. Furthermore, if a secondary battery is present, the antenna may be used for contactless power transmission.

[0355] The display unit of an electronic device according to one aspect of the present invention may display, for example, Full HD, 4K2K, 8K4 It can display video with resolutions of K, 16K, 8K, or higher.

[0356] Examples of electronic devices include television equipment, notebook personal computers, Equipped with relatively large screens such as monitors, digital signage, pachinko machines, and game machines. In addition to electronic devices, digital cameras, digital video cameras, digital photo frames, and portable devices are also available. Examples include mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0357] An electronic device to which one aspect of the present invention is applied is located on the interior or exterior walls of a house or building. It can be incorporated along the flat or curved surfaces of walls, the interior or exterior of automobiles, etc. .

[0358] Figure 16A shows the external appearance of the camera 8000 with the viewfinder 8100 attached. That is the case.

[0359] The camera 8000 consists of a housing 8001, a display unit 8002, operation buttons 8003, and a shutter. It has buttons 8004, etc. The camera 8000 also has a detachable lens 8006. It is attached.

[0360] The camera 8000 may have the lens 8006 and the housing integrated into a single unit.

[0361] Camera 8000 can be operated by pressing the shutter button 8004, or by using the touch panel function. Image capture can be performed by touching the display unit 8002.

[0362] The housing 8001 has a mount with electrodes, and in addition to the viewfinder 8100, it also has a strobe It can be connected to devices such as power supply units.

[0363] The viewfinder 8100 has a housing 8101, a display unit 8102, buttons 8103, etc. .

[0364] The housing 8101 engages with the mount of the camera 8000 via a mount, and the camera 800 It is attached to the 0. The viewfinder 8100 receives images and other data from the camera 8000. This can be displayed on the display unit 8102.

[0365] Button 8103 functions as a power button, etc.

[0366] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are equipped with this A display device according to one embodiment of the invention can be applied. Note that a camera with a built-in viewfinder can also be used. It could also be 8000.

[0367] Figure 16B shows the external appearance of the head-mounted display 8200.

[0368] The head-mounted display 8200 consists of a mounting part 8201, lenses 8202, and a main body 82 03, it has a display unit 8204, a cable 8205, etc. Also, the mounting part 8201 has It has a built-in 8206 battery.

[0369] Cable 8205 supplies power from battery 8206 to main unit 8203. Unit 203 is equipped with a wireless receiver and can display the received video information on the display unit 8204. It can. In addition, the main unit 8203 is equipped with a camera to input information about the user's eyeball or eyelid movements. It can be used as a means of force.

[0370] Furthermore, the attachment part 8201 is positioned in a location that touches the user, and the flow follows the movement of the user's eyeballs. Multiple electrodes capable of detecting currents may be provided, and the device may also have a function to recognize line of sight. Furthermore, the device may have a function to monitor the user's pulse rate based on the current flowing through the electrode. Furthermore, the mounting section 8201 is equipped with various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. Even if it is not set up, it may have a function to display the user's biometric information on the display unit 8204, and the movement of the user's head It may also have a function to change the image displayed on the display unit 8204 according to the time.

[0371] A display device according to one aspect of the present invention can be applied to the display unit 8204.

[0372] Figures 16C, 16D, and 16E show the appearance of the head-mounted display 8300. The diagram shows the head-mounted display 8300, which consists of a housing 8301 and a display unit 830 It comprises 2, a band-shaped fixing device 8304, and a pair of lenses 8305.

[0373] The user can view the display on the display unit 8302 through the lens 8305. Furthermore, by arranging the display unit 8302 in a curved shape, the user can experience a high level of realism. This is preferable. Also, another image displayed in a different area of ​​the display unit 8302 is displayed by the lens 8 By viewing through the 305, it is also possible to perform 3D displays using parallax. The configuration is not limited to having one display unit 8302, but can also have two display units 8302, allowing one of the users to... One display unit may be placed for each eye.

[0374] Furthermore, a display device according to one embodiment of the present invention can be applied to the display unit 8302. A display device having a semiconductor device according to one embodiment has extremely high resolution, as shown in Figure 16E. Even when magnified using lens 8305, the user cannot see the individual pixels, resulting in a more detailed view. It can display highly realistic images.

[0375] The electronic equipment shown in Figures 17A to 17G consists of a housing 9000, a display unit 9001, and a speaker 9 003, Operation key 9005 (including power switch or operation switch), Connection terminal 900 6. Sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, Magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity (Including functions for measuring degrees, inclines, vibrations, odors, or infrared radiation), Microphone 900 8, etc.

[0376] The electronic devices shown in Figures 17A to 17G have various functions. For example, various information ( Functions to display still images, videos, text images, etc. on the display unit, touch panel function, calendar A function that displays the date or time, etc., through various software (programs) Functions that control processing, wireless communication functions, programs or data recorded on recording media It can have functions such as reading and processing data. Furthermore, the functions of electronic devices are related to these. It is not limited and can have a variety of functions. Even if an electronic device has multiple display units Good. Also, an electronic device may be equipped with a camera, etc., to take still images or videos and record them on a recording medium (external... It has functions such as saving to the camera (built into the camera), and displaying the captured image on the display unit. It's okay to be there.

[0377] The details of the electronic equipment shown in Figures 17A to 17G will be explained below.

[0378] Figure 17A is a perspective view showing the television equipment 9100. 0 is a display unit 9001 with a large screen, for example, 50 inches or larger, or 100 inches or larger. It is possible to insert it.

[0379] Figure 17B is a perspective view showing the personal digital assistant 9101. The personal digital assistant 9101 is, for example, For example, it can be used as a smartphone. Note that the mobile information terminal 9101 is a speed A connector (9003), connection terminal (9006), sensor (9007), etc. may be provided. Also, a portable information terminal may be provided. The 9101 can display text, image information, etc., on its multiple surfaces. In Figure 17B, This shows an example displaying three icons 9050. Also, information 905 is shown by a dashed rectangle. 1 can also be displayed on other sides of the display unit 9001. An example of information 9051 is: Notifications for incoming emails, social media messages, and phone calls; subject and sender information for emails or social media messages. This includes name, date and time, battery level, antenna signal strength, etc. Alternatively, Information 90 You may also display an icon such as 9050 in the position where 51 is displayed.

[0380] Figure 17C is a perspective view showing the personal digital assistant 9102. The personal digital assistant 9102 is a table The display unit 9001 has the function of displaying information on three or more sides. Here, information 9052, information This shows an example where information 9053 and information 9054 are displayed on different sides. For example, the user With the mobile information terminal 9102 stored in the breast pocket of his clothing, the mobile information terminal 9102 Information 9053, displayed in a position visible from above, can also be viewed. The user can, You can check the display without taking the 9102 personal digital assistant out of your pocket, for example, to answer a phone call. It is possible to determine whether or not to do so.

[0381] Figure 17D is a perspective view showing a wristwatch-type portable information terminal 9200. Also, the display unit 90 01 has a curved display surface, and can display information along the curved surface. Furthermore, the portable information terminal 9200 can communicate with, for example, a wireless headset. This also allows for hands-free calling. Furthermore, the 9200 mobile information terminal is connected The connection terminal 9006 is used for mutual data transmission with other information terminals, or for charging. It is also possible to perform the charging operation via wireless power supply.

[0382] Figures 17E, 17F, and 17G show a foldable portable information terminal 9201 from an oblique angle. This is a visual view. Figure 17E shows the mobile information terminal 9201 in its unfolded state, and Figure 17G shows it folded. Figure 17F is a perspective view of the state in which Figure 17E and Figure 17G are transitioning from one to the other. The portable information terminal 9201 is highly portable when folded, and when unfolded... The seamless, wide display area provides excellent readability. (Features of the 9201 mobile information terminal) The display unit 9001 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. Cut.

[0383] Figure 18A shows an example of a television system. The television system 7100 has a housing 710 The display unit 7500 is incorporated into 1. Here, the stand 7103 connects to the housing 710. This shows the configuration that supports option 1.

[0384] The television device 7100 shown in Figure 18A is operated by the operation switches provided on the housing 7101. This can be done by the 75 or a separate remote control unit 7111. Alternatively, the display unit 75 A touch panel is applied to 00, and the television device 7100 is operated by touching it. Alternatively, the remote control unit 7111 may have a display in addition to the operation buttons.

[0385] The television equipment 7100 is a television broadcast receiver or a network-connected device. They may have a communication device for that purpose.

[0386] Figure 18B shows the 7200 notebook personal computer. The Computer 7200 consists of a casing 7211, a keyboard 7212, and a pointing device 7 It has external connection ports 7214, etc. The display unit 7500 is incorporated into the housing 7211. It is being made.

[0387] Figures 18C and 18D show digital signage. An example of an electronic sign is shown.

[0388] The digital signage 7300 shown in Figure 18C consists of a housing 7301, a display unit 7500, and It has a speaker 7303, etc. Furthermore, it has an LED lamp, operation keys (power switch, or It may include an operating switch, connection terminals, various sensors, a microphone, etc. .

[0389] Figure 18D shows a digital signage 7400 mounted on a cylindrical column 7401. Yes. The digital signage 7400 has a display unit 75 that is installed along the curved surface of the column 7401. It has 00.

[0390] The larger the display unit 7500, the more information can be provided at once, and the more human eyes... Because it is easily absorbed, it can, for example, enhance the effectiveness of advertising.

[0391] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. This allows for applications beyond advertising, such as route information, traffic information, or commercial facility guidance information. It can also be used to provide users with the information they are looking for.

[0392] Furthermore, as shown in Figures 18C and 18D, the digital signage 7300 or digital Talsignage 7400 is an information terminal 7311 such as a smartphone owned by the user. It is preferable that it be possible to communicate with it via wireless communication. For example, displayed on the display unit 7500 The advertising information can be displayed on the screen of the information terminal 7311. By operating the 311, you can also switch the display on the 7500 display unit.

[0393] Additionally, information terminals can be connected to the Digital Signage 7300 or Digital Signage 7400. It is also possible to run games using the 7311 as the control device (controller). This allows a large number of users to participate in and enjoy the game simultaneously.

[0394] A display device according to one embodiment of the present invention is applied to the display unit 7500 in Figures 18A to 18D. It is possible.

[0395] Although the electronic device in this embodiment has a display unit, electronic devices that do not have a display unit can also be used. An embodiment of the present invention can also be applied.

[0396] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination. [Explanation of Symbols]

[0397] 10: Display device 11: Pixel section 12: Circuit 13: Circuit 15a, 15b: Terminal section 1 6a-16c: Wiring 17: IC 20: Pixel unit 21a-21b: Pixel 22: Display area 31-33: Pixel electrodes 41-43: Pixel circuit 51-53: Wiring 60: Front Display element 61-62: Transistor 63: Capacitive element 71-73: Sub-pixel 100: Rangista 102: Substrate 103a-103b: Insulating layer 104: Insulating layer 106, 1 06a, 106b: conductive layer; 108, 108a, 108b: semiconductor layer; 108n: low resistance Region 110: Insulating layer 112, 112a, 112b: Conductive layer 112f: Conductive film 11 4: Metal oxide layer 114f: Metal oxide film 116, 118: Insulating layer 120a-12 0c: Conductive layer 121-121d: Conductive layer 130: Conductive layer 131-133: Resin layer 140: Impurity element 141a-141b: Opening 142-144: Opening 150: conductive layer

Claims

1. Each pixel has a first transistor, a second transistor, and a light-emitting element. The first transistor has a channel formation region in the first semiconductor layer, The second transistor is a display device having a channel formation region in the second semiconductor layer, A first conductive layer and An insulating layer having a region located above the first conductive layer, A second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, each having a region located above the insulating layer, A first layer having a region located above the second conductive layer, a region located above the third conductive layer, a region located above the fourth conductive layer, and a region located above the fifth conductive layer, A sixth conductive layer, a seventh conductive layer, and an eighth conductive layer having a region located above the first layer, A second layer having a region located above the sixth conductive layer, a region located above the seventh conductive layer, and a region located above the eighth conductive layer, A ninth conductive layer having a region located above the second layer, The second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer each have a region in contact with the upper surface of the insulating layer. The sixth conductive layer, the seventh conductive layer, and the eighth conductive layer each have a region in contact with the upper surface of the first layer. The first layer and the second layer each have a resin, The first conductive layer functions as a first wiring that inputs a signal to the gate of the first transistor. The second conductive layer has the function of electrically connecting the first semiconductor layer and the gate of the second transistor. The sixth conductive layer has the function of a second wiring, The potential corresponding to the signal input to the second wiring is input to the gate of the second transistor via the channel formation region of the first transistor. The third conductive layer is electrically connected to the sixth conductive layer, The seventh conductive layer has the function of a third wiring, The fourth conductive layer has the function of electrically connecting the second semiconductor layer and the seventh conductive layer. The ninth conductive layer has the function of a pixel electrode of the light-emitting element, The fifth conductive layer and the eighth conductive layer have the function of electrically connecting the second semiconductor layer and the ninth conductive layer. The sixth conductive layer overlaps with the first conductive layer via the insulating layer and the first layer. A display device wherein the seventh conductive layer overlaps with the first conductive layer via the insulating layer and the first layer.

2. Each pixel has a first transistor, a second transistor, and a light-emitting element. The first transistor has a channel formation region in the first semiconductor layer, The second transistor is a display device having a channel formation region in the second semiconductor layer, A first conductive layer and An insulating layer having a region located above the first conductive layer, A second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, each having a region located above the insulating layer, A first layer having a region located above the second conductive layer, a region located above the third conductive layer, a region located above the fourth conductive layer, and a region located above the fifth conductive layer, A sixth conductive layer, a seventh conductive layer, and an eighth conductive layer having a region located above the first layer, A second layer having a region located above the sixth conductive layer, a region located above the seventh conductive layer, and a region located above the eighth conductive layer, A ninth conductive layer having a region located above the second layer, The second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer each have a region in contact with the upper surface of the insulating layer. The sixth conductive layer, the seventh conductive layer, and the eighth conductive layer each have a region in contact with the upper surface of the first layer. The first layer and the second layer each have a resin, The first conductive layer functions as a first wiring that inputs a signal to the gate of the first transistor. The second conductive layer has the function of electrically connecting the first semiconductor layer and the gate of the second transistor. The sixth conductive layer has the function of a second wiring, The potential corresponding to the signal input to the second wiring is input to the gate of the second transistor via the channel formation region of the first transistor. The third conductive layer is electrically connected to the sixth conductive layer, The seventh conductive layer has the function of a third wiring, The fourth conductive layer has the function of electrically connecting the second semiconductor layer and the seventh conductive layer. The ninth conductive layer has the function of a pixel electrode of the light-emitting element, The fifth conductive layer and the eighth conductive layer have the function of electrically connecting the second semiconductor layer and the ninth conductive layer. The sixth conductive layer overlaps with the first conductive layer via the insulating layer and the first layer. The seventh conductive layer overlaps with the first conductive layer via the insulating layer and the first layer. A display device wherein the seventh conductive layer is arranged to overlap the entirety of the second conductive layer via the first layer.

3. Each pixel has a first transistor, a second transistor, and a light-emitting element. The first transistor has a channel formation region in the first semiconductor layer, The second transistor is a display device having a channel formation region in the second semiconductor layer, A first conductive layer and An insulating layer having a region located above the first conductive layer, A second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, each having a region located above the insulating layer, A first layer having a region located above the second conductive layer, a region located above the third conductive layer, a region located above the fourth conductive layer, and a region located above the fifth conductive layer, A sixth conductive layer, a seventh conductive layer, and an eighth conductive layer having a region located above the first layer, A second layer having a region located above the sixth conductive layer, a region located above the seventh conductive layer, and a region located above the eighth conductive layer, A ninth conductive layer having a region located above the second layer, The second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer each have a region in contact with the upper surface of the insulating layer. The sixth conductive layer, the seventh conductive layer, and the eighth conductive layer each have a region in contact with the upper surface of the first layer. The first layer and the second layer each have a resin, The first conductive layer functions as a first wiring that inputs a signal to the gate of the first transistor. The second conductive layer has the function of electrically connecting the first semiconductor layer and the gate of the second transistor. The sixth conductive layer has the function of a second wiring, The potential corresponding to the signal input to the second wiring is input to the gate of the second transistor via the channel formation region of the first transistor. The third conductive layer is electrically connected to the sixth conductive layer, The seventh conductive layer has the function of a third wiring, The fourth conductive layer has the function of electrically connecting the second semiconductor layer and the seventh conductive layer. The ninth conductive layer has the function of a pixel electrode of the light-emitting element, The fifth conductive layer and the eighth conductive layer have the function of electrically connecting the second semiconductor layer and the ninth conductive layer. The sixth conductive layer overlaps with the first conductive layer via the insulating layer and the first layer. The seventh conductive layer overlaps with the first conductive layer via the insulating layer and the first layer. In a plan view of the pixel, the first conductive layer is arranged to be stretched in a first direction. In the plan view, the sixth conductive layer is arranged to extend in a second direction intersecting the first direction, in a display device.

4. Each pixel has a first transistor, a second transistor, and a light-emitting element. The first transistor has a channel formation region in the first semiconductor layer, The second transistor is a display device having a channel formation region in the second semiconductor layer, A first conductive layer and An insulating layer having a region located above the first conductive layer, A second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, each having a region located above the insulating layer, A first layer having a region located above the second conductive layer, a region located above the third conductive layer, a region located above the fourth conductive layer, and a region located above the fifth conductive layer, A sixth conductive layer, a seventh conductive layer, and an eighth conductive layer having a region located above the first layer, A second layer having a region located above the sixth conductive layer, a region located above the seventh conductive layer, and a region located above the eighth conductive layer, A ninth conductive layer having a region located above the second layer, The second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer each have a region in contact with the upper surface of the insulating layer. The sixth conductive layer, the seventh conductive layer, and the eighth conductive layer each have a region in contact with the upper surface of the first layer. The first layer and the second layer each have a resin, The first conductive layer functions as a first wiring that inputs a signal to the gate of the first transistor. The second conductive layer has the function of electrically connecting the first semiconductor layer and the gate of the second transistor. The sixth conductive layer has the function of a second wiring, The potential corresponding to the signal input to the second wiring is input to the gate of the second transistor via the channel formation region of the first transistor. The third conductive layer is electrically connected to the sixth conductive layer, The seventh conductive layer has the function of a third wiring, The fourth conductive layer has the function of electrically connecting the second semiconductor layer and the seventh conductive layer. The ninth conductive layer has the function of a pixel electrode of the light-emitting element, The fifth conductive layer and the eighth conductive layer have the function of electrically connecting the second semiconductor layer and the ninth conductive layer. The sixth conductive layer overlaps with the first conductive layer via the insulating layer and the first layer. The seventh conductive layer overlaps with the first conductive layer via the insulating layer and the first layer. The seventh conductive layer is arranged so as to overlap the entirety of the second conductive layer via the first layer. In a plan view of the pixel, the first conductive layer is arranged to be stretched in a first direction. In the plan view, the sixth conductive layer is arranged to extend in a second direction intersecting the first direction, in a display device.

Images