Inverter device, solar power generation system, and method for discharging an inverter circuit

Abstract

Discharge the charge that requires discharge in the inverter device. [Solution] The inverter device comprises an inverter circuit and an inverter control unit. The inverter circuit comprises a DC terminal pair consisting of a first DC terminal and a second DC terminal, an AC terminal pair consisting of a plurality of AC terminals, a first capacitor and a second capacitor connected in series between the first DC terminal and the second DC terminal, and a plurality of switch elements connected between the DC terminal pair and the AC terminal pair in a predetermined connection pattern, each being made of semiconductors and having a parasitic diode. When the inverter control unit detects an interruption in the DC power input from the DC terminal pair, it controls the plurality of switch elements to turn on and off, clamping the voltage of the first capacitor with the reverse voltage of the parasitic diode of the switched element that is turned off, and clamping the voltage of the second capacitor with the reverse voltage of the parasitic diode of the switched element that is turned off.

Description

Technical Field

[0001] It relates to a discharge technology in case of abnormality in an inverter device to which high-current power such as that of a photovoltaic power generation system is input.

Background Art

[0002] Patent Document 1 describes a system for performing rapid shutdown in a photovoltaic power generation system. The system of Patent Document 1 includes a power conversion device that converts DC power generated by a solar panel into AC power.

[0003] When the power conversion device acquires a signal indicating an emergency, it reduces the DC voltage between the positive transmission line and the negative transmission line of the solar panel to 30 V or less.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When converting power generated by DC (DC power) such as that of a photovoltaic power generation system into AC power, an inverter device is provided in the power conversion circuit. And usually, a capacitor is connected to the input terminal on the side (DC side) of the inverter device that is connected to the solar panel.

[0006] However, in a conventional system including the system of Patent Document 1, it was difficult to discharge the charge accumulated in the capacitor of the inverter device in case of an emergency (rapid shutdown).

[0007] Therefore, an object of the present invention is to discharge the charge that requires discharge in the inverter device.

Means for Solving the Problems

[0008] An inverter device according to one embodiment of this invention comprises an inverter circuit and an inverter control unit.

[0009] The inverter circuit comprises a DC terminal pair consisting of a first DC terminal and a second DC terminal, an AC terminal pair consisting of a plurality of AC terminals, a first capacitor and a second capacitor connected in series between the first DC terminal and the second DC terminal, and a plurality of switch elements connected between the DC terminal pair and the AC terminal pair in a predetermined connection pattern, each being made of semiconductor material and having a parasitic diode.

[0010] When the inverter control unit detects a break in the DC power input from the DC terminal pair, it controls multiple switch elements to turn on and off, clamping the voltage of the first capacitor with the reverse voltage of the parasitic diode of the switched element that is turned off, and clamping the voltage of the second capacitor with the reverse voltage of the parasitic diode of the switched element that is turned off.

[0011] In this configuration, the charge stored in the first capacitor is discharged into the inverter circuit until the voltage across the first capacitor becomes the reverse voltage of the parasitic diode. Similarly, the charge stored in the second capacitor is discharged into the inverter circuit until the voltage across the second capacitor becomes the reverse voltage of the parasitic diode. As a result, any unwanted charge stored in the first and second capacitors located within the inverter circuit is removed without leaking to the outside. [Effects of the Invention]

[0012] According to this invention, unwanted charges accumulated in the capacitor of an inverter device can be discharged. [Brief explanation of the drawing]

[0013] [Figure 1] Figure 1 is a functional block diagram of a photovoltaic power generation system according to the first embodiment of the present invention. [Figure 2]Figure 2 is an equivalent circuit diagram of an inverter device according to the first embodiment of the present invention. [Figure 3] Figure 3 is a flowchart showing an example of a discharge method for an inverter circuit according to the first embodiment of the present invention. [Figure 4] Figure 4 is a table showing an example of the state transitions of the switch element in an inverter circuit according to the first embodiment of the present invention. [Figure 5] Figure 5 is an equivalent circuit diagram of the inverter circuit according to the first embodiment of the present invention, showing the discharge control of capacitors C1 and Cf1. [Figure 6] Figure 6 is an equivalent circuit diagram of the inverter circuit according to the first embodiment of the present invention, showing the discharge control of capacitors C4 and Cf1. [Figure 7] Figure 7 is an equivalent circuit diagram of the inverter circuit according to the first embodiment of the present invention when the discharge of capacitor Cf2 is controlled. [Figure 8] Figure 8 is an equivalent circuit diagram of the inverter circuit according to the first embodiment of the present invention when the discharge of capacitor Cf3 is controlled. [Figure 9] Figure 9 is a flowchart showing an example of a discharge method for an inverter circuit according to a second embodiment of the present invention. [Figure 10] Figure 10 is a table showing an example of the state transitions of the switch element in an inverter circuit according to a second embodiment of the present invention. [Figure 11] Figure 11 is an equivalent circuit diagram of the inverter circuit according to the second embodiment of the present invention when the discharge of capacitor Cf1 is controlled. [Figure 12] Figure 12 is a flowchart showing another example of a discharge method for an inverter circuit according to a second embodiment of the present invention. [Figure 13] Figure 13 is a table showing another example of the state transitions of the switch element in an inverter circuit according to a second embodiment of the present invention. [Figure 14] Figure 14 is an equivalent circuit diagram of the inverter circuit according to the second embodiment of the present invention when the discharge of capacitor C1 is controlled. [Figure 15]FIG. 15 is an equivalent circuit diagram when discharging the capacitor C4 in the inverter circuit according to the second embodiment of the present invention. [Figure 16] FIG. 16 is a flowchart showing an example of a discharge method of the inverter circuit according to the third embodiment of the present invention. [Figure 17] FIG. 17 is a table showing an example of the state transition of the switch element in the inverter circuit according to the third embodiment of the present invention. [Figure 18] FIG. 18 is an equivalent circuit diagram when discharging the capacitor C1 and the capacitor Cf2 in the inverter circuit according to the third embodiment of the present invention. [Figure 19] FIG. 19 is an equivalent circuit diagram when discharging the capacitor C4 and the capacitor Cf2 in the inverter circuit according to the third embodiment of the present invention. [Figure 20] FIG. 20 is a flowchart showing an example of a discharge method of the inverter circuit according to the fourth embodiment of the present invention. [Figure 21] FIG. 21 is a table showing an example of the state transition of the switch element in the inverter circuit according to the fourth embodiment of the present invention. [Figure 22] FIG. 22 is an equivalent circuit diagram when discharging the capacitor C1 and the capacitor Cf3 in the inverter circuit according to the fourth embodiment of the present invention. [Figure 23] FIG. 23 is an equivalent circuit diagram when discharging the capacitor C4 and the capacitor Cf3 in the inverter circuit according to the fourth embodiment of the present invention. [Figure 24] FIG. 24 is a flowchart showing an example of a discharge method of the inverter circuit according to the fifth embodiment of the present invention.

MODE FOR CARRYING OUT THE INVENTION

[0014] [First Embodiment] An inverter device and a photovoltaic power generation system according to the first embodiment of the present invention will be described with reference to the figures. In each embodiment, including this embodiment, the inverter device is applied to a photovoltaic power generation system, but the inverter device configuration shown below can be applied to any system in which a large DC current (high power) is input to the inverter device.

[0015] (Solar power generation system) Figure 1 is a functional block diagram of a photovoltaic power generation system according to the first embodiment of the present invention. As shown in Figure 1, the photovoltaic power generation system 1 comprises an inverter device 10, a plurality of photovoltaic power generation panels SP, a PV control unit 20, and a shut-off switch 30. The number of photovoltaic power generation panels SP may be one or more.

[0016] Multiple solar power generation panels SP are connected to a PV control unit 20. The multiple solar power generation panels SP and the PV control unit 20 constitute the solar power generation device of the present invention.

[0017] The PV control unit 20 controls the power generation of multiple solar power generation panels SP. The PV control unit 20 combines the power generated by the multiple solar power generation panels SP and outputs a desired DC power.

[0018] The inverter device 10 includes a first DC terminal PV+, a second DC terminal PV-, and a plurality of AC terminals OUT1, OUT2, and OUT3. The first DC terminal PV+ and the second DC terminal PV- constitute the DC terminal pair of the inverter device 10. The plurality of AC terminals OUT1, OUT2, and OUT3 connect the AC terminal pair of the inverter device 10.

[0019] The DC terminal pair (first DC terminal PV+ and second DC terminal PV-) is connected to the output terminal pair of the PV control unit 20. The AC terminal pair is connected to an AC load, commercial power grid, etc.

[0020] The inverter device 10 converts the DC power input through the DC terminal pair into AC power of a predetermined voltage and outputs it from the AC terminal pair.

[0021] The shut-off switch 30 is a switch for rapid shutdown. When the shut-off switch 30 receives a shut-off operation input, it outputs a shutdown signal to the PV control unit 20 and the inverter device 10.

[0022] When the PV control unit 20 receives a shutdown signal, it stops outputting DC power to the inverter device 10.

[0023] The inverter device 10 detects the interruption of DC power input to the DC terminal pair by receiving a shutdown signal. The inverter device 10 may also be equipped with sensors, etc., to detect the interruption of DC power input to the DC terminal pair.

[0024] When the inverter device 10 detects a DC power interruption, it performs discharge control. Discharge control is, in general terms, a control that causes the charge stored in the capacitor within the inverter device 10 to be consumed within the inverter device 10.

[0025] (Inverter device 10) Figure 2 is an equivalent circuit diagram of an inverter device according to a first embodiment of the present invention. As shown in Figure 2, the inverter device 10 comprises an inverter circuit 11, a filter circuit 12, and an inverter control unit 19.

[0026] The inverter circuit 11 comprises a plurality of switching elements Q1-Q12, capacitor C1, and capacitor C4. Capacitor C1 corresponds to the first capacitor of the present invention. Capacitor C2 corresponds to the second capacitor of the present invention.

[0027] Multiple switch elements Q1-Q12 are each constructed using semiconductors and have parasitic diodes. Multiple switch elements Q1-Q12 have the same characteristics. Multiple switch elements Q1-Q12 are constructed using, for example, IGBTs. Switch elements Q1, Q5, and Q9 correspond to the "first switch element" of the present invention. Switch elements Q2, Q6, and Q10 correspond to the "second switch element" of the present invention. Switch elements Q3, Q7, and Q11 correspond to the "third switch element" of the present invention. Switch elements Q4, Q8, and Q12 correspond to the "fourth switch element" of the present invention.

[0028] The inverter circuit 11 includes wiring 111, 112, 1131, 1132, 1133, 114, 1151, 1152, and 1153. Wiring 111 corresponds to the "first wiring" of the present invention, and wiring 112 corresponds to the "second wiring" of the present invention. Wiring 114 corresponds to the "third wiring" of the present invention. Wiring 1131, 1132, and 1133 each correspond to the "fourth wiring" of the present invention.

[0029] The filter circuit 12 comprises inductors Lf11, Lf12, Lf21, Lf22, Lf31, Lf32, capacitors Cf1, Cf2, and Cf3. Capacitors Cf1, Cf2, and Cf3 correspond to the filter capacitors of the present invention.

[0030] The filter circuit 12 includes wiring 1131, 1132, 1133, 121, 122, and 123. Wiring 1131, 1132, and 1133 are arranged across the inverter circuit 11 and the filter circuit 12.

[0031] (Specific connection configuration of inverter circuit 11) The first DC terminal PV+ is the positive DC terminal. The second DC terminal PV- is the negative DC terminal. Wiring 111 is connected to the first DC terminal PV+. Wiring 112 is connected to the second DC terminal PV-.

[0032] Capacitors C1 and C4 are connected in series between the first DC terminal PV+ (wire 111) and the second DC terminal PV- (wire 112) by wiring 114. In this configuration, capacitor C1 is positioned on the side of the first DC terminal PV+, and capacitor C4 is positioned on the side of the second DC terminal PV-. The connection point between wiring 111 and wiring 114 is connection node ND11. The connection point between wiring 112 and wiring 114 is connection node ND21.

[0033] Switch elements Q1 and Q4 are connected between wires 111 and 112 by wire 1151. More specifically, the collector terminal of switch element Q1 is connected to connection node ND12 between wire 1151 and wire 111. The emitter terminal of switch element Q1 and the collector terminal of switch element Q4 are connected to each other. The emitter terminal of switch element Q4 is connected to connection node ND22 between wire 1151 and wire 112.

[0034] Wiring 1131 is connected to the portion of wiring 114 between capacitors C1 and C4. The connection point between wiring 1131 and wiring 114 is connection node ND31. Wiring 1131 is connected to AC terminal OUT1 through filter circuit 12. Wiring 1131 is connected to the portion of wiring 1151 between switch elements Q1 and Q4. This connection point is connection node ND32.

[0035] Switch elements Q2 and Q3 are connected between connection node ND31 and connection node ND32. More specifically, the collector terminal of switch element Q2 is connected to connection node ND31. The emitter terminal of switch element Q2 and the emitter terminal of switch element Q3 are connected to each other. The collector terminal of switch element Q3 is connected to connection node ND32. As a result, switch elements Q2 and Q3 are connected in a state where their switch polarities are reversed (the polarities of their respective parasitic diodes are reversed).

[0036] Switch elements Q5 and Q8 are connected between wires 111 and 112 by wire 1152. More specifically, the collector terminal of switch element Q5 is connected to connection node ND13 between wire 1152 and wire 111. The emitter terminal of switch element Q5 and the collector terminal of switch element Q8 are connected to each other. The emitter terminal of switch element Q8 is connected to connection node ND23 between wire 1152 and wire 112.

[0037] Wiring 1132 is connected to the portion of wiring 114 between capacitors C1 and C4. The connection point between wiring 1132 and wiring 114 is connection node ND41. Wiring 1132 is connected to AC terminal OUT2 through filter circuit 12. Wiring 1132 is connected to the portion of wiring 1152 between switch elements Q5 and Q8. This connection point is connection node ND42.

[0038] Switch elements Q6 and Q7 are connected between connection node ND41 and connection node ND42. More specifically, the collector terminal of switch element Q6 is connected to connection node ND41. The emitter terminal of switch element Q6 and the emitter terminal of switch element Q7 are connected to each other. The collector terminal of switch element Q7 is connected to connection node ND42. As a result, switch elements Q7 and Q8 are connected in a state where their switch polarities are reversed (the polarities of their respective parasitic diodes are reversed).

[0039] Switch elements Q9 and Q12 are connected between wires 111 and 112 by wire 1153. More specifically, the collector terminal of switch element Q9 is connected to wire 111 through wire 1152. The emitter terminal of switch element Q9 and the collector terminal of switch element Q12 are connected to each other. The emitter terminal of switch element Q12 is connected to wire 112 through wire 1152.

[0040] Wiring 1133 is connected to the portion of wiring 114 between capacitors C1 and C4. The connection point between wiring 1133 and wiring 114 is connection node ND51. Wiring 1133 is connected to AC terminal OUT3 through filter circuit 12. Wiring 1133 is connected to the portion of wiring 1153 between switch elements Q9 and Q12. This connection point is connection node ND52.

[0041] Switch elements Q10 and Q11 are connected between connection node ND51 and connection node ND52. More specifically, the collector terminal of switch element Q10 is connected to connection node ND51. The emitter terminal of switch element Q10 and the emitter terminal of switch element Q11 are connected to each other. The collector terminal of switch element Q11 is connected to connection node ND52. As a result, switch elements Q10 and Q11 are connected in a state where their switch polarities are reversed (the polarities of their respective parasitic diodes are reversed).

[0042] With this configuration, the inverter circuit 11 connects multiple switch elements Q1-Q12 in a predetermined connection pattern and comprises capacitors C1 and C4 on the DC input side. With this configuration, in the inverter circuit 11, connection nodes ND31, ND41, ND51, and ND80 become a reference potential which is the intermediate potential between the potential of the first DC terminal PV+ and the potential of the second DC terminal PV-.

[0043] (Specific connection configuration of filter circuit 12) Inductors Lf11 and Lf12 are connected in series between the connection node ND32 and the AC terminal OUT1 of the inverter circuit 11. Inductor Lf11 is connected to connection node ND32, and inductor Lf12 is connected to the AC terminal OUT1.

[0044] A capacitor Cf1 is connected to the portion between inductors Lf11 and Lf12 in wiring 1131 using wiring 121.

[0045] Inductors Lf21 and Lf22 are connected in series between the connection node ND42 and the AC terminal OUT2 of the inverter circuit 11. Inductor Lf21 is connected to connection node ND42, and inductor Lf22 is connected to the AC terminal OUT2.

[0046] A capacitor Cf2 is connected to the portion between inductors Lf21 and Lf22 in wiring 1132 using wiring 122.

[0047] Inductors Lf31 and Lf32 are connected in series between the connection node ND52 and the AC terminal OUT3 of the inverter circuit 11. Inductor Lf31 is connected to connection node ND52, and inductor Lf32 is connected to the AC terminal OUT3.

[0048] A capacitor Cf3 is connected to the portion between inductors Lf31 and Lf32 in wiring 1133 using wiring 123.

[0049] Capacitors Cf1, Cf2, and Cf3 are connected to each other. This connection point is connection node ND70.

[0050] With this configuration, the filter circuit 12 forms a low-pass filter circuit by combining three sets of T-type LC filters.

[0051] Connection node ND70 is connected via wiring 130 to the portion of wiring 114 between capacitors C1 and C4. The connection point between wiring 114 and wiring 130 is connection node ND80.

[0052] (Control of the inverter control unit 19) When performing normal inverter control, the inverter control unit 19 controls the on / off state of multiple switch elements Q1-Q12 in a predetermined pattern. As a result, the inverter circuit 11 converts the DC power input from the DC terminal pair (first DC terminal PV+ and second DC terminal PV-) into AC power of a predetermined frequency and outputs it from the AC terminal pair (AC terminals OUT1, OUT2, and OUT3).

[0053] Furthermore, when the inverter control unit 19 detects a DC power interruption, it performs the following discharge control.

[0054] Figure 3 is a flowchart showing an example of a discharge method for an inverter circuit according to the first embodiment of the present invention. Figure 4 is a table showing an example of state transitions of a switch element in an inverter circuit according to the first embodiment of the present invention.

[0055] (A) When the inverter control unit 19 receives a rapid shutdown operation (S10), it controls all the switch elements Q1-Q12 of the inverter circuit 11 to be turned off (open). This prevents unwanted power from being supplied to the load in the event of an abnormality.

[0056] (B) The inverter control unit 19 controls the discharge of capacitor C1 and capacitor Cf1 (S11). Figure 5 is an equivalent circuit diagram of the inverter circuit according to the first embodiment of the present invention when the discharge of capacitor C1 and capacitor Cf1 is controlled.

[0057] As shown in Figures 4 and 5, the inverter control unit 19 controls switch elements Q1 and Q2 to be ON (conductive control) and controls the other switch elements (multiple switch elements Q3-Q12) to be OFF.

[0058] As a result, as shown in Figure 5, the inverter circuit 11 is configured with a circuit DSL1A in which the capacitor C1 and the parasitic diode of the switch element Q3 are connected in parallel. Circuit DSL1A corresponds to the "first circuit" of the present invention.

[0059] In circuit DSL1A, the high-potential terminal of capacitor C1 is connected to the cathode terminal of the parasitic diode of switch element Q3 via wiring 114, connection node ND11, wiring 111, connection node ND12, wiring 1151 to which the conducting switch element Q1 is connected, and connection node ND32. The anode terminal of the parasitic diode of switch element Q3 is connected to the low-potential terminal of capacitor C1 via wiring 1131 to which the conducting switch element Q2 is connected, connection node ND31, and wiring 114.

[0060] In other words, in circuit DSL1A, the high-potential terminal of capacitor C1 is connected to the cathode terminal of the parasitic diode of switch element Q3. In circuit DSL1A, the low-potential terminal of capacitor C1 is connected to the anode terminal of the parasitic diode of switch element Q3.

[0061] With the configuration of circuit DSL1A, the voltage across capacitor C1 is clamped by the reverse voltage across the parasitic diode of switch element Q3. That is, capacitor C1 discharges its stored charge until the voltage across it becomes the reverse voltage across the parasitic diode of switch element Q3. The charge discharged from capacitor C1 is consumed, for example, by the wiring resistance of circuit DSL1A.

[0062] This allows the inverter device 10 to discharge capacitor C1 more reliably. Furthermore, compared to a discharge method that utilizes both the forward and reverse voltages of the switching element, the inverter device 10 can clamp the voltage across capacitor C1 with a voltage lower by the forward voltage. Therefore, the inverter device 10 can discharge more of the charge stored in capacitor C1. As a result, the inverter device 10 can increase the safety against damage to capacitor C1.

[0063] Furthermore, as shown in Figure 5, the inverter circuit 11 forms a circuit DSLf1A in which the parasitic diode of the switch element Q3, the inductor Lf11, and the capacitor Cf1 are connected in sequence.

[0064] In circuit DSLf1A, the high-potential terminal of capacitor Cf1 is connected to inductor Lf11 via wiring 121, connection node ND61, and wiring 1131. Inductor Lf11 is connected to the cathode terminal of the parasitic diode of switch element Q3 via wiring 1131. The anode terminal of the parasitic diode of switch element Q3 is connected to the low-potential terminal of capacitor Cf1 via wiring 1131, connection node ND80, wiring 130, connection node ND70, and wiring 121, to which the conducting switch element Q2 is connected.

[0065] With the configuration of circuit DSLf1A, capacitor Cf1 discharges its stored charge until the voltage across it reaches the reverse voltage of the parasitic diode of switch element Q3. The charge discharged from capacitor Cf1 is then consumed by, for example, the inductor Lf11 and wiring resistance of circuit DSLf1A.

[0066] As a result, the inverter device 10 can discharge capacitor Cf1 in the same way as capacitor C1.

[0067] In this case, the duration of the ON control of switch elements Q1 and Q2 is set based on at least the discharge time constant of capacitor C1. That is, the duration of the ON control is set to be longer than the time it takes for the charge remaining in capacitor C1 to discharge to a charge equivalent to the reverse voltage due to the parasitic diode. This allows the inverter device 10 to discharge the charge of capacitor C1 more reliably. It is even more preferable to set this ON control duration taking into consideration the discharge time of the charge of capacitor Cf1.

[0068] After this control, the inverter control unit 19 turns off all switching elements Q1-Q12 (the first interval in Figure 4).

[0069] (C) The inverter control unit 19 controls the discharge of capacitor C4 and capacitor Cf1 (S11). Figure 6 is an equivalent circuit diagram of the inverter circuit according to the first embodiment of the present invention when the discharge of capacitor C4 and capacitor Cf1 is controlled.

[0070] As shown in Figures 4 and 6, the inverter control unit 19 controls switch elements Q3 and Q4 to be ON (conductive control) and controls the other switch elements (multiple switch elements Q1, Q2, Q5-Q12) to be OFF.

[0071] As a result, as shown in Figure 6, the inverter circuit 11 forms a circuit DSL4A in which the capacitor C4 and the parasitic diode of the switch element Q2 are connected in parallel. Circuit DSL4A corresponds to the "second circuit" of the present invention.

[0072] In circuit DSL4A, the high-potential terminal of capacitor C4 is connected to the cathode terminal of the parasitic diode of switch element Q2 via wiring 114, connection node ND31, and wiring 1131. The anode terminal of the parasitic diode of switch element Q2 is connected to the low-potential terminal of capacitor C4 via wiring 1131, connection node ND32, to which the conducting switch element Q3 is connected, wiring 1151, connection node ND22, wiring 112, connection node ND21, and wiring 114, to which the conducting switch element Q4 is connected.

[0073] In other words, in circuit DSL4A, the high-potential terminal of capacitor C4 is connected to the cathode terminal of the parasitic diode of switch element Q2. In circuit DSL4A, the low-potential terminal of capacitor C4 is connected to the anode terminal of the parasitic diode of switch element Q2.

[0074] With the configuration of circuit DSL4A, the voltage across capacitor C4 is clamped by the reverse voltage across the parasitic diode of switch element Q2. That is, capacitor C4 discharges its stored charge until the voltage across it becomes the reverse voltage across the parasitic diode of switch element Q2. The charge discharged from capacitor C4 is consumed, for example, by the wiring resistance of circuit DSL4A.

[0075] This allows the inverter device 10 to discharge capacitor C4 more reliably. Furthermore, compared to a discharge method that utilizes both the forward and reverse voltages of the switching element, the inverter device 10 can clamp the voltage across capacitor C4 with a voltage lower by the forward voltage. Therefore, the inverter device 10 can discharge more of the charge stored in capacitor C4. As a result, the inverter device 10 can increase the safety against damage to capacitor C4.

[0076] Furthermore, as shown in Figure 5, the inverter circuit 11 forms a circuit DSLf1B in which the parasitic diode of the switch element Q2, the inductor Lf11, and the capacitor Cf1 are connected in sequence. With the formation of circuit DSLf1B, the capacitor Cf1 discharges the charge it had accumulated until the voltage across its terminals becomes the reverse voltage of the parasitic diode of the switch element Q2. The charge discharged from capacitor Cf1 is consumed, for example, by the inductor Lf11 and wiring resistance of circuit DSLf1A.

[0077] As a result, the inverter device 10 can discharge capacitor Cf1, just like capacitor C4.

[0078] In this case, the duration of the ON control of switch elements Q3 and Q4 is set based on at least the discharge time constant of capacitor C4. That is, the duration of the ON control is set to be longer than the time it takes for the charge remaining in capacitor C4 to discharge to a charge equivalent to the reverse voltage due to the parasitic diode. This allows the inverter device 10 to discharge the charge of capacitor C4 more reliably. It is even more preferable to set this ON control duration taking into account the discharge time of the charge of capacitor Cf1.

[0079] After this control, the inverter control unit 19 turns off all switch elements Q1-Q12 (second interval in Figure 4).

[0080] (D) The inverter control unit 19 controls the discharge of capacitors Cf2 and Cf3 (S13). In this case, the inverter control unit 19 controls the discharge of capacitor Cf2 and capacitor Cf3 individually and sequentially.

[0081] Figure 7 is an equivalent circuit diagram of the inverter circuit according to the first embodiment of the present invention when the discharge of capacitor Cf2 is controlled. Figure 8 is an equivalent circuit diagram of the inverter circuit according to the first embodiment of the present invention when the discharge of capacitor Cf3 is controlled.

[0082] As shown in Figures 4 and 7, the inverter control unit 19 controls switch element Q6 to be ON (conductive control) and controls the other switch elements (multiple switch elements Q1-Q5, Q7-Q12) to be OFF.

[0083] As a result, as shown in Figure 7, the inverter circuit 11 forms a circuit DSLf2A in which the parasitic diode of the switch element Q7, the inductor Lf21, and the capacitor Cf2 are connected in sequence.

[0084] In circuit DSLf2A, the high-potential terminal of capacitor Cf2 is connected to inductor Lf21 via wiring 122, connection node ND62, and wiring 1132. Inductor Lf21 is connected to the cathode terminal of the parasitic diode of switch element Q7 via wiring 1132. The anode terminal of the parasitic diode of switch element Q7 is connected to the low-potential terminal of capacitor Cf2 via wiring 1132, connection node ND80, wiring 130, connection node ND70, and wiring 122, to which the conducting switch element Q6 is connected.

[0085] With the configuration of circuit DSLf2A, capacitor Cf2 discharges its stored charge until the voltage across it reaches the reverse voltage of the parasitic diode of switch element Q7. The charge discharged from capacitor Cf2 is then consumed by, for example, the inductor Lf21 and wiring resistance of circuit DSLf2A.

[0086] This allows the inverter device 10 to discharge the capacitor Cf2.

[0087] In this case, the duration of the ON control of the switch element Q7 is set based on at least the discharge time constant of the capacitor Cf2. That is, the duration of the ON control is set to be longer than the time it takes for the charge remaining in the capacitor Cf2 to discharge to a charge equivalent to the reverse voltage by the parasitic diode. This allows the inverter device 10 to more reliably discharge the charge from the capacitor Cf2.

[0088] After this control, the inverter control unit 19 turns off all switching elements Q1-Q12 (the third interval in Figure 4).

[0089] As shown in Figures 4 and 8, the inverter control unit 19 controls the switch element Q10 to be ON (conductive control) and controls the other switch elements (multiple switch elements Q1-Q9, Q11, Q12) to be OFF.

[0090] As a result, as shown in Figure 8, the inverter circuit 11 forms a circuit DSLf3A in which the parasitic diode of the switch element Q11, the inductor Lf31, and the capacitor Cf3 are connected in sequence.

[0091] In circuit DSLf3A, the high-potential terminal of capacitor Cf3 is connected to inductor Lf31 via wiring 123, connection node ND63, and wiring 1133. Inductor Lf31 is connected to the cathode terminal of the parasitic diode of switch element Q11 via wiring 1133. The anode terminal of the parasitic diode of switch element Q11 is connected to the low-potential terminal of capacitor Cf3 via wiring 1133, connection node ND80, wiring 130, connection node ND70, and wiring 123, to which the conducting switch element Q10 is connected.

[0092] With the configuration of circuit DSLf3A, capacitor Cf3 discharges its stored charge until the voltage across it becomes the reverse voltage of the parasitic diode of switch element Q11. The charge discharged from capacitor Cf3 is then consumed by, for example, the inductor Lf31 and wiring resistance of circuit DSLf3A.

[0093] This allows the inverter device 10 to discharge the capacitor Cf3.

[0094] In this case, the duration of the ON control of the switch element Q11 is set based on at least the discharge time constant of the capacitor Cf3. That is, the duration of the ON control is set to be longer than the time it takes for the charge remaining in the capacitor Cf3 to discharge to a charge equivalent to the reverse voltage by the parasitic diode. This allows the inverter device 10 to more reliably discharge the charge from the capacitor Cf3.

[0095] Although the intervals described above can be omitted, providing them allows the inverter device 10 to suppress the temporal overlap of multiple different discharge control circuit configurations. This enables the inverter device 10 to discharge the charge of each capacitor more reliably and appropriately.

[0096] [Second Embodiment] An inverter device and photovoltaic power generation system according to a second embodiment of the present invention will be described with reference to the figures. The circuit configuration of the inverter device and photovoltaic power generation system according to the second embodiment is the same as that of the inverter device and photovoltaic power generation system according to the first embodiment, and therefore will not be described. The inverter device according to the second embodiment differs from the inverter device according to the first embodiment in the control performed by the inverter control unit 19.

[0097] Figure 9 is a flowchart showing an example of a discharge method for an inverter circuit according to a second embodiment of the present invention. Figure 10 is a table showing an example of state transitions of a switch element in an inverter circuit according to a second embodiment of the present invention.

[0098] As shown in Figures 9 and 10, the inverter control unit 19 according to the second embodiment further performs control to discharge only the capacitor Cf1 of the filter circuit 12.

[0099] As shown in Figure 9, the inverter control unit 19 accepts a rapid shutdown operation (S10) and controls all switch elements Q1-Q12 of the inverter circuit 11 to be turned off (open). The inverter control unit 19 controls the discharge of capacitors C1 and Cf1 (S11). The inverter control unit 19 controls the discharge of capacitors C4 and Cf1 (S12).

[0100] The inverter control unit 19 sequentially controls the discharge of capacitors Cf1, Cf2, and Cf3 (S13A).

[0101] Figure 11 is an equivalent circuit diagram of the inverter circuit according to the second embodiment of the present invention when the discharge of capacitor Cf1 is controlled.

[0102] As shown in Figures 10 and 11, the inverter control unit 19 controls switch element Q2 to be ON (conductive control) and controls the other switch elements (multiple switch elements Q1, Q3-Q12) to be OFF.

[0103] As a result, as shown in Figure 11, the inverter circuit 11 forms a circuit DSLf1A in which the parasitic diode of the switch element Q3, the inductor Lf11, and the capacitor Cf1 are connected in that order.

[0104] In circuit DSLf1A, the high-potential terminal of capacitor Cf1 is connected to inductor Lf11 via wiring 121, connection node ND61, and wiring 1131. Inductor Lf11 is connected to the cathode terminal of the parasitic diode of switch element Q3 via wiring 1131. The anode terminal of the parasitic diode of switch element Q3 is connected to the low-potential terminal of capacitor Cf1 via wiring 1131, connection node ND80, wiring 130, connection node ND70, and wiring 121, to which the conducting switch element Q2 is connected.

[0105] With the configuration of circuit DSLf1A, capacitor Cf1 discharges its stored charge until the voltage across it reaches the reverse voltage of the parasitic diode of switch element Q3. The charge discharged from capacitor Cf1 is then consumed by, for example, the inductor Lf11 and wiring resistance of circuit DSLf1A.

[0106] This allows the inverter device 10 to discharge the capacitor Cf1.

[0107] In this case, the duration of the ON control of the switch element Q3 is set based on at least the discharge time constant of the capacitor Cf1. Here, capacitor Cf1 is already discharge-controlled together with capacitors C1 and C4. Therefore, the duration of the ON control of the switch element Q3 can be set by subtracting the duration of the ON control for capacitors C1 and C4. This allows the inverter device 10 to shorten the time during which capacitor Cf1 is discharged independently.

[0108] In this embodiment, the inverter control unit 19 can also sequentially perform discharge control of capacitor Cf1, then capacitor C1, and then capacitor C4, as shown below.

[0109] Figure 12 is a flowchart showing another example of a discharge method for an inverter circuit according to a second embodiment of the present invention. Figure 13 is a table showing another example of a state transition of a switch element in an inverter circuit according to a second embodiment of the present invention.

[0110] As shown in Figures 12 and 13, the inverter control unit 19 accepts a rapid shutdown operation (S10) and controls all switch elements Q1-Q12 of the inverter circuit 11 to be turned off (open). The inverter control unit 19 also controls the discharge of capacitor Cf1 (S21). The discharge control of capacitor Cf1 is performed by the circuit configuration shown in Figure 11, as described above.

[0111] The inverter control unit 19 controls the discharge of the capacitor C1 (S22).

[0112] Figure 14 is an equivalent circuit diagram of the inverter circuit according to the second embodiment of the present invention when the discharge of capacitor C1 is controlled.

[0113] As shown in Figures 13 and 14, the inverter control unit 19 controls switch elements Q1 and Q2 to be ON (conductive control) and controls the other switch elements (multiple switch elements Q3-Q12) to be OFF.

[0114] As a result, as shown in Figure 14, the inverter circuit 11 is configured with a circuit DSL1A in which the capacitor C1 and the parasitic diode of the switching element Q3 are connected in parallel.

[0115] In circuit DSL1A, the high-potential terminal of capacitor C1 is connected to the cathode terminal of the parasitic diode of switch element Q3 via wiring 114, connection node ND11, wiring 111, connection node ND12, wiring 1151 to which the conducting switch element Q1 is connected, and connection node ND32. The anode terminal of the parasitic diode of switch element Q3 is connected to the low-potential terminal of capacitor C1 via wiring 1131 to which the conducting switch element Q2 is connected, connection node ND31, and wiring 114.

[0116] In other words, in circuit DSL1A, the high-potential terminal of capacitor C1 is connected to the cathode terminal of the parasitic diode of switch element Q3. In circuit DSL1A, the low-potential terminal of capacitor C1 is connected to the anode terminal of the parasitic diode of switch element Q3.

[0117] With the configuration of circuit DSL1A, the voltage across capacitor C1 is clamped by the reverse voltage across the parasitic diode of switch element Q3. That is, capacitor C1 discharges its stored charge until the voltage across it becomes the reverse voltage across the parasitic diode of switch element Q3. The charge discharged from capacitor C1 is consumed, for example, by the wiring resistance of circuit DSL1A.

[0118] This allows the inverter device 10 to discharge the capacitor C1 more reliably.

[0119] This circuit configuration is similar to the discharge control of capacitors C1 and Cf1 in the first embodiment, but capacitor Cf1 has already been discharged and its terminal voltage is the same as the reverse voltage due to the parasitic diode of the switch element Q3. Therefore, this control ensures that capacitor C1 is discharged more reliably.

[0120] The inverter control unit 19 controls the discharge of the capacitor C4 (S23).

[0121] Figure 15 is an equivalent circuit diagram of the inverter circuit according to the second embodiment of the present invention when the discharge of capacitor C4 is controlled.

[0122] As shown in Figures 13 and 15, the inverter control unit 19 controls switch elements Q3 and Q4 to be ON (conductive control) and controls the other switch elements (multiple switch elements Q1, Q2, Q5-Q12) to be OFF.

[0123] As a result, as shown in Figure 15, the inverter circuit 11 is configured with a circuit DSL4A in which the capacitor C4 and the parasitic diode of the switching element Q2 are connected in parallel.

[0124] In circuit DSL4A, the high-potential terminal of capacitor C4 is connected to the cathode terminal of the parasitic diode of switch element Q2 via wiring 114, connection node ND31, and wiring 1131. The anode terminal of the parasitic diode of switch element Q2 is connected to the low-potential terminal of capacitor C4 via wiring 1131, connection node ND32, to which the conducting switch element Q3 is connected, wiring 1151, connection node ND22, wiring 112, connection node ND21, and wiring 114, to which the conducting switch element Q4 is connected.

[0125] In other words, in circuit DSL4A, the high-potential terminal of capacitor C4 is connected to the cathode terminal of the parasitic diode of switch element Q2. In circuit DSL4A, the low-potential terminal of capacitor C4 is connected to the anode terminal of the parasitic diode of switch element Q2.

[0126] With the configuration of circuit DSL4A, the voltage across capacitor C4 is clamped by the reverse voltage across the parasitic diode of switch element Q2. That is, capacitor C4 discharges its stored charge until the voltage across it becomes the reverse voltage across the parasitic diode of switch element Q2. The charge discharged from capacitor C4 is consumed, for example, by the wiring resistance of circuit DSL4A.

[0127] This allows the inverter device 10 to discharge the capacitor C4 more reliably.

[0128] This circuit configuration is similar to the discharge control of capacitors C4 and Cf1 in the first embodiment, but capacitor Cf1 has already been discharged and its terminal voltage is the same as the reverse voltage due to the parasitic diode of the switching element Q2. Therefore, in this control, capacitor C4 is discharged more reliably.

[0129] Next, the inverter control unit 19 sequentially controls the discharge of capacitor Cf2 and capacitor Cf3 (S23).

[0130] [Third Embodiment] An inverter device and photovoltaic power generation system according to a third embodiment of the present invention will be described with reference to the figures. The circuit configuration of the inverter device and photovoltaic power generation system according to the third embodiment is the same as that of the inverter device and photovoltaic power generation system according to the first embodiment, and therefore will not be described. The inverter device according to the third embodiment differs from the inverter device according to the first embodiment in the control performed by the inverter control unit 19.

[0131] Figure 16 is a flowchart showing an example of a discharge method for an inverter circuit according to the third embodiment of the present invention. Figure 17 is a table showing an example of the state transitions of a switch element in an inverter circuit according to the third embodiment of the present invention.

[0132] As shown in Figures 16 and 17, the inverter device according to the third embodiment discharges capacitors C1, C4, Cf1, Cf2, and Cf3 using a different combination of switches than the inverter device according to the first embodiment. Note that the explanation of the parts in the third embodiment that perform the same control as in the above-described embodiments will be omitted as appropriate.

[0133] As shown in Figure 16, the inverter control unit 19 accepts a rapid shutdown operation (S10) and controls all switch elements Q1-Q12 of the inverter circuit 11 to be turned off (open).

[0134] The inverter control unit 19 controls the discharge of capacitors C1 and Cf2 (S31). Figure 18 is an equivalent circuit diagram of the inverter circuit according to the third embodiment of the present invention during the discharge control of capacitors C1 and Cf2.

[0135] As shown in Figures 17 and 18, the inverter control unit 19 controls switch elements Q5 and Q6 to be ON (conductive control) and controls the other switch elements (multiple switch elements Q1-Q4, Q7-Q12) to be OFF.

[0136] As a result, as shown in Figure 18, the inverter circuit 11 is configured with a circuit DSL1B in which the parasitic diode of the capacitor C1 and the switch element Q7 are connected in parallel. Circuit DSL1B corresponds to the "first circuit" of the present invention.

[0137] In circuit DSL1B, the high-potential terminal of capacitor C1 is connected to the cathode terminal of the parasitic diode of switch element Q7 via wiring 114, connection node ND11, wiring 111, connection node ND13, wiring 1152 to which the conducting switch element Q5 is connected, and connection node ND42. The anode terminal of the parasitic diode of switch element Q7 is connected to the low-potential terminal of capacitor C1 via wiring 1132 to which the conducting switch element Q6 is connected, connection node ND41, and wiring 114.

[0138] In other words, in circuit DSL1B, the high-potential terminal of capacitor C1 is connected to the cathode terminal of the parasitic diode of switch element Q7. In circuit DSL1B, the low-potential terminal of capacitor C1 is connected to the anode terminal of the parasitic diode of switch element Q7.

[0139] With the configuration of circuit DSL1B, the voltage across capacitor C1 is clamped by the reverse voltage across the parasitic diode of switch element Q7. That is, capacitor C1 discharges its stored charge until the voltage across it becomes the reverse voltage across the parasitic diode of switch element Q7. The charge discharged from capacitor C1 is consumed, for example, by the wiring resistance of circuit DSL1B.

[0140] This allows the inverter device 10 to discharge the capacitor C1 more reliably.

[0141] Furthermore, as shown in Figure 18, the inverter circuit 11 forms a circuit DSLf2A in which the parasitic diode of the switch element Q7, the inductor Lf21, and the capacitor Cf2 are connected in sequence.

[0142] In circuit DSLf2A, the high-potential terminal of capacitor Cf2 is connected to inductor Lf21 via wiring 122, connection node ND62, and wiring 1132. Inductor Lf21 is connected to the cathode terminal of the parasitic diode of switch element Q7 via wiring 1132. The anode terminal of the parasitic diode of switch element Q7 is connected to the low-potential terminal of capacitor Cf2 via wiring 1132, connection node ND80, wiring 130, connection node ND70, and wiring 122, to which the conducting switch element Q6 is connected.

[0143] With the configuration of circuit DSLf2A, capacitor Cf2 discharges its stored charge until the voltage across it reaches the reverse voltage of the parasitic diode of switch element Q7. The charge discharged from capacitor Cf2 is then consumed by, for example, the inductor Lf21 and wiring resistance of circuit DSLf2A.

[0144] As a result, the inverter device 10 can discharge capacitor Cf2 in the same way as capacitor C1.

[0145] The inverter control unit 19 controls the discharge of capacitors C4 and Cf2 (S32). Figure 19 is an equivalent circuit diagram of the inverter circuit according to the third embodiment of the present invention during the discharge control of capacitors C4 and Cf2.

[0146] As shown in Figures 17 and 19, the inverter control unit 19 controls switch elements Q7 and Q8 to be ON (conductive control) and controls the other switch elements (multiple switch elements Q1-Q6, Q9-Q12) to be OFF.

[0147] As a result, as shown in Figure 19, the inverter circuit 11 is configured with a circuit DSL4B in which the parasitic diode of the capacitor C4 and the switching element Q6 are connected in parallel. Circuit DSL4B corresponds to the "second circuit" of the present invention.

[0148] In circuit DSL4B, the high-potential terminal of capacitor C4 is connected to the cathode terminal of the parasitic diode of switch element Q6 via wiring 114, connection node ND41, and wiring 1132. The anode terminal of the parasitic diode of switch element Q6 is connected to the low-potential terminal of capacitor C4 via wiring 1132, connection node ND42, to which the conducting switch element Q7 is connected, wiring 1152, connection node ND23, wiring 112, connection node ND21, and wiring 114, to which the conducting switch element Q8 is connected.

[0149] In other words, in circuit DSL4B, the high-potential terminal of capacitor C4 is connected to the cathode terminal of the parasitic diode of switch element Q6. In circuit DSL4B, the low-potential terminal of capacitor C4 is connected to the anode terminal of the parasitic diode of switch element Q6.

[0150] With the configuration of circuit DSL4B, the voltage across capacitor C4 is clamped by the reverse voltage across the parasitic diode of switch element Q6. That is, capacitor C4 discharges its stored charge until the voltage across it becomes the reverse voltage across the parasitic diode of switch element Q6. The charge discharged from capacitor C4 is consumed, for example, by the wiring resistance of circuit DSL4B.

[0151] This allows the inverter device 10 to discharge the capacitor C4 more reliably.

[0152] Furthermore, as shown in Figure 19, the inverter circuit 11 forms a circuit DSLf2B in which the parasitic diode of the switch element Q6, the inductor Lf21, and the capacitor Cf2 are connected in sequence. With the formation of circuit DSLf2B, the capacitor Cf2 discharges the charge it had accumulated until the voltage across its terminals becomes the reverse voltage of the parasitic diode of the switch element Q6. The charge discharged from capacitor Cf2 is consumed, for example, by the inductor Lf21 and wiring resistance of circuit DSLf2B.

[0153] As a result, the inverter device 10 can discharge capacitor Cf2, just like capacitor C4.

[0154] Subsequently, the inverter control unit 19 sequentially controls the discharge of capacitor Cf1 and capacitor Cf3 (S33).

[0155] [Fourth Embodiment] An inverter device and photovoltaic power generation system according to a fourth embodiment of the present invention will be described with reference to the figures. The circuit configuration of the inverter device and photovoltaic power generation system according to the fourth embodiment is the same as that of the inverter device and photovoltaic power generation system according to the first embodiment, and therefore will not be described. The inverter device according to the fourth embodiment differs from the inverter device according to the first embodiment in the control performed by the inverter control unit 19.

[0156] Figure 20 is a flowchart showing an example of a discharge method for an inverter circuit according to the fourth embodiment of the present invention. Figure 21 is a table showing an example of state transitions of a switch element in an inverter circuit according to the fourth embodiment of the present invention.

[0157] As shown in Figures 20 and 21, the inverter device according to the fourth embodiment discharges capacitors C1, C4, Cf1, Cf2, and Cf3 using a different combination of switches than the inverter device according to the first embodiment. Note that the explanation of the control performed in the fourth embodiment, similar to that in the above-described embodiments, will be omitted as appropriate.

[0158] As shown in Figure 20, the inverter control unit 19 accepts a rapid shutdown operation (S10) and controls all switch elements Q1-Q12 of the inverter circuit 11 to be turned off (open).

[0159] The inverter control unit 19 controls the discharge of capacitors C1 and Cf3 (S41). Figure 22 is an equivalent circuit diagram of the inverter circuit according to the fourth embodiment of the present invention when the discharge of capacitors C1 and Cf3 is controlled.

[0160] As shown in Figures 21 and 22, the inverter control unit 19 controls switch elements Q9 and Q10 to be ON (conductive control) and controls the other switch elements (multiple switch elements Q1-Q8, Q11, Q12) to be OFF.

[0161] As a result, as shown in Figure 22, the inverter circuit 11 is configured with a circuit DSL1C in which the parasitic diode of the capacitor C1 and the switch element Q11 are connected in parallel. Circuit DSL1C corresponds to the "first circuit" of the present invention.

[0162] In circuit DSL1C, the high-potential terminal of capacitor C1 is connected to the cathode terminal of the parasitic diode of switch element Q11 via wiring 114, connection node ND11, wiring 111, wiring 1153 to which the conducting switch element Q9 is connected, and connection node ND52. The anode terminal of the parasitic diode of switch element Q11 is connected to the low-potential terminal of capacitor C1 via wiring 1133 to which the conducting switch element Q10 is connected, connection node ND51, and wiring 114.

[0163] In other words, in circuit DSL1C, the high-potential terminal of capacitor C1 is connected to the cathode terminal of the parasitic diode of switch element Q11. In circuit DSL1C, the low-potential terminal of capacitor C1 is connected to the anode terminal of the parasitic diode of switch element Q11.

[0164] With the configuration of circuit DSL1C, the voltage across capacitor C1 is clamped by the reverse voltage across the parasitic diode of switch element Q11. That is, capacitor C1 discharges its stored charge until the voltage across it becomes the reverse voltage across the parasitic diode of switch element Q11. The charge discharged from capacitor C1 is consumed, for example, by the wiring resistance of circuit DSL1C.

[0165] This allows the inverter device 10 to discharge the capacitor C1 more reliably.

[0166] Furthermore, as shown in Figure 22, the inverter circuit 11 forms a circuit DSLf3A in which the parasitic diode of the switch element Q11, the inductor Lf31, and the capacitor Cf3 are connected in sequence.

[0167] In circuit DSLf3A, the high-potential terminal of capacitor Cf3 is connected to inductor Lf31 via wiring 123, connection node ND63, and wiring 1133. Inductor Lf31 is connected to the cathode terminal of the parasitic diode of switch element Q11 via wiring 1133. The anode terminal of the parasitic diode of switch element Q11 is connected to the low-potential terminal of capacitor Cf3 via wiring 1133, connection node ND80, wiring 130, connection node ND70, and wiring 123, to which the conducting switch element Q10 is connected.

[0168] With the configuration of circuit DSLf3A, capacitor Cf3 discharges its stored charge until the voltage across it becomes the reverse voltage of the parasitic diode of switch element Q11. The charge discharged from capacitor Cf3 is then consumed by, for example, the inductor Lf31 and wiring resistance of circuit DSLf3A.

[0169] As a result, the inverter device 10 can discharge capacitor Cf3 in the same way as capacitor C1.

[0170] The inverter control unit 19 controls the discharge of capacitors C4 and Cf3 (S42). Figure 23 is an equivalent circuit diagram of the inverter circuit according to the fourth embodiment of the present invention during the discharge control of capacitors C4 and Cf3.

[0171] As shown in Figures 21 and 23, the inverter control unit 19 controls switch elements Q11 and Q12 to be ON (conductive control) and controls the other switch elements (multiple switch elements Q1-Q10) to be OFF.

[0172] As a result, as shown in Figure 23, the inverter circuit 11 is configured with a circuit DSL4C in which the parasitic diode of the capacitor C4 and the switch element Q10 are connected in parallel. Circuit DSL4C corresponds to the "second circuit" of the present invention.

[0173] In circuit DSL4C, the high-potential terminal of capacitor C4 is connected to the cathode terminal of the parasitic diode of switch element Q10 via wiring 114, connection node ND51, and wiring 1133. The anode terminal of the parasitic diode of switch element Q10 is connected to the low-potential terminal of capacitor C4 via wiring 1133, connection node ND52, to which the conducting switch element Q11 is connected, and wiring 1153, wiring 112, connection node ND21, and wiring 114 to which the conducting switch element Q12 is connected.

[0174] In other words, in circuit DSL4C, the high-potential terminal of capacitor C4 is connected to the cathode terminal of the parasitic diode of switch element Q10. In circuit DSL4C, the low-potential terminal of capacitor C4 is connected to the anode terminal of the parasitic diode of switch element Q10.

[0175] With the configuration of circuit DSL4C, the voltage across capacitor C4 is clamped by the reverse voltage across the parasitic diode of switch element Q10. That is, capacitor C4 discharges its stored charge until the voltage across it becomes the reverse voltage across the parasitic diode of switch element Q10. The charge discharged from capacitor C4 is consumed, for example, by the wiring resistance of circuit DSL4C.

[0176] This allows the inverter device 10 to discharge the capacitor C4 more reliably.

[0177] Furthermore, as shown in Figure 23, the inverter circuit 11 forms a circuit DSLf3B in which the parasitic diode of the switch element Q10, the inductor Lf31, and the capacitor Cf3 are connected in sequence. With the formation of circuit DSLf3B, the capacitor Cf3 discharges the charge it had accumulated until the voltage across its terminals becomes the reverse voltage of the parasitic diode of the switch element Q10. The charge discharged from the capacitor Cf3 is consumed, for example, by the inductor Lf31, wiring resistance, etc. of circuit DSLf3B.

[0178] As a result, the inverter device 10 can discharge capacitor Cf3, just like capacitor C4.

[0179] Subsequently, the inverter control unit 19 sequentially controls the discharge of capacitor Cf1 and capacitor Cf2 (S43).

[0180] [Fifth Embodiment] An inverter device and photovoltaic power generation system according to a fifth embodiment of the present invention will be described with reference to the figures. The circuit configuration of the inverter device and photovoltaic power generation system according to the fifth embodiment is the same as that of the inverter device and photovoltaic power generation system according to the first embodiment, and therefore will not be described. The inverter device according to the fifth embodiment differs from the inverter device according to the first embodiment in the control performed by the inverter control unit 19.

[0181] Figure 24 is a flowchart showing an example of a discharge method for an inverter circuit according to the fifth embodiment of the present invention. As shown in Figure 24, the fifth embodiment differs from the first embodiment in that it controls the discharge of capacitors C1, C4, Cf1, Cf2, and Cf3 by switching different combinations of switches in a time series. The combinations of on / off control of the switches in each discharge control are specifically shown in the embodiments described above, so the explanation will be omitted below as appropriate, except for content that needs to be added.

[0182] As shown in Figure 24, the inverter control unit 19 accepts a rapid shutdown operation (S10) and controls all switch elements Q1-Q12 of the inverter circuit 11 to be turned off (open).

[0183] The inverter control unit 19 controls the discharge of capacitors C1 and Cf1 (S51). The inverter control unit 19 controls the discharge of capacitors C1 and Cf1 using the on / off control of switch elements Q1-Q4. At this time, switch elements Q5-Q12 are turned off.

[0184] The inverter control unit 19 controls the discharge of capacitors C1 and Cf2 (S52). The inverter control unit 19 controls the discharge of capacitors C1 and Cf2 using the on / off control of switch elements Q5-Q8. At this time, switch elements Q1-Q4 and Q9-Q12 are turned off.

[0185] The inverter control unit 19 controls the discharge of capacitors C1 and Cf3 (S53). The inverter control unit 19 controls the discharge of capacitors C1 and Cf3 using the on / off control of switch elements Q9-Q12. At this time, switch elements Q1-Q8 are turned off.

[0186] The inverter control unit 19 controls the discharge of capacitors C4 and Cf1 (S54). The inverter control unit 19 controls the discharge of capacitors C4 and Cf1 using the on / off control of switch elements Q1-Q4. At this time, switch elements Q5-Q12 are turned off.

[0187] The inverter control unit 19 controls the discharge of capacitors C4 and Cf2 (S55). The inverter control unit 19 controls the discharge of capacitors C4 and Cf2 using the on / off control of switch elements Q5-Q8. At this time, switch elements Q1-Q4 and Q9-Q12 are turned off.

[0188] The inverter control unit 19 controls the discharge of capacitors C4 and Cf3 (S56). Specifically, the inverter control unit 19 controls the discharge of capacitors C4 and Cf3 using the on / off control of switch elements Q9-Q12. At this time, switch elements Q1-Q8 are turned off.

[0189] Through this control, the inverter device 10 can reliably discharge capacitors C1, C4, Cf1, Cf2, and Cf3. Furthermore, the inverter device 10 switches the discharge of each capacitor using multiple types of circuits with different configurations. This allows the inverter device 10 to suppress the degradation of multiple switching elements Q1-Q12 due to the discharge current of each capacitor.

[0190] The control sequence described above is just one example; the control sequence can be set as appropriate, as long as the control sequentially clamps the voltage across each capacitor using the reverse voltage from the parasitic diode of the switched element that has been turned off. In this case, capacitors C1 and C4 of the inverter circuit 11 may be discharged individually, and capacitors Cf1, Cf2, and Cf3 of the filter circuit 12 may be discharged individually, or the discharge of the capacitors of the inverter circuit 11 and the capacitors of the filter circuit 12 may be performed together. [Explanation of Symbols]

[0191] 1: Solar power generation system 10: Inverter device 11: Inverter Circuit 12: Filter Circuit 19: Inverter Control Unit 20: PV Control Unit 30: Shut-off switch 111, 112, 114, 121, 122, 123, 130, 1131, 1132, 1133, 1151, 1152, 1153: Wiring C1, C4, Cf1, Cf2, Cf3: Capacitors DSL1A, DSL1B, DSL1C, DSL4A, DSL4B, DSL4C, DSLf1A, DSLf1B, DSLf2A, DSLf2B, DSLf3A, DSLf3B: Circuit Lf11, Lf12, Lf21, Lf22, Lf31, Lf32: Inductors ND11, ND12, ND13, ND21, ND22, ND23, ND31, ND32, ND41, ND42, ND51, ND52, ND61, ND62, ND63, ND70, ND80: Connected nodes OUT1, OUT2, OUT3: AC terminal PV+: 1st DC terminal PV-: 2nd DC terminal Q1-Q12: Switching elements SP: Solar power panels

Claims

1. It includes an inverter circuit and an inverter control unit, The aforementioned inverter circuit A pair of DC terminals consisting of a first DC terminal and a second DC terminal, A pair of AC terminals consisting of multiple AC terminals, A first capacitor and a second capacitor connected in series between the first DC terminal and the second DC terminal, A plurality of switch elements are connected between the DC terminal pair and the AC terminal pair in a predetermined connection pattern, each being constructed using semiconductors and having a parasitic diode. Equipped with, The inverter control unit, When a disconnection of DC power input from the aforementioned DC terminal pair is detected, The multiple switch elements are controlled to be switched on and off, The voltage of the first capacitor is clamped by the reverse voltage of the parasitic diode of the switched element that is controlled to be off. The voltage of the second capacitor is clamped by the reverse voltage of the parasitic diode of the switched element that is controlled to be off. Inverter device.

2. The inverter control unit, The plurality of switch elements are controlled by on / off control. A first circuit is formed in which a first switch element and a first capacitor that are controlled to be in the off position are connected in parallel, and the cathode of the parasitic diode of the first switch element that is controlled to be in the off position is connected to the high-potential terminal of the first capacitor. A second circuit is formed in which a second switch element that is controlled to be off and the second capacitor are connected in parallel, and the cathode terminal of the parasitic diode of the second switch element that is controlled to be off is connected to the high-potential side terminal of the second capacitor. The inverter device according to claim 1.

3. The aforementioned inverter circuit The first wiring connected to the first DC terminal, The second wiring connected to the second DC terminal, A third wiring is provided between the first DC terminal and the second DC terminal, connecting the first capacitor and the second capacitor in series. A fourth wiring connected to the nodes of the first capacitor and the second capacitor, Equipped with, The aforementioned plurality of switch elements are A first switch element connected between the first wiring and the fourth wiring, A second switch element and a third switch element are connected to the fourth wiring such that their switch polarities are reversed, A fourth switch element connected between the second wiring and the fourth wiring, Equipped with, The inverter control unit configures the first circuit or the second circuit by controlling the on / off state of the first switch element, the second switch element, the third switch element, and the fourth switch element. The inverter device according to claim 2.

4. The inverter control unit, The first switch element and the second switch element are controlled to be ON, The third switch element and the fourth switch element are turned off. The first circuit is configured as follows: The inverter device according to claim 3.

5. The inverter control unit, The first switch element and the second switch element are controlled to be turned off. The third switch element and the fourth switch element are turned ON, The second circuit described above is configured as follows: The inverter device according to claim 3 or claim 4.

6. The aforementioned inverter circuit The system comprises multiple sets of the first switch element, the second switch element, the third switch element, and the fourth switch element. The inverter device according to any one of claims 3 to 5.

7. The inverter control unit executes the multiple sets of controls sequentially in a time series. The inverter device according to claim 6.

8. A filter circuit including a filter capacitor is provided between the plurality of switch elements and the AC terminal pair. The inverter control unit, The multiple switch elements are controlled to be switched on and off, The voltage of the filter capacitor is clamped by the reverse voltage of the parasitic diode of the switched element that is controlled to be off. An inverter device according to any one of claims 1 to 7.

9. The aforementioned switch element is configured using an IGBT. An inverter device according to any one of claims 1 to 8.

10. An inverter device according to any one of claims 1 to 9, A photovoltaic power generation device connected to the aforementioned DC terminal pair, A solar power generation system equipped with these features.

11. An inverter circuit comprising: a DC terminal pair consisting of a first DC terminal and a second DC terminal; an AC terminal pair consisting of a plurality of AC terminals; a first capacitor and a second capacitor connected in series between the first DC terminal and the second DC terminal; and a plurality of switch elements connected between the DC terminal pair and the AC terminal pair in a predetermined connection pattern, each being made of semiconductor material and having a parasitic diode; The inverter control unit, When a disconnection of DC power input from the aforementioned DC terminal pair is detected, The multiple switch elements are controlled to be switched on and off, The voltage of the first capacitor is clamped by the reverse voltage of the parasitic diode of the switched element that is controlled to be off. The voltage of the second capacitor is clamped by the reverse voltage of the parasitic diode of the switched element that is controlled to be off. Discharge method for inverter circuits.

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