Image processing device

Abstract

The present invention provides an image processing device capable of fixing the delay time when capturing and outputting a video signal. [Configuration] The image processing device according to this disclosure writes a video signal to memory, reads the written video signal from memory at the timing of the output clock signal, and outputs it as an output video signal. In doing so, it generates a clock signal that is phase-synchronized to both the horizontal synchronization signal and the vertical synchronization signal of the video signal as the output clock signal.

Description

Technical Field

[0001] The present disclosure relates to an image processing apparatus.

Background Art

[0002] In recent years, a display system has been commercialized that captures the scenery outside a vehicle such as an automobile and displays it in real time on an in-vehicle display device (see, for example, Patent Document 1).

[0003] The display system includes a camera that captures the outside of the vehicle, and an image processing apparatus that supplies a video signal adjusted so as to be captured at the timing of the display device side to the display device from the video signal output from the camera. Note that the image processing apparatus includes a frame memory, writes the video signal output from the camera into the frame memory at the timing of a horizontal synchronization signal synchronized with the video signal, and reads the video signal from the frame memory at the timing of a synchronization signal asynchronous with the horizontal synchronization signal. Then, the image processing apparatus supplies the video signal read from this frame memory to the display device.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] According to the image processing apparatus described in Patent Document 1, the delay time until the video signal output from the camera is supplied to the display device can be suppressed within one frame period, but the delay time within that one frame period is not fixed.

[0006] The image processing apparatus according to this disclosure includes: a memory that writes a video signal in response to an input video signal, reads the written video signal at the timing of an output clock signal and outputs it as an output video signal; a synchronization detection circuit that detects a horizontal synchronization signal and a vertical synchronization signal from the video signal; a first frequency divider that generates a clock signal obtained by dividing the output clock signal as a first frequency divider clock signal; a first phase comparator that generates a first phase difference signal indicating the phase difference between the phase of the horizontal synchronization signal and the phase of the first frequency divider clock signal; a first lock circuit that receives a self-propelled clock signal and generates a first reference clock signal by shifting the phase of the self-propelled clock signal based on the first phase difference signal so as to eliminate the phase difference between the self-propelled clock signal and the horizontal synchronization signal; a second frequency divider that generates a second frequency divider clock signal obtained by dividing the first frequency divider clock signal; and the phase of the vertical synchronization signal The system includes: a second phase comparator that generates a second phase difference signal indicating the phase difference between the phase of the second divided clock signal and the phase of the second divided clock signal; a second lock circuit that receives the self-propelled clock signal and generates a second reference clock signal by shifting the phase of the self-propelled clock signal based on the second phase difference signal so as to eliminate the phase difference between the self-propelled clock signal and the vertical synchronization signal; a selection circuit that receives the first reference clock signal and the second reference clock signal and outputs the first reference clock signal as a selected reference clock signal when the first lock circuit is in an unlocked state, and outputs the second reference clock signal as the selected reference clock signal when the first lock circuit is in a locked state; and a phase synchronization circuit that generates an oscillation signal having a dot frequency and generates an output clock signal with the phase of the oscillation signal locked to the phase of the selected reference clock signal. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram showing the configuration of the video system 100, including the image processing device related to this disclosure. [Figure 2] This is a block diagram showing an example of the internal configuration of the image processing device 20. [Figure 3]This is a time chart showing the operation of the image processing device 20.

[0008] [Detailed explanation] The embodiments of this disclosure will be described in detail below with reference to the drawings.

[0009] Figure 1 is a block diagram showing the configuration of a video system 100 including an image processing device according to this disclosure.

[0010] As shown in Figure 1, the video system 100 includes a video signal generator 10, an image processing device 20, and a display device 30.

[0011] The video signal generation device 10 consists of, for example, a camera, a DVD or Blu-ray player (recorder), or a television tuner, and supplies the video signal it has acquired or played back as a video signal VD to the image processing device 20. The video signal VD includes a horizontal synchronization signal, a vertical synchronization signal, and a series of pixel data fragments indicating the brightness level at each pixel that makes up the screen of the display device 30.

[0012] When the image processing device 20 receives a video signal VD from the video signal generation device 10, it generates an output clock signal CLKX for use on the display device 30, and an output video signal VDX synchronized with the output clock signal CLKX, based on the video signal VD. The image processing device 20 then outputs these output clock signal CLKX and output video signal VDX to the display device 30.

[0013] The display device 30 is a display that uses, for example, liquid crystal or organic EL, and captures the output video signal VDX at a timing synchronized with the output clock signal CLKX, and displays an image based on the output video signal VDX.

[0014] Figure 2 is a block diagram showing an example of the internal configuration of the image processing device 20.

[0015] As shown in Figure 2, the image processing device 20 includes a horizontal synchronization detection circuit 201, a vertical synchronization detection circuit 202, an input detection circuit 203, a frequency multiplier 204, frequency dividers 205 and 206, and phase comparators 207a and 207b. Furthermore, the image processing device 20 includes lock circuits 208a and 208b, a switching control circuit 209, a selector 210, a PLL (Phase Locked Loop) 211, and a frame memory 212.

[0016] When the horizontal synchronization detection circuit 201 receives a video signal VD, it detects a horizontal synchronization signal from the video signal VD and supplies a horizontal synchronization signal Hsyn, in which a single pulse appears, to the frequency multiplier 204 each time the horizontal synchronization signal is detected.

[0017] The vertical synchronization detection circuit 202 detects a vertical synchronization signal from the video signal VD when it receives the video signal VD, and supplies a vertical synchronization signal Vsyn, in which a single pulse appears each time the vertical synchronization signal is detected, to the phase comparator 207b.

[0018] The input detection circuit 203 detects whether or not a video signal VD has been input to the image processing device 20, and supplies the detection result, i.e., an input detection signal Id indicating "input present" or "no input," to the lock circuits 208a and 208b.

[0019] The frequency multiplier 204 supplies a signal obtained by multiplying the frequency of the horizontal synchronization signal Hsyn by N (where N is a real number greater than 1) to the phase comparator 207a as a horizontal synchronization multiplier signal Hm.

[0020] The frequency divider 205 receives the output clock signal CLKX output by the image processing device 20, divides this output clock signal CLKX to generate a divided clock signal CLn having a frequency N times the horizontal synchronization frequency, and supplies this to the phase comparator 207a and the frequency divider 206.

[0021] The frequency divider 206 receives the divided clock signal CLd, divides this divided clock signal CLd to generate a divided clock signal CLv having the same frequency as the vertical synchronization frequency, and supplies this to the phase comparator 207b.

[0022] The phase comparator 207a compares the phase of the above-described horizontal synchronization multiplication signal Hm with the phase of the divided clock signal CLn, and supplies a phase difference signal Ph representing the phase difference between the two to the lock circuit 208a.

[0023] The phase comparator 207b compares the phase of the above-described vertical synchronization signal Vsyn with the phase of the divided clock signal CLv, and supplies a phase difference signal Pv representing the phase difference between the two to the lock circuit 208b.

[0024] The lock circuit 208a receives the free-running clock signal CLKF together with the phase difference signal Ph and the input detection signal Id. Here, this free-running clock signal CLKF is a free-running clock signal having the dot frequency of the video signal, which is generated by the oscillation operation of an oscillation circuit (not shown) provided outside the image processing apparatus 20, for example. When the input detection signal Id indicates "input present", the lock circuit 208a generates a signal obtained by shifting the phase of the free-running clock signal CLKF based on the phase difference signal Ph so as to eliminate the phase difference between the free-running clock signal CLKF and the horizontal synchronization signal as the reference clock signal CKh. On the other hand, when the input detection signal Id indicates "no input", the lock circuit 208a outputs the free-running clock signal CLKF as the reference clock signal CKh as it is. The lock circuit 208a supplies the above-described reference clock signal CKh to the selector 210.

[0025] In addition, the lock circuit 208a includes a lock state determination unit that determines whether itself (the lock circuit 208a) is in a locked state or an unlocked state according to whether the phase difference between the reference clock signal CKh and the horizontal synchronization signal is greater than a predetermined value.

[0026] The lock state determination unit determines that the lock circuit 208a is in an unlocked state if the phase difference between the reference clock signal CKh and the horizontal synchronization signal is greater than a predetermined value, and the phase of the reference clock signal CKh is not synchronized with the phase of the horizontal synchronization signal Hsyn. In this case, the lock state determination unit supplies a logic level 0 lock state determination signal LK to the switching control circuit 209, indicating that the lock circuit 208a is in an "unlocked state". On the other hand, if the phase difference between the reference clock signal CKh and the horizontal synchronization signal is less than or equal to a predetermined value, the lock state determination unit determines that the phase of the reference clock signal CKh is synchronized with the phase of the horizontal synchronization signal Hsyn, and supplies a logic level 1 lock state determination signal LK to the switching control circuit 209, indicating that the lock circuit 208a is in a "locked state".

[0027] The lock circuit 208b receives the self-driving clock signal CLKF along with the phase difference signal Pv and the input detection signal Id. If the input detection signal Id indicates "input present", the lock circuit 208b generates a reference clock signal CKv by shifting the phase of the self-driving clock signal CLKF based on the phase difference signal Pv to eliminate the phase difference between the self-driving clock signal CLKF and the vertical synchronization signal. On the other hand, if the input detection signal Id indicates "no input", the lock circuit 208b outputs the self-driving clock signal CLKF as is as the reference clock signal CKv. The lock circuit 208b supplies the above-mentioned reference clock signal CKv to the selector 210.

[0028] While the switching control circuit 209 receives a logic level 0 lock state determination signal LK indicating an "unlocked state" from the lock circuit 208a, it supplies a selection signal SEL to the selector 210 that specifies a reference clock signal CKh. On the other hand, while receiving a logic level 1 lock state determination signal LK indicating a "locked state", the switching control circuit 209 supplies a selection signal SEL to the selector 210 that specifies a reference clock signal CKv.

[0029] The selector 210 receives the above-mentioned reference clock signals CKh and CKv, selects the one specified by the selection signal SEL from the two, and supplies it to the PLL 211 as the selected reference clock signal CLK.

[0030] The PLL211 includes a loop filter and a VCO (Voltage-controlled oscillator), generates an oscillation signal having the dot frequency of the input video signal VD, and locks the phase of this oscillation signal to the phase of the selected reference clock signal CLK to generate the output clock signal CLKX described above. The PLL211 supplies the generated output clock signal CLKX to the frequency divider 205 and the frame memory 212, and also outputs it to the display device 30.

[0031] The frame memory 212 captures and writes the video signal VD, and reads the written video signals in the order they were written at the timing of the output clock signal CLKX, and outputs them to the display device 30 as the output video signal VDX.

[0032] The operation of the image processing device 20 will be explained below with reference to the time chart shown in Figure 3.

[0033] In other words, when the image processing device 20 generates an output clock signal CLKX that is phase-synchronized with the video signal VD, it first executes a horizontal synchronization mode, and then executes a vertical synchronization mode, as shown in Figure 3.

[0034] In horizontal synchronization mode, the switching control circuit 209 supplies a selection signal SEL to the selector 210, which specifies the reference clock signal CKh. This forms a phase synchronization loop within the image processing device 20, consisting of the phase comparator 207a, lock circuit 208a, selector 210, PLL 211, and frequency divider 205, as shown in Figure 1. The lock circuit 208a generates the reference clock signal CKh by shifting the phase of the self-propelled clock signal CLKF based on the phase difference signal Ph, so as to eliminate the phase difference between the self-propelled clock signal CLKF and the horizontal synchronization signal Hsyn. This reference clock signal CKh is supplied to the PLL 211 via the selector 210. The phase difference signal Ph indicates the phase difference between the output clock signal CLKX and the horizontal synchronization signal Hsyn. Therefore, in this horizontal synchronization mode, the phase difference between the reference clock signal CKh and the horizontal synchronization signal Hsyn gradually decreases, and consequently, the phase difference between the output clock signal CLKX and the horizontal synchronization signal Hsyn also gradually decreases.

[0035] Here, for example, at time t1 shown in Figure 3, if the phase difference becomes less than or equal to a predetermined value, that is, if it is determined that the reference clock signal CKh is phase-synchronized with the horizontal synchronization signal Hsyn, the lock circuit 208a outputs a logic level 1 lock state determination signal LK indicating a "locked state". In response, the switching control circuit 209 supplies a selection signal SEL to the selector 210, specifying the reference clock signal CKv. As a result, the image processing device 20 switches from the horizontal synchronization mode to the vertical synchronization mode.

[0036] In vertical synchronization mode, a phase synchronization loop is formed within the image processing device 20 by the phase comparator 207b, lock circuit 208b, selector 210, PLL 211, and frequency dividers 205 and 206 as shown in Figure 1. Through this phase synchronization loop, the lock circuit 208b generates a reference clock signal CKv by shifting the phase of the self-propelled clock signal CLKF based on the phase difference signal Pv, so as to eliminate the phase difference between the self-propelled clock signal CLKF and the vertical synchronization signal Vsyn. This reference clock signal CKv is supplied to the PLL 211 via the selector 210. The phase difference signal Pv indicates the phase difference between the output clock signal CLKX and the vertical synchronization signal Vsyn.

[0037] Therefore, in the image processing device 20, the phase difference between the reference clock signal CKv and the vertical synchronization signal Vsyn gradually decreases in this vertical synchronization mode, and consequently, the phase difference between the output clock signal CLKX and the vertical synchronization signal Vsyn also gradually decreases. In other words, the image processing device 20 generates an output clock signal CLKX that is phase-synchronized with the vertical synchronization signal Vsyn.

[0038] Therefore, by executing the horizontal synchronization mode and vertical synchronization mode described above, the image processing device 20 generates an output clock signal CLKX that is phase-synchronized with both the horizontal synchronization signal and the vertical synchronization signal of the input video signal VD, and outputs this to the display device 30. Furthermore, the image processing device 20 outputs the output video signal VDX read from the frame memory 212 to the display device 30 at the timing of this output clock signal CLKX.

[0039] Furthermore, as mentioned above, the output clock signal CLKX generated by the image processing device 20 is phase-synchronized not only with the horizontal synchronization signal of the input video signal VD, but also with the vertical synchronization signal.

[0040] This makes it possible to fix the delay time from when a video signal VD is input to the image processing device 20 until the output video signal VDX corresponding to the video signal VD is output to a fixed time equal to the vertical period (frame period).

[0041] Furthermore, in the image processing device 20, the phase comparison between the self-propelled clock signal CLKF and the horizontal synchronization signal Hsyn in horizontal synchronization mode is performed using a frequency of the horizontal synchronization signal Hsyn multiplied by N (Hm) and a frequency of the output clock signal CLKX divided to a frequency equivalent to N times the horizontal synchronization frequency (CLn). As a result, the number of phase comparisons performed per horizontal scanning period in horizontal synchronization mode is increased to more than one, enabling rapid phase synchronization. Therefore, the image processing device 20 makes it possible to generate an output video signal VDX that is phase-synchronized with high accuracy even for high-speed input video signals compliant with standards such as LVDS (Low Voltage Differential Signaling) and MIPI (Mobile Industry Processor Interface).

[0042] In the configuration shown in Figure 2, the output clock signal CLKX is generated using an externally supplied self-propelled clock signal CLKF. However, the oscillation circuit that generates this self-propelled clock signal CLKF may be provided within the image processing device 20.

[0043] In short, the image processing apparatus of the present disclosure may include the following: memory, synchronization detection circuit, first and second frequency dividers, first and second phase comparators, first and second lock circuits, selection circuit, and phase synchronization circuit.

[0044] The memory (212) writes the video signal (VD) in response to the input, and reads the written video signal at the timing of the output clock signal (CLKX), outputting it as the output video signal (VDX).

[0045] The synchronization detection circuits (201, 202) detect the horizontal synchronization signal (Hsyn) and the vertical synchronization signal (Vsyn) from the video signal (VD). The first frequency divider (205) generates a clock signal obtained by dividing the output clock signal as the first divided clock signal (CLn). The first phase comparator (207a) generates a first phase difference signal (Ph) that indicates the phase difference between the phase of the horizontal synchronization signal and the phase of the first divided clock signal. The first lock circuit (208a) receives the self-driving clock signal (CLKF) and generates a first reference clock signal (CKh) by shifting the phase of the self-driving clock signal based on the first phase difference signal (Ph) to eliminate the phase difference between this clock signal and the horizontal synchronization signal.

[0046] The second frequency divider (206) generates a second divided clock signal (CLv) by dividing the first divided clock signal. The second phase comparator (207b) generates a second phase difference signal (Pv) indicating the phase difference between the phase of the vertical synchronization signal and the phase of the second divided clock signal (CLv). The second lock circuit (208b) receives the self-driving clock signal (CLKF) and generates a second reference clock signal (CKv) by shifting the phase of the self-driving clock signal based on the second phase difference signal (Pv) to eliminate the phase difference between the self-driving clock signal and the vertical synchronization signal.

[0047] The selection circuits (209, 210) receive the first and second reference clock signals. When the first lock circuit is unlocked, they output the first reference clock signal (CKh) as the selected reference clock signal (CLK). When the first lock circuit is locked, they output the second reference clock signal (CKv) as the selected reference clock signal. The phase-locking circuit (211) generates an output clock signal (CLKX) by locking the phase of an oscillation signal having a dot frequency to the phase of the selected reference clock signal (CLK).

[0048] Furthermore, this disclosure is not limited to the forms shown in Figures 1 and 2 above, and various improvements and design modifications are possible without departing from the gist of this disclosure.

[0049] [Note] This specification discloses the following configuration:

[0050] (Composition 1) A memory that writes the video signal in response to the input video signal and reads the written video signal at the timing of the output clock signal and outputs it as an output video signal; a synchronization detection circuit that detects a horizontal synchronization signal and a vertical synchronization signal from the video signal; a first frequency divider that generates a clock signal obtained by dividing the output clock signal as a first frequency divider clock signal; a first phase comparator that generates a first phase difference signal indicating the phase difference between the phase of the horizontal synchronization signal and the phase of the first frequency divider clock signal; a first lock circuit that receives a self-propelled clock signal and generates a first reference clock signal by shifting the phase of the self-propelled clock signal based on the first phase difference signal so as to eliminate the phase difference between the self-propelled clock signal and the horizontal synchronization signal; a second frequency divider that generates a second frequency divider clock signal obtained by dividing the first frequency divider clock signal; and a phase comparator that compares the phase of the vertical synchronization signal and the phase comparator of the second frequency divider clock signal Image processing apparatus comprising: a second phase comparator that generates a second phase difference signal indicating the phase difference between the phase of a clock signal and the phase of a clock signal; a second lock circuit that receives the self-driving clock signal and generates a second reference clock signal by shifting the phase of the self-driving clock signal based on the second phase difference signal so as to eliminate the phase difference between the self-driving clock signal and the vertical synchronization signal; a selection circuit that receives the first reference clock signal and the second reference clock signal and outputs the first reference clock signal as a selected reference clock signal when the first lock circuit is in an unlocked state, and outputs the second reference clock signal as the selected reference clock signal when the first lock circuit is in a locked state; and a phase synchronization circuit that generates an oscillation signal having a dot frequency and generates an output clock signal in which the phase of the oscillation signal is locked to the phase of the selected reference clock signal.

[0051] (Configuration 2) The image processing apparatus according to configuration 1, which includes a lock state determination unit that determines the first lock circuit is in the unlocked state when the phase difference between the first reference clock signal and the horizontal synchronization signal is greater than a predetermined value, and determines the first lock circuit is in the locked state when the phase difference between the first reference clock signal and the horizontal synchronization signal is less than or equal to the predetermined value.

[0052] (Composition 3) The image processing apparatus according to configuration 1 or 2, further comprising a multiplier that supplies the horizontal synchronization signal detected by the synchronization detection circuit, multiplied by N (a real number greater than 1), as the horizontal synchronization signal to the first phase comparator.

[0053] (Composition 4) An image processing apparatus according to any one of the above configurations 1 to 3, comprising an input detection circuit that detects whether or not the aforementioned video signal has been input and generates an input detection signal indicating whether or not there is an input, wherein the first lock circuit uses the self-propelled clock signal as a first reference clock signal when the input detection signal indicates no input, and the second lock circuit uses the self-propelled clock signal as a second reference clock signal when the input detection signal indicates no input.

[0054] (Composition 5) The image processing apparatus according to any one of the above configurations 1 to 4, wherein the memory is a frame memory. [Explanation of symbols]

[0055] 20 Image Processing Devices 201 Horizontal Synchronization Detection Circuit 202 Vertical Synchronization Detection Circuit 204 Multiplier 205, 206 frequency divider 207a, 207b phase comparator 208a, 208b Locking Circuit 209 Switching control circuit 210 Selector 211 PLL 212 frame memory

Claims

1. A memory that writes the video signal in response to the input video signal, reads the written video signal at the timing of the output clock signal, and outputs it as the output video signal, A synchronization detection circuit that detects a horizontal synchronization signal and a vertical synchronization signal from the aforementioned video signal, A first frequency divider generates a clock signal obtained by dividing the output clock signal as a first divided clock signal, A first phase comparator that generates a first phase difference signal indicating the phase difference between the phase of the horizontal synchronization signal and the phase of the first frequency divider clock signal, A first lock circuit that receives a self-propelled clock signal and generates a first reference clock signal by shifting the phase of the self-propelled clock signal based on a first phase difference signal so as to eliminate the phase difference between the self-propelled clock signal and the horizontal synchronization signal, A second frequency divider that generates a second frequency divider clock signal obtained by dividing the first frequency divider clock signal, A second phase comparator that generates a second phase difference signal indicating the phase difference between the phase of the vertical synchronization signal and the phase of the second frequency divide clock signal, A second lock circuit receives the self-propelled clock signal and generates a second reference clock signal by shifting the phase of the self-propelled clock signal based on the second phase difference signal so as to eliminate the phase difference between the self-propelled clock signal and the vertical synchronization signal. A selection circuit that receives the first reference clock signal and the second reference clock signal, outputs the first reference clock signal as the selected reference clock signal when the first lock circuit is unlocked, and outputs the second reference clock signal as the selected reference clock signal when the first lock circuit is locked, An image processing apparatus having a phase-locking circuit that generates an oscillation signal having a dot frequency and generates an output clock signal by locking the phase of the oscillation signal to the phase of the selected reference clock signal.

2. The image processing apparatus according to claim 1, comprising a lock state determination unit that determines the first lock circuit is in the unlocked state when the phase difference between the first reference clock signal and the horizontal synchronization signal is greater than a predetermined value, and determines the first lock circuit is in the locked state when the phase difference between the first reference clock signal and the horizontal synchronization signal is less than or equal to the predetermined value.

3. The image processing apparatus according to claim 1 or 2, further comprising a frequency multiplier that multiplies the frequency of the horizontal synchronization signal detected by the synchronization detection circuit by N (a real number greater than 1) and supplies the result to the first phase comparator as the horizontal synchronization signal.

4. Includes an input detection circuit that detects whether or not the aforementioned video signal has been input and generates an input detection signal indicating whether or not there is an input, The first lock circuit, when the input detection signal indicates no input, uses the self-propelled clock signal as the first reference clock signal. The image processing apparatus according to claim 1 or 2, wherein the second lock circuit uses the self-propelled clock signal as the second reference clock signal when the input detection signal indicates no input.

5. The image processing apparatus according to claim 1 or 2, wherein the memory is a frame memory.

Images