Semiconductor devices, power supply systems, and vehicles

Abstract

It can accommodate the specifications of various devices to which the output voltage is supplied. [Solution] The semiconductor device (1) comprises a multi-channel power supply circuit (51-57), a first input terminal (EN terminal) configured to receive an enable signal (EN), and a control unit (4) configured to control the first power supply circuit included in the multi-channel power supply circuit to start and shut down according to the enable signal, and to control the second power supply circuit included in the multi-channel power supply circuit to continue in an output-on state after startup, regardless of the enable signal.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Conventionally, a PMIC (Power Management IC) having a plurality of channels of power supply circuits has been known (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] In a PMIC, the startup timing and shutdown timing of each channel are determined according to user requirements. For example, in-vehicle PMICs are required to control various startups and shutdowns in order to support the specifications of all devices mounted on a vehicle.

[0005] A semiconductor device according to one aspect of the present disclosure includes a plurality of channels of power supply circuits, a first input terminal configured to receive an enable signal, a control unit configured to control the first power supply circuit included in the plurality of channels of power supply circuits to be started up and shut down according to the enable signal, and to control the second power supply circuit included in the plurality of channels of power supply circuits to continue to be in an output-on state regardless of the enable signal after startup.

Brief Description of Drawings

[0006] [Figure 1] FIG. 1 is a block diagram showing the configuration of a semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 2] FIG. 2 shows a plan view of the semiconductor device viewed from above. [Figure 3] Figure 3 shows a register map for setting the delay time to determine the startup timing. [Figure 4] Figure 4 shows a register map for setting the delay time to determine the shutdown timing. [Figure 5] Figure 5 shows the register map for setting functions such as the always-on function. [Figure 6] Figure 6 is a timing chart showing an example of startup and shutdown control operation in a semiconductor device. [Figure 7] Figure 7 shows an example of a power supply system configuration using semiconductor equipment. [Figure 8] Figure 8 is a timing chart showing an example of operation in a power supply system. [Figure 9] Figure 9 shows another example configuration of a power supply system using semiconductor equipment. [Figure 10] Figure 10 shows an example of the configuration of a vehicle equipped with semiconductor devices.

[0007] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0008] <1. PMIC Configuration> Figure 1 is a block diagram showing the configuration of a semiconductor device 1 according to an exemplary embodiment of the present disclosure. The semiconductor device 1 is configured as a PMIC. The semiconductor device 1 includes a multi-channel power supply circuit (BUCK1-4, LDO5-7) as described later.

[0009] The semiconductor device 1 is equipped with the following external terminals for establishing an electrical connection with the outside: VIN terminal, STBY terminal, EN terminal, VREG15 terminal, VREGIN terminal, SYNC terminal, SCL terminal, SDA terminal, PRSTB terminal, IF1 terminal, IF2 terminal, ERRB_ADDPRSTB2 terminal, INTB_ADDPRSTB1 terminal, and GND terminal.

[0010] The semiconductor device 1 includes, internally, an internal power supply circuit 2, a SYNC circuit 3, a control unit (control logic) 4, step-down power supply circuits 51-54, and LDO (Low Drop Out) circuits 55-57. The semiconductor device 1 integrates the above internal configuration onto a single chip. Specifically, the semiconductor device 1 includes four channels of step-down power supply circuits and three channels of LDO circuits, for a total of seven power supply circuits.

[0011] The semiconductor device 1 is equipped with external terminals corresponding to the step-down power supply circuits 51 to 54, namely PVIN1 to PVIN4 terminals, SW1 to SW4 terminals, FBP1 to FBP4 terminals, and FBN1 to FBN4 terminals. In addition, an external terminal PGND12 is provided corresponding to step-down power supply circuits 51 and 52, and an external terminal PGND34 is provided corresponding to step-down power supply circuits 53 and 54.

[0012] Furthermore, the semiconductor device 1 is equipped with PVIN5 to PVIN7 terminals and VOUT5 to VOUT7 terminals as external terminals corresponding to LDO55 to 57. In addition, an external terminal GATE7 terminal is provided for LDO57.

[0013] An external input voltage VIN is applied to the VIN terminal, and a bypass capacitor C1 is externally connected between it and ground.

[0014] The STBY terminal receives an external standby signal (STBY). The EN terminal receives an external enable signal (EN). The enable signal (EN) can be either high or low level.

[0015] The internal power supply circuit 2 generates the internal power supply voltage VREG15 based on the input voltage VIN. The internal power supply voltage VREG15 is a voltage of 1.5V and is used as the power supply voltage inside the IC, and is output from the VREG15 terminal. A bypass capacitor C2 is connected between the VREG15 terminal and ground. The internal power supply voltage VREG15 is input to the VREGIN terminal and supplied to the control unit 4 and each power supply circuit (51~57).

[0016] The SYNC terminal is a terminal used for the SYNC (synchronization) function. An external clock signal is input to the SYNC terminal, and the switching periods of the step-down power supply circuits 51 to 54 are synchronized with the external clock signal.

[0017] The SCL terminal and the SDA terminal are provided for I2C (Inter-Integrated Circuit) communication. I2C is a type of serial communication standard. The clock signal SCL is transmitted and received between the SCL terminal and an external device, and the data signal SDA is transmitted and received between the SDA terminal and the external device. The external device includes an EEPROM (Electrically Erasable Programmable Read-Only Memory) 10. The SCL terminal and the SDA terminal are pulled up by pull-up resistors Rp1 and RP2, respectively. Note that the serial communication is not limited to I2C, and for example, SPI (Serial Peripheral Interface) etc. may be used.

[0018] The PRSTB (Power-On Reset) terminal is a terminal for outputting a reset signal PRSTB, and is pulled up by a pull-up resistor Rp3. The reset signal PRSTB is an open-drain signal and indicates an active (reset state) at a low level.

[0019] The IF1 terminal and the IF2 terminal are terminals for communication between the semiconductor device 1 and an external PMIC, respectively. The IF1 terminal and the IF2 terminal are pulled up by pull-up resistors Rp4 and Rp5, respectively.

[0020] The ERRB_ADDPRSTB2 terminal is used for both the error notification function and the second additional power-on reset function. The ERRB_ADDPRSTB2 terminal allows for the addition of a second additional power-on reset function without increasing the number of terminals. The second additional power-on reset function and the first additional power-on reset function (described later) are added to the power-on reset function that uses the reset signal PRSTB. When the error notification function is enabled, an error signal is output from the ERRB_ADDPRSTB2 terminal. Also, when the second additional power-on reset function is enabled, the additional reset signal ADD_PRSTB2 is output from the ERRB_ADDPRSTB2 terminal. Whether to enable the error notification function or the second additional power-on reset function is set in register 41. The ERRB_ADDPRSTB2 terminal is pulled up by the pull-up resistor Rp6. The ERRB_ADDPRSTB2 terminal is active at a low level via open drain.

[0021] The INTB_ADDPRSTB1 terminal is used in common by both the interrupt function and the first additional power-on reset function. The INTB_ADDPRSTB1 terminal allows for the addition of the first additional power-on reset function without increasing the number of terminals. When the interrupt function is enabled, the interrupt signal is output from the INTB_ADDPRSTB1 terminal. When the first additional power-on reset function is enabled, the additional reset signal ADD_PRSTB1 is output from the INTB_ADDPRSTB1 terminal. Whether to enable the interrupt function or the first additional power-on reset function is set in register 41. The INTB_ADDPRSTB1 terminal is pulled up by the pull-up resistor Rp7. The INTB_ADDPRSTB1 terminal is active at a low level due to its open-drain configuration.

[0022] Next, the step-down power supply circuit will be described. Here, the step-down power supply circuit 51 will be described as a representative example. The step-down power supply circuit 51 comprises a half-bridge consisting of a high-side switch and a low-side switch (neither shown), and a control circuit (not shown) that drives and controls the high-side switch and the low-side switch. The step-down power supply circuit 51, inductor Lo1, and output capacitor Co1 constitute a DC / DC converter (switching regulator) that steps down the input voltage VIN to generate the output voltage VOUT1.

[0023] An external input voltage VIN is input to the PVIN1 terminal. Ground potential is applied to the PGND12 terminal. Here, as an example, the high-side switch is composed of a P-channel MOSFET and the low-side switch is composed of an N-channel MOSFET. The source of the high-side switch is connected to the PVIN terminal, the drain of the high-side switch is connected to the drain of the low-side switch, and the source of the low-side switch is connected to the PGND12 terminal. In other words, the high-side switch and the low-side switch are connected between the PVIN terminal and the PGND12 terminal. The node to which the drains of the high-side switch and the drain of the low-side switch are connected is connected to the SW1 terminal. One end of inductor Lo1 is externally connected to the SW1 terminal. The other end of inductor Lo1 is connected to one end of output capacitor Co1. The other end of output capacitor Co1 is connected to ground. One end of output capacitor Co1 is connected to the FBP1 terminal, and the other end of output capacitor Co1 is connected to the FBN1 terminal. The voltage between the FBP1 terminal and the FBN1 terminal is input to the step-down power supply circuit 51 as a feedback voltage, and the control circuit is used to provide feedback control so that the output voltage VOUT1 becomes the target voltage. The ground applied to the PGND12 terminal is shared by the step-down power supply circuits 51 and 52, and the ground applied to the PGND34 terminal is shared by the step-down power supply circuits 53 and 54.

[0024] Next, the LDO circuit will be described. Here, the LDO circuit 55 will be described as a representative example. The LDO circuit 55 has an output transistor and a control circuit (neither of which is shown) that drives and controls the output transistor. The LDO circuit 55 is a DC / DC converter (series regulator) that steps down the input voltage VIN to generate the output voltage VOUT5. The output transistor is composed of a P-channel MOSFET.

[0025] An external input voltage VIN is input to the PVIN5 terminal. The PVIN5 terminal is connected to the source of the output transistor. The VOUT5 terminal is connected to the drain of the output transistor. The output voltage VOUT5 generated at the VOUT5 terminal is fed back to the control circuit, and feedback control is performed so that the output voltage VOUT5 becomes the target voltage.

[0026] The GATE7 terminal is used to drive the gate of an external output transistor when an external output transistor is used for the LDO circuit 57.

[0027] <Layout of external terminals> Figure 2 shows a plan view of the semiconductor device 1 as seen from above. Figure 2 shows the layout of the external terminals (pin numbers 1 to 48). In Figure 2, the first direction X (vertical direction on the paper) is shown as one side X1 and the other side X2 of the first direction, and the second direction Y (horizontal direction on the paper) is shown as one side Y1 and the other side Y2 of the second direction.

[0028] The semiconductor device 1 has a rectangular shape when viewed from above and has a first side L1, a second side L2, a third side L3, and a fourth side L4. The first side L1 and the third side L3 extend in a first direction, and the second side L2 and the fourth side L4 extend in a second direction. The first side L1 and the third side L3 face each other in a second direction, and the second side L2 and the fourth side L4 face each other in a first direction. The other end of the first side L1 in the first direction is connected to one end of the second side L2 in the second direction. The other end of the second side L2 in the second direction is connected to the other end of the third side L3 in the first direction. One end of the third side L3 in the first direction is connected to the other end of the fourth side L4 in the second direction. One end of the fourth side L4 in the second direction is connected to one end of the first side L1 in the first direction.

[0029] Along the first side L1, in order from one side in the first direction, the following terminals are arranged: IF1 terminal, IF2 terminal, VREG15 terminal, VREG15IN terminal, SDA terminal, SCL terminal, EN terminal, INT_BPRSTB1 terminal, SYNC terminal, VIN terminal, NC (unconnected) terminal, and NC terminal.

[0030] Along the second side L2, the following terminals are arranged in order from one side in the second direction: FBP1 terminal, FBN1 terminal, PVIN1 terminal, SW1 terminal, PGND12 terminal, SW2 terminal, PVIN2 terminal, FBN2 terminal, FBP2 terminal, NC terminal, NC terminal, and GATE7 terminal.

[0031] Along the third side L3, the following terminals are arranged in order from the other side in the first direction: NC terminal, NC terminal, PVIN7 terminal, VOUT7 terminal, PVIN6 terminal, VOUT6 terminal, GND terminal, VOUT5 terminal, PVIN5 terminal, STBY terminal, PRSTB terminal, and ERRB_PRSTB2 terminal.

[0032] Along the fourth side L4, in the second direction from the other side, the following terminals are arranged in order: FBP3 terminal, FBN3 terminal, PVIN3 terminal, SW3 terminal, SW3 terminal, PGND34 terminal, PGND34 terminal, SW4 terminal, SW4 terminal, PVIN4 terminal, FBN4 terminal, and FBP4 terminal.

[0033] Furthermore, heat dissipation pads (EXP-PADs) are placed on the underside of the semiconductor device 1 and at the four rectangular corners.

[0034] <Normal control of startup and shutdown> Next, the normal control of startup and shutdown in semiconductor device 1 will be described. In normal control, the startup timing (the timing at which the output voltage starts to rise) and shutdown timing (the timing at which the output voltage starts to fall) of the step-down power supply circuits 51-54 and LDO circuits 55-57 are controlled based on the enable signal EN. Startup and shutdown control is performed by the control unit 4. Here, the register map in register 41 for setting startup timing control and shutdown timing control will be described.

[0035] Figure 3 shows a register map for setting the delay time to determine the startup timing. In the register maps shown in Figure 3 and subsequent figures, the register address, data name, and setting data are shown. The setting data is, for example, 8-bit data (Bit[7] to Bit[0]). The delay time set here is the delay time after the enable signal EN rises.

[0036] BUCK1_DELAY_PON to BUCK4_DELAY_PON are data used to set the delay time for each of the step-down power supply circuits 51 to 54, respectively. LDO5_DELAY_PON to LDO7_DELAY_PON are data used to set the delay time for each of the LDO circuits 55 to 57, respectively. PRSTB_DELAY_PON is data used to set the delay time for the reset signal PRSTB.

[0037] Figure 4 shows a register map for setting the delay time to determine the shutdown timing. The delay time set here is the delay time after the enable signal EN falls.

[0038] BUCK1_DELAY_POFF to BUCK4_DELAY_POFF are data used to set the delay time for each of the step-down power supply circuits 51 to 54, respectively. LDO5_DELAY_POFF to LDO7_DELAY_POFF are data used to set the delay time for each of the LDO circuits 55 to 57, respectively. PRSTB_DELAY_POFF is data used to set the delay time for the reset signal PRSTB.

[0039] The register map configuration data shown in Figures 3 and 4 is set, for example, as follows. If the setting data is 0x00, the delay time is 2μs. If the setting data is 0x01 to 0x80, the delay time is 128 μs to 16.384 ms (step = 128 μs). If the setting data is 0x80 to 0xA0, the delay time is 16.384ms to 24.576ms (step = 256μs). If the setting data is 0xA0 to 0xC0, the delay time is 24.576ms to 40.960ms (step = 512μs). If the setting data is 0xC0 to 0xE0, the delay time is 40.960 μs to 73.728 ms (step = 1.024 ms). If the setting data is 0xE0 to 0xFF, the delay time is 73.728 μs to 137.216 ms (step = 2.048 ms).

[0040] In this way, the longer the delay time, the longer the step size. This allows for setting a delay time over as wide a range as possible while suppressing an increase in the number of bits in the configuration data.

[0041] The upper part of Figure 5 shows the register map for setting whether to enable the always-on function (ALWAYS_ON) for each channel. The always-on function is a function that allows the channel output to remain in an on state (outputting an output voltage) at all times after the channel is started, regardless of the enable signal EN, and is distinct from the normal control described above.

[0042] BUCK1_ALWAYS_ON to BUCK4_ALWAYS_ON are data (1 bit data) used to set whether normal control or always-on function is enabled for each of the step-down power supply circuits 51 to 54. LDO5_ALWAYS_ON to LDO7_ALWAYS_ON are data (1 bit data) used to set whether normal control or always-on function is enabled for each of the LDO circuits 55 to 57.

[0043] PRSTB_ALWAYS_ON is a single-bit data value used to determine whether to enable normal control or the always-on function for the reset signal.

[0044] For example, in each of the above bit data, setting it to "0" enables normal control, and setting it to "1" enables the always-on function. Details of the always-on function will be described later.

[0045] Next, an example of normal startup and shutdown control operation will be explained using Figure 6. Figure 6 is a timing chart showing an example of startup and shutdown control operation in semiconductor device 1. In Figure 6, the input voltage VIN, internal power supply voltage VREG15, standby signal STBY, and enable signal EN are shown in order from top to bottom. Next, the setting values ​​for BUCK2_ALWAYS_ON, BUCK3_ALWAYS_ON, and BUCK4_ALWAYS_ON (Figure 5) are shown. Next, the internal state, I2C communication state, the output voltages corresponding to the step-down power supply circuits 51~54 (BUCK1~BUCK4), and the output voltages corresponding to the LDO circuits 55~57 (LDO5~LDO7) are shown. The reset signal PRSTB and the additional reset signal ADD_PRSTB1 shown at the bottom of Figure 6 will be described later.

[0046] At timing t1, the input voltage VIN begins to rise. Then, at timing t2, the standby signal STBY rises (switches to the ON state), activating the internal power supply circuit 2, and the internal power supply voltage VREG15 begins to rise. At timing t3, the UVLO (Under Voltage Lock Out) of the internal power supply voltage VREG15 is released. The internal state is shut off until timing t2, and VREG15 is ON from timing t2 to t3.

[0047] From timing t3 onward, the internal state transitions to the digital BIST (built-in self-test) for the control unit 4. Specifically, it transitions in the following order: the digital BIST (DBIST), the OTP (One Time Programmable ROM) read state, the EEPROM read state, and the analog BIST for various protection circuits.

[0048] Subsequently, at timing t5, the internal state becomes standby. Then, at timing t10, the enable signal EN rises (switching to a level indicating activation).

[0049] In the example shown in Figure 6, the register map shown in Figure 5 enables normal control for the step-down power supply circuit 51 (BCUK1) and the LDO circuits 55-57 (LDO5-7). As a result, the step-down power supply circuit 51 and the LDO circuits 55-57 are started at each timing, which is the start timing after the respective delay times (BUCK1_DELAY_PON and LDO5_DELAY_PON~LDO7_DELAY_PON) set by the register map shown in Figure 3, starting from timing 10 (rising edge of enable signal EN). At this start timing, each output voltage begins to rise.

[0050] Subsequently, at timing t13, the enable signal EN falls (switching to a level indicating shutdown). As a result, each timing that elapses from timing 13 by the respective delay times (BUCK1_DELAY_POFF, and LDO5_DELAY_POFF~LDO7_DELAY_POFF) set by the register map shown in Figure 4 is designated as the shutdown timing, and the step-down power supply circuit 51 and LDO circuits 55~57 shut down. At this shutdown timing, each output voltage begins to fall.

[0051] Thus, for channels where normal control is enabled, startup and shutdown control can be performed according to the enable signal EN.

[0052] <Always-on function> Next, we will explain the operation using the always-on function, referring to Figure 6.

[0053] In the internal state of OTP read mode, data is read from OTP42 (Figure 1) included in the control unit 4. OTP is a non-volatile memory that can be written to only once. In the internal state of EEPROM read mode, data is read from EEPROM10. EEPROM is a type of non-volatile memory.

[0054] Data read from the OTP or EEPROM can be used to write the always-on function to the register map shown in Figure 5. Channels with the always-on function enabled will start up when the internal state transitions to the standby state. In the example in Figure 6, at timing t4, BUCK2_ALWAYS_ON is written to the register map to enable the always-on function for the buck power supply circuit 52 (BUCK2), so the buck power supply circuit 52 starts up at timing t5 when the system transitions to the standby state.

[0055] Furthermore, it is possible to enable the always-on function by writing to the register map shown in Figure 5 from outside the semiconductor device 1 using I2C communication. However, writing to register 41 using I2C communication is only possible when the internal state is either standby (STANBY in Figure 6) or active (ACTIVE in Figure 6). The active state is transitioned from the power-on state (POWER_ON in Figure 6), which is defined as the period from when the enable signal EN rises until the last channel is started up by normal control.

[0056] When the internal state is in standby mode, channels that have been programmed to enable the always-on function in the register map using I2C communication will be activated at that time. For example, in the example in Figure 6, at timing t7, BUCK3_ALWAYS_ON is programmed into the register map to enable the always-on function for the buck power supply circuit 53 (BUCK3), so the buck power supply circuit 53 is activated at timing t7.

[0057] For channels with the always-on function enabled, the output will remain on even after the enable signal EN falls, unless the following shutdown conditions are met. The shutdown conditions are: (1) The standby signal STBY is set to the OFF state. (2) The register 41 was written to disable the always-on function using I2C communication, and the enable signal EN fell. It must satisfy one of the following conditions.

[0058] However, if (2) above is met, the system will shut down after the enable signal EN has fallen and the delay time set by the register map shown in Figure 4 for the target channel has elapsed.

[0059] In the example shown in Figure 6, the step-down power supply circuit 52 (BUCK2), which has the always-on function enabled, does not satisfy the above shutdown conditions, and therefore the output remains in the ON state even at the timing t13 when the enable signal EN falls.

[0060] Furthermore, for the step-down power supply circuit 53 (BUCK3) with the always-on function enabled, at timing t9 (standby state) or timing t13 (active state), BUCK3_ALWAYS_ON in the register map is written to disable the always-on function, and at timing t13 the enable signal EN falls, so the circuit is shut down at timing t13. In other words, even if the always-on function is written to disable it in register 41 before the timing when the enable signal EN falls, the circuit is not shut down at that timing, but is shut down in a sequence based on the enable signal EN.

[0061] Furthermore, if a channel with normal control enabled is started when the enable signal EN rises, and the register 41 is written to enable the always-on function for that channel using I2C communication while the internal state is active, then the output will remain on even when the enable signal EN falls, unless the above shutdown conditions are met. For example, in the example in Figure 6, the step-down power supply circuit 54 (BUCK4) with normal control enabled is started when the enable signal EN rises at timing t10, and then, at timing t12 in the active state, the always-on function is written to BUCK4_ALWAYS_ON in the register map, so the output remains on even when the enable signal EN falls at timing t13.

[0062] Furthermore, the example in Figure 6 shows the case where the standby signal STBY falls to an off state at timing t15 (condition (1) above), causing the internal power supply circuit 2 to shut down and the internal power supply voltage VREG15 to fall. As a result, UVLO is detected at timing t16, and the step-down power supply circuits 52, 54 (BUCK2, 4) are shut down.

[0063] Note that the shutdowns under the above shutdown conditions (1) and (2) are shutdowns under normal operation conditions. For channels with the always-on function enabled, a shutdown will also occur if a specific protection circuit for that channel detects an abnormality. These specific protection circuits are, for example, the OVP (Over Voltage Protection), UVP (Under Voltage Protection), and UVLO (Under Voltage Protection) circuits for the PVIN terminal, which are provided in the step-down power supply circuits 51-54 and the LDO circuits 55-57, respectively.

[0064] Thus, in this embodiment, by enabling the always-on function, the output can remain in the ON state even after the enable signal EN falls after startup, and can accommodate the specifications of various targets to which the output voltage is supplied.

[0065] <Reset signal> Next, we will explain the reset signal in power-on reset.

[0066] For the reset signal PRSTB, the PRSTB_ALWAYS_ON setting in the register map shown in Figure 5 allows you to configure whether to enable normal control or the always-on function. If the reset signal PRSTB is set to enable normal control, the reset signal PRSTB will behave based on the enable signal EN. Specifically, the reset signal PRSTB transitions to the reset-release state (high level) after the rising edge of the enable signal EN has elapsed for the delay time set by PRSTB_DELAY_PON in the register map shown in Figure 3, and transitions to the reset state (low level) after the falling edge of the enable signal EN has elapsed for the delay time set by PRSTB_DELAY_POFF in the register map shown in Figure 4.

[0067] In the example in Figure 6, the reset signal PRSTB is normally set to enabled. The system transitions to the reset-off state after the delay time set by PRSTB_DELAY_PON has elapsed from the timing t10 ​​when the enable signal EN rises, and to the reset state after the delay time set by PRSTB_DELAY_POFF has elapsed from the timing t13 when the enable signal EN falls.

[0068] On the other hand, if the reset signal PRSTB is set to always-on, the system will transition to the reset-off state after the delay time set by PRSTB_DELAY_PON has elapsed from the moment the enable signal EN rises, and the reset-off state will continue even after the enable signal EN falls.

[0069] Next, we will explain the additional power-on reset function. In the register map shown in Figure 5, "ADD_PRSTB" indicates the setting data for the additional power-on reset function.

[0070] The ADD_PRSTB1 stored in the first and second bits from the least significant is data for enabling or disabling the first additional power-on reset function. Specifically, for example, If ADD_PRSTB1=00, the first additional power-on reset function is disabled, meaning the interrupt function is enabled. If ADD_PRSTB1=01, the always-on function for the first additional power-on reset function is enabled.

[0071] The ADD_PRSTB1_DELAY, stored in the third and fourth bits from the lowest, is data for setting the delay time for the first additional power-on reset function. When the first additional power-on reset function is enabled as an always-on function, in the standby state, each time a channel with the always-on function enabled has finished starting up, the additional reset signal ADD_PRSTB1 transitions to the reset release state (high level) after the delay time set by ADD_PRSTB1_DELAY has elapsed. Also, in the standby state, each time a channel with the always-on function enabled is started up, the additional reset signal ADD_PRSTB1 transitions to the reset state (low level). Furthermore, the additional reset signal ADD_PRSTB1 remains in the reset release state even after the enable signal EN falls.

[0072] In the example shown in Figure 6, since the first additional power-on reset function is set to always-on, the additional reset signal ADD_PRSTB1 transitions to the reset-released state with a delay from the startup completion timing t6 of the step-down power supply circuit 52 (BUCK2), which has the always-on function enabled. Then, at the startup timing t7 of the step-down power supply circuit 53 (BUCK3), which has the always-on function enabled, the additional reset signal ADD_PRSTB1 transitions to the reset state. Then, with a delay from the startup completion timing t8 of the step-down power supply circuit 53, the additional reset signal ADD_PRSTB1 transitions to the reset-released state. Finally, at the timing t13 when the enable signal EN falls, the additional reset signal ADD_PRSTB1 remains in the reset-released state.

[0073] Note that ADD_PRSTB2 and ADD_PRSTB2_DELAY in the register map shown in Figure 5 are data for setting the second additional power-on reset function, and are the same as those for the first additional power-on reset function described above, so a detailed explanation is omitted.

[0074] ADD_PRSTB1_DELAY and ADD_PRSTB2_DELAY are set as follows, for example. If ADD_PRSTB1_DELAY or ADD_PRSTB2_DELAY = 00, the delay time = 2μs If ADD_PRSTB1_DELAY or ADD_PRSTB2_DELAY=01, the delay time is 1.211ms. If ADD_PRSTB1_DELAY or ADD_PRSTB2_DELAY = 10, the delay time = 4.845 ms If ADD_PRSTB1_DELAY or ADD_PRSTB2_DELAY = 11, the delay time = 9.690 ms

[0075] <Power supply system> Next, an example of the configuration of a power supply system (also called a power tree) using the semiconductor device 1 according to the embodiment of this disclosure described above will be explained.

[0076] Figure 7 shows the configuration of a power supply system 25 using a semiconductor device 1. The power supply system 25 comprises the semiconductor device 1, an EEPROM 10, a primary DC / DC converter 15, and a microcontroller 20.

[0077] The primary DC / DC converter 15 supplies the input voltage VIN generated by the DC / DC conversion to the semiconductor device 1 and the EEPROM 10. Here, the VIN terminal is short-circuited to the STBY terminal. Therefore, the input voltage VIN and the standby signal STBY are the same signal. In addition, the primary DC / DC converter 15 inputs an enable signal EN to the semiconductor device 1. The microcontroller 20 is supplied with the output voltage generated by the step-down power supply circuit 52 (BUCK2) in the semiconductor device 1.

[0078] The operation of the power supply system 25 with this configuration will be explained using the timing chart shown in Figure 8. In Figure 8, from top to bottom, the input voltage VIN, internal power supply voltage VREG15, standby signal STBY, enable signal EN, BUCK2_ALWAYS_ON setting value, internal state, and output voltage of the step-down power supply circuit 52 are shown.

[0079] First, at timing ta, the input voltage VIN is activated, and consequently, the standby signal STBY is activated. This is because the VIN terminal and the STBY terminal are short-circuited as described above. As a result, the internal power supply voltage VREG15 rises, UVLO is released at timing tb, and the system transitions to DBIST, etc. At this point, the data read from OTP42 is used to write BUCK2_ALWAYS_ON in register 41 so that the always-on function is enabled (timing tc). Therefore, at timing td, when the system transitions to the standby state, the step-down power supply circuit 52 is activated. Furthermore, at timing te, when the enable signal EN falls, the step-down power supply circuit 52 can continue to keep its output ON.

[0080] In this way, since the standby signal STBY can be activated simultaneously with the activation of the input voltage VIN, the UVLO release of VREG15 is accelerated, and the step-down power supply circuit 52 that supplies the output voltage to the microcontroller 20 can be activated earlier. Furthermore, because the transition to the standby state is faster, channel activation can also be performed earlier by writing to register 41 to enable the always-on function using I2C communication.

[0081] Figure 9 shows another example configuration of a power supply system using the semiconductor device 1. The power supply system 45 shown in Figure 9 includes the aforementioned semiconductor device 1, primary DC / DC converter 15, and microcontroller 20, as well as a primary DC / DC converter 30, a PMIC 35, and an SoC 40.

[0082] The primary DC / DC converter 30 supplies the power supply voltage to the PMIC 35. The PMIC 35 supplies the output voltage to the SoC 40. The SoC 40 outputs a standby signal STBY and an enable signal EN to the semiconductor device 1.

[0083] In this configuration, the power supply circuit in PMIC35 that supplies the output voltage to SoC40 starts up, and then SoC40 switches the standby signal STBY to the ON state. Subsequently, UVLO of VREG15 in semiconductor device 1 is released, and BUCK2_ALWAYS_ON is written to enable the always-on function by reading from OTP42. Then, at the timing of transitioning to the standby state, the step-down power supply circuit 52 starts up and supplies the output voltage to the microcontroller 20.

[0084] This power supply system 45 can accommodate the specification of starting up the SoC 40 before the microcontroller 20.

[0085] <Vehicle> Figure 10 shows an example configuration when the semiconductor device 1 according to this embodiment is mounted on a vehicle. In the configuration shown in Figure 10, the vehicle 50 is equipped with a touch panel 501, a camera device 502, an SD card device 503, and a USB interface 504. In addition, semiconductor devices 1A to 1D are provided on the vehicle 50, corresponding to the touch panel 501, camera device 502, SD card device 503, and USB interface 504, respectively.

[0086] The touch panel 501 is installed on the in-vehicle display and is configured to allow operation of the car navigation system, audio system, air conditioner, etc. The touch panel 501 is equipped with a microcontroller 501A. The semiconductor device 1A supplies an output voltage to the microcontroller 501A.

[0087] The camera device 502 is used for applications such as a drive recorder, rearview monitor, pedestrian detection, and autonomous driving, and is equipped with an SoC 502A. The semiconductor device 1B supplies an output voltage to the SoC 502A.

[0088] The SD card device 503 is a device that reads and writes data to and from an SD card, and is supplied with an output voltage from the semiconductor device 1C.

[0089] The USB interface 504 is configured to allow connection of USB devices such as smartphones, and is supplied with an output voltage from the semiconductor device 1D.

[0090] Since the semiconductor devices 1A to 1D have the always-on function described above, they can be used with devices that require a constant power supply, such as the microcontroller 501A, SoC 502A, SD card device 503, and USB interface 504.

[0091] <Other> Furthermore, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of this disclosure should be understood to include all modifications that fall within the meaning and scope equivalent to the claims, rather than being limited to the embodiments described above.

[0092] <Note> As described above, the semiconductor device (1) according to one aspect of this disclosure is Multiple channel power supply circuits (51-57), A first input terminal (EN terminal) configured to receive an enable signal (EN), The configuration includes a control unit (4) configured to control a first power supply circuit included in the multi-channel power supply circuit to start and shut down according to the enable signal, and to control a second power supply circuit included in the multi-channel power supply circuit to continue in an output-on state after startup, regardless of the enable signal (first configuration).

[0093] This configuration allows for compatibility with the specifications of various devices to which the output voltage is supplied.

[0094] Furthermore, the first configuration described above includes a register (41) configured to enable either normal control or always-on function for each channel, For channels in which normal control is enabled in the register, the control unit controls startup and shutdown according to the enable signal. For channels in the register where the always-on function is enabled, the control unit may be configured to allow the output to remain on regardless of the enable signal (second configuration).

[0095] Furthermore, in the second configuration described above, non-volatile memory (42,10) is provided, If the data read from the non-volatile memory is written to the register so that the always-on function is enabled, the control unit may be configured to start the channel with the always-on function enabled when it transitions to the standby state (third configuration).

[0096] Furthermore, in the second or third configuration described above, if the register is written to enable the always-on function via communication from outside the semiconductor device, the control unit may be configured to activate the channel in which the always-on function is enabled (fourth configuration).

[0097] Furthermore, in the fourth configuration described above, writing to the register via external communication may be possible in either the standby state or the active state, which is entered when the last started channel among the channels for which normal control is enabled has finished starting up (fifth configuration).

[0098] Furthermore, in any of the second to fifth configurations described above, if a channel in which the normal control is enabled is activated according to the enable signal, and then the channel is programmed to enable the always-on function via communication from outside the semiconductor device, the control unit may be configured to maintain the output-on state for that channel regardless of the enable signal (sixth configuration).

[0099] Furthermore, in any of the second to sixth configurations described above, for channels where the always-on function is enabled, (1) The standby signal input to the semiconductor device is set to the OFF state. (2) The register has been written to disable the always-on function using external communication from the semiconductor device, and the enable signal has been switched to a level indicating shutdown. The system may be configured to shut down if any of the following conditions are met (the seventh configuration).

[0100] Furthermore, in any of the third to fifth configurations described above, a second input terminal (VIN terminal) is configured to receive an input voltage (VIN), A third input terminal (STBY terminal) configured to receive a standby signal (STBY), The system comprises an internal power supply circuit (2) configured to generate an internal power supply voltage (VREG15), When the standby signal is activated, the internal power supply circuit is activated, the UVLO of the internal power supply voltage is released, and writing to the register becomes possible. The second input terminal and the third input terminal may be short-circuited (the eighth configuration).

[0101] Furthermore, one aspect of this disclosure is a power supply system comprising a semiconductor device having the configuration of the eighth configuration described above, and a microcontroller (20) configured to receive an output voltage from a channel in which the always-on function is set to be enabled (the ninth configuration).

[0102] Furthermore, one aspect of this disclosure is a power supply system comprising a semiconductor device having one of the configurations described in the first to eighth above, and an external device (501A, 502A, 503, 504) configured to receive an output voltage from the power supply circuit (the tenth configuration).

[0103] Furthermore, one aspect of this disclosure is a vehicle equipped with a power supply system of the ninth or tenth configuration described above (the eleventh configuration). [Industrial applicability]

[0104] This disclosure can be used, for example, in power supply systems for various applications. [Explanation of symbols]

[0105] 1 Semiconductor device 1A~1D Semiconductor Equipment 2 Microcontroller 2 Internal power circuit 3 SYNC circuit 4. Control Unit 7 Bit[ 9 Timing 12 Timing 15 Primary DC / DC Converter 20 Microcontrollers 25 Power supply systems 30 Primary DC / DC Converters 35 PMIC 40 SoC 41 Registers 42 OTP 45 Power supply system 50 vehicles 51-54 Step-down power supply circuit 55-57 LDO Circuit 501 Touch Panel 501A Microcontroller 502 Camera equipment 502A SoC 503 SD card device 504 USB Interface C1, C2 Capacitors Co1 output capacitor L1, first side L2, second side L3, third side L4, 4th side Lo1 Inductor Rp1~RP7 Pull-up resistors

Claims

1. A multi-channel power supply circuit, A first input terminal configured to receive an enable signal, A control unit is configured to control a first power supply circuit included in the multi-channel power supply circuit to start and shut down according to the enable signal, and to control a second power supply circuit included in the multi-channel power supply circuit to maintain an output ON state after startup, regardless of the enable signal. A semiconductor device equipped with the following features.

2. It includes a register that allows you to configure whether to enable normal control or the always-on function for each channel. For channels in which normal control is enabled in the register, the control unit controls startup and shutdown according to the enable signal. The semiconductor device according to claim 1, wherein, for channels in the register where the always-on function is enabled, the control unit enables the output to remain on regardless of the enable signal.

3. Equipped with non-volatile memory, The semiconductor device according to claim 2, wherein, when data read from the non-volatile memory is written to the register so that the always-on function is enabled, the control unit activates the channel in which the always-on function is enabled when transitioning to a standby state.

4. The semiconductor device according to claim 2, wherein when the register is written to enable the always-on function via communication from outside the semiconductor device, the control unit activates the channel to which the always-on function is enabled.

5. The semiconductor device according to claim 4, wherein writing to the register via external communication is possible in either the standby state or the active state, which is entered when the last started channel among the channels in which the normal control is enabled has finished starting up.

6. The semiconductor device according to claim 2, wherein, after a channel in which the normal control is enabled is activated in accordance with the enable signal, if the channel is written to enable the always-on function via communication from outside the semiconductor device, the control unit causes the channel to continue in an output-on state regardless of the enable signal.

7. For channels where the always-on function is enabled, (1) The standby signal input to the semiconductor device is set to the OFF state. (2) The register has been written to disable the always-on function using external communication from the semiconductor device, and the enable signal has been switched to a level indicating shutdown. The semiconductor device according to claim 2, which is shut down if any of the following conditions are met.

8. A second input terminal configured to receive an input voltage, A third input terminal configured to receive a standby signal, It comprises an internal power supply circuit configured to generate an internal power supply voltage, When the standby signal is activated, the internal power supply circuit is activated, the UVLO of the internal power supply voltage is released, and writing to the register becomes possible. The semiconductor device according to any one of claims 3 to 5, wherein the second input terminal and the third input terminal are short-circuited.

9. A power supply system comprising a semiconductor device according to claim 8, and a microcontroller configured to receive an output voltage from a channel in which the always-on function is enabled.

10. A power supply system comprising a semiconductor device according to claim 1 and an external device configured to receive an output voltage from the power supply circuit.

11. A vehicle equipped with the power supply system described in claim 10.

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