Successive approximation AD conversion circuit

Abstract

Reduce the time required from the start of the sample to the completion of outputting the converted data. [Solution] The successive approximation AD conversion circuit (1) comprises a sample-and-hold circuit (2) configured to sample and hold an analog input signal, a D / A converter (3) configured to convert a digital signal into an analog voltage, a comparator (4) configured to compare the output of the sample-and-hold circuit with the output of the D / A converter, and a control circuit (5) configured to generate the digital signal based on the output of the comparator and supply it to the D / A converter, determine each bit of the digital output signal based on the output of the comparator, and output the digital output signal serially in order from the determined bits.

Description

Technical Field

[0001] The present disclosure relates to a successive comparison type AD (Analog-to-Digital) conversion circuit.

Background Art

[0002] As one type of AD conversion circuit, there is a successive comparison type AD conversion circuit that performs AD conversion using binary search (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] However, in the successive comparison type AD conversion circuit, there is room for improvement in shortening the time required from the start of sampling to the completion of output of the converted data.

[0005] The successive comparison type AD conversion circuit according to the present disclosure includes a sample hold circuit configured to sample and hold an analog input signal, a D / A converter configured to convert a digital signal into an analog voltage, a comparator configured to compare an output of the sample hold circuit and an output of the D / A converter, and a control circuit configured to generate the digital signal based on an output of the comparator, supply the digital signal to the D / A converter, determine each bit of a digital output signal based on the output of the comparator, and output the digital output signal serially in order from the determined bits.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a diagram showing the configuration of a successive comparison type A / D converter. [Figure 2] FIG. 2 is a diagram showing an operation sequence according to a comparative example. [Figure 3] Figure 3 shows the operation sequence according to the first embodiment. [Figure 4] Figure 4 shows the operation sequence according to the first embodiment when a sudden sample start instruction is received during A / D conversion. [Figure 5] Figure 5 shows the operation sequence according to the second embodiment when a sudden sample start instruction is received during A / D conversion. [Figure 6] Figure 6 shows an example configuration of a control circuit according to the second embodiment. [Figure 7] Figure 7 is a timing chart showing the waveforms of various signals. [Figure 8] Figure 8 shows a modified example of the operation sequence. [Figure 9] Figure 9 shows another variation of the operation sequence. [Figure 10] Figure 10 shows yet another variation of the operation sequence.

[0007] [Detailed explanation] <Successive approximation A / D converter (comparative example)> Figure 1 shows the configuration of a successive approximation A / D converter according to a comparative example (= a general configuration to be compared with the embodiment described later). The successive approximation A / D converter 1 shown in Figure 1 comprises a sample-and-hold circuit 2, a D / A converter 3, a comparator 4, and a control circuit 5.

[0008] The sample-and-hold circuit 2 is configured to sample and hold the analog input signal Ain.

[0009] The D / A converter 3 is configured to convert a digital signal Sd into an analog voltage Sa.

[0010] Comparator 4 is configured to compare the output of sample-and-hold circuit 2 with the output of D / A converter 3 (analog voltage Sa).

[0011] In this comparative example, the control circuit 5 generates a digital signal Sd based on the output Scmp of the comparator 4 and supplies it to the D / A converter 3. After determining all the bits of the digital output signal Sout based on the output Scmp of the comparator, the control circuit 5 is configured to output the digital output signal Sout, which is obtained by encoding all the bits of the successive comparison register provided in the control circuit 5, in serial mode.

[0012] Figure 2 shows the operation sequence for this comparative example. The operation sequence shown in Figure 2 is the operation sequence when the resolution of the successive approximation A / D converter 1 is 8 bits.

[0013] As shown in Figure 2, in this comparative example, when the successive approximation A / D converter 1 is instructed to start sampling, the successive approximation A / D converter 1 first performs a sampling operation. Specifically, the sample-and-hold circuit 2 samples (samples and holds) the analog input signal Ain.

[0014] Once the sampling operation is complete, the successive approximation A / D converter 1 performs a successive comparison operation. Specifically, the control circuit 5 sets the most significant bit (MSB) of the successive approximation register located in the control circuit 5 to "1" and sets the other bits of the successive approximation register to "0". Then, the D / A converter 3 converts the digital value (digital signal Sd) of the successive approximation register into an analog voltage Sa. Based on the output Scmp of the comparator 4, the control circuit 5 determines the most significant bit of the successive approximation register to "1" if the output of the sample-and-hold circuit 2 is greater than the output of the D / A converter 3, and determines the most significant bit of the successive approximation register to "0" if the output of the sample-and-hold circuit 2 is not greater than the output of the D / A converter 3. This determines the most significant bit of the digital output signal Sout. Subsequently, the successive approximation A / D converter 1 repeats the same successive comparison until the least significant bit (LSB) of the successive approximation register is reached.

[0015] When the successive comparison operation is completed, the successive approximation type A / D converter 1 performs an encoding operation and a result output operation. Specifically, the control circuit 5 encodes all bits of the successive approximation register provided in the control circuit 5, and serially outputs the digital output signal Sout obtained by the encoding to the outside of the successive approximation type A / D converter 1.

[0016] In the successive approximation type A / D converter 1 according to the comparative example, the total time required for the sampling operation, the successive comparison operation, the encoding, and the result output operation is the total time required for A / D conversion (the time required from the start of the sample to the completion of the output of the converted data). Therefore, in the successive approximation type A / D converter 1 according to the comparative example, it has been difficult to shorten the total time required for A / D conversion (the time required from the start of the sample to the completion of the output of the converted data).

[0017] <Successive approximation type A / D converter (First Embodiment)> The successive approximation type A / D converter 1 according to the first embodiment has the same configuration shown in FIG. 1 as the successive approximation type A / D converter 1 according to the comparative example.

[0018] In the present embodiment, the control circuit 5 generates a digital signal Sd based on the output Scmp of the comparator 4 and supplies it to the D / A converter 3, determines each bit of the digital output signal Sout based on the output Scmp of the comparator, and is configured to output the digital output signal Sout serially in order from the determined bits.

[0019] FIG. 3 is a diagram showing the operation sequence according to the present embodiment. The operation sequence shown in FIG. 3 is the operation sequence when the resolution of the successive approximation type A / D converter 1 is 8 bits.

[0020] As shown in FIG. 3, in this comparative example, when the sequential comparison type A / D converter 1 is instructed to start sampling, the sequential comparison type A / D converter 1 first performs a sampling operation. Specifically, the sample hold circuit 2 samples (samples and holds) the analog input signal Ain.

[0021] When the sampling operation is completed, the sequential comparison type A / D converter 1 performs a sequential comparison operation. Specifically, the control circuit 5 sets "1" to the most significant bit of the sequential comparison register provided in the control circuit 5 and sets "0" to the other bits of the sequential comparison register. Then, the D / A converter 3 converts the digital value (digital signal Sd) of the sequential comparison register into an analog voltage Sa. Based on the output Scmp of the comparator 4, the control circuit 5 determines the most significant bit of the sequential comparison register as "1" when the output of the sample hold circuit 2 is greater than the output of the D / A converter 3, and determines the most significant bit of the sequential comparison register as "0" when the output of the sample hold circuit 2 is not greater than the output of the D / A converter 3. Thus, the most significant bit of the digital output signal Sout is determined. Thereafter, the sequential comparison type A / D converter 1 repeats the same sequential comparison up to the least significant bit of the sequential comparison register.

[0022] Before the completion of the sequential comparison operation, the sequential comparison type A / D converter 1 starts an encoding operation and a result output operation. Specifically, the control circuit 5 determines each bit of the sequential comparison register provided in the control circuit 5, encodes the determined bits of the sequential comparison register provided in the control circuit 5 even before the completion of the sequential comparison operation, and outputs them serially in order from the bits of the digital output signal Sout obtained by the encoding.

[0023] In the successive approximation A / D converter 1 according to this embodiment, the period during which the successive comparison operation is performed partially overlaps with the period during which the encoding operation and the period during which the result output operation are performed. Therefore, the total time required for A / D conversion (the time required from the start of sampling to the completion of outputting the converted data) is shorter than the sum of the time required for sampling, the time required for successive comparison, the time required for encoding, and the time required for result output operation. Consequently, the successive approximation A / D converter 1 according to this embodiment can shorten the total time required for A / D conversion (the time required from the start of sampling to the completion of outputting the converted data) compared to the successive approximation A / D converter 1 according to the comparative example.

[0024] However, in the successive approximation A / D converter 1 according to this embodiment, as shown in Figure 4, if a sudden sample start instruction is received during A / D conversion, the result output operation is interrupted midway. As a result, an incorrect digital output signal Sout is output from the successive approximation A / D converter 1 according to this embodiment.

[0025] <Successive approximation A / D converter (second embodiment)> The successive approximation A / D converter 1 according to the second embodiment has the same configuration as the successive approximation A / D converter 1 according to the comparative example and the successive approximation A / D converter 1 according to the first embodiment, as shown in Figure 1.

[0026] In this embodiment, similar to the first embodiment, the control circuit 5 is configured to generate a digital signal Sd based on the output Scmp of the comparator 4 and supply it to the D / A converter 3, determine each bit of the digital output signal Sout based on the output Scmp of the comparator, and output the digital output signal Sout serially in order from the determined bits.

[0027] In this embodiment, the successive approximation A / D converter 1 outputs an error signal indicating that the number of bits in the digital output signal Sout is insufficient when the number of bits in the digital output signal Sout is insufficient for the resolution of the successive approximation A / D converter 1 in this embodiment. As a result, a device receiving the digital output signal Sout and the error signal can detect that an incorrect digital output signal Sout was output from the successive approximation A / D converter 1 in this embodiment by using the error signal, even if an incorrect digital output signal Sout is output from the successive approximation A / D converter 1 in this embodiment.

[0028] An abnormal signal is a high-level Fail signal Sfail, as shown in Figure 5. Note that a low-level Fail signal Sfail is not considered an abnormal signal.

[0029] Figure 6 shows an example configuration of the control circuit 5 according to this embodiment. The control circuit 5 shown in Figure 6 comprises a comparison data acquisition unit 51, an encoding unit 52, a conversion trigger detection unit 53, a timing generation unit 54, a digital signal generation unit 55, and an irregularity detection unit 56.

[0030] The comparison data acquisition unit 51 receives the output Scmp from the comparator 4. The comparison data acquisition unit 51 is equipped with the sequential comparison register described above.

[0031] The encoding unit 52 encodes the bits of the successive comparison register and outputs the digital output signal Sout serially.

[0032] The conversion trigger detection unit 53 receives the trigger signal St and informs the timing generation unit 54 and the irregular detection unit 56 of the sample start timing. The high-level trigger signal St is a sample start signal that instructs the sample-hold circuit 2 to start sampling. Note that the low-level trigger signal St does not correspond to a sample start signal.

[0033] The timing generation unit 54 receives the clock signal CLK and generates the update timing for the digital signal Sd and the reset timing for the abnormal signal based on the clock signal CLK. The timing generation unit 54 also outputs an output flag signal Sf. The output flag signal Sf is a signal that is at a low level during the period when the digital output signal Sout is output from the successive approximation A / D converter 1 according to this embodiment, and at a high level during the period when the digital output signal Sout is not output from the successive approximation A / D converter 1 according to this embodiment.

[0034] The digital signal generation unit 55 reads each bit of the successive comparison register, generates a digital signal Sd, and outputs it.

[0035] The irregular detection unit 56 generates and outputs a Fail signal Sfail based on the output of the conversion trigger detection unit 53 and the output of the timing generation unit 54. The irregular detection unit 56 uses the sample start signal to determine whether the number of bits in the digital output signal Sout is insufficient for the resolution of the successive approximation A / D converter 1 according to this embodiment. Specifically, at the timing when the sample start signal is input, the irregular detection unit 56 determines whether the number of bits in the digital output signal Sout corresponding to the resolution of the successive approximation A / D converter 1 according to this embodiment is output, and sets the Fail signal Sfail to a High level if the number of bits in the digital output signal Sout corresponding to the resolution of the successive approximation A / D converter 1 according to this embodiment is not output. Subsequently, the irregular detection unit 56 resets the abnormal signal by switching the Fail signal Sfail from a High level to a Low level at the timing when the next digital output signal Sout starts to be output.

[0036] The waveforms of the clock signal CLK, trigger signal St, digital output signal Sout, output flag signal Sf, and Fail signal Sfail used in the control circuit 5 shown in Figure 6 are as shown in the timing chart in Figure 7, for example. In the timing chart shown in Figure 7, the sampling operation period is set to 8 cycles of the clock signal CLK, and the period from the start to the completion of the successive comparison operation is set to 8 cycles of the clock signal CLK.

[0037] <Other> The embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of this disclosure is indicated by the claims rather than by the description of the embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0038] For example, in the first and second embodiments described above, the output of the sample-and-hold circuit 2 was supplied to the non-inverting input terminal of the comparator 2, and the output of the DAC3 was supplied to the inverting input terminal of the comparator 2. However, a configuration in which the output of the sample-and-hold circuit 2 is supplied to the inverting input terminal of the comparator 2, and the output of the DAC3 is supplied to the non-inverting input terminal of the comparator 2, is also possible.

[0039] For example, in the first and second embodiments described above, the start timing of the encoding period is delayed by one cycle of the clock signal CLK compared to the start timing of the successive comparison operation, and the start timing of the result output operation is delayed by one cycle of the clock signal CLK compared to the start timing of the encoding period. However, this delay amount is merely illustrative. Therefore, for example, the delay may be two cycles of the clock signal CLK as shown in Figure 8, or three cycles of the clock signal CLK as shown in Figure 9, or even different from each other as shown in Figure 10.

[0040] <Note> The successive approximation AD conversion circuit described herein can shorten the time required from the start of sampling to the completion of outputting the converted data. The above disclosure is described below.

[0041] [Note 1] A sample-and-hold circuit (2) configured to sample and hold an analog input signal, A D / A converter (3) configured to convert a digital signal to an analog voltage, A comparator (4) configured to compare the output of the sample-and-hold circuit with the output of the D / A converter, A control circuit (5) is configured to generate the digital signal based on the output of the comparator and supply it to the D / A converter, to determine each bit of the digital output signal based on the output of the comparator, and to output the digital output signal serially in order from the determined bits, A successive approximation A / D converter (1) is provided.

[0042] [Note 2] The successive approximation A / D converter according to Appendix 1, further comprising an abnormal signal output circuit (56) configured to output an abnormal signal indicating that the number of bits in the digital output signal is insufficient when the number of bits in the digital output signal is insufficient for the resolution of the successive approximation A / D converter.

[0043] [Note 3] The successive approximation A / D converter as described in Appendix 2, wherein the abnormal signal output circuit is configured to determine whether the number of bits of the digital output signal is insufficient for the resolution of the successive approximation A / D converter, using a sample start signal to instruct the sample-hold circuit to start sampling.

[0044] [Note 4] The successive approximation A / D converter described in Appendix 3, wherein the abnormal signal output circuit is configured to determine whether or not the number of bits of the digital output signal corresponding to the resolution of the successive approximation A / D converter is output at the timing when the sample start signal is input.

[0045] [Note 5] The successive approximation A / D converter according to any one of the appendices 2 to 4, wherein the abnormal signal output circuit is configured to reset the abnormal signal at the timing of the start of output of the next digital output signal. [Explanation of symbols]

[0046] 1. Successive approximation A / D converter 2 Sample-and-Hold Circuit 3 D / A converters 4 Comparator 5 Control circuits 51 Comparison Data Acquisition Unit 52 Encoding section 53 Conversion trigger detection unit 54 Timing generation unit 55 Digital signal generation unit 56 Irregular Detection Unit

Claims

1. A sample-and-hold circuit configured to sample and hold an analog input signal, A D / A converter configured to convert digital signals to analog voltages, A comparator configured to compare the output of the sample-and-hold circuit with the output of the D / A converter, A control circuit is configured to generate the digital signal based on the output of the comparator and supply it to the D / A converter, to determine each bit of the digital output signal based on the output of the comparator, and to output the digital output signal serially in order from the determined bits, A successive approximation A / D converter equipped with [the following features].

2. The successive approximation A / D converter according to claim 1, further comprising an abnormal signal output circuit configured to output an abnormal signal indicating that the number of bits in the digital output signal is insufficient when the number of bits in the digital output signal is insufficient for the resolution of the successive approximation A / D converter.

3. The successive approximation type A / D converter according to claim 2, wherein the abnormal signal output circuit is configured to determine whether the number of bits of the digital output signal is insufficient for the resolution of the successive approximation type A / D converter, using a sample start signal to instruct the sample hold circuit to start sampling.

4. The successive approximation A / D converter according to claim 3, wherein the abnormal signal output circuit is configured to determine whether or not the number of bits of the digital output signal corresponding to the resolution of the successive approximation A / D converter is output at the timing when the sample start signal is input.

5. The successive approximation A / D converter according to any one of claims 2 to 4, wherein the abnormal signal output circuit is configured to reset the abnormal signal at the timing of the start of output of the next digital output signal.

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