Semiconductor equipment
The multi-chip semiconductor device addresses data communication challenges by using P-channel and N-channel transistors to adjust signal timing and load capacitance, ensuring precise setup and hold times for efficient data transfer.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- ROHM CO LTD
- Filing Date
- 2025-01-16
- Publication Date
- 2026-07-29
AI Technical Summary
Existing multi-chip semiconductor devices face challenges in accurately performing data communication due to wiring defects and inadequate setup and hold times, which are not adequately addressed post-package assembly.
A multi-chip semiconductor device with a first chip and a second chip connected via a signal supply line, featuring an output circuit with P-channel and N-channel transistors for adjusting signal timing and a load adjustment circuit with capacitive elements to control load capacitance, allowing for precise setup and hold time adjustment.
The device enables accurate data communication by adjusting signal timing and load capacitance, ensuring optimal setup and hold times even after package assembly, enhancing data transfer efficiency between chips.
Smart Images
Figure 2026122767000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a multi-chip semiconductor device.
Background Art
[0002] In recent years, multi-chip semiconductor devices that perform data communication between multiple chips have been widely used. In such multi-chip semiconductor devices, semiconductor devices capable of detecting wiring defects between chips have been proposed (for example, Patent Document 1).
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
[0004] [Summary] In order to accurately perform data communication between chips, in addition to no wiring defects, it is necessary to ensure sufficient setup and hold times for input data. Therefore, it is desired that the setup and hold times can be adjusted after the package assembly of the multi-chip semiconductor.
[0005] A semiconductor device according to an aspect of the present disclosure is a multi-chip semiconductor device having a first chip and a second chip connected to each other via a signal supply line, wherein the first chip includes an output circuit including at least one transistor pair including a P-channel type first transistor having a source connected to a supply line of a first voltage and a drain connected to the signal supply line, and an N-channel type second transistor having a source connected to a supply line of a second voltage lower than the first voltage and a drain connected to the signal supply line, a control circuit for controlling on and off of the first transistor and the second transistor, and an instruction reception unit for receiving an instruction for controlling on and off of the first transistor and the second transistor.
Brief Description of the Drawings
[0006] [Figure 1] This is a block diagram showing the configuration of a semiconductor device according to an embodiment of the present disclosure. [Figure 2] This is a block diagram showing the input / output portions of the clock signal in the first and second chips. [Figure 3] This is a circuit diagram showing the configuration of the output circuit in the first chip. [Figure 4] This is a truth table of input and output signals in an output control circuit. [Figure 5] This is a circuit diagram showing the configuration of the load adjustment circuit in the second chip. [Detailed Description] Preferred embodiments of the present disclosure are described in detail below. In the following descriptions and accompanying drawings, substantially identical or equivalent parts are denoted by the same reference numerals.
[0007] Figure 1 is a block diagram showing the configuration of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 is a multi-chip semiconductor device and is composed of a first chip 11 and a second chip 12.
[0008] Both the first chip 11 and the second chip 12 operate by receiving a power supply voltage VCC, which is an external power supply voltage. The first chip 11 outputs a clock signal CLK, a command signal CMD, and an addressing signal ADD, and supplies them to the second chip 12.
[0009] The second chip 12 operates in synchronization with the clock signal CLK (hereinafter also referred to as the CLK output) output from the first chip 11. The second chip 12 communicates data with the first chip 11 by transmitting data at the address specified by the addressing signal ADD output from the first chip 11 via data input / output I / O, according to the instructions received based on the command signal CMD output from the first chip 11.
[0010] Figure 2 is a block diagram showing the input / output portions of the clock signal CLK in the first chip 11 and the second chip 12.
[0011] The output section of the clock signal CLK in the first chip 11 consists of an output circuit 21, an output control circuit 22, and a trimming circuit 23.
[0012] The output circuit 21 is a circuit that outputs a clock signal CLK. The input terminal of the output circuit 21 is connected to the output terminal of the output control circuit 22 and the internal clock signal CLK 11 of the first chip 11.
[0013] The output control circuit 22 outputs a (n+1) bit (where n is a natural number) output control signal CO <n:0>and the inverted output control signal COB with its logic level inverted. <n:0>This is output from the output terminal and supplied to the output circuit 21.
[0014] The trimming circuit 23 outputs a (n+1) bit trimming signal TB1 <n:0>and the inverted trimmed signal TB1B, which is the logic level of the inverted signal. <n:0>This is supplied to the output control circuit 22. The trimming circuit 23 is an instruction receiving unit that receives instructions for output control by the output control circuit 22, and is composed of, for example, an electronic fuse or an MTP (Multiple Time Programmable) memory. The trimming circuit 23 receives instructions from an external signal input, etc., and receives a trimming signal TB1 in response. <n:0>and inverted trimming signal TB1B <n:0>This is supplied to the output control circuit 22.
[0015] The input section for the clock signal CLK in the second chip 12 consists of an input circuit 31, a load adjustment circuit 32, and a trimming circuit 33.
[0016] The input circuit 31 is a circuit that receives the clock signal CLK output from the first chip 11. The input terminal of the input circuit 31 is connected to the clock signal supply line L1 that connects the first chip 11 and the second chip 12.
[0017] The load adjustment circuit 32 consists of multiple load capacitors (capacitive elements) that are connected to the clock signal supply line L1. The load adjustment circuit 32 receives the (n+1) bit trimming signal TB2 from the trimming circuit 33. <n:0>and the inverted trimmed signal TB2B, which is the logic level of the inverted signal. <n:0>Upon receiving the power supply, the load capacitance connected to the clock signal supply line L1 is selectively switched accordingly. This adjusts the load on the clock signal supply line L1.
[0018] The trimming circuit 33 receives the trimming signal TB2 <n:0>and inverted trimming signal TB2B <n:0>This is supplied to the load adjustment circuit 32. The trimming circuit 33 consists of an electronic fuse, an MTP memory, etc., and receives an external signal input and applies a corresponding trimming signal TB2. <n:0>and inverted trimming signal TB2B <n:0>Output it.
[0019] FIG. 3 is a circuit diagram showing the configuration of an output circuit 21 provided in the first chip 11. Here, the circuit configuration when the output control signal CO and the trimming signal TB1 are 2 bits, that is, when n = 1, is shown as an example.
[0020] The output circuit 21 includes transistors PM0, PM1, NM0, and NM1. The output circuit 21 also includes NAND gate circuits ND1 and ND2, and AND gate circuits AD1 and AD2.
[0021] The transistor PM0 is composed of a P-channel MOS transistor. The source of the transistor PM0 is connected to the supply line of the power supply voltage VCC. The drain of the transistor PM0 is connected to the clock signal supply line L1. The gate of the transistor PM0 is connected to the output terminal of the NAND gate circuit ND1.
[0022] The NAND gate circuit ND1 receives the signal obtained by inverting the inverted output control signal COB<0> via an inverter and the input of the internal clock signal CLK11, and outputs the negative logical product of these. The output signal is supplied to the gate of the transistor PM0.
[0023] The transistor PM1 is composed of a P-channel MOS transistor. The source of the transistor PM1 is connected to the supply line of the power supply voltage VCC. The drain of the transistor PM1 is connected to the clock signal supply line L1. The gate of the transistor PM1 is connected to the output terminal of the NAND gate circuit ND2.
[0024] The NAND gate circuit ND2 receives the signal obtained by inverting the inverted output control signal COB<1> via an inverter and the input of the internal clock signal CLK11, and outputs the negative logical product of these. The output signal is supplied to the gate of the transistor PM1.
[0025] Transistor NM0 is composed of an N-channel MOS transistor. The source of transistor NM0 is connected to the reference voltage VSS (e.g., ground potential) supply line. The drain of transistor NM0 is connected to the clock signal supply line L1. The gate of transistor NM0 is connected to the output terminal of the AND gate circuit AD1.
[0026] The AND gate circuit AD1 inverts the internal clock signal CLK11 via an inverter and outputs the control signal CO <0> It receives the inputs and outputs their logical AND. The output signal is supplied to the gate of transistor NM0.
[0027] Transistor NM1 is composed of an N-channel MOS transistor. The source of transistor NM1 is connected to the supply line of the reference voltage VSS. The drain of transistor NM1 is connected to the clock signal supply line L1. The gate of transistor NM1 is connected to the output terminal of the AND gate circuit AD2.
[0028] The AND gate circuit AD2 receives the signal obtained by inverting the internal clock signal CLK11 via an inverter, and the output control signal CO <1> It receives the inputs and outputs their logical AND. The output signal is supplied to the gate of transistor NM1.
[0029] In the output circuit 21 with this configuration, the inverting output control signal COB <0> and COB <1> By setting one or both of these to the voltage level of the reference voltage VSS, which is logic level 0 (i.e., L level), one or both of transistors PM0 and PM1 turn on at the timing when the internal clock signal CLK11 becomes logic level 1. This increases the current (charging current) flowing from the power supply voltage VCC supply line to the clock signal supply line L1, and allows adjustment of the timing of the change in the signal level of the clock signal CLK.
[0030] Also, the output control signal CO <0> and CO <1> By setting one or both of these to the voltage level of the power supply voltage VCC, which is logic level 1 (i.e., high level), one or both of transistors NM0 and NM1 will turn on at the timing when the clock signal CLK becomes logic level 0. This increases the current flowing from the clock signal supply line L1 to the reference voltage VSS supply line, thereby adjusting the timing of the change in the signal level of the clock signal CLK.
[0031] The signal levels of the output control signal CO<1:0> and the inverted output control signal COB<1:0> are set based on the trimming signal TB1<1:0> and the inverted trimming signal TB1B<1:0>, which are the output signals of the trimming circuit 23.
[0032] Figure 4 is a truth table showing the correspondence between the trimming signal TB1 and the inverted trimming signal TB1B, which are input signals of the output control circuit 22, and the output control signal CO and the inverted output control signal COB, which are output signals.
[0033] When the trimming signal TB1 is at a high level, the output control signal CO is also at a high level. Additionally, the inverted trimming signal TB1B is at a low level, and the inverted output control signal COB is at a low level.
[0034] When the trimming signal TB1 is at a low level, the output control signal CO is also at a low level. In addition, the inverted trimming signal TB1B is at a high level, and the inverted output control signal COB is at a high level.
[0035] Figure 5 is a circuit diagram showing the configuration of the load adjustment circuit 32 provided on the second chip 12. Here, the circuit configuration is shown as an example when the trimming signal TB2 is 2 bits, i.e., n=1. The load adjustment circuit 32 includes transistors PM2, PM3, NM2, and NM3.
[0036] Transistor PM2 is composed of a P-channel MOS transistor. The source and drain of transistor PM2 are connected to each other and to the clock signal supply line L1. The gate of transistor PM2 receives the inverting trimming signal TB2B. <0> It will be supplied.
[0037] Transistor PM3 is composed of a P-channel MOS transistor. The source and drain of transistor PM3 are connected to each other and to the clock signal supply line L1. The gate of transistor PM3 receives the inverting trimming signal TB2B. <1> It will be supplied.
[0038] Transistor NM2 is composed of an N-channel MOS transistor. The source and drain of transistor NM2 are connected to each other and to the clock signal supply line L1. The gate of transistor NM2 receives the trimming signal TB2. <0> It will be supplied.
[0039] Transistor NM3 is composed of an N-channel MOS transistor. The source and drain of transistor NM3 are connected to each other and to the clock signal supply line L1. The gate of transistor NM3 receives the trimming signal TB2. <1> It will be supplied.
[0040] With this configuration, the load adjustment circuit 32 can adjust the terminal capacitance (load capacitance) connected to the clock signal supply line L1 by utilizing the fact that the parasitic capacitance between the common source and drain terminals and the gate terminal of each transistor changes between the on and off states of the transistor. In other words, by controlling the power supply voltage applied to the gate terminals of multiple capacitance adjustment transistors (PM2, PM3, NM2, and NM3) connected in parallel, the total value of the parasitic capacitance of the on and off transistors can be adjusted.
[0041] For example, the inverted trimming signal TB2B <0> and inverted trimming signal TB2B <1> By setting either one or both of these to the voltage level of the reference voltage VSS, which is logic level 0 (i.e., L level), one or both of transistors PM2 and PM3 are turned on. This allows the load capacitance (PMOS load capacitance) connected to the clock signal supply line L1 to be increased.
[0042] Also, trimming signal TB2 <0> and trimming signal TB2 <1> By setting one or both of these to the power supply voltage VCC, which is logic level 1 (i.e., high level), one or both of transistors NM2 and NM3 are turned on. This allows the load capacitance (NMOS load capacitance) connected to the clock signal supply line L1 to be increased.
[0043] As described above, the semiconductor device 100 of this embodiment has an output circuit 21 provided on the first chip 11, which includes P-channel type MOS transistors (PM0, PM1) whose source is connected to the power supply voltage VCC supply line and whose drain is connected to the clock signal supply line L1, and N-channel type MOS transistors (NM0, NM1) whose source is connected to the reference voltage VSS supply line and whose drain is connected to the clock signal supply line L1. By selectively turning each transistor on or off according to the timing of the signal change of the clock signal CLK, the charging and discharging of the current in the clock signal supply line L1 can be adjusted, and the signal waveform of the clock signal CLK can be adjusted.
[0044] Therefore, according to the semiconductor device 100 of this embodiment, by adjusting the timing of the signal change of the clock signal CLK, it is possible to adjust the setup and hold time for data input from the first chip 11 to the second chip 12, even after the package assembly of the multi-chip semiconductor device.
[0045] Furthermore, the semiconductor device 100 of this embodiment has a load adjustment circuit 32 provided on the second chip 12, which includes transistors (PM2, PM3, NM2, and NM3) whose source and drain are connected to the clock signal supply line L1. By controlling the gate voltage to selectively turn each transistor on or off, the load capacitance connected to the clock signal supply line L1 can be changed. This makes it possible to adjust the data setup and hold time not only on the first chip 11 but also on the second chip 12.
[0046] This disclosure is not limited to the embodiments described above. For example, the embodiments described above describe a case in which two sets of transistor pairs (PM0 and NM0, PM1 and NM1) are provided, each consisting of a P-channel MOS transistor whose source is connected to the power supply voltage VCC and whose drain is connected to the clock signal supply line L1, and an N-channel MOS transistor whose source is connected to the reference voltage VSS and whose drain is connected to the clock signal supply line L1. However, the number of transistor pairs having such a configuration is not limited to this, and there may be three or more, or only one.
[0047] Furthermore, in the above embodiment, the transistors PM0, PM1, NM0, and NM1 constituting the output circuit 21, which is the output circuit of the clock signal CLK of the first chip 11, are connected to the clock signal supply line L1, and the signal waveform of the clock signal CLK is adjusted by adjusting the charging and discharging of the current in the clock signal supply line L1. However, alternatively, the data output circuit may have a similar configuration, and the setup-hold time may be adjusted by changing the charging and discharging of the current in the data supply line. Similarly, the load adjustment circuit 32 in the second chip 12 may be configured to adjust the setup-hold time by changing the load capacitance connected to the data supply line.
[0048] Furthermore, in the above embodiment, the output circuit 21 of the first chip 11 has the above configuration, and the load adjustment circuit 32 of the second chip 12 also has the above configuration, so that it is possible to adjust the data setup and hold time on both the first chip 11 and the second chip 12. However, it is not necessarily required that both configurations be present, and it is sufficient to have at least one of the above configurations of the output circuit 21 and load adjustment circuit 32, and to be configured so that the setup and hold time can be adjusted on either the first chip 11 side or the second chip 12 side.
[0049] [Note] This specification discloses the following configuration:
[0050] (Composition 1) A multi-chip semiconductor device having a first chip and a second chip connected to each other via a signal supply line, wherein the first chip includes an output circuit including at least one pair of transistors: a first P-channel transistor whose source is connected to a supply line for a first voltage and whose drain is connected to the signal supply line, and a second N-channel transistor whose source is connected to a supply line for a second voltage lower than the first voltage and whose drain is connected to the signal supply line; a control circuit for controlling the on and off of the first and second transistors; and an instruction receiving unit for receiving instructions for controlling the on and off of the first and second transistors.
[0051] (Configuration 2) The semiconductor device according to configuration 1, wherein the control circuit controls the first transistor and the second transistor to be turned on and off in a complementary manner.
[0052] (Composition 3) A semiconductor device according to configuration 1 or 2, wherein the first voltage is a power supply voltage, the second voltage is a reference voltage, and the output circuit adjusts the charging and discharging of the signal supply line in accordance with the on and off control of the first transistor and the second transistor by the control circuit.
[0053] (Composition 4) The semiconductor device according to configuration 3, wherein the signal supply line is a supply line that supplies a clock signal from the first chip to the second chip, and the output circuit changes the timing of the signal change of the clock signal by adjusting the charging and discharging of the signal supply line.
[0054] (Composition 5) The instruction receiving unit is comprised of an electronic fuse or an MTP (Multiple Time Programmable) memory, as described in any one of configurations 1 to 4.
[0055] (Composition 6) The semiconductor device according to any one of configurations 1 to 5, wherein the second chip includes an input circuit that receives a signal input from the signal supply line, and a load adjustment circuit that includes one or more capacitive elements connected to the signal supply line and is configured to adjust the load capacitance connected to the signal supply line.
[0056] (Composition 7) The semiconductor device according to configuration 6, wherein the one or more capacitive elements are composed of one or more MOS transistors whose sources and drains are connected to each other, and the load adjustment circuit adjusts the load capacitance connected to the signal supply line by controlling the gate voltage of the MOS transistors. [Explanation of Symbols]
[0057] 100 Semiconductor Equipment 11 First chip 12 Second chip 21 Output Circuit 22 Output control circuit 23. Trimming Circuit 31 Input Circuit 32 Load adjustment circuit 33. Trimming Circuit
Claims
1. A multi-chip semiconductor device having a first chip and a second chip connected to each other via a signal supply line, The first chip is, An output circuit comprising at least one pair of transistors, consisting of a first P-channel transistor whose source is connected to a supply line for a first voltage and whose drain is connected to the signal supply line, and a second N-channel transistor whose source is connected to a supply line for a second voltage lower than the first voltage and whose drain is connected to the signal supply line, A control circuit for controlling the on and off states of the first transistor and the second transistor, An instruction receiving unit that receives instructions for controlling the on and off states of the first transistor and the second transistor, Semiconductor device.
2. The semiconductor device according to claim 1, wherein the control circuit controls the first transistor and the second transistor to be switched on and off in a complementary manner.
3. The first voltage is the power supply voltage, The aforementioned second voltage is a reference voltage, The semiconductor device according to claim 1, wherein the output circuit adjusts the charging and discharging of the signal supply line in accordance with the on / off control of the first transistor and the second transistor by the control circuit.
4. The signal supply line is a supply line that supplies a clock signal from the first chip to the second chip. The semiconductor device according to claim 3, wherein the output circuit changes the timing of the signal change of the clock signal by adjusting the charging and discharging of the signal supply line.
5. The semiconductor device according to claim 1, wherein the instruction receiving unit is composed of an electronic fuse or an MTP (Multiple Time Programmable) memory.
6. The second chip is, An input circuit that receives a signal input from the aforementioned signal supply line, A load adjustment circuit includes one or more capacitive elements arranged to be connectable to the signal supply line, and is configured to adjust the load capacitance connected to the signal supply line, A semiconductor device according to claim 1, having the following features.
7. The one or more capacitive elements are composed of one or more MOS transistors whose sources and drains are connected to each other. The load adjustment circuit adjusts the load capacitance connected to the signal supply line by controlling the gate voltage of the MOS transistor. The semiconductor device according to claim 6.