System and method for controlling devices in superconducting circuits

Abstract

Reset the superconducting flux storage device and the digital-to-analog converter (DAC) in a superconducting integrated circuit. [Solution] A system including a superconducting integrated circuit and a controller operates to reset each of the multiple flux storage devices by applying one or more pulses to each of the multiple flux storage devices of the superconducting integrated circuit via one of the multiple addressing lines for each power level in a sequence of discrete power levels on one of the multiple power lines.

Description

[Technical Field]

[0001] Technical field This disclosure relates, in general, to systems and methods for addressing devices in superconducting circuits, and more specifically, to systems and methods for resetting superconducting flux storage devices and digital-to-analog converters (DACs) in superconducting integrated circuits. [Background technology]

[0002] background Superconducting integrated circuits Superconductivity is a set of physical properties observed in materials in which the electrical resistance of the material disappears and magnetic flux fields are driven out of the material. Materials exhibiting these properties are referred to in this application as superconductors. Materials exhibiting these properties are also referred to in this application as superconducting materials. Superconductors typically have a characteristic critical temperature at which the electrical resistance of the superconductor drops to zero. The current in a loop of a superconducting material can be sustained indefinitely without a power source.

[0003] A superconducting integrated circuit is an integrated circuit that contains superconducting materials. Superconducting materials are materials that become superconducting below a critical temperature. For example, niobium is a superconducting material that becomes superconducting below 9.2K. [Overview of the project] [Means for solving the problem]

[0004] overview According to the embodiment, a method for operating a system, the system comprising a superconducting integrated circuit and a controller, the superconducting integrated circuit comprising a plurality of flux storage devices, each of the plurality of flux storage devices comprising a superconducting loop interrupted by its respective composite Josephson junction, each composite Josephson junction comprising each pair of Josephson junctions, each of the plurality of flux storage devices being communicatively coupled to each of a plurality of addressing lines and each of a plurality of power lines, the method being performed by the controller, the method comprising: estimating the worst asymmetry between the Josephson junctions of each pair of Josephson junctions for the plurality of flux storage devices; estimating the mean critical current for the plurality of flux storage devices; and determining the starting level for the current on each of a plurality of power lines for each of the plurality of flux storage devices, A method is provided which includes determining the starting level, at least in part, based on the worst asymmetry and mean critical current; determining the power level increment; generating a sequence of discrete power levels, the sequence including a positive power level between the starting level and zero, which decreases by the power level increment; and a negative power level between the additive inverse of the starting level and zero, which increases by the power level increment, with the positive and negative power levels alternating in the generated sequence of discrete power levels; and for each power level in the sequence of discrete power levels, resetting each of the plurality of flux storage devices by applying one or more pulses through one of a plurality of addressing lines to each of the plurality of flux storage devices.

[0005] In other embodiments, the method may further include checking a superconducting integrated circuit for reset errors and updating the start level if a reset error is detected; for a plurality of flux storage devices, estimating the worst asymmetry between each pair of Josephson junctions of a Josephson junction may include determining the variation of the respective critical current of each of the Josephson junctions in or adjacent to the superconducting integrated circuit; determining the variation of the respective critical current of each of the Josephson junctions in or adjacent to the superconducting integrated circuit may include determining the variation of the respective critical current of each of the Josephson junctions in or adjacent to the superconducting integrated circuit at room temperature; for each power level of a sequence of discrete power levels, applying one or more pulses to each of the composite Josephson junctions of each of the plurality of flux storage devices via one of each of the plurality of addressing lines simultaneously; Resetting each of the multiple flux storage devices by applying one or more pulses to each of the composite Josephson junctions of each of the multiple flux storage devices via one of the multiple addressing lines for each power level of a discrete power level sequence may include resetting a superconducting digital-to-analog converter (DAC) by applying one or more pulses to each of the composite Josephson junctions of each of the multiple flux storage devices via one of the multiple addressing lines for each power level of a discrete power level sequence, and resetting a superconducting DAC by applying one or more pulses to each of the composite Josephson junctions of each of the multiple flux storage devices via one of the multiple addressing lines for each power level of a discrete power level sequence,Resetting a superconducting DAC that includes a loop of superconducting material interrupted by an inductance, wherein the inductance is at least one of the lumped element inductance, distributed inductance, kinetic inductance and intrinsic inductance of the loop of superconducting material, and for each power level of a sequence of discrete power levels, resetting a superconducting DAC that includes a loop of superconducting material interrupted by an inductance by applying one or more pulses to each composite Josephson junction of each of a plurality of flux storage devices via one of a plurality of addressing lines, and for each power level of a sequence of discrete power levels, resetting a superconducting DAC that includes a loop of superconducting material interrupted by an inductance Resetting a superconducting DAC by applying one or more pulses to the junction via one of the multiple addressing lines may include, for each power level in a sequence of discrete power levels, resetting a superconducting DAC by applying one or more pulses to each composite Josephson junction of each of the multiple flux storage devices via one of the multiple addressing lines, where the superconducting DAC is one of the multiple superconducting DACs, each of the multiple superconducting DACs is communicably coupled to a pair of addressing lines from the multiple addressing lines, and an operating superconducting DAC is addressable by a pair of addressing lines, each addressing line in a pair of addressing lines may be shared with at least one other superconducting DAC, and determining the starting level for the current on one of the multiple power lines of each of the multiple flux storage devices may include determining the starting level for the current on one of the multiple power lines, each power line from the multiple power lines may be shared with at least one other superconducting DAC, for each power level in a sequence of discrete power levels,Resetting each of the multiple flux storage devices by applying one or more pulses to each of their composite Josephson junctions via one of the multiple addressing lines may include, for each power level in a sequence of discrete power levels, resetting each of the multiple flux storage devices to its ground state by applying one or more pulses to each of their composite Josephson junctions via one of the multiple addressing lines.

[0006] In one embodiment, a method is provided for operating a system, the system comprising a superconducting integrated circuit and a controller, the superconducting integrated circuit comprising a plurality of flux storage devices, each of the plurality of flux storage devices being commutatably coupled to each pair of a plurality of addressing lines and each of a plurality of power lines, the method being performed by the controller, the method comprising dividing the plurality of addressing lines into one or more groups of addressing lines, and for each pair coupling of the addressing line group, applying each sequence of pulses to each addressing line of each pair coupling of the addressing line group to reset one or more of the plurality of flux storage devices.

[0007] In other embodiments, resetting a flux storage device among a plurality of flux storage devices may include resetting a superconducting digital-to-analog converter (DAC), resetting a superconducting DAC may include resetting a superconducting DAC that includes a loop of superconducting material that is interrupted by an inductance, the inductance being at least one of lumped element inductance, distributed inductance, kinetic inductance and intrinsic inductance of the loop of superconducting material, resetting a superconducting DAC that includes a loop of superconducting material that is interrupted by an inductance may include resetting a superconducting DAC, the superconducting DAC is inductively coupled to a programmable device via at least a portion of the inductance, resetting a superconducting DAC may include resetting a superconducting DAC to a ground state, dividing a plurality of addressing lines into one or more groups of addressing lines, Determining the number m of multiple addressing lines that are operated simultaneously may include determining the number m of multiple addressing lines that can be operated to reset one or more of the multiple flux storage devices while maintaining the temperature of the superconducting integrated circuit below a predetermined temperature threshold; determining the number m of multiple addressing lines that are operated simultaneously may include determining the number m of multiple addressing lines that can be operated to reset the multiple flux storage devices within a duration of less than a predetermined duration threshold; and resetting one or more of the multiple flux storage devices by applying a sequence of pulses to each addressing line of each pair of addresses in the addressing line group may include applying a sequence of pulses to each addressing line of each pair of addresses in the addressing line group in succession.

[0008] In one embodiment, a method for operating a system is provided, the system comprising a superconducting integrated circuit and a controller, the superconducting integrated circuit comprising a plurality of flux storage devices, each of the plurality of flux storage devices being communicatively coupled to at least one of a plurality of addressing lines and one of a plurality of power lines, the method being performed by the controller, the method comprising the controller determining a first subset of the plurality of addressing lines and a second subset of the plurality of power lines, and the controller resetting a flux storage device among the plurality of flux storage devices by simultaneously activating the first subset of the plurality of addressing lines and the second subset of the plurality of power lines.

[0009] In another embodiment, resetting a flux storage device among a plurality of flux storage devices may include resetting a superconducting digital-to-analog converter (DAC), and resetting a superconducting DAC may include resetting a superconducting DAC that includes a loop of superconducting material that is interrupted by an inductance, the inductance being at least one of lumped element inductance, distributed inductance, kinetic inductance and intrinsic inductance of the loop of superconducting material, and resetting a superconducting DAC that includes a loop of superconducting material that is interrupted by an inductance may include resetting a superconducting DAC, the superconducting DAC may be inductively coupled to a programmable device via at least a portion of the inductance, and resetting a superconducting DAC may include resetting a superconducting DAC to its ground state.

[0010] In other embodiments, as will be apparent to those skilled in the art, the above-described features can be combined in any reasonable combination.

[0011] In drawings, the same reference numerals identify similar elements or actions. The size and relative position of elements in drawings are not necessarily proportional to the actual size. For example, the shapes and angles of various elements are not necessarily proportional to the actual size, and some of these elements may be arbitrarily enlarged and positioned to improve the readability of the drawing. Furthermore, the specific shapes of elements as shown are not necessarily intended to convey any information about the actual shape of a particular element, but are selected solely to facilitate recognition in the drawing. [Brief explanation of the drawing]

[0012] A brief explanation of some of the figures in the drawing. [Figure 1] This is a schematic diagram showing an example of an implementation form of the superconducting DAC according to this disclosure. [Figure 2A] This is a plot of an example of a time-dependent signal applied to the power lines of a DAC according to the present disclosure. [Figure 2B] This is a plot of an example of a time-dependent signal applied to a composite Josephson junction (CJJ) loop of a DAC according to the present disclosure. [Figure 3A] This is a plot of an example of the sequence of current and magnetic flux changes during DAC reset according to this disclosure. [Figure 3B] This is a plot of another example of the sequence of current and magnetic flux changes during DAC reset according to the present disclosure. [Figure 3C] This is a flowchart illustrating an example implementation of a method for resetting the DAC set in a superconducting integrated circuit according to this disclosure. [Figure 4] This is a schematic diagram of an example of a DAC array implementation according to this disclosure. [Figure 5A] This is a plot of an example of a time-dependent signal applied to each power line of each DAC in a pair of DACs according to the present disclosure. [Figure 5B] Figure 5B of this disclosure shows an example plot of time-dependent signals applied to each CJJ loop of each DAC in the same pair of DACs. [Figure 6A]This is a plot of an example of a time-dependent signal applied to each power line of each DAC in a pair of DACs (DAC1 and DAC2) according to the present disclosure. [Figure 6B] This is a plot of an example of a time-dependent signal applied to the CJJ loop of the first DAC (DAC1) of the same pair of DACs referenced in Figure 6A of the present disclosure. [Figure 6C] This is a plot of an example of a time-dependent signal applied to the CJJ loop of the second DAC (DAC2) of the same pair of DACs referenced in Figures 6A and 6B of this disclosure. [Figure 7A] This is a plot of an example of a time-dependent signal applied to the power lines of a DAC according to the present disclosure. [Figure 7B] This is a plot of an example of a time-dependent signal applied to the CJJ loop of the same DAC referenced in Figure 7A of this disclosure. [Figure 8A] This is a plot of an example of a time-dependent signal applied to each power line of each DAC (DAC1 and DAC2) of a pair of DACs according to the present disclosure. [Figure 8B] This is a plot of an example of a time-dependent signal applied to the addressing lines (ADDR and TRIG) of DAC1 as referenced in Figure 6A of this disclosure. [Figure 8C] Figures 6A and 6B of this disclosure show plots of examples of time-dependent signals applied to the addressing lines (ADDR and TRIG) of DAC2. [Figure 9A] This is a flowchart illustrating an example of a method for resetting the set of DACs in a superconducting integrated circuit according to this disclosure. [Figure 9B] This is a table of example pulse sequences for the distributed annealing reset procedure shown in Figure 9A of this disclosure. [Figure 10A] This is a flowchart illustrating another example of a method for resetting the set of DACs in a superconducting integrated circuit according to this disclosure. [Figure 10B] This is a table of example pulse sequences for the distributed annealing reset procedure shown in Figure 10A of this disclosure. [Figure 11]This is a schematic diagram of an exemplary computing system, including a digital computer and an analog computer, as disclosed herein. [Modes for carrying out the invention]

[0013] Detailed explanation preamble In the following description, several specific details are included to give a full understanding of the various implementations and embodiments of the disclosure. However, those skilled in the art will see that embodiments can be carried out without one or more of these specific details or using other methods, components, materials, etc. In other cases, well-known structures relating to superconducting devices and integrated superconducting circuits are not illustrated or described in detail to avoid unnecessarily ambiguous descriptions of implementations or embodiments of the Method. Throughout this specification and the appended claims, one or more terms “elements” are used to include all such structures, systems and devices (but not limited to them) relating to superconducting circuits and integrated superconducting circuits.

[0014] Unless the context requires otherwise, throughout the following specification and claims, the term “includes” is synonymous with “inclusive,” and is inclusive or unrestricted (i.e., does not exclude additional non-enumerated elements or actions).

[0015] Throughout this specification, references such as “one embodiment,” “a certain embodiment,” “another embodiment,” “one example,” “a certain example,” “another example,” “one implementation,” and “another implementation” mean that the specific indicated feature, structure, or characteristic described in relation to an embodiment, example, or implementation is included in at least one embodiment, example, or implementation. Therefore, all occurrences of terms such as “in one embodiment,” “in a certain embodiment,” and “another embodiment” in various places throughout this specification do not necessarily refer to the same embodiment, example, or implementation. Furthermore, specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments, examples, or implementations.

[0016] It should be noted that, as used herein and in the appended claims, the singular forms “a,” “an,” and “it” include multiple references unless otherwise explicitly indicated. Therefore, for example, a reference to a readout system including a “superconducting resonator” includes a single superconducting resonator or two or more superconducting resonators. It should also be noted that the term “or” is generally used to include “and / or” unless otherwise explicitly indicated.

[0017] The headings given herein are for convenience only and do not imply any scope or meaning of the embodiments.

[0018] Superconducting flux storage device A superconducting integrated circuit (also referred to in this application as a superconducting chip) may include, for example, a quantum processor. The quantum processor may include a plurality of qubits and at least one coupling device that communicatively couples at least one pair of qubits from the plurality of qubits. The qubits and the coupling device can be controlled by adjusting a plurality of control parameters. In some implementations, the qubits may have six control parameters, and the coupling device may have a single control parameter.

[0019] When the number of devices on a superconducting integrated circuit is sufficiently small, the devices can be controlled by dedicated analog lines driven by electronics at room temperature. For quantum processors with tens, hundreds, or thousands of devices, using analog lines may become impractical, and it becomes desirable to implement the control circuits on top of the superconducting chip.

[0020] For example, a superconducting quantum processor can be programmed by a static flux bias applied to the superconducting loops in the qubits and coupling device of the superconducting quantum processor. A desired value of the static flux bias can be programmed into an on-chip control device using a relatively small number of control lines that transmit digital signals generated at room temperature.

[0021] On-chip control devices may include superconducting flux storage devices such as superconducting digital-to-analog converters (DACs) (also referred to in this application as flux DACs). Flux DACs can combine the functions of persistent memory and digital-to-analog conversion. In some implementations, flux DACs have dimensions on the order of 10 μm. Having several flux DACs attached to a single qubit in a quantum processor may set a lower limit on the qubit size and may affect possible qubit shapes, hardware graph topology, and processor architecture.

[0022] XYZ addressing of the magnetic flux DAC In an example of a quantum processor implementation, 512 qubits and associated coupling devices can be controlled by 4608 flux DACs. The XYZ addressing method allows the quantum processor to be controlled using only 56 lines. The processor can be arranged as an 8x8 array of tiles, each tile having 72 flux DACs. The flux DACs of each tile can be arranged in each 3-DAC bracket. One of each set of three DACs in the 3-DAC bracket can be selected using one of three lines (referred to in this application as address (ADDR) lines), and in an arrangement where 15 ADDR lines and 5 TRIG lines are used to address the DACs to the tiles, all three lines share another line (referred to in this application as a trigger (TRIG) line). An 8x8 tile array can be divided into 16 regions (referred to as power (PWR) regions in this application), and arranged to address 4608 flux DACs using a total of 30 ADDR lines, 10 TRIG lines, and 16 PWR lines. See, for example, Bunyk P. et al., “ARCHITECTURAL CONSIDERATIONS IN THE DESIGN OF A SUPERCONDUCTING QUANTUM ANNEALING PROCESSOR”, arXiv:1401.5504v1, 21 January 2014.

[0023] One example of an addressing method for DACs can be found in U.S. Patent No. 10,528,886 and U.S. Patent Application Publication No. 2021 / 0190885.

[0024] DAC Josephson junction asymmetry This technology includes a system and method for resetting one or more flux storage devices (e.g., flux DACs) in a superconducting integrated circuit. Resetting a flux storage device may include returning the device to its ground state.

[0025] In several implementations, a flux storage device includes one or more Josephson junctions. A Josephson junction may be a composite Josephson junction or a composite-composite Josephson junction. A composite Josephson junction (CJJ) includes two parallel electrical current paths, each interrupted by at least one Josephson junction. A composite-composite Josephson junction (CCJJ) is a composite Josephson junction that includes two parallel electrical current paths, with at least one of the two parallel electrical current paths interrupted by at least one composite Josephson junction.

[0026] The asymmetry of a pair of constituent Josephson junctions (for example, a pair of Josephson junctions that each interrupts one of the electrical parallel current paths in a composite Josephson junction of a flux storage device) can reset the storage device to a state other than the ground state. Resetting the storage device to a state other than the ground state can result in a reduction in the number of pulses that can be stored in the storage device. For this reason at least, resetting the flux storage device to the ground state is advantageous.

[0027] Resetting a flux storage device may involve transmitting a series of current and flux pulses to the device. Resetting a flux storage device may also involve repeating the transmission of a series of current and flux pulses for each of several power levels. The power level can be determined at least partially based on the circulating current of the flux storage device. Each iteration may reset each group of flux storage devices characterized by each junction asymmetry.

[0028] A superconducting quantum processor may include one or more flux storage devices. In some implementations, the flux storage device is a DAC. In some implementations, the superconducting quantum processor includes a superconducting integrated circuit, and the superconducting integrated circuit includes multiple on-chip DACs.

[0029] An on-chip DAC includes at least one DAC stage. In some implementations, the input signal to the on-chip DAC can be represented in binary form (i.e., using only the binary numbers "0" and "1"). If each DAC stage of the on-chip DAC has only two states (e.g., "0" and "1"), the resolution of the on-chip DAC can be represented in terms of multiple stages. For example, an 8-stage DAC can be represented in terms of 2 8 = 256 discrete values ​​can be stored. The following description refers to a single-stage DAC, but this technique can be applied to each stage of a multi-stage DAC. In particular, the following description refers to resetting a DAC or sharing lines between DACs, but this term is used to include different stages of the same multi-stage DAC.

[0030] An on-chip DAC can be used, for example, in the operation of a superconducting quantum processor. A typical scenario in the operation of a superconducting quantum processor may include a) initialization of the superconducting quantum processor and b) evolution of the superconducting quantum processor. Initialization of the superconducting quantum processor may include the initialization of multiple DACs. Initialization of the DAC may include initializing the DAC to an initial state (e.g., the ground state). Initialization of the DAC is also referred to in this application as resetting the DAC. Evolution of the superconducting quantum processor may include programming multiple DACs to a state different from the initial state. Evolution of the superconducting quantum processor is also referred to in this application as annealing. However, other types of evolution (e.g., evolution of a series of gates on one or more qubits in a gate model processor) may be performed by the quantum processor.

[0031] Annealing Reset Figure 1 is a schematic diagram of an example of an implementation of the superconducting DAC100 according to this disclosure. The superconducting DAC100 may be an element of an input / output system. The input / output system may be an element of a quantum computer or a hybrid digital / quantum computer system. The input / output system may write data to a quantum processor and read data from a quantum processor.

[0032] The DAC100 includes a superconducting loop 102. The superconducting loop 102 may contain or consist of a superconducting material. The superconducting material may be a superconducting metal (e.g., niobium, aluminum, etc.). Magnetic flux can be stored using the superconducting loop 102. Magnetic flux can be compressed into the superconducting loop 102 of the DAC100 with multiple magnetic flux quanta.

[0033] The superconducting loop 102 of the DAC100 is interrupted by an inductance 104. The inductance 104 may be the lumped element inductance, distributed inductance, kinetic inductance, intrinsic inductance, or a combination thereof of the loop 102. The DAC100 can be inductively coupled to a device (not shown in Figure 1) by the inductance 104 and mutual inductance M. The device may be a programmable device. The device may be a tunable device. The device may be, for example, a qubit or a coupled device.

[0034] Furthermore, the superconducting loop 102 of the DAC 100 is interrupted by a composite Josephson junction (CJJ) 106. The CJJ 106 includes two electrically parallel superconducting paths, each of which is interrupted by Josephson junctions 108 and 110.

[0035] A power line (also referred to in this application as a PWR line or simply PWR) is superconductively coupled to the superconducting loop 102 of the DAC 100 at nodes 112 and 114. Current enters from the PWR line at node 112 and exits the superconducting loop 102 at node 114.

[0036] CJJ106 interrupts the superconducting loop 102 between node 116 and node 118. The inductance 120 between node 116 and Josephson junction 108 is inductively coupled to the ADDR line 122. The inductance 124 between node 116 and Josephson junction 110 is inductively coupled to the TRIG line 126. The ADDR line and TRIG lines 122 and 126 are addressing lines. See, for example, the description of XYZ addressing of a flux DAC earlier in this application. The ADDR line, TRIG line and PWR line may be collectively referred to as control lines. The ends 128 and 130 of the arrows indicate the direction of the magnetic flux in the superconducting loop 102 and CJJ106 to the plane of Figure 1, respectively.

[0037] In several implementations of the DAC100, the Josephson junctions 108 and 110 are asymmetric. Junction asymmetry means a difference in critical current between a pair of Josephson junctions. Junction asymmetry can also mean a difference in critical current between a pair of Josephson junctions in a composite Josephson junction (e.g., Josephson junctions 108 and 110).

[0038] The difference in critical current between a pair of Josephson junctions may be at least partially dependent on the difference in size between the Josephson junctions. In other configurations, Josephson junctions may have different critical currents even if they are at least substantially the same size. Asymmetry can be introduced, for example, during manufacturing. In some configurations, junction asymmetry may be intentionally introduced, but in other configurations, junction asymmetry may be unintentional and may be due to, for example, limitations in the precision of the manufacturing technique, or introduced by natural variations in materials or contamination of manufacturing equipment.

[0039] In this application, a CJJ having asymmetry of its Josephson junction means a CJJ containing two parallel electrical current paths, each parallel current path being interrupted by each Josephson junction, and the critical current of the Josephson junction that interrupts one of the two parallel current paths of the CJJ is not the same as the critical current of the Josephson junction that interrupts the other of the two parallel current paths of the CJJ.

[0040] The critical current has a specific meaning for Josephson junctions known to those skilled in the art. The equations controlling the dynamics and Josephson effect of a Josephson junction include the following:

number

[0041] current I cis a constant called the critical current of the Josephson junction. These equations can be found, for example, in Barone, A., and Paterno, G., Physics and Applications of the Josephson Effect, (1982), John Wiley & Sons, ISBN 978-0-471-01469-0. The critical current is the current in a superconducting material that is normal (i.e., not superconducting) and superconducting at a given temperature in the absence of an external magnetic field. See, for example, Critical Current. (nd) McGraw-Hill Dictionary of Scientific & Technical Terms, 6E. (2003) (retrieved from https: / / encyclopedia2.thefreedictionary.com / Critical+Current on October 23, 2018).

[0042] In some cases, junction asymmetry can be undesirable. For example, junction asymmetry can introduce uncertainty in the initialization of a DAC having a CJJ with an asymmetric Josephson junction. This uncertainty in DAC initialization can lead to the DAC being initialized to a state other than the desired state (e.g., a state other than the ground state). This uncertainty in DAC initialization can lead to errors in the evolution of a superconducting quantum processor (whether or not the evolution involves programming the DAC to a state different from its initial state).

[0043] One method to eliminate or at least reduce reset errors (e.g., reset errors caused by junction asymmetry) is to check each DAC bit for reset errors. The drawback of this method is that it can be very time-consuming. Each check is time-consuming, and there may be multiple DACs to check.

[0044] This technology can reduce the time required to eliminate or at least reduce reset errors. The technology includes transmitting a predetermined pulse sequence to an on-chip DAC to reliably reset the DAC to an initial state (e.g., ground state), even in the presence of junction asymmetry. In fact, some degree of junction asymmetry is likely to exist in most DACs.

[0045] The technology described in this application can be used to reliably reset a DAC if a) the accuracy with which the current of a control line (e.g., a PWR line) can be set is of the order of at least one magnitude greater than the change in the circulating current of the DAC body, and the change in the circulating current is due to a change in one flux quantum in the flux stored in the DAC, and b) the change in the circulating current is of the order of at least one magnitude greater than i) noise of the DAC body and ii) the effective temperature reached by the DAC due to thermal energy released while exceeding the DAC critical current.

[0046] In several implementations of the systems and methods described below, on-chip DACs with a high asymmetry of up to 10% can be reset. Furthermore, for example, in the case of devices with very high asymmetry, this technique can be used in combination with the inspection and recovery of specific devices. Resetting a DAC means initializing all DACs to the same initial state or an initial state having the same value for a predetermined required precision. In some implementations, this may be the ground state, although other initial states may be used.

[0047] Figure 2A is a plot 200a of an example of a time-dependent signal 202 applied to the power lines of the DAC according to this disclosure. The signal 202 may be a current applied to the body of the DAC.

[0048] Figure 2B is a plot 200b of an example of a time-dependent signal 214 applied to the CJJ loop of a DAC according to this disclosure (e.g., the superconducting DAC 100 in Figure 1). The signal 214 may be applied to the CJJ loop by one or both of the addressing lines (e.g., the ADDR line and TRIG lines 122 and 126 in Figure 1). In normal operation, the signal 214 is typically applied to the CJJ loop by both addressing lines. The signal 214 can be proportional to the total magnetic flux applied to the CJJ loop. In some implementations, the signals applied to the ADDR line and the TRIG line may be the same as each other. In other implementations, the signals applied to the ADDR line and the TRIG line may differ only in sign.

[0049] Plots 200a and 200b in Figures 2A and 2B contain seven time intervals 204a, 204b, 204c, 204d, 204e, 204f, and 204g (collectively referred to as time interval 204), respectively. Adjacent time intervals in time interval 204 are demarcated from each other by vertical dashed lines. The polarity of signal 202 is reversed for each time interval. For example, the peak current 206 in time interval 204a is positive, and the peak current 208 in time interval 204b is negative.

[0050] The peak current can vary with each time interval. For example, there is a change in peak current 210a from time interval 204b to time interval 204c, a change in peak current 210b from time interval 204d to time interval 204e, and a change in peak current 210c from time interval 204f to time interval 204g. In some implementations, at least two of the changes (e.g., two of changes 210a, 210b, and 210c) may be the same. In some implementations, changes 210a, 210b, and 210c are the same as each other.

[0051] Plot 200a in Figure 2A shows the maximum value I at peak current 206. MAX This is an example of a power current sequence from zero at point 212. In some implementations, changes 210a, 210b, and 210c are the same, and Δ PWRThis can be shown as follows. Each set of pulses can be applied to the CJJ loop of the DAC at each time interval. In some implementations, each set of pulses consists of a single pulse. The pulse shapes in the pulse sets in Figures 2A and 2B are examples of shapes. Various other shapes are used in other implementations. The peak amplitude of each set of pulses may differ from set to set. In some implementations, for each power current, each set of pulses contains each negative peak whose magnitude is at least approximately equal to each positive peak.

[0052] Plot 200a in Figure 2A includes a set of seven pulses 212a, 212b, 212c, 212d, 212e, 212f, and 212g with varying amplitudes. In an example of an implementation (for example, the implementation shown in Figure 2A), the amplitude of the set of seven pulses (i.e., I in a time interval 204) PWR The peak value of has the following column of values ​​(+0.45, -0.45, +0.3, -0.3, +0.15, -0.15, 0.0).

[0053] The first value in the column is also referred to as the starting level in this application.

[0054] Plot 200b in Figure 2B includes a set of seven pulses 216a, 216b, 216c, 216d, 216e, 216f, and 216g with at least approximately equal amplitude. Plot 200b includes an additional pulse 218 with a lower amplitude after the end of time interval 204g. The additional pulse 218 may cause the final state of the DAC to stabilize. For example, the additional pulse may cause the final state of the DAC to be the total flux quantum (Φ0) state in the superconducting loop 102. The half-flux quantum (Φ0 / 2) state in the superconducting loop 102 may be an intermediate state used for resetting and programming the DAC. The half-flux quantum state may be stable when there are few pulses in the DAC, and may gradually become more unstable as the number of pulses increases.

[0055] Figure 3A is a steady-state level plot 300a for the positive power line current according to the present disclosure. The positions above the plot 300a are called coordinates. The coordinates can be the operating points of the flux DAC (e.g., the superconducting DAC 100 in FIG. 1). For a given power level, both the power current and the flux are initialized to zero at the coordinate 302(0, 0). The power current is increased to +I along the trajectory 304(0, I) to the coordinate 306(0, +I). MAX ) to the trajectory 304(0, I PWR ) along +I MAX . The flux is increased to +Φ along the trajectory 308(Φ, +I) to the coordinate 310(+Φ……

[0056] Figure 3B is a steady-state level plot 300b for the negative power line current according to the present disclosure. The positions above the plot 300b are called coordinates. The coordinates can be the operating points of the flux DAC (e.g., the superconducting DAC 100 in FIG. 1). For a given power level, both the power current and the flux are initialized to zero at the coordinate 328(0, 0). The power current is decreased to -I along the trajectory 330(0, I) to the coordinate 332(0, -I MAX ) along the trajectory 330(0, I PWR ) to -I​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​MAX It decreases to the magnetic flux, coordinate 336(+Φ MAX ,-I MAX ) to orbit 334(Φ, -I MAX ) along +Φ MAX It increases to the power current, coordinate 340(+Φ MAX , +I MAX ) to orbit 338(+Φ MAX , I PWR ) along +I MAX It increases to the magnetic flux, coordinate 344(-Φ MAX , +I MAX ) to orbit 342(Φ, +I MAX ) along -Φ MAX It decreases to the power current, coordinate 348(-Φ MAX ,-I MAX ) to orbit 346(-Φ MAX , I PWR ) along -I MAX It decreases to the magnetic flux, coordinate 332(0, -I MAX ) to orbit 350(Φ, -I MAX It increases to zero along the line. Finally, the power current is set to the orbit 352(0, I) to coordinate 328(0, 0). PWR Reset to zero according to the specified parameters.

[0057] The circulating current in a superconducting DAC can be influenced by the DAC's magnetic flux state, which is the number of magnetic flux quanta stored in the main loop. A change in the DAC's magnetic flux state due to a single pulse can be expressed as equivalent to a change in the circulating current given by the following: I CIRC =Φ0 / L BODY Here, Φ0 is the magnetic flux quantum, and L BODY This is the inductance of the DAC, which can be expressed as follows: L BODY =L S +L cjj1 L cjj2 / (L cjj1 +L cjj2 ) Here, L S This is the inductance 104 in Figure 1, L cjj1 This is the inductance 120 in Figure 1, Lcjj2 This is the inductance 124 in Figure 1.

[0058] The CJJ of the DAC contains two parallel current paths, each interrupted by one of the pair of Josephson junctions. The asymmetry between the Josephson junctions of the pair is as follows: current I ASYM It can be expressed in relation to this. I ASYM =γ(I C1 +I C2 ) Here, γ is the degree of asymmetry, and I C1 and I C2 These are the critical currents of each part of the Josephson junction.

[0059] During each time interval of 204, the current applied to the power line can be compared with the following currents representing the programmed DAC state.

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[0060] Generally, since the state of the DAC may be unknown, the case where n > 0 (where n represents the state of the DAC) when the peak current applied to the power line is positive can be handled with a reset signal. Similarly, the case where n < 0 when the peak current is negative can be handled. Below, only the case where n > 0 will be explained.

[0061] In the example, the first peak is positive, and the peak current I peak The time interval 204a in Figure 2A corresponds to a peak current of 206. The behavior of the superconducting integrated circuit may be as follows. 1.

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[0062] Another example is when the first peak is negative and the peak current I peak The time interval 204b in Figure 2A corresponds to a peak current of 208. The behavior of the superconducting integrated circuit in this example can be similar to the behavior described in the example above.

[0063] I MAX It starts with Δ PWR CIRC Repeating time intervals, each with a power level decreasing by 2, can reset a group of DACs with different asymmetries.

[0064] In fact, I MAX Generally, this is greater than the maximum asymmetric current on the chip, or at least greater than the asymmetric current of the DACs on the chip in the set of DACs that should be reset.

[0065] ​To reset the DAC, a current I is applied to the CJJ loop of the DAC PWR and is followed immediately by a current of -|I PWR |.

[0066] The increment Δ PWR can be expressed as follows. Δ PWR = α × Φ0 / L BODY In some implementations, it is desirable to satisfy the constraint α < 0.5.

[0067] Δ PWR and I MAX being determined, the method generates a list of N + 1 power levels from I MAX down to zero as follows. {+I PWR (0), -I PWR (0), +I PWR (1), -I PWR (1),... +I PWR (N - 1), -I PWR (N - 1), +I PWR (N), -I PWR (N), 0.0} Here, I PWR (0) = I MAX , I PWR (N) = I PWR (N - 1) - Δ PWR and I PWR (N) = Δ PWR .

[0068] The length of the list may depend on the values of I MAX and Δ PWR and the time required to reset the DAC on the chip may depend on the length of the list. A longer list generally results in a longer time required to reset the DAC. It is beneficial to generate the shortest list necessary to recover the maximum number of DACs.

[0069] In some implementations, a trade-off can be made between the length of the power level list and the number of resettable DACs to reduce the total time required to reset all DACs. In this case, by forming an appropriate sequence of pulses, MAX DACs with a greater asymmetry can be individually reset (recovered).

[0070] One approach is to generate a list of power-currents based on room-temperature measurements and then improve the list using low-temperature measurements.

[0071] Figure 3C is a flowchart illustrating an example implementation of method 300c for resetting the set of DACs in a superconducting integrated circuit according to the present disclosure. Those skilled in the art will see that in alternative implementations, certain operations may be omitted and / or additional operations may be added, although method 300c includes operations 354-372. Those skilled in the art will see that the order in which the operations are illustrated is shown for illustrative purposes only and may vary in alternative implementations.

[0072] In 354, we invoke method 300c. In some implementations, we invoke method 300c when the superconducting integrated circuit is cooled to a temperature in which its elements are superconducting, the readout circuit is operational, and the superconducting integrated circuit is ready for calibration.

[0073] In 356, the system determines the level of junction asymmetry γ based on an estimate of the asymmetry between the critical currents of the pair of Josephson junctions at the CJJ of the set of DACs. In some implementations, the estimate is an estimate of the worst (i.e., maximum or upper limit) asymmetry. The level of junction asymmetry γ can be determined using room temperature measurements. The worst junction asymmetry γ for the chip can be estimated by a) measuring the variation (e.g., standard deviation) of the critical current at room temperature of a Josephson junction (or Josephson junction inspection structure) in or near a superconducting integrated circuit, and then b) estimating the worst junction asymmetry. In some implementations, estimating the worst junction asymmetry involves multiplying the standard deviation by 6. In some implementations, due to on-chip variation, the junction asymmetry value can be in the range of -0.15 < γ < 0.15.

[0074] In 358, the system is the average critical current of the set of DACs corresponding to the sum of the critical currents of the two junctions in CJJ106.

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[0075] In 360, the system measures parameters that characterize a subset of DACs. In some implementations, the subset of DACs includes DACs with at least a larger body inductance. The body inductance of a DAC is generally intentionally known. The parameter is the cyclic bit weight I cThis can include the DAC critical current and the mutual inductance between the element analog lines (i.e., the ADDR line and / or TRIG line) and the CJJ106. The DAC critical current can be used to improve the estimate of the average critical current obtained in 358.

[0076] In 362, the system operates at power level I PWR Generate a list of positive power levels. MAX It starts at -I and gradually decreases to zero. Negative power levels are -I PWR It starts at and gradually increases to zero. An example of a list of power levels is shown below. {+0.45, -0.45, +0.3, -0.3, +0.15, -0.15, 0.0}

[0077] At 364, the system applies a CJJ reset pulse to the first power level, resetting one or more DACs in the set of DACs on the chip. At 366, the system determines if there is another power level. If there is another power level ("yes"), the method returns control to 364, and the system applies another CJJ reset pulse to the next power level.

[0078] If a reset pulse is applied to all power levels and there is no next power level ("no"), the procedure proceeds to 368, and the system checks for a reset error. In 370, the system determines whether there is a reset error. If a reset error is detected, the procedure proceeds to I MAX The process can be repeated for higher values. One or more iterations can be performed until no more reset errors are detected. If a reset error is detected ("yes"), control is returned to 362 and the system generates another list of power levels. If no reset error is detected ("no"), the method proceeds to 372 and the method terminates.

[0079] The benefits of the technology described in this application include: initializing the stages belonging to each DAC in a set of DACs to be reset to the same state, thereby eliminating or at least reducing errors in the initialization of the DACs; and initializing each DAC in a set of DACs to be reset to its respective exact ground state (i.e., the state corresponding to the global minimum of the DAC's potential energy).

[0080] Distribution annealing reset A superconducting circuit may include one or more multistage DACs. In one implementation, the multistage DAC is a four-stage DAC. Each stage of the multistage DAC can be controlled by the coupling of each pair of power lines (PWR) and addressing lines (ADDR and TRIG). The four stages of a four-stage DAC can be controlled by the same PWR line. In some implementations, one pair of addressing lines (ADDR and TRIG) can control the two higher stages of the four-stage DAC, and the other pair of addressing lines (ADDR and TRIG) can control the two lower stages. In other implementations, one of the addressing lines (ADDR or TRIG) that controls the two higher stages of the four-stage DAC can also be used to control the two lower stages.

[0081] Superconducting circuits can be, for example, quantum processors or parts of quantum processors.

[0082] Figure 4 is a schematic diagram of an example implementation of the DAC array 400 (also called a DAC bracket) according to this disclosure. The DAC array 400 includes N DACs 400-1, 400-2, ..., 400-N (where N ≥ 2). The DAC array 400 in the example implementation of Figure 4 includes at least 3 DACs. When N = 3, the DAC array 400 includes 3 DACs.

[0083] Each DAC in the DAC array 400 may be a superconducting DAC (for example, the superconducting DAC 100 in Figure 1). For example, DAC 400-1 includes a superconducting loop 402, an inductor 404, and a CJJ 406.

[0084] Each DAC in the DAC array 400 can be controlled by the coupling of each pair of power lines and addressing lines. For example, DAC400-1 can be controlled by power line 408 (PWR1) and addressing lines 410 (ADDR1) and 412 (TRIG1). In other implementations, each DAC can be controlled by a power line and a single addressing line or a power line and multiple addressing lines. In some implementations, power lines can be shared among multiple DACs, and a single addressing line or multiple addressing lines can be shared among multiple DACs.

[0085] Each DAC in the DAC array 400 may be a multistable radio frequency superconducting quantum interference device (RF-SQUID) whose metastable state corresponds to an integer flux quantum stored in the body of the RF-SQUID (e.g., loop 102 of the superconducting DAC 100 in Figure 1). The superconducting DAC is also referred to in this application as a flux storage device and a programmable magnetic memory. During programming, the state of the DAC can be adjusted by an integer flux quantum of positive or negative polarity up to a predetermined maximum single flux quantum (SFQ).

[0086] The RF-SQUID can also be reset to a zero state. The zero state can be the ground state. Programming the DAC to a desired state typically starts from the zero state. The zero state can be achieved through a reset procedure. The DAC can be reset from a known or unknown state.

[0087] One method for resetting a DAC involves setting the power line (PWR) to zero and simultaneously applying pulses to the addressing lines (ADDR and TRIG) with an amplitude large enough to ensure that the DAC is in a transition state that "deprograms" the DAC until it reaches the lowest energy zero SFQ state where the circulating current is zero. During the procedure, DACs communically coupled to the same addressing lines can receive the same signal and are simultaneously resettable.

[0088] In some implementations, multiple DACs are reset by activating power lines and addressing lines that are communicatively coupled to the DACs, thereby simultaneously applying a sequence of pulses to the DACs. In some implementations, resetting the DACs may include applying a sequence of pulses at different power levels. Applying a sequence of pulses at different power levels can increase the number of pulses applied during the DAC reset.

[0089] Resetting a DAC may involve applying a sequence of pulses exceeding the critical current of the DAC, which can cause the DAC to transition from a superconducting state to a normal (non-superconducting) state. Repeated transitions between the superconducting and normal states can cause an increase in the temperature of the superconducting integrated circuit. This temperature increase can affect the performance of the superconducting integrated circuit, for example, during calibration and / or operation.

[0090] One way to mitigate the effects of rising temperatures is to allow the superconducting integrated circuit to dissipate the heat resulting from repeated transitions between the superconducting and normal states, and to wait at least a sufficient amount of time for the superconducting integrated circuit to return to a reference temperature. The reference temperature is the operating temperature of the superconducting integrated circuit before the DAC is reset. In practice, the waiting time can be on the order of a few seconds.

[0091] Eliminating or at least reducing latency is beneficial. A delay of several seconds can negatively impact calibration and / or problem solving. For example, in the case of a quantum processor, a delay caused by a DAC reset can increase the time it takes for the quantum processor to return a result.

[0092] This disclosure describes a system and method for dividing an addressing line into two or more groups and simultaneously resetting a DAC that is communicably coupled to the addressing line belonging to each group. These systems and methods are also referred to in this application as distributed annealing reset.

[0093] The groups can be reset sequentially and / or simultaneously. The number of groups can be selected at least in part based on a) a desired duration for the reset procedure and b) an acceptable value for the peak temperature reached by the superconducting integrated circuit during the reset procedure.

[0094] In some implementations, the desired duration is less than a predetermined duration threshold. In some implementations, the acceptable value for peak temperature is a temperature less than a predetermined temperature threshold.

[0095] Multiple DACs can be reset simultaneously by activating the addressing lines belonging to a group of DACs. DACs that are communicatively coupled to the addressing lines of groups other than the one being activated may remain in their current state; that is, the number of magnetic flux quanta stored in the bodies of those DACs may remain unchanged.

[0096] One method for performing a distributed annealing reset is to a) select a subset of addressing lines and use an annealing power sequence (e.g., the annealing power sequence described above) to reset the group of DACs that are communicably coupled to the subset of addressing lines to the zero state of the DACs, and then b) repeat this process for other subsets of addressing lines to reset other groups of DACs.

[0097] Another approach is to a) define a sequence of annealing power levels, b) apply a sequence of pulses to each group of DACs for the first power level, and c) repeat this for each power level.

[0098] A group of DACs can be selected to meet many criteria. For example, a group can be selected such that the average number of DACs addressed simultaneously is at least approximately the same (i.e., the average number of DACs addressed simultaneously varies within a given tolerance). In one implementation, the average number of DACs addressed simultaneously varies within a tolerance of 10%. In another implementation, the average number of DACs addressed simultaneously varies within a tolerance such that the standard deviation of the number of DACs addressed simultaneously is 25% of the average number of DACs addressed simultaneously.

[0099] In another example, groups of DACs are selected such that the constituent DACs of each group are similarly distributed at least substantially uniformly across the superconducting integrated circuit.

[0100] Figure 5A is a plot 500a of examples of time-dependent signals 502 and 504 applied to each power line of each DAC in a pair of DACs according to this disclosure. Each DAC in the pair of DACs may be a superconducting DAC (e.g., the superconducting DAC in Figure 1).

[0101] Figure 5B is a plot 500b of examples of time-dependent signals 506 and 508 applied to each CJJ loop of each DAC in the same pair of DACs referenced in Figure 5B of this disclosure.

[0102] In an example of a superconducting integrated circuit implementation including a superconducting quantum processor (referred to as a P16 processor), the system and method described in this application can control 86,736 quad-stage DACs having 128 power channels and 57 addressing channels. In another example of a superconducting integrated circuit implementation including a superconducting quantum processor (referred to as a P6 processor), the system and method described in this application can control 10,296 quad-stage DACs having 29 power channels and 61 addressing channels.

[0103] In Figures 5A and 5B, even when the two DACs have a common addressing line, the signal causes DAC1 and DAC2 to reset at different times. The process is essentially equivalent to resetting DAC1 using the protocol described above, referring to Figures 2A, 2B, 3A, 3B, and 3C, and then resetting DAC2.

[0104] Figure 6A is a plot 600a of an example of time-dependent signals 602 and 604 applied to each power line of each DAC in a pair of DACs (DAC1 and DAC2) according to the present disclosure. Signals 602 and 604 can be applied to the power lines of DAC1 and DAC2 at each of many power levels. Signals 602 and 604 can be applied continuously. Signals 602 and 604 may be the same as each other. Signals 602 and 604 may overlap.

[0105] Figure 6B is a plot 600b of an example of a time-dependent signal 606 applied to the CJJ loop of the first DAC (DAC1) of the same pair of DACs referenced in Figure 6A of this disclosure.

[0106] Figure 6C is a plot of an example of a time-dependent signal 608 applied to the CJJ loop of the second DAC (DAC2) of the same pair of DACs referenced in Figures 6A and 6B of this disclosure.

[0107] Figure 7A is a plot 700a of an example of a time-dependent signal 702 applied to the power lines of the DAC according to this disclosure. Signal 702 is the current applied to the body of the DAC.

[0108] Figure 7B is a plot 700b of an example of a time-dependent signal 704 applied to the CJJ loop of the same DAC referenced in Figure 7A of this disclosure. Signal 704 is the magnetic flux applied to the CJJ loop.

[0109] Figure 8A is a plot 800a of examples of time-dependent signals 802 and 804 applied to each power line of each DAC (DAC1 and DAC2) of a pair of DACs according to the present disclosure.

[0110] Figure 8B is a plot 800b of an example of a time-dependent signal 806 applied to the addressing lines (ADDR and TRIG) of DAC1 in Figure 8A according to this disclosure.

[0111] Figure 8C is a plot 800c of an example of a time-dependent signal 808 applied to the addressing lines (ADDR and TRIG) of DAC2 in Figure 8A according to this disclosure.

[0112] Assuming that a DAC can only be activated by the additive combination of signals in pairs of addressing lines, the number of addressable DACs by activating a pair of addressing lines selected from l addressing lines is N. DAC This can be expressed as follows: N DAC =l! / [2×(l-2)!] For example, by activating pairs of addressing lines selected from six addressing lines, 15 DACs can be addressed.

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[0113] In fact, if one of two DACs is operated by additive coupling of signals on a line and the other DAC is operated by subtractive coupling of signals on a line (for example, additive coupling (+1, +1) and subtractive coupling (+1, -1)), the two DACs can share the same pair of addressing lines.

[0114] Figure 9A is a flowchart 900a of an example of a method for resetting a set of DACs in a superconducting integrated circuit according to the present disclosure. A method for performing the distributed annealing reset illustrated in Figure 9A includes the following: • Addressing line N G These are the groups G1, G2, ...GN G It is divided into groups, and the size of each group is m / 2. ·

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[0115] In one implementation, dividing addressing lines into groups may include a) determining an even number of m addressing lines that can operate simultaneously without the chip temperature increasing beyond a predetermined threshold, and b) dividing the addressing lines into groups of size m / 2.

[0116] Advantageously, the techniques described in this application, including the method shown in Figure 9A, can reduce the heating of the chip during the reset procedure. For example, advantageously, the techniques described in this application can reduce the heating of qubits and other superconducting devices in a superconducting quantum processor during the reset procedure. In some implementations, the temperature of the chip after reset is nonlinear with respect to the number of groups. For example, doubling the number of groups can result in a temperature increase of more than half.

[0117] Those skilled in the art will see that in alternative implementations, certain operations may be omitted and / or additional operations may be added, although method 900a includes operations 902-914. Those skilled in the art will see that the order in which the operations are illustrated is shown for illustrative purposes only and may vary in alternative implementations.

[0118] In 902, we invoke method 900a. In some implementations, we invoke method 900a when the superconducting integrated circuit is cooled to a temperature in which its elements are superconducting, the readout circuit is operational, and the superconducting integrated circuit is ready for calibration.

[0119] In 904, the system divides the addressing lines into groups. The system can divide the addressing lines into groups as described above. For example, groups can be selected at least in part based on a) a desired duration for the reset procedure and / or b) an acceptable value for the peak temperature reached by the superconducting integrated circuit during the reset procedure. In another example, groups can be selected so that the DACs reset by activating the lines in each group are distributed at least substantially uniformly across the superconducting integrated circuit.

[0120] In 906, the system initializes the loop variables. Initializing the loop variables may include initializing i=1 and j=i+1 as described above. In 908, the system applies a sequence of pulses to reset a subset of DACs. A subset of DACs may be DACs actuated by addressing lines belonging to one or more groups of addressing lines. A sequence of pulses can be selected to reset addressable DACs that are communicably coupled to addressing lines in groups Gi and Gj. Figure 900b (below) shows an example of a pulse sequence.

[0121] At 910, the system determines if there are more groups to be joined. If there are more groups, method 900a returns to 908 and applies another sequence of pulses to reset another subset of the DAC. If there are no more groups to be joined, method 900a proceeds to 912, where the system determines if there is another group. If there is another group, method 900a returns to 908. If the system determines that there are no more groups, method proceeds to 914, and method terminates.

[0122] Figure 9B is Table 900b, which shows an example of pulse sequences for the distributed annealing reset procedure of Figure 9A according to this disclosure.

[0123] Table 900b includes six addressing lines a1, a2, a3, a4, a5, and a6 arranged in three groups G1, G2, and G3. Group G1 consists of addressing lines a1 and a2. Group G2 consists of addressing lines a3 and a4. Group G3 consists of addressing lines a5 and a6. Each DAC can be reset by activating two of the addressing lines a1, a2, a3, a4, a5, and a6.

[0124] Each row in Table 900b corresponds to the combination of two operational addressing lines. For example, row 1 corresponds to the combination of operational addressing lines a1 and a2. The operation of each addressing line is indicated in Table 900 by "1" in each column. Each inactive addressing line is indicated in Table 900 by "0" in each column.

[0125] A blank space indicates that the addressing line is not active (effectively "0") and is used to help identify the group.

[0126] Table 900b shows the paired connections of groups. For example, in rows 1-6 of Table 900b, groups G1 and G2 are reset simultaneously. For each row (i.e., for each connection of the operational addressing line), the distributed annealing reset procedure applies a sequence of pulses to the addressable DAC. The addressable DAC is a DAC that is communicably coupled to the operational addressing line. The sequence of pulses applied to the addressable DAC causes it to reset.

[0127] In rows 7-12 of Table 900b, groups G2 and G3 are reset simultaneously, and in rows 13-18 of Table 900b, groups G1 and G3 are reset simultaneously.

[0128] Figure 10A is a flowchart of another example of method 1000a of resetting a set of DACs in a superconducting integrated circuit according to the present disclosure. Method 1000a of performing the distributed annealing reset illustrated in Figure 10A includes the following: • Determine an even number of addressing lines that can operate simultaneously without the chip temperature exceeding a predetermined temperature threshold. • Addressing line N G It is divided into groups, each of which is an addressing line of size m / 2. • Calculate a column that allows addressing each addressable DAC in each group (or, if lines can be joined, join lines to address all addressable DACs). For each addressing line, generate an array of a size equal to the total number of addressable DACs, which can be represented as follows for the additive coupling of signals to the ADDR and TRIG lines. N DAC =l! / [2×(l-2)!](where l is the number of address lines) ·

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[0129] Those skilled in the art will see that in alternative implementations, certain operations may be omitted and / or additional operations may be added, although method 1000a includes operations 1002-1018. Those skilled in the art will see that the order in which the operations are illustrated is shown for illustrative purposes only and may vary in alternative implementations.

[0130] In 1002, we invoke method 1000a. In some implementations, we invoke method 1000a when the superconducting integrated circuit is cooled to a temperature in which the elements of the superconducting integrated circuit are superconducting, the readout circuit is operational, and the superconducting integrated circuit is ready for calibration.

[0131] In 1004, the system determines the number of lines (m) that are operated simultaneously. In 1006, the system divides the lines into groups of size m / 2. In other implementations, the system divides the lines into groups of other sizes (e.g., m / 3 or m / 4). In 1008, the system calculates a pulse sequence and resets a subset of the DACs. Dividing the lines into groups and calculating the pulse sequence is described above with reference to Figure 900a. Figure 1000b shows an example of a pulse sequence.

[0132] In 1010, the system generates an array for addressable DACs. In 1012, the system applies a column to the line in a group join (e.g., a join of two groups, also called a pair join in this application). In 1014, the system determines if there are any other groups to join. If there are, method 1000a returns to 1012 and applies another sequence of pulses to reset another subset of DACs. If there are no more groups to join, method 1000a proceeds to 1016, where the system determines if there are any more groups. If there are, method 1000a returns to 1012. If the system determines that there are no more groups, method proceeds to 1018, and method terminates.

[0133] Figure 10B is Table 1000b, which shows an example of pulse sequences for the distributed annealing reset procedure of Figure 10A according to this disclosure.

[0134] Table 1000b includes eight addressing lines a1, a2, a3, a4, a5, a6, a7, and a8 arranged in four groups G1, G2, G3, and G4. Group G1 consists of addressing lines a1 and a2. Group G2 consists of addressing lines a3 and a4. Group G3 consists of addressing lines a5 and a6. Group G4 consists of addressing lines a7 and a8. Each DAC can be reset by activating two of the addressing lines a1, a2, a3, a4, a5, a6, a7, and a8.

[0135] Enter the data from Table 1000b as follows. In each group of the example shown in Table 1000b, the only available column is (+1, +1). First, merge Group 1 with Group 2 to give a first column where lines a1 to a4 are +1 and the rest are 0. Second, merge Group 1 with Group 3 to give a second column where lines a1, a2, a5 and a6 are +1 and the rest are 0. Third, merge Group 1 with Group 4 to give a third column where lines a1, a2, a7 and a8 are +1 and the rest are 0.

[0136] Fourth, merge group 2 with group 3 to give a fourth column where lines a3 to a6 are +1 and the rest are 0. Fifth, merge group 2 with group 4 to give a fifth column where lines a3, a4, a7 and a8 are +1 and the rest are 0. Sixth, merge group 3 with group 4 to give a sixth column where lines a5 to a8 are +1 and the rest are 0.

[0137] Generally, method 1000a in Figure 10A may be more efficient than method 900a in Figure 9A, and the total number of reset pulses used in method 1000a may be less than or equal to the total number of reset pulses used in method 900a.

[0138] For at least the reasons mentioned above, it is desirable to operate only 20 lines simultaneously. In an example scenario of a circuit with 60 addressing lines, the lines are divided into groups of 10 lines. There are 6 groups, and each group can operate each other in a total of 15 columns.

[0139] If we label the lines L1-L60 (not in any particular order) and group the lines by number, the six groups are L1-L10, L11-L20, L21-L30, L31-L40, L41-L50, and L51-L60. The column that can reset the DAC can be activated for the lines in each pair of groups, as shown below. L1~L10 L11~L20, L1~L10 L21~L30, L1~L10 L31~L40, L1~L10 L41~L50, L1~L10 L51~L60, L11~L20 L21~L30, L11~L20 L31~L40, L11~L20 L41~L50, L11~L20 L51~L60, L21~L30 L31~L40, L21~L30 L41~L50, L21~L30 L51~L60, L31~L40 L41~L50, L31~L40 L51~L60, L41~L50 L51~L60.

[0140] In another scenario, where there are 60 addressing lines, each capable of operating only 15 lines simultaneously, 12 groups of 5 lines can be formed. Columns capable of resetting the DAC can be generated for various combinations of the three groups.

[0141] Figure 11 shows a hybrid computing system 1100 in at least one exemplary implementation, which includes a digital computer 1102 and a quantum computer 1104 that can incorporate the systems and methods described in this application, including a magnetic flux storage device (e.g., DAC).

[0142] The digital computer 1102 includes a CPU 1106, user interface elements 1108, 1110, 1112, and 1114, a disk 1116, a controller 1118, a bus 1120, and memory 1122. Memory 1122 includes modules 1124, 1126, 1128, 1130, 1132, and 1134. Module 1134 includes a DAC reset instruction that can be used, for example, to reset one or more DACs by the method described in this application.

[0143] The quantum computer 1104 may incorporate one or more flux storage devices (e.g., the DAC 100 in Figure 1 and / or the DAC array 400 in Figure 4). The quantum computer 1104 includes a quantum processor 1136, a readout control system 1138, a qubit control system 1140, and a coupler control system 1142.

[0144] Further embodiments can be provided by combining the various embodiments described above. To the extent that they do not conflict with the specific teachings and definitions described herein, refer to International Publication No. 2019222514A1, U.S. Patent No. 10,528,886, U.S. Patent Application Publication No. 2021 / 0190885, “SYSTEMS AND METHODS FOR ADDRESSING DEVICES IN A SUPERCONDUCTING CIRCUIT,” filed May 16, 2019, U.S. Patent Application No. 16 / 996,595, “SYSTEMS AND METHODS FOR ADDRESSING DEVICES IN A SUPERCONDUCTING CIRCUIT,” filed August 19, 2019, and “SYSTEMS AND METHODS FOR CONTROLLING DEVICES IN A SUPERCONDUCTING CIRCUIT,” filed December 21, 2021. All U.S. patents, U.S. patent applications, U.S. patent publications, U.S. patent applications, foreign patents and foreign patent applications listed in the application data sheet referenced herein and / or assigned to the assignee of this patent application, including U.S. Patent Application No. 63 / 128,416 for "CIRCUIT" (but not limited to these), are incorporated herein by reference as a whole. The aspects of the embodiments may be modified as necessary to give further embodiments using various patents, applications and publications' systems, circuits and concepts.

[0145] Based on the detailed description above, these and other modifications to the embodiments may be made. In general, the terms used in the following claims should not be construed to limit the claims to any particular embodiment disclosed herein and in the claims, but rather to include all possible embodiments together with the entire scope of equivalents given to such claims. Accordingly, the claims are not limited by this disclosure.

Claims

1. A method of operating a system, the system comprising a superconducting integrated circuit and a controller, the superconducting integrated circuit comprising a plurality of flux storage devices, each of the plurality of flux storage devices comprising a superconducting loop interrupted by its respective composite Josephson junction, each of the composite Josephson junctions comprising its respective pair of Josephson junctions, each of the plurality of flux storage devices being commutatably coupled to each of a plurality of addressing lines and each of a plurality of power lines, the method being performed by the controller, the method is For the plurality of magnetic flux storage devices, estimate the worst asymmetry between each pair of Josephson junctions of the Josephson junctions, To estimate the average critical current for the aforementioned multiple magnetic flux storage devices, Determining the starting level for the current on each of the multiple power lines of each of the multiple magnetic flux storage devices, wherein the starting level is determined to be at least in part based on the worst asymmetry and the mean critical current. To determine the increase in power level, To generate a sequence of discrete power levels, wherein the sequence is A positive power level between the starting level and zero, which decreases by the amount of the power level increase, A negative power level between the additive inverse of the starting level and zero, which increases by the amount of the power level increase, and the positive power level and the negative power level alternate in the generated sequence of the discrete power levels. Including generating, For each power level in the sequence of discrete power levels, one or more pulses are applied to each of the multiple flux storage devices via one of the multiple addressing lines to reset each of the multiple flux storage devices. Methods that include...

2. To inspect the aforementioned superconducting integrated circuit for reset errors, If a reset error is detected, update the start level. The method according to claim 1, further comprising:

3. The method according to claim 1, wherein, with respect to the plurality of magnetic flux storage devices, estimating the worst asymmetry between each pair of Josephson junctions of the Josephson junctions includes determining the variation in the critical current of each of the one or more Josephson junctions in or adjacent to the superconducting integrated circuit.

4. The method according to claim 3, wherein determining the fluctuation of the respective critical current of each of the Josephson junctions in or adjacent to the superconducting integrated circuit includes determining the fluctuation of the respective critical current of each of the Josephson junctions in or adjacent to the superconducting integrated circuit at room temperature.

5. The method according to claim 1, wherein, for each power level of the discrete power level sequence, applying one or more pulses to each of the composite Josephson junctions of each of the plurality of flux storage devices via each of the plurality of addressing lines simultaneously includes applying one or more pulses to each of the composite Josephson junctions of each of the plurality of flux storage devices via a pair of addressing lines.

6. The method according to claim 1, wherein resetting each of the plurality of flux storage devices by applying one or more pulses to each of the plurality of composite Josephson junctions of each of the plurality of flux storage devices via each of the plurality of addressing lines, includes resetting a superconducting digital-to-analog converter (DAC) by applying one or more pulses to each of the plurality of composite Josephson junctions of each of the plurality of flux storage devices via each of the plurality of addressing lines, for each of the discrete power level sequences.

7. The method according to claim 6, wherein resetting a superconducting DAC by applying one or more pulses to each of the composite Josephson junctions of each of the plurality of flux storage devices via each of the plurality of addressing lines for each power level of the discrete power level sequence includes resetting a superconducting DAC including a loop of superconducting material that is interrupted by an inductance, wherein the inductance is at least one of the lumped element inductance, distributed inductance, kinetic inductance and intrinsic inductance of the loop of superconducting material.

8. The method according to claim 7, wherein for each power level of the discrete power level sequence, one or more pulses are applied to each of the composite Josephson junctions of each of the plurality of flux storage devices via each of the plurality of addressing lines to reset a superconducting DAC including a loop of superconducting material interrupted by an inductance, the superconducting DAC is inductively coupled to a programmable device via at least a portion of the inductance.

9. The method according to claim 6, wherein resetting a superconducting DAC for each power level in the sequence of discrete power levels involves applying one or more pulses to each of the composite Josephson junctions of each of the plurality of flux storage devices via each of the plurality of addressing lines, wherein the superconducting DAC is one of a plurality of superconducting DACs, each of the plurality of superconducting DACs is commutably coupled to a pair of addressing lines from the plurality of addressing lines, the operating superconducting DAC is addressable by the pair of addressing lines, and each addressing line in the pair of addressing lines is shared with at least one other superconducting DAC.

10. The method according to claim 9, wherein determining an initiation level for the current on each of the plurality of power lines of each of the plurality of magnetic flux storage devices includes determining an initiation level for the current on each of the plurality of power lines, wherein each of the plurality of power lines is shared with at least one other superconducting DAC.

11. The method according to claim 1, wherein for each power level of the discrete power level sequence, one or more pulses are applied to each of the plurality of flux storage devices via one of the plurality of addressing lines to reset each of the plurality of flux storage devices, wherein for each power level of the discrete power level sequence, one or more pulses are applied to each of the plurality of flux storage devices via one of the plurality of addressing lines to reset each of the plurality of flux storage devices to the ground state.

12. A method of operating a system, wherein the system includes a superconducting integrated circuit and a controller, the superconducting integrated circuit includes a plurality of flux storage devices, each of the plurality of flux storage devices being commutatably coupled to each pair of a plurality of addressing lines and each of a plurality of power lines, the method being performed by the controller, the method is Dividing the aforementioned multiple addressing lines into one or more groups of addressing lines, For each paired connection in the addressing line group, a sequence of pulses is applied to each addressing line of each paired connection in the addressing line group to reset one or more of the plurality of magnetic flux storage devices. Methods that include...

13. The method according to claim 12, wherein resetting one of the plurality of flux storage devices includes resetting a superconducting digital-to-analog converter (DAC).

14. The method according to claim 13, wherein resetting the superconducting DAC includes resetting a superconducting DAC that includes a loop of superconducting material that is interrupted by an inductance, the inductance being at least one of the lumped element inductance, distributed inductance, kinetic inductance and intrinsic inductance of the loop of superconducting material.

15. The method according to claim 14, wherein resetting a superconducting DAC including a loop of superconducting material that is interrupted by an inductance includes resetting the superconducting DAC, the superconducting DAC being inductively coupled to a programmable device via at least a portion of the inductance.

16. The method according to claim 12, wherein the resetting of the superconducting DAC includes resetting the superconducting DAC to its ground state.

17. The method according to claim 12, wherein dividing the plurality of addressing lines into one or more addressing line groups includes determining the number m of the plurality of addressing lines that are operated simultaneously, and dividing the plurality of addressing lines into groups of size m / 2.

18. The method according to claim 17, wherein determining the number m of the plurality of addressing lines that are operated simultaneously includes determining the number m of the plurality of addressing lines that can be operated to reset one or more of the plurality of flux storage devices while maintaining the temperature of the superconducting integrated circuit below a predetermined temperature threshold.

19. The method according to claim 17, wherein determining the number m of the plurality of addressing lines that are operated simultaneously includes determining the number m of the plurality of addressing lines that can be operated to reset the plurality of flux storage devices within a duration of time less than a predetermined duration threshold.

20. The method according to claim 12, wherein the procedure for resetting one or more of the plurality of flux storage devices by applying the respective sequence of pulses to each addressing line of each pair of addresses in the addressing line group comprises continuously applying the respective sequence of pulses to each addressing line of each pair of addresses in the addressing line group.

21. A method of operating a system, wherein the system includes a superconducting integrated circuit and a controller, the superconducting integrated circuit includes a plurality of flux storage devices, each of the plurality of flux storage devices being communicatively coupled to at least one of a plurality of addressing lines and one of a plurality of power lines, the method being performed by the controller, the method is The controller determines a first subset of the plurality of addressing lines and a second subset of the plurality of power lines, The controller simultaneously operates the first subset of the plurality of addressing lines and the second subset of the plurality of power lines, thereby resetting the magnetic flux storage device among the plurality of magnetic flux storage devices. Methods that include...

22. The method according to claim 21, wherein resetting one of the plurality of flux storage devices includes resetting a superconducting digital-to-analog converter (DAC).

23. The method according to claim 22, wherein resetting the superconducting DAC includes resetting the superconducting DAC which includes a loop of superconducting material that is interrupted by an inductance, the inductance being at least one of the lumped element inductance, distributed inductance, kinetic inductance and intrinsic inductance of the loop of superconducting material.

24. The method according to claim 23, wherein resetting a superconducting DAC including a loop of superconducting material that is interrupted by an inductance includes resetting the superconducting DAC, the superconducting DAC being inductively coupled to a programmable device via at least a portion of the inductance.

25. The method according to claim 23, wherein resetting the superconducting DAC includes resetting the superconducting DAC to its ground state.

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