Photoelectric converter

Abstract

To provide a photoelectric converter capable of outputting a more appropriate signal according to the illuminance. [Solution] The system includes an avalanche photodiode that outputs a signal corresponding to incident light, a pulse generation circuit that generates a pulse signal based on the output signal from the avalanche photodiode, a counter that generates and holds a first count value of N bits (N is an integer of 2 or more) by counting the number of pulses included in the pulse signal, an illuminance determination circuit that generates an illuminance signal indicating illuminance based on the values ​​of at least some of the bits of the first count value, a selector that outputs a second count value which is M bits (M is an integer of 1 or more and is less than N) of the first count value, and an output circuit that outputs data based on the first count value or the second count value, wherein the selector selects the range of bits of the second count value in the first count value based on the illuminance signal.

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device.

Background Art

[0002] Patent Document 1 discloses a photoelectric conversion device in which a plurality of pixels each including an avalanche photodiode are arranged in a two-dimensional array. The photoelectric conversion device of Patent Document 1 outputs a count value indicating the number of photons when the illuminance is less than a predetermined value, and outputs a predetermined fixed value when the illuminance exceeds the predetermined value.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a photoelectric conversion device that outputs a value according to illuminance as described in Patent Document 1, optimization of an output signal may be required. Therefore, an object of the present invention is to provide a photoelectric conversion device that can output a more appropriate signal according to illuminance.

Means for Solving the Problems

[0005] According to one disclosure of this specification, a photoelectric converter is provided, comprising: an avalanche photodiode that outputs a signal corresponding to incident light; a pulse generation circuit that generates a pulse signal based on the output signal from the avalanche photodiode; a counter that generates and holds a first count value of N bits (where N is an integer of 2 or more) by counting the number of pulses included in the pulse signal; an illuminance determination circuit that generates an illuminance signal indicating illuminance based on the values ​​of at least some of the bits of the first count value; a selector that outputs a second count value which is M bits (where M is an integer of 1 or more and is less than N) of the first count value; and an output circuit that outputs data based on the first count value or the second count value, wherein the selector selects a range of bits of the second count value in the first count value based on the illuminance signal. [Effects of the Invention]

[0006] According to the present invention, a photoelectric converter is provided that can output a more appropriate signal according to the illuminance. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic diagram showing the overall configuration of the photoelectric conversion device according to the first embodiment. [Figure 2] This is a schematic block diagram showing an example of the configuration of a sensor substrate according to the first embodiment. [Figure 3] This is a schematic block diagram showing an example of the configuration of a circuit board according to the first embodiment. [Figure 4] This is a schematic block diagram showing an example of the configuration of one pixel in the photoelectric conversion unit and pixel signal processing unit according to the first embodiment. [Figure 5] This is a diagram illustrating the operation of an avalanche photodiode according to the first embodiment. [Figure 6] This figure shows an example of the configuration of a pixel signal processing unit for two adjacent pixels according to the first embodiment. [Figure 7]This diagram illustrates the operation in high frame rate mode and non-high frame rate mode according to the first embodiment. [Figure 8] This is a timing chart showing the operation of the pixel signal processing unit for two adjacent pixels in high frame rate mode according to the first embodiment. [Figure 9] This is a timing chart showing the operation of the pixel signal processing unit according to the first embodiment in a non-high frame rate mode. [Figure 10] This figure shows an example of the configuration of the pixel signal processing unit according to the second embodiment. [Figure 11] This diagram illustrates the operation in high frame rate mode and non-high frame rate mode according to the second embodiment. [Figure 12] This is a timing chart showing the operation of the pixel signal processing unit in high frame rate mode according to the second embodiment. [Figure 13] This is a timing chart showing the operation of the pixel signal processing unit in a non-high frame rate mode according to the second embodiment. [Figure 14] This figure shows an example of the configuration of the pixel signal processing unit according to the third embodiment. [Figure 15] This figure shows an example configuration of an extraction circuit according to the third embodiment. [Figure 16] This figure shows an example of the configuration of the pixel signal processing unit according to the fourth embodiment. [Figure 17] This diagram illustrates the operation in high frame rate mode and non-high frame rate mode according to the fourth embodiment. [Figure 18] This figure shows an example configuration of an extraction circuit according to the fourth embodiment. [Figure 19] This is a timing chart showing the operation of the pixel signal processing unit in high frame rate mode according to the fourth embodiment. [Figure 20] This is a timing chart showing the operation of the pixel signal processing unit in a non-high frame rate mode according to the fourth embodiment. [Figure 21] This is a block diagram showing the schematic configuration of the equipment according to the fifth embodiment. [Figure 22] It is a block diagram showing a schematic configuration of a device according to the sixth embodiment. [Figure 23] It is a diagram showing a setting area of a high frame rate mode and a non-high frame rate mode according to the ninth embodiment. [Embodiments for Carrying Out the Invention]

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same elements or corresponding elements are given common reference numerals throughout the plurality of drawings, and the description thereof may be omitted or simplified.

[0009] [First Embodiment] FIG. 1 is a schematic diagram showing an overall configuration of a photoelectric conversion device 100 according to the present embodiment. The photoelectric conversion device 100 includes a sensor substrate 11 (first substrate) and a circuit substrate 21 (second substrate) laminated on each other. The sensor substrate 11 and the circuit substrate 21 are electrically connected to each other. The sensor substrate 11 has a pixel region 12 in which a plurality of pixels 101 are arranged so as to form a plurality of rows and a plurality of columns. The circuit substrate 21 has a first circuit region 22 in which a plurality of pixel signal processing units 103 are arranged so as to form a plurality of rows and a plurality of columns, and a second circuit region 23 arranged on the outer periphery of the first circuit region 22. The second circuit region 23 may include a circuit for controlling a plurality of pixel signal processing units 103. The sensor substrate 11 has a light incident surface for receiving incident light and a connection surface facing the light incident surface. The sensor substrate 11 is connected to the circuit substrate 21 on the connection surface side. That is, the photoelectric conversion device 100 is a so-called backside illumination type.

[0010] In this specification, "planar view" refers to viewing from a direction perpendicular to the surface on the opposite side of the light incident surface. Further, a cross section refers to a surface in a direction perpendicular to the surface on the opposite side of the light incident surface of the sensor substrate 11. Note that although the light incident surface may be a rough surface when viewed microscopically, in that case, the planar view is defined based on the light incident surface when viewed macroscopically.

[0011] In the following description, the sensor substrate 11 and the circuit board 21 are assumed to be diced chips, but the sensor substrate 11 and the circuit board 21 are not limited to chips. For example, the sensor substrate 11 and the circuit board 21 may be wafers. Furthermore, if the sensor substrate 11 and the circuit board 21 are diced chips, the photoelectric converter 100 may be manufactured by stacking wafers and then dicing them, or by stacking wafers after dicing them.

[0012] Figure 2 is a schematic block diagram showing an example of the arrangement of the sensor substrate 11. Multiple pixels 101 are arranged in multiple rows and multiple columns in the pixel region 12. Each of the multiple pixels 101 has a photoelectric conversion unit 102 on the substrate, which includes an avalanche photodiode (hereinafter referred to as APD) as a photoelectric conversion element.

[0013] Each of the multiple pixels 101 typically generates a signal that constitutes an image. However, when the photoelectric converter 100 is used in a TOF (Time of Flight) type ranging device, the generated signal does not necessarily have to be used to construct an image. That is, each of the multiple pixels 101 may generate a signal for measuring the time and amount of light that arrived.

[0014] In an APD (Automated Precipitator), the conductivity type of the charge used as the signal charge is called the first conductivity type. The first conductivity type refers to a conductivity type in which the majority carriers are charges of the same polarity as the signal charge. Conversely, the conductivity type opposite to the first conductivity type, i.e., a conductivity type in which the majority carriers are charges of a different polarity than the signal charge, is called the second conductivity type. In the APD described below, the anode of the APD is at a fixed potential, and the signal is extracted from the cathode of the APD. Therefore, the semiconductor region of the first conductivity type is the N-type semiconductor region, and the semiconductor region of the second conductivity type is the P-type semiconductor region. Alternatively, the cathode of the APD may be at a fixed potential, and the signal may be extracted from the anode of the APD. In this case, the semiconductor region of the first conductivity type is the P-type semiconductor region, and the semiconductor region of the second conductivity type is the N-type semiconductor region. Furthermore, the following description focuses on the case where one node of the APD is at a fixed potential, but a configuration in which the potentials of both nodes fluctuate is also possible.

[0015] The pixel region 12 includes a light-receiving region 14 and an optical black region (hereinafter referred to as the "OB region") 15. Pixels 101 within the light-receiving region 14 generate signals corresponding to incident light. A light-shielding film is provided in the photoelectric conversion unit 102 within the OB region 15 to block incident light. As a result, pixels 101 within the OB region 15 generate signals at a black level equivalent to the absence of incident light. The OB region 15 is typically arranged along two sides of the perimeter of the light-receiving region 14. In the example shown in Figure 2, the OB region 15 is arranged in an L-shaped region along the left and bottom edges of the light-receiving region 14. The arrangement of the light-receiving region 14 and the OB region 15 is not particularly limited.

[0016] Figure 3 is a schematic block diagram showing an example of the configuration of the circuit board 21. The circuit board 21 has a first circuit region 22 in which multiple pixel signal processing units 103 are arranged in multiple rows and multiple columns. Region 24 in Figure 3 shows the area in which the pixel signal processing units 103 corresponding to the pixels 101 of the light-receiving region 14 are arranged. Region 25 in Figure 3 shows the area in which the pixel signal processing units 103 corresponding to the pixels 101 of the OB region 15 are arranged.

[0017] Furthermore, the circuit board 21 includes a vertical scanning circuit 110, a horizontal scanning circuit 111, a readout circuit 112, a pixel output signal line 113, an output circuit 114, and a control signal generation unit 115. The multiple photoelectric conversion units 102 shown in Figure 2 and the multiple pixel signal processing units 103 shown in Figure 3 are electrically connected via connecting wiring provided for each pixel 101.

[0018] The control signal generation unit 115 is a control circuit that generates and supplies control signals to drive the vertical scanning circuit 110, the horizontal scanning circuit 111, and the readout circuit 112. In this way, the control signal generation unit 115 controls the drive timing and other aspects of each component.

[0019] The vertical scanning circuit 110 supplies control signals to each of the multiple pixel signal processing units 103 based on the control signals supplied from the control signal generation unit 115. The vertical scanning circuit 110 supplies control signals to each pixel signal processing unit 103 row by row via drive lines provided for each row of the first circuit region 22. As will be described later, there may be multiple drive lines for each row. Logic circuits such as shift registers and address decoders may be used in the vertical scanning circuit 110. This allows the vertical scanning circuit 110 to select the row from which the pixel signal processing unit 103 will output a signal.

[0020] The signal output from the photoelectric conversion unit 102 of the pixel 101 is processed by the pixel signal processing unit 103. The pixel signal processing unit 103 acquires and stores a digital signal having multiple bits by counting the number of pulses output from the APD included in the photoelectric conversion unit 102.

[0021] The horizontal scanning circuit 111 supplies control signals to the readout circuit 112 based on control signals supplied from the control signal generation unit 115. The pixel signal processing unit 103 is connected to the readout circuit 112 via pixel output signal lines 113, which are provided for each column of the first circuit region 22. The pixel output signal line 113 of one column is shared by multiple pixel signal processing units 103 of the corresponding column. The pixel output signal line 113 includes multiple wires and has at least the function of outputting a digital signal from each pixel signal processing unit 103 to the readout circuit 112, and the function of supplying a control signal to the pixel signal processing unit 103 for selecting the column from which to output a signal. The readout circuit 112 outputs a signal to an external storage unit or signal processing unit of the photoelectric converter 100 via the output circuit 114 based on the control signals supplied from the control signal generation unit 115.

[0022] The photoelectric conversion units 102 in the pixel region 12 may be arranged in a one-dimensional manner. Furthermore, the pixel signal processing unit 103 does not necessarily have to be provided for every pixel 101. For example, a single pixel signal processing unit 103 may be shared by multiple pixels 101. In this case, the pixel signal processing unit 103 provides signal processing functionality to each pixel 101 by sequentially processing the signals output from each photoelectric conversion unit 102.

[0023] As shown in Figures 2 and 3, a first circuit region 22, in which multiple pixel signal processing units 103 are arranged, is located in a region that overlaps with the pixel region 12 in a plan view. A vertical scanning circuit 110, a horizontal scanning circuit 111, a readout circuit 112, an output circuit 114, and a control signal generation unit 115 are arranged so as to overlap between the edge of the sensor substrate 11 and the edge of the pixel region 12 in a plan view. In other words, the sensor substrate 11 has a pixel region 12 and a non-pixel region arranged around the pixel region 12. A second circuit region 23 (mentioned above in Figure 1) is located in the circuit substrate 21, in a region that overlaps with the non-pixel region in a plan view, and in which the vertical scanning circuit 110, a horizontal scanning circuit 111, a readout circuit 112, an output circuit 114, and a control signal generation unit 115 are arranged.

[0024] Note that the arrangement of the pixel output signal lines 113, the readout circuit 112, and the output circuit 114 is not limited to those shown in Figure 3. For example, the pixel output signal lines 113 may be arranged to extend in the row direction and be shared by multiple pixel signal processing units 103 in the corresponding row. The readout circuit 112 may be arranged so that the pixel output signal lines 113 of each row are connected.

[0025] Figure 4 is a schematic block diagram showing an example of the configuration of one pixel of the photoelectric conversion unit 102 and the pixel signal processing unit 103 according to this embodiment. Figure 4 schematically shows a more specific configuration example, including the connection relationship between the photoelectric conversion unit 102 arranged on the sensor substrate 11 and the pixel signal processing unit 103 arranged on the circuit board 21. In Figure 4, the drive lines between the vertical scanning circuit 110 and the pixel signal processing unit 103 in Figure 3 are shown as drive lines 213 and 214.

[0026] The photoelectric conversion unit 102 has an APD 201. The pixel signal processing unit 103 has a quench element 202, a waveform shaping unit 210, a counter circuit 211, and a selection circuit 212.

[0027] The APD201 generates a charge corresponding to the incident light through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD201. The cathode of the APD201 is connected to the first terminal of the quench element 202 and the input terminal of the waveform shaping unit 210. A voltage VH (second voltage), which is higher than the voltage VL supplied to the anode, is supplied to the cathode of the APD201. As a result, a reverse bias voltage is supplied to the anode and cathode of the APD201, causing the APD201 to perform avalanche multiplication. When a charge is generated by the incident light in the APD201 with the reverse bias voltage supplied, this charge undergoes avalanche multiplication, generating an avalanche current.

[0028] When a reverse bias voltage is supplied to the APD201, there are two operating modes: Geiger mode and linear mode. Geiger mode is a mode in which the anode and cathode potential difference is greater than the breakdown voltage, while linear mode is a mode in which the anode and cathode potential difference is near or below the breakdown voltage.

[0029] An APD operating in Geiger mode is called a SPAD (Single Photon Avalanche Diode). In this case, for example, the voltage VL (first voltage) is -30V and the voltage VH (second voltage) is 1V. The APD201 may operate in linear mode or Geiger mode. In the case of a SPAD, the potential difference is larger compared to a linear-mode APD, and the avalanche multiplication effect is more pronounced, so it is preferable to use a SPAD.

[0030] The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication. The quench element 202 suppresses the voltage supplied to the APD201, thereby suppressing avalanche multiplication (quench operation). The quench element 202 also restores the voltage supplied to the APD201 to voltage VH by flowing a current corresponding to the voltage drop caused by the quench operation (recharge operation). The quench element 202 may be, for example, a resistor.

[0031] The waveform shaping unit 210 shapes the cathode potential change of the APD201 obtained during photon detection and outputs a pulse signal. For example, an inverter circuit can be used as the waveform shaping unit 210. Figure 4 shows an example in which one inverter is used as the waveform shaping unit 210, but the waveform shaping unit 210 may also be a circuit in which multiple inverters are connected in series, or it may be any other circuit that has a waveform shaping effect.

[0032] The counter circuit 211 counts the pulse signals output from the waveform shaping unit 210 and holds a digital signal indicating the count value. When a control signal is supplied from the vertical scanning circuit 110 via the drive line 213, the counter circuit 211 resets the signal it is holding.

[0033] The selection circuit 212 receives a control signal from the vertical scanning circuit 110 shown in Figure 3 via the drive line 214 shown in Figure 4. In response to this control signal, the selection circuit 212 switches between electrically connecting and disconnecting the counter circuit 211 and the pixel output signal line 113. The selection circuit 212 includes, for example, a buffer circuit for outputting a signal corresponding to the value held in the counter circuit 211.

[0034] In the example shown in Figure 4, the selection circuit 212 switches between electrical connection and disconnection between the counter circuit 211 and the pixel output signal line 113. However, the method for controlling the signal output to the pixel output signal line 113 is not limited to this. For example, switches such as transistors may be placed at nodes such as between the quench element 202 and the APD 201, or between the photoelectric conversion unit 102 and the pixel signal processing unit 103, to switch between electrical connection and disconnection and control the signal output to the pixel output signal line 113. Alternatively, the signal output to the pixel output signal line 113 may be controlled by changing the value of the voltage VH or voltage VL supplied to the photoelectric conversion unit 102 using a switch such as a transistor.

[0035] Figures 5(a), 5(b), and 5(c) illustrate the operation of the APD201 according to this embodiment. Figure 5(a) is a diagram showing the APD201, quench element 202, and waveform shaping unit 210 extracted from Figure 4. As shown in Figure 5(a), the connection node of the input terminals of the APD201, quench element 202, and waveform shaping unit 210 is designated as nodeA. Also, as shown in Figure 5(a), the output side of the waveform shaping unit 210 is designated as nodeB.

[0036] Figure 5(b) is a graph showing the time evolution of the potential of node A in Figure 5(a). Figure 5(c) is a graph showing the time evolution of the potential of node B in Figure 5(a). During the period from time t0 to time t1, a voltage of VH-VL is applied to APD201 in Figure 5(a). When a photon is incident on APD201 at time t1, avalanche multiplication occurs in APD201. This causes an avalanche current to flow in the quench element 202, and the potential of node A drops. Subsequently, the amount of potential drop increases further, and the voltage applied to APD201 gradually decreases. Then, at time t2, avalanche multiplication in APD201 stops. As a result, the voltage level of node A no longer drops below a certain value. Subsequently, during the period from time t2 to time t3, a current flows from the node with voltage VH to node A to compensate for the voltage drop, and at time t3, node A settles to its original potential.

[0037] In the process described above, the potential of node B becomes high-level during the period when the potential of node A is below a certain threshold. In this way, the waveform of the potential drop at node A caused by the photon incidence is shaped by the waveform shaping unit 210 and output as a pulse to node B.

[0038] Figure 6 shows an example of the configuration of two adjacent pixel signal processing units 103 according to this embodiment. Figure 6 shows in more detail the configuration of two of the multiple pixel signal processing units 103 arranged in a two-dimensional manner. The pixel signal processing unit 103 includes a counter circuit 211, a pulse generation circuit 220, an illumination determination circuit 230, a selector 240, and a pixel output circuit 250. Figure 6 shows one of the multiple pixel signal processing units 103 arranged in even rows and one of the multiple pixel signal processing units 103 arranged in odd rows.

[0039] The pulse generation circuit 220 includes a quench element 202 and a waveform shaping unit 210, as shown in Figure 4. The counter circuit 211 includes a bit output unit 211a and a bit output unit 211b. The pixel output circuit 250 includes a selector 251 and a selection circuit 212, as shown in Figure 4. Figure 6 also illustrates the drive line 215 that supplies the drive signal CNTEN to control the operation of the counter circuit 211, and the 14 signal lines that constitute the pixel output signal line 113.

[0040] The counter circuit 211 generates and holds a count value (first count value) by counting the number of pulses contained in the pulse signal output from the pulse generation circuit 220. The counter circuit 211 also resets the held count value when a control pulse P_RES is supplied from the control signal generation unit 115 via the vertical scanning circuit 110 and drive line 213. Furthermore, the counter circuit 211 starts counting when the drive signal CNTEN supplied from the control signal generation unit 115 via the vertical scanning circuit 110 and drive line 215 becomes high level. Subsequently, the counter circuit 211 stops counting when the drive signal CNTEN becomes low level. In other words, the drive signal CNTEN is a signal that controls the exposure period. The counter circuit 211 is, for example, a 12-bit counter.

[0041] If the counter circuit 211 is a 12-bit counter, for example, the bit output unit 211a is configured to output the upper 6 bits of the signal held by the 12-bit counter. The bit output unit 211b is configured to output the lower 6 bits of the signal held by the 12-bit counter. In this way, the counter circuit 211 can output the 12-bit data it holds by dividing it into two ranges (first range and second range) of the upper 6 bits and the lower 6 bits. In this embodiment, the range of bits output by bit output unit 211a and the range of bits output by bit output unit 211b are set so as not to overlap, but they may overlap. The least significant bit (LSB) of the 12-bit data is defined as the 0th bit, and the most significant bit (MSB) is defined as the 11th bit.

[0042] The illuminance determination circuit 230 receives the upper 6 bits of data output from the bit output unit 211a. Based on the input 6-bit data, the illuminance determination circuit 230 generates an illuminance signal and outputs it as a control signal to the selector 240 and the selection circuit 212. The illuminance determination circuit 230 outputs a control signal indicating "1" to the selector 240 and the selection circuit 212 if the value of at least one bit of this 6-bit data is "1". The illuminance determination circuit 230 also outputs a control signal indicating "0" to the selector 240 and the selection circuit 212 if the above condition is not met. In other words, the illuminance determination circuit 230 outputs a control signal indicating "1" when the illuminance is high enough that the count value of the 12-bit counter of the counter circuit 211 reaches the upper 6 bits. The illuminance determination circuit 230 may include, for example, an OR circuit that calculates the logical OR of the values ​​of each bit of the 6-bit data. This OR gate outputs a signal indicating "0" if all six input bits are zero, and a signal indicating "1" otherwise.

[0043] The bit output unit 211a and bit output unit 211b are connected to the two input terminals of the selector 240, respectively. When a control signal indicating "1" is input to the selector 240 from the illuminance determination circuit 230, the selector 240 selects and outputs the upper 6 bits of data output from bit output unit 211a. When a control signal indicating "0" is input to the selector 240 from the illuminance determination circuit 230, the selector 240 selects and outputs the lower 6 bits of data output from bit output unit 211b.

[0044] The pixel output circuit 250 expands the 6-bit data (second count value) output from the selector 240 into 12-bit data and inputs it to the selector 251. The method of expansion differs between the pixel signal processing units 103 for even-numbered rows and the pixel signal processing units 103 for odd-numbered rows. For example, in the pixel signal processing unit 103 for even-numbered rows, the 6-bit data output from the selector 240 is stored in the lower 6 bits of the expanded 12-bit data. In contrast, in the pixel signal processing unit 103 for odd-numbered rows, the 6-bit data output from the selector 240 is stored in the upper 6 bits of the expanded 12-bit data.

[0045] The two input terminals of selector 251 receive 12-bit data, which is an expanded version of the 6-bit data output from selector 240, and 12-bit data, which represents the count value held in counter circuit 211, respectively. Selector 251 is controlled by a mode setting value input from an external system (not shown). The mode setting value indicates whether or not the photoelectric converter 100 operates in high frame rate mode.

[0046] When the photoelectric converter 100 is not operating in high frame rate mode, the selector 251 selects 12-bit data representing the count value held in the counter circuit 211 and outputs it to the selection circuit 212. When the photoelectric converter 100 is operating in high frame rate mode, the selector 251 selects and outputs 12-bit data which is an expanded version of the 6-bit data output from the selector 240. As described above, in the pixel signal processing unit 103 for even-numbered rows, the valid data is stored in the lower 6 bits of the expanded 12-bit data, and in the pixel signal processing unit 103 for odd-numbered rows, the valid data is stored in the upper 6 bits of the expanded 12-bit data.

[0047] The selection circuit 212 switches the electrical connection between the selector 251 and the illumination determination circuit 230 and the pixel output signal line 113 based on the control pulse P_SEL supplied from the control signal generation unit 115 via the vertical scanning circuit 110 and the drive line 214. The selection circuit 212 includes, for example, a buffer circuit for outputting signals.

[0048] The selection circuit 212 is controlled by the mode setting value, similar to the selector 251. First, we will describe the case when the photoelectric converter 100 is not operating in high frame rate mode. In this case, when a row is selected by the control pulse P_SEL, the selection circuit 212 connects the signal lines that transmit the 12-bit data output from the selector 251 to the signal lines of bits 0 to 11 of the pixel output signal line 113, respectively. The numbers "0" to "13" written on the 14 signal lines that make up the pixel output signal line 113 in Figure 6 indicate that these signal lines transmit data from bit 0 to bit 13, respectively.

[0049] The case where the photoelectric converter 100 is operating in high frame rate mode is described below. In this case, the connection method differs depending on whether the pixel signal processing unit 103 for even-numbered rows is selected by the control pulse P_SEL or whether the pixel signal processing unit 103 for odd-numbered rows is selected by the control pulse P_SEL.

[0050] The selection circuit 212 of the even-numbered row pixel signal processing unit 103 connects the signal lines of the lower 6 bits, which are the valid data of the 12-bit data output from the selector 251, to the signal lines of bits 0 through 5 of the pixel output signal line 113, respectively. In addition, the selection circuit 212 of the even-numbered row pixel signal processing unit 103 connects the signal line that transmits the 1-bit control signal output from the illumination determination circuit 230 to the signal line of bit 12 of the pixel output signal line 113. The processing circuit that performs subsequent processing can determine whether the data read from the even-numbered row is a count value output from either bit output unit 211a or bit output unit 211b by referring to the value of bit 12 of the pixel output signal line 113 as an attribute value.

[0051] The selection circuit 212 of the odd-numbered row pixel signal processing unit 103 connects the signal lines of the upper 6 bits, which are the valid data of the 12-bit data output from the selector 251, to the signal lines of the 6th to 11th bits of the pixel output signal line 113, respectively. In addition, the selection circuit 212 of the odd-numbered row pixel signal processing unit 103 connects the signal line that transmits the 1-bit control signal output from the illumination determination circuit 230 to the signal line of the 13th bit of the pixel output signal line 113. The processing circuit that performs subsequent processing can determine whether the data read from the odd-numbered row is a count value output from either the bit output unit 211a or the bit output unit 211b by referring to the value of the 13th bit of the pixel output signal line 113 as an attribute value.

[0052] Thus, in high frame rate mode, the signal lines for bits 0 to 5 of the pixel output signal line 113 are used for even-numbered rows, and the signal lines for bits 6 to 11 of the pixel output signal line 113 are used for odd-numbered rows. In addition, the signal lines for bits 12 and 13 of the pixel output signal line 113 are used for attribute values. However, this is just one example, and for instance, the signal lines for bits 0 to 5 of the pixel output signal line 113 may be used for odd-numbered rows, and the signal lines for bits 6 to 11 of the pixel output signal line 113 may be used for even-numbered rows.

[0053] In this high frame rate mode, the pixel output signal line 113 is shared by multiple pixel signal processing units 103 in a single row, so that the signal lines from the 0th to the 11th bit of the pixel output signal line 113 are shared by the even-numbered and odd-numbered pixel signal processing units 103. However, this configuration is just one example, and the pixel output signal line 113 may be shared by multiple pixel signal processing units 103 in a single row. In this case, the signal lines from the 0th to the 11th bit of the pixel output signal line 113 may be shared by the even-numbered and odd-numbered pixel signal processing units 103.

[0054] Figures 7(a) and 7(b) illustrate the operation in high frame rate mode and non-high frame rate mode according to this embodiment. Figures 7(a) and 7(b) show the control pulse P_SEL of the 0th row. <0> From the Xth row control pulse P_SEL <x>The time evolution is shown. The numbers in angle brackets indicate the line number of the pixel signal processing unit 103 to which the control pulse P_SEL is supplied.

[0055] Figure 7(a) shows the readout operation in non-high frame rate mode (second mode). In non-high frame rate mode, the selected row selection circuit 212 connects the signal lines that transmit the 12-bit data output from the selector 251 to the signal lines of bits 0 to 11 of the pixel output signal line 113, respectively. That is, when reading one row, all of the signal lines of bits 0 to 11 of the pixel output signal line 113 are occupied. Therefore, the control pulse P_SEL <0> , P_SEL <1> , P_SEL <2> , P_SEL <3> ,...,P_SEL <x-1>P_SEL <x>As the level increases sequentially, reading is performed one line at a time.

[0056] Figure 7(b) shows the readout operation in high frame rate mode (first mode). In high frame rate mode, different operations are performed depending on whether the selected row is even or odd. For even rows, the selection circuit 212 of the pixel signal processing unit 103 connects the signal lines of the lower 6 bits, which are the valid data of the 12-bit data output from the selector 251, to the signal lines of bits 0 to 5 of the pixel output signal line 113. For odd rows, the selection circuit 212 of the pixel signal processing unit 103 connects the signal lines of the upper 6 bits, which are the valid data of the 12-bit data output from the selector 251, to the signal lines of bits 6 to 11 of the pixel output signal line 113. In other words, when reading out two rows, an even and an odd row, the signal lines of bits 0 to 11 of the pixel output signal line 113 can be shared. Therefore, first the control pulse P_SEL <0> , P_SEL <1> The two simultaneously reach a high level, followed by the control pulse P_SEL. <2> , P_SEL <3> As a result of the simultaneous activation of high levels and other operations occurring sequentially, two lines are read out at a time. Thus, in the high frame rate mode of this embodiment, simultaneous reading of multiple lines is possible. As a result, the reading time in high frame rate mode is halved compared to non-high frame rate mode, achieving twice the reading speed. Therefore, in high frame rate mode, imaging at a higher frame rate is possible than in non-high frame rate mode.

[0057] Figure 8 is a timing chart showing the operation of the pixel signal processing unit 103 for two adjacent pixels in high frame rate mode according to this embodiment. Figure 8 shows the time changes of the drive signal CNTEN<0 / 1> and the control pulses P_RES<0 / 1> and P_SEL<0 / 1> in the 0th and 1st rows. Figure 8 also shows the time changes of the count value in each part of the pixel signal processing unit 103 and the time changes of the control signal output from the illuminance determination circuit 230. The operation of even-numbered rows from the 2nd row onward is the same as the operation of the 0th row, and the operation of odd-numbered rows from the 3rd row onward is the same as the operation of the 1st row, so the explanation is omitted. The notation "0 / 1" in angle brackets indicates that the same level of signal is supplied to the 0th and 1st rows.

[0058] At time T0, the first frame period begins. After time T0, the control pulse P_RES<0 / 1> becomes high level, and then at the following time T1, the control pulse P_RES<0 / 1> becomes low level. As a result, the count value held in the counter circuit 211 is reset to "0". Consequently, the count values ​​output from the bit output units 211a and 211b are also reset to "0".

[0059] At time T2, the drive signal CNTEN<0 / 1> becomes high level, and the counting operation in the counter circuit 211 begins. In other words, time T2 is the start time of the exposure period. Also at time T2, the count value of the bit output section 211b, which corresponds to the lower 6 bits of the counter circuit 211, begins to increase.

[0060] At time T3, the value is carried to the LSB of the upper 6 bits of the counter circuit 211 of the 0th row. As a result, the count value of the bit output section 211a corresponding to the upper 6 bits of the counter circuit 211 of the 0th row begins to increase. Also at time T3, because one of the upper 6 bits of the counter circuit 211 of the 0th row becomes "1", the value of the control signal output from the illuminance determination circuit 230 of the 0th row also becomes "1".

[0061] At time T4, the drive signal CNTEN<0 / 1> becomes low level, and the counting operation in the counter circuit 211 ends. In other words, time T4 is the end time of the exposure period.

[0062] At time T4, the count value of the counter circuit 211 in row 0 is "12'b1000_1100_1110". Therefore, the count value of the bit output section 211a, which is the upper 6 bits of the counter circuit 211, is "6'b10_0011", and the count value of the bit output section 211b, which is the lower 6 bits of the counter circuit 211, is "6'b00_1110". In these notations of count values, "12'b" and "6'b" indicate that the number of bits in the count value is 12 bits and 6 bits, respectively, and "1000_1100_1110", etc., indicate each bit value of the count value separated by 4 bits.

[0063] Since the control signal output from the illuminance determination circuit 230 in row 0 is "1", the selector 240 in row 0 selects the count value of the bit output unit 211a. The pixel output circuit 250 in row 0 expands the 6-bit data output from selector 240 to 12 bits and inputs it to selector 251. At this time, the 6-bit data output from selector 240 is stored in the lower 6 bits of the expanded 12-bit data. Therefore, the expanded count value becomes "12'b0000_0010_0011". In high frame rate mode, selector 251 in row 0 outputs this expanded count value to the selection circuit 212.

[0064] Furthermore, at time T4, the count value of the first row of the counter circuit 211 is "12'b0000_0010_1010". Therefore, the count value of the upper 6 bits of the counter circuit 211, bit output section 211a, is "6'b00_0000", and the count value of the lower 6 bits of the counter circuit 211, bit output section 211b, is "6'b10_1010".

[0065] Since the control signal output from the first row's illuminance determination circuit 230 is "0", the first row's selector 240 selects the count value of the bit output unit 211b. The first row's pixel output circuit 250 expands the 6-bit data output from selector 240 to 12 bits and inputs it to selector 251. At this time, the 6-bit data output from selector 240 is stored in the upper 6 bits of the expanded 12-bit data. Therefore, the expanded count value becomes "12'b1010_1000_0000". In high frame rate mode, the first row's selector 251 outputs this expanded count value to the selection circuit 212.

[0066] At time T5, the control pulse P_SEL<0 / 1> becomes high level, and at time T6, the control pulse P_SEL<0 / 1> becomes low level. This operation causes the 0th and 1st rows to be read out during the period from time T5 to time T6.

[0067] The selection circuit 212 in row 0 connects the signal lines of the lower 6 bits, which are valid data from the count value "12'b0000_0010_0011" output from selector 251, to the signal lines of bits 0 through 5 of the pixel output signal line 113, respectively. In addition, the selection circuit 212 in row 0 connects the signal line that transmits the control signal value "1" output from illuminance determination circuit 230 to the signal line of bit 12 of the pixel output signal line 113.

[0068] The first row of selection circuit 212 connects the signal lines of the upper 6 bits, which are valid data from the count value "12'b1010_1000_0000" output from selector 251, to the signal lines of bits 6 through 11 of pixel output signal line 113, respectively. In addition, the first row of selection circuit 212 connects the signal line that transmits the control signal value "0" output from illuminance determination circuit 230 to the signal line of bit 13 of pixel output signal line 113.

[0069] Therefore, during the period from time T5 to time T6, the pixel output signal line 113 outputs a 14-bit value "14'b01_1010_1010_0011" which represents the count value of the 0th row, the count value of the 1st row, and the attribute value. Here, the upper 6 bits of the count value of the counter circuit 211 of the 0th row are extracted and output, and the lower 6 bits of the count value of the counter circuit 211 of the 1st row are extracted and output.

[0070] At time T7, the first frame period ends. That is, the period from time T0 to time T7 is the first frame period. Then, the second frame period begins at time T7.

[0071] After time T7, the control pulse P_RES<0 / 1> becomes high level, and then at time T8, the control pulse P_RES<0 / 1> becomes low level. As a result, the count value held in the counter circuit 211 is reset to "0". Therefore, the count values ​​output from the bit output units 211a and 211b are also reset to "0". In addition, the value of the control signal output from the illuminance determination circuit 230 is also reset to "0".

[0072] At time T9, the drive signal CNTEN<0 / 1> becomes high level, and the counting operation in the counter circuit 211 begins. In other words, time T9 is the start time of the exposure period. Also at time T9, the count value of the bit output section 211b, which corresponds to the lower 6 bits of the counter circuit 211, begins to increase.

[0073] At time T10, the value is carried to the LSB of the upper 6 bits of the first row counter circuit 211. As a result, the count value of the bit output section 211a corresponding to the upper 6 bits of the first row counter circuit 211 begins to increase. Also at time T10, because one of the upper 6 bits of the first row counter circuit 211 becomes "1", the value of the control signal output from the first row illuminance determination circuit 230 also becomes "1".

[0074] At time T11, the drive signal CNTEN<0 / 1> becomes low level, and the counting operation in the counter circuit 211 ends. In other words, time T11 is the end time of the exposure period.

[0075] At time T11, the count value of the counter circuit 211 in the 0th row is "12'b0000_0011_1000". Therefore, the count value of the bit output section 211a, which is the upper 6 bits of the counter circuit 211, is "6'b00_0000", and the count value of the bit output section 211b, which is the lower 6 bits of the counter circuit 211, is "6'b11_1000".

[0076] Since the control signal output from the illuminance determination circuit 230 in row 0 is "0", the selector 240 in row 0 selects the count value of the bit output unit 211b. The pixel output circuit 250 in row 0 expands the 6-bit data output from selector 240 to 12 bits and inputs it to selector 251. At this time, the 6-bit data output from selector 240 is stored in the lower 6 bits of the expanded 12-bit data. Therefore, the expanded count value becomes "12'b0000_0011_1000". In high frame rate mode, selector 251 in row 0 outputs this expanded count value to the selection circuit 212.

[0077] Furthermore, at time T11, the count value of the first row counter circuit 211 is "12'b0110_0110_0110". Therefore, the count value of the upper 6 bits of the counter circuit 211, bit output section 211a, is "6'b01_1001", and the count value of the lower 6 bits of the counter circuit 211, bit output section 211b, is "6'b10_0110".

[0078] Since the control signal output from the first row's illuminance determination circuit 230 is "1", the first row's selector 240 selects the count value of the bit output unit 211a. The first row's pixel output circuit 250 expands the 6-bit data output from selector 240 to 12 bits and inputs it to selector 251. At this time, the 6-bit data output from selector 240 is stored in the upper 6 bits of the expanded 12-bit data. Therefore, the expanded count value becomes "12'b0110_0100_0000". In high frame rate mode, the first row's selector 251 outputs this expanded count value to the selection circuit 212.

[0079] At time T12, the control pulse P_SEL<0 / 1> becomes high level, and at time T13, the control pulse P_SEL<0 / 1> becomes low level. This operation causes the 0th and 1st rows to be read out during the period from time T12 to time T13.

[0080] The selection circuit 212 in the 0th row connects the signal lines of the lower 6 bits, which are valid data from the count value "12'b0000_0011_1000" output from the selector 251, to the signal lines of bits 0 through 5 of the pixel output signal line 113, respectively. In addition, the selection circuit 212 in the 0th row connects the signal line that transmits the control signal value "0" output from the illuminance determination circuit 230 to the signal line of bit 12 of the pixel output signal line 113.

[0081] The first row of selection circuit 212 connects the signal lines of the upper 6 bits, which are valid data from the count value "12'b0110_0100_0000" output from selector 251, to the signal lines of bits 6 through 11 of pixel output signal line 113, respectively. In addition, the first row of selection circuit 212 connects the signal line that transmits the control signal value "1" output from illuminance determination circuit 230 to the signal line of bit 13 of pixel output signal line 113.

[0082] Therefore, during the period from time T12 to time T13, the pixel output signal line 113 outputs a 14-bit value "14'b10_0110_0111_1000" which represents the count value of the 0th row, the count value of the 1st row, and the attribute value. Here, the lower 6 bits of the count value of the counter circuit 211 of the 0th row are extracted and output, and the upper 6 bits of the count value of the counter circuit 211 of the 1st row are extracted and output.

[0083] At time T14, the second frame period ends. That is, the period from time T7 to time T14 is the second frame period. Further explanation of subsequent operations is omitted.

[0084] Figure 9 is a timing chart showing the operation of the pixel signal processing unit 103 according to this embodiment in a non-high frame rate mode. Figure 9 shows the drive signal CNTEN in row 0. <0> Time variation and control pulse P_RES <0> , P_SEL <0> The time evolution is shown. However, in non-high frame rate mode, there is no difference in operation between even and odd rows, and the same reading is performed for each row. The differences from high frame rate mode are explained below.

[0085] The operation from time T20 to time T24 is the same as the operation of the 0th row from time T0 to time T4 in Figure 8, so the explanation is omitted. At time T24, the count value of the counter circuit 211 in the 0th row is "12'b1000_1100_1110". In non-high frame rate mode, the selector 251 outputs this count value to the selection circuit 212. That is, in non-high frame rate mode, the count value of the counter circuit 211 is output directly to the selection circuit 212 regardless of the judgment result of the illuminance judgment circuit 230.

[0086] Control pulse P_SEL at time T25 <0> The level becomes high, and at time T26, the control pulse P_SEL <0> This goes to a low level. This action causes the 0th row to be read during the period from time T25 to time T26.

[0087] The selection circuit 212 in row 0 connects the signal lines that transmit the count value "12'b1000_1100_1110" output from selector 251 to the signal lines of bits 0 through 11 of the pixel output signal line 113, respectively. In addition, bits 12 and 13 of the pixel output signal line 113 are don't care bits.

[0088] Therefore, during the period from time T25 to time T26, the pixel output signal line 113 outputs a 14-bit value "14'b**_1000_1100_1110" which represents the count value of the 0th row. The symbol "*" indicates a don't care bit. The first frame period ends at time T27.

[0089] In this embodiment, the illuminance determination circuit 230 determines the illuminance, and the selector 240 selects either the upper 6 bits or the lower 6 bits from a 12-bit count value according to the illuminance determination result and outputs 6-bit data. As a result, a signal with bits within a range containing useful information according to the illuminance is output. Therefore, according to this embodiment, a photoelectric converter is provided that can output a more appropriate signal according to the illuminance.

[0090] Furthermore, in this embodiment, in high frame rate mode, even-numbered row data is read from bit 0 to bit 5 of the pixel output signal line 113, and odd-numbered row data is read from bit 6 to bit 11 of the pixel output signal line 113. In other words, the pixel output signal line 113 is shared by the pixel signal processing unit 103 for adjacent even-numbered and odd-numbered rows. As a result, count values ​​can be read two rows at a time simultaneously, reducing the read time to half and achieving twice the read speed compared to the non-high frame rate mode where count values ​​are read one row at a time.

[0091] In this embodiment, the case where the counter circuit 211 is a 12-bit counter is mainly illustrated, but the number of bits in the counter circuit 211 can be changed as appropriate. For example, the number of bits of data held by the counter circuit 211 (12 bits) may be read as N bits (where N is an integer of 2 or more). Also, the number of bits of data output by the bit output units 211a and 211b (6 bits) may be read as M bits (where M is an integer of 1 or more and is less than N). Furthermore, as in the specific example of this embodiment, typically N = 2M. In addition, the pixel output signal line 113 may include (N+2) signal lines. The configuration and operation of this embodiment can be generalized by the above reinterpretations.

[0092] [Second Embodiment] This embodiment describes modified configurations of the pixel signal processing unit 103 and the pixel output signal line 113, as well as the reading method. In this embodiment, elements common to the first embodiment may be omitted or simplified in their description.

[0093] Figure 10 shows an example of the configuration of the pixel signal processing unit 103 according to this embodiment. This embodiment differs from the first embodiment shown in Figure 6 in that there is no difference in operation between even-numbered rows and odd-numbered rows. In addition, in this embodiment, the pixel output signal line 113 is composed of seven signal lines, and the sixth bit signal line of the seven signal lines transmits the attribute value.

[0094] In this embodiment, two types of control pulses, P_SEL1 and P_SEL2, are supplied to the selection circuit 212. Control pulse P_SEL1 is supplied from the control signal generation unit 115 to the selection circuit 212 via the vertical scanning circuit 110 and the drive line 214a. Control pulse P_SEL2 is supplied from the control signal generation unit 115 to the selection circuit 212 via the vertical scanning circuit 110 and the drive line 214b.

[0095] The pixel output circuit 250 expands the 6-bit data output from the selector 240 into 12-bit data by storing it in the upper 6 bits, and then inputs it to the selector 251. Therefore, the upper 6 bits of the expanded 12-bit data contain the valid data.

[0096] When a row is selected by control pulse P_SEL1, the selection circuit 212 connects the signal lines of the upper 6 bits of the 12-bit data output from selector 251 to the signal lines of bits 0 through 5 of the pixel output signal line 113, respectively. When a row is selected by control pulse P_SEL2, the selection circuit 212 connects the signal lines of the lower 6 bits of the 12-bit data output from selector 251 to the signal lines of bits 0 through 5 of the pixel output signal line 113, respectively. In addition, regardless of whether a row is selected by control pulse P_SEL1 or control pulse P_SEL2, the selection circuit 212 connects the signal line that transmits the 1-bit control signal output from illuminance determination circuit 230 to the signal line of bit 6 of the pixel output signal line 113.

[0097] When not in high frame rate mode, the control signal generation unit 115 alternately supplies control pulses P_SEL1 and P_SEL2 to the selection circuit 212. As a result, the upper 6 bits and lower 6 bits of the 12-bit data output from the selector 251 are alternately output to bits 0 through 5 of the pixel output signal line 113.

[0098] In high frame rate mode, the control signal generation unit 115 continuously supplies only the control pulse P_SEL1 to the selection circuit 212. As a result, only the upper 6 bits, which are the valid data of the 12-bit data output from the selector 251, are output to bits 0 through 5 of the pixel output signal line 113. The processing circuit that performs subsequent processing can determine whether the read data is a count value output from either bit output unit 211a or bit output unit 211b by referring to the value of bit 6 of the pixel output signal line 113 as an attribute value.

[0099] Figures 11(a) and 11(b) illustrate the operation in the high frame rate mode and non-high frame rate mode according to this embodiment. Figures 11(a) and 11(b) show the control pulse P_SEL1 of the 0th row. <0> , P_SEL2 <0> Control pulse P_SEL1 of the Xth row <x>、P_SEL2 <x>The time evolution is shown.

[0100] Figure 11(a) shows the read operation in non-high frame rate mode. In non-high frame rate mode, the control signal generation unit 115 controls the selection circuit 212 so that all bits of the 12-bit data output from the selector 251 are read. Therefore, the control pulse P_SEL1 <0> , P_SEL2 <0> , P_SEL1 <1> , P_SEL2 <1> ,...,P_SEL1 <x>、P_SEL2 <x>As the level increases sequentially, each line is read twice.

[0101] Figure 11(b) shows the read operation in high frame rate mode. In high frame rate mode, the control signal generation unit 115 controls the selection circuit 212 so that only the upper 6 bits, which are valid data, are read from the 12-bit data output from the selector 251. Therefore, P_SEL1 <0> , P_SEL1 <1> ,...,P_SEL1 <x>The levels gradually increase, P_SEL2 <0> , P_SEL2 <1> ,...,P_SEL2 <x>Because it is kept at a low level, each line is read only once. This results in a 1 / 20 reading speed in high frame rate mode, as the reading time is halved compared to non-high frame rate mode.

[0102] Figure 12 is a timing chart showing the operation of the pixel signal processing unit 103 according to this embodiment in high frame rate mode. Figure 12 shows the time variation of the drive signal CNTEN and the time variation of the control pulses P_RES, P_SEL1, and P_SEL2 in one row. Figure 12 also shows the time variation of the count value in each part of the pixel signal processing unit 103 and the time variation of the control signal output from the illumination determination circuit 230. As shown in Figure 12, in high frame rate mode, the control pulse P_SEL2 is always at a low level.

[0103] At time T30, the first frame period begins. After time T30, the control pulse P_RES becomes high, and then at time T31, the control pulse P_RES becomes low. As a result, the count value held in the counter circuit 211 is reset to "0". Consequently, the count values ​​output from the bit output units 211a and 211b are also reset to "0".

[0104] At time T32, the drive signal CNTEN becomes high level, and the counting operation in the counter circuit 211 begins. In other words, time T32 is the start time of the exposure period. Also at time T32, the count value of the bit output section 211b, which corresponds to the lower 6 bits of the counter circuit 211, begins to increase.

[0105] At time T33, the value is carried to the LSB of the upper 6 bits of the counter circuit 211. As a result, the count value of the bit output section 211a, which corresponds to the upper 6 bits of the counter circuit 211, begins to increase. Also at time T33, because one of the upper 6 bits of the counter circuit 211 becomes "1", the value of the control signal output from the illuminance determination circuit 230 also becomes "1".

[0106] At time T34, the drive signal CNTEN becomes low level, and the counting operation in the counter circuit 211 ends. In other words, time T34 is the end time of the exposure period.

[0107] At time T34, the count value of the counter circuit 211 is "12'b1000_1100_1110". Therefore, the count value of the bit output section 211a, which is the upper 6 bits of the counter circuit 211, is "6'b10_0011", and the count value of the bit output section 211b, which is the lower 6 bits of the counter circuit 211, is "6'b00_1110".

[0108] Since the control signal output from the illuminance determination circuit 230 is "1", the selector 240 selects the count value of the bit output unit 211a. The pixel output circuit 250 expands the 6-bit data output from selector 240 to 12 bits and inputs it to selector 251. At this time, the 6-bit data output from selector 240 is stored in the upper 6 bits of the expanded 12-bit data. Therefore, the expanded count value becomes "12'b1000_1100_0000". In high frame rate mode, selector 251 outputs this expanded count value to selection circuit 212.

[0109] At time T35, the control pulse P_SEL1 becomes high level, and at time T36, the control pulse P_SEL1 becomes low level. This operation causes reading to occur during the period from time T35 to time T36.

[0110] The selection circuit 212 connects the signal lines of the upper 6 bits, which are valid data from the count value "12'b1000_1100_0000" output from the selector 251, to the signal lines of bits 0 through 5 of the pixel output signal line 113, respectively. In addition, the selection circuit 212 connects the signal line that transmits the control signal value "1" output from the illuminance determination circuit 230 to the signal line of bit 6 of the pixel output signal line 113.

[0111] Therefore, during the period from time T35 to time T36, the pixel output signal line 113 outputs "7'b110_0011", which represents the upper 6 bits of the count value of the counter circuit 211 and the attribute value.

[0112] At time T37, the first frame period ends. That is, the period from time T30 to time T37 is the first frame period. Then, the second frame period begins at time T37.

[0113] After time T37, the control pulse P_RES becomes high level, and then at time T38, the control pulse P_RES becomes low level. As a result, the count value held in the counter circuit 211 is reset to "0". Consequently, the count values ​​output from the bit output units 211a and 211b are also reset to "0". In addition, the value of the control signal output from the illuminance determination circuit 230 is also reset to "0".

[0114] At time T39, the drive signal CNTEN becomes high level, and the counting operation in the counter circuit 211 begins. In other words, time T39 is the start time of the exposure period. Also at time T39, the count value of the bit output section 211b, which corresponds to the lower 6 bits of the counter circuit 211, begins to increase.

[0115] At T40, the drive signal CNTEN becomes low level, and the counting operation in the counter circuit 211 ends. In other words, time T40 is the end time of the exposure period.

[0116] At time T40, the count value of the counter circuit 211 is "12'b0000_0011_1000". Therefore, the count value of the bit output section 211a, which is the upper 6 bits of the counter circuit 211, is "6'b00_0000", and the count value of the bit output section 211b, which is the lower 6 bits of the counter circuit 211, is "6'b11_1000".

[0117] Since the control signal output from the illuminance determination circuit 230 is "0", the selector 240 selects the count value of the bit output unit 211b. The pixel output circuit 250 expands the 6-bit data output from selector 240 to 12 bits and inputs it to selector 251. At this time, the 6-bit data output from selector 240 is stored in the upper 6 bits of the expanded 12-bit data. Therefore, the expanded count value becomes "12'b1110_0000_0000". In high frame rate mode, selector 251 outputs this expanded count value to selection circuit 212.

[0118] At time T41, the control pulse P_SEL1 becomes high level, and at time T42, the control pulse P_SEL1 becomes low level. This operation causes reading to occur during the period from time T41 to time T42.

[0119] The selection circuit 212 connects the signal lines of the upper 6 bits, which are valid data from the count value "12'b1110_0000_0000" output from the selector 251, to the signal lines of bits 0 through 5 of the pixel output signal line 113, respectively. The selection circuit 212 also connects the signal line that transmits the control signal value "0" output from the illuminance determination circuit 230 to the signal line of bit 6 of the pixel output signal line 113.

[0120] Therefore, during the period from time T41 to time T42, the pixel output signal line 113 outputs "7'b011_1000", which represents the lower 6 bits of the count value of the counter circuit 211 and the attribute value.

[0121] At time T43, the second frame period ends. That is, the period from time T37 to time T43 is the second frame period. Further explanation of subsequent operations is omitted.

[0122] Figure 13 is a timing chart showing the operation of the pixel signal processing unit 103 according to this embodiment in non-high frame rate mode. The differences from high frame rate mode will be explained below.

[0123] The operation from time T50 to time T54 is the same as the operation from time T30 to time T34 in Figure 12, so the explanation is omitted. At time T54, the count value of the counter circuit 211 is "12'b1000_1100_1110". In non-high frame rate mode, the selector 251 outputs this count value to the selection circuit 212. That is, in non-high frame rate mode, regardless of the judgment result of the illuminance judgment circuit 230, the count value of the counter circuit 211 is output directly to the selection circuit 212.

[0124] At time T55, the control pulse P_SEL1 becomes high, and at time T56, the control pulse P_SEL1 becomes low. This operation causes the upper 6 bits to be read during the period from time T55 to time T56.

[0125] The selection circuit 212 connects the signal lines of the upper 6 bits of the count value "12'b1000_1100_1110" output from the selector 251 to the signal lines of bits 0 through 5 of the pixel output signal line 113, respectively. Bit 6 of the pixel output signal line 113 is the don't care bit.

[0126] Therefore, during the period from time T55 to time T56, the pixel output signal line 113 outputs "7'b*10_0011", which represents the upper 6 bits of the count value of the counter circuit 211.

[0127] At time T57, the control pulse P_SEL2 becomes high, and at time T58, the control pulse P_SEL2 becomes low. This operation causes the lower 6 bits to be read during the period from time T57 to time T58.

[0128] The selection circuit 212 connects the lower 6 bits of the count value "12'b1000_1100_1110" output from the selector 251 to the signal lines of bits 0 through 5 of the pixel output signal line 113, respectively. Bit 6 of the pixel output signal line 113 is the don't care bit.

[0129] Therefore, during the period from time T57 to time T58, the pixel output signal line 113 outputs "7'b*00_1110", which represents the lower 6 bits of the count value of the counter circuit 211. The first frame period ends at time T59.

[0130] Similar to the first embodiment, this embodiment also provides a photoelectric converter capable of outputting a more appropriate signal according to the illuminance. Furthermore, in this embodiment, in non-high frame rate mode, each row is read out in multiple steps by control pulses P_SEL1 and P_SEL2. In contrast, in high frame rate mode, each row is read out once by control pulse P_SEL1. As a result, in high frame rate mode, the read time is halved compared to non-high frame rate mode, and twice the read speed is achieved.

[0131] In this embodiment as well, the number of bits in the counter circuit 211 can be changed as appropriate. For example, the number of bits in the data held by the counter circuit 211 (12 bits) may be read as N bits (where N is an integer of 2 or more). Also, the number of bits in the data output by the bit output units 211a and 211b (6 bits) may be read as M bits (where M is an integer of 1 or more and is less than N). Furthermore, as in the specific example of this embodiment, typically N = 2M. In addition, the pixel output signal line 113 may include (M+1) or (N / 2+1) signal lines. The configuration and operation of this embodiment can be generalized by the above-mentioned reinterpretations.

[0132] [Third Embodiment] This embodiment describes modified configurations of the pixel signal processing unit 103 and the pixel output signal line 113, as well as the reading method. In this embodiment, elements common to the first or second embodiment may be omitted or simplified in their description.

[0133] Figure 14 shows an example of the configuration of the pixel signal processing unit 103 according to this embodiment. In this embodiment, the counter circuit 211 has four bit output units 211a, 211b, 211c, and 211d. In this embodiment, the pixel output signal line 113 is composed of eight signal lines, with a seventh bit signal line for transmitting attribute values ​​added compared to the configuration of the second embodiment. In this embodiment, the circuit block including the counter circuit 211, the illuminance determination circuit 230, and the selector 240 is called the extraction circuit 260.

[0134] The bit output unit 211a outputs the data CNT[11:6], which consists of the upper 6 bits of the 12-bit data held in the counter circuit 211. Here, the two numbers in square brackets of "CNT[11:6]" indicate the range of bit values ​​included in the output data from the 12-bit data. That is, the data CNT[11:6] includes bit values ​​from the 6th bit to the 11th bit of the 12-bit data.

[0135] Furthermore, bit output unit 211b outputs the upper-middle 6 bits of the 12-bit data held by the counter circuit 211, CNT[9:4]. Bit output unit 211c outputs the lower-middle 6 bits of the 12-bit data held by the counter circuit 211, CNT[7:2]. Bit output unit 211d outputs the lower 6 bits of the 12-bit data held by the counter circuit 211, CNT[5:0]. In this way, the counter circuit 211 can output the 12-bit data it holds in four ranges (first range, second range, third range, and fourth range): the upper 6 bits, the upper-middle 6 bits, the lower-middle 6 bits, and the lower 6 bits. In this embodiment, the ranges of bits output by the four bit output units are set to partially overlap.

[0136] The illuminance determination circuit 230 receives the upper 6 bits of data CNT[11:6] output from the bit output unit 211a. Based on the data CNT[11:6], the illuminance determination circuit 230 outputs control signals indicating the illuminance to the selector 240 and the selection circuit 212. The selector 240 selects one of the data CNT[11:6], CNT[9:4], CNT[7:2], or CNT[5:0] according to the control signal input from the illuminance determination circuit 230 and outputs it to the pixel output circuit 250.

[0137] In this embodiment, a 2-bit control signal is input to the selection circuit 212 from the illuminance determination circuit 230. Regardless of whether a row is selected for control pulse P_SEL1 or P_SEL2, the selection circuit 212 connects the signal line that transmits the 2-bit control signal output from the illuminance determination circuit 230 to the 6th and 7th bit signal lines of the pixel output signal line 113. The other operations of the pixel output circuit 250 are the same as in the second embodiment. The processing circuit that performs subsequent processing can determine whether the read data is a count value output from any of the bit output units 211a, 211b, 211c, or 211d by referring to the values ​​of the 6th and 7th bits of the pixel output signal line 113 as attribute values.

[0138] Figure 15 shows an example configuration of the extraction circuit 260 according to this embodiment. In Figure 15, the configuration of the extraction circuit 260 in Figure 14 is shown in more detail. The selectors 240a, 240b, and 240c in Figure 15 are separate representations of the selector 240 in Figure 14.

[0139] Figure 15 also shows the four types of control signals ATTR[1:0], A_SEL, B_SEL, and C_SEL output from the illuminance determination circuit 230. The illuminance determination circuit 230 outputs control signal A_SEL to selector 240a, control signal B_SEL to selector 240b, and control signal C_SEL to selector 240c. Each of the control signals A_SEL, B_SEL, and C_SEL is a 1-bit signal. The illuminance determination circuit 230 outputs the control signal ATTR[1:0] to the selection circuit 212. The control signal ATTR[1:0] is a 2-bit signal composed of the first bit control signal ATTR[1] and the zeroth bit control signal ATTR[0].

[0140] Selector 240c receives data CNT[7:2] and CNT[5:0] as inputs. Selector 240c outputs data CNT[7:2] when the control signal C_SEL is "1", and outputs data CNT[5:0] when the control signal C_SEL is "0".

[0141] Selector 240b receives the data CNT[9:4] and the output signal of selector 240c as inputs. Selector 240b outputs the data CNT[9:4] when the control signal B_SEL is "1", and outputs the output signal of selector 240c when the control signal B_SEL is "0".

[0142] Selector 240a receives the data CNT[11:6] and the output signal of selector 240b. Selector 240a outputs the data CNT[11:6] when the control signal A_SEL is "1", and outputs the output signal of selector 240b when the control signal A_SEL is "0".

[0143] The illuminance determination circuit 230 calculates the values ​​of control signals A_SEL, B_SEL, and C_SEL using the values ​​of each bit that make up the data CNT[11:6] output from the bit output unit 211a, according to the following equations (1) to (3). Note that "|" indicates bitwise OR. A_SEL=CNT

[11] |CNT

[10] (1) B_SEL=CNT[9]|CNT[8] (2) C_SEL=CNT[7]|CNT[6] (3)

[0144] Furthermore, the illuminance determination circuit 230 calculates the value of the control signal ATTR[1:0] using the values ​​of control signals A_SEL, B_SEL, and C_SEL according to the following equations (4) and (5). Note that "~" indicates bit inversion and "&" indicates bitwise AND. ATTR[1]=A_SEL|B_SEL (4) ATTR[0]=A_SEL|(~B_SEL&C_SEL) (5)

[0145] For example, if the count value of the counter circuit 211 is "12'b0000_0010_1011", then the control signals A_SEL, B_SEL, and C_SEL are all "0". In this case, the 6-bit data output from selector 240a corresponds to the data CNT[5:0] output from bit output unit 211d, which is "6'b10_1011". Also, the control signal ATTR[1:0] is "2'b00".

[0146] In another example, if the count value of the counter circuit 211 is "12'b0000_1010_1111", then both control signals A_SEL and B_SEL are "0", and control signal C_SEL is "1". In this case, the 6-bit data output from selector 240a corresponds to the data CNT[7:2] output from bit output unit 211c, which is "6'b10_1011". Also, the control signal ATTR[1:0] is "2'b01".

[0147] In another example, if the count value of the counter circuit 211 is "12'b0010_1011_1111", then the control signal A_SEL is "0", and both control signals B_SEL and C_SEL are "1". In this case, the count value output from selector 240a corresponds to the data CNT[9:4] output from bit output unit 211b, which is "6'b10_1011". Also, the control signal ATTR[1:0] is "2'b10".

[0148] In another example, if the count value of the counter circuit 211 is "12'b1010_1111_1111", then the control signals A_SEL, B_SEL, and C_SEL are all "1". In this case, the count value output from selector 240a is "6'b10_1011", which corresponds to the data CNT[11:6] output from bit output unit 211a. Also, the control signal ATTR[1:0] is "2'b11".

[0149] Specifically, when the count value reaches the upper two bits of the output data of the bit output unit 211a, the extraction circuit 260 outputs data CNT[11:6]. Similarly, when the count value reaches the upper two bits of the output data of the bit output unit 211b, the extraction circuit 260 outputs data CNT[9:4]. When the count value reaches the upper two bits of the output data of the bit output unit 211c, the extraction circuit 260 outputs data CNT[7:2]. If the count value does not reach the upper two bits of the output data of the bit output unit 211c, the extraction circuit 260 outputs data CNT[5:0].

[0150] In this embodiment, the same effects as in the second embodiment can be obtained. Furthermore, in this embodiment, the bit output units 211a, 211b, 211c, and 211d output data containing bits of four different ranges, and the range of bits included in the output data can be switched in four stages depending on the bit reached by the count value. As a result, in this embodiment, data containing more useful information can be output compared to the configuration of the second embodiment.

[0151] In this embodiment as well, the number of bits in the counter circuit 211 can be changed as appropriate. For example, the number of bits in the data held by the counter circuit 211 (12 bits) may be read as N bits (where N is an integer of 2 or more). Also, the number of bits in the data output by the bit output units 211a, 211b, 211c, and 211d (6 bits) may be read as M bits (where M is an integer of 1 or more and is less than N). Furthermore, as in the specific example of this embodiment, typically N = 2M. In addition, the pixel output signal line 113 may include (M+2) or (N / 2+2) signal lines. The configuration and operation of this embodiment can be generalized by the above-mentioned reinterpretations.

[0152] [Fourth Embodiment] This embodiment describes modified configurations of the pixel signal processing unit 103 and the pixel output signal line 113, as well as the reading method. In this embodiment, elements common to the first to third embodiments may be omitted or simplified in their description.

[0153] Figure 16 shows an example of the configuration of the pixel signal processing unit 103 according to this embodiment. In this embodiment, the counter circuit 211 has three bit output units 211a, 211b, and 211c. Also, in this embodiment, the pixel output signal line 113 is composed of five signal lines, and the fourth bit signal line of the five signal lines transmits the attribute value.

[0154] In this embodiment, in addition to control pulses P_SEL1 and P_SEL2, a control pulse P_SEL3 is also supplied to the selection circuit 212. The control pulse P_SEL3 is supplied from the control signal generation unit 115 to the selection circuit 212 via the vertical scanning circuit 110 and the drive line 214c.

[0155] Bit output unit 211a outputs the upper 8 bits of the 12-bit data held in the counter circuit 211, CNT[11:4]. Bit output unit 211b outputs the middle 8 bits of the 12-bit data held in the counter circuit 211, CNT[9:2]. Bit output unit 211c outputs the lower 8 bits of the 12-bit data held in the counter circuit 211, CNT[7:0].

[0156] The illuminance determination circuit 230 receives the upper 8 bits of data CNT[11:4] output from the bit output unit 211a. Based on the data CNT[11:4], the illuminance determination circuit 230 outputs control signals indicating the illuminance to the selector 240 and the selection circuit 212. The selector 240 selects one of the data CNT[11:4], CNT[9:2], or CNT[7:0] according to the control signal input from the illuminance determination circuit 230 and outputs it to the pixel output circuit 250.

[0157] The pixel output circuit 250 expands the 8-bit data output from the selector 240 into 12-bit data by storing it in the upper 8 bits, and then inputs it to the selector 251. Therefore, the upper 8 bits of the expanded 12-bit data contain the valid data.

[0158] When a row is selected by the control pulse P_SEL1, the selection circuit 212 connects the signal lines of the upper four bits of the 12-bit data output from the selector 251 to the signal lines of bits 0 through 3 of the pixel output signal line 113, respectively. At the same time, the selection circuit 212 also connects the signal line of the upper one bit of the 2-bit control signal output from the illuminance determination circuit 230 to the signal line of bit 4 of the pixel output signal line 113.

[0159] When a row is selected by the control pulse P_SEL2, the selection circuit 212 connects the middle four bits of the 12-bit data output from the selector 251 to the signal lines of bits 0 through 3 of the pixel output signal line 113, respectively. At the same time, the selection circuit 212 also connects the lower one bit of the two-bit control signal output from the illuminance determination circuit 230 to the signal line of bit 4 of the pixel output signal line 113.

[0160] When a row is selected by the control pulse P_SEL3, the selection circuit 212 connects the signal lines of the lower 4 bits of the 12-bit data output from the selector 251 to the signal lines of the 0th to 3rd bits of the pixel output signal line 113, respectively.

[0161] When not in high frame rate mode, the control signal generation unit 115 cyclically supplies control pulses P_SEL1, P_SEL2, and P_SEL3 to the selection circuit 212. As a result, the upper 4 bits, middle 4 bits, and lower 4 bits of the 12-bit data output from the selector 251 are cyclically output to bits 0 through 3 of the pixel output signal line 113.

[0162] In high frame rate mode, the control signal generation unit 115 alternately supplies control pulses P_SEL1 and P_SEL2 to the selection circuit 212. As a result, only the upper 4 bits and middle 4 bits, which are the valid data of the 12-bit data output from the selector 251, are output to bits 0 through 3 of the pixel output signal line 113. The processing circuit that performs subsequent processing can determine whether the read data is a count value output from either bit output unit 211a or 211b by referring to the value of bit 4 of the pixel output signal line 113 as an attribute value.

[0163] Figures 17(a) and 17(b) illustrate the operation in the high frame rate mode and non-high frame rate mode according to this embodiment. Figures 17(a) and 17(b) show the control pulse P_SEL1 of the 0th row. <0> , P_SEL2 <0> , P_SEL3 <0> Control pulse P_SEL1 of the Xth row <x>、P_SEL2 <x>、P_SEL3 <x>The time evolution is shown.

[0164] Figure 17(a) shows the read operation in non-high frame rate mode. In non-high frame rate mode, the control signal generation unit 115 controls the selection circuit 212 so that all bits of the 12-bit data output from the selector 251 are read. Therefore, the control pulse P_SEL1 <0> , P_SEL2 <0> , P_SEL3 <0> ,...,P_SEL1 <x>、P_SEL2 <x>、P_SEL3 <x>As the level increases sequentially, each line is read three times.

[0165] Figure 17(b) shows the read operation in high frame rate mode. In high frame rate mode, the control signal generation unit 115 controls the selection circuit 212 so that only the upper 8 bits, which are valid data, are read from the 12-bit data output from the selector 251. Therefore, the control pulse P_SEL1 <0> , P_SEL2 <0> , P_SEL1 <1> , P_SEL2 <1> ,...,P_SEL1 <x>、P_SEL2 <x>The levels will gradually increase. Also, the control pulse P_SEL3 <0> , P_SEL3 <1> ,...,P_SEL3 <x>This is kept at a low level. Therefore, each line is read twice. This reduces the read time to 2 / 3 in high frame rate mode compared to non-high frame rate mode, resulting in a 1.5 times faster read speed.

[0166] In this embodiment, in non-high frame rate mode, the 12-bit count value is read out in three 4-bit increments, while in high frame rate mode, 8 of the 12 bits are read out in two 4-bit increments. However, in high frame rate mode, 4 of the 12 bits may be read out in a single increment. Thus, the number of bits read out at one time, the total number of bits read out, the number of reads, etc., are not limited to the illustrated examples.

[0167] For example, in non-high frame rate mode, the 12-bit count value may be read out in 2-bit increments six times, and in high frame rate mode, 10 of the 12 bits may be read out in 2-bit increments five times. In this case, each bit output unit can output 10-bit data. Alternatively, for example, in non-high frame rate mode, the 12-bit count value may be read out in 2-bit increments six times, and in high frame rate mode, 4 of the 12 bits may be read out in 2-bit increments twice. In this case, each bit output unit can output 4-bit data.

[0168] Figure 18 shows an example of the configuration of the extraction circuit 260 according to this embodiment. In Figure 18, the configuration of the extraction circuit 260 in Figure 16 is shown in more detail. The selectors 240a and 240b in Figure 18 are separate representations of the selector 240 in Figure 16.

[0169] Figure 18 also shows the three types of control signals ATTR[1:0], A_SEL, and B_SEL output from the illuminance determination circuit 230. The illuminance determination circuit 230 outputs the control signal A_SEL to selector 240a and the control signal B_SEL to selector 240b. The illuminance determination circuit 230 outputs the control signal ATTR[1:0] to selection circuit 212. The control signal ATTR[1:0] is a 2-bit signal, and each of the control signals A_SEL and B_SEL is a 1-bit signal.

[0170] Selector 240b receives data CNT[9:2] and data CNT[7:0] as inputs. Selector 240b outputs data CNT[9:2] when the control signal B_SEL is "1", and outputs data CNT[7:0] when the control signal B_SEL is "0".

[0171] Selector 240a receives the data CNT[11:4] and the output signal of selector 240b. Selector 240a outputs the data CNT[11:4] when the control signal A_SEL is "1", and outputs the output signal of selector 240b when the control signal A_SEL is "0".

[0172] The illuminance determination circuit 230 calculates the values ​​of control signals A_SEL and B_SEL using the values ​​of the upper 4 bits of the data CNT[11:4] output from the bit output unit 211a, according to the following equations (6) and (7). A_SEL=CNT

[11] |CNT

[10] (6) B_SEL=CNT[9]|CNT[8] (7)

[0173] Furthermore, the illuminance determination circuit 230 calculates the value of the control signal ATTR[1:0] using the values ​​of control signals A_SEL and B_SEL, according to the following equations (8) and (9). ATTR[1]=A_SEL (8) ATTR[0]=B_SEL (9)

[0174] For example, if the count value of the counter circuit 211 is "12'b0000_0010_1011", then both control signals A_SEL and B_SEL are "0". In this case, the 8-bit data output from selector 240a is "8'b0010_1011", which corresponds to the data CNT[7:0] output from bit output unit 211c. Also, the control signal ATTR[1:0] is "2'b00".

[0175] In another example, when the count value of the counter circuit 211 is "12'b0000_1010_1111", both control signals A_SEL and B_SEL are "0". In this case, the 8-bit data output from selector 240a is "8'b1010_1111", which corresponds to the data CNT[7:0] output from bit output unit 211c. Also, the control signal ATTR[1:0] is "2'b00".

[0176] In another example, if the count value of the counter circuit 211 is "12'b0010_1011_1111", then the control signal A_SEL is "0" and the control signal B_SEL is "1". In this case, the 8-bit data output from selector 240a is "8'b1010_1111", which corresponds to the data CNT[9:2] output from bit output unit 211b. Also, the control signal ATTR[1:0] is "2'b01".

[0177] In another example, if the count value of the counter circuit 211 is "12'b1010_1111_1111", then both control signals A_SEL and B_SEL are "1". In this case, the 8-bit data output from selector 240a is "8'b1010_1111", which corresponds to the data CNT[11:4] output from bit output unit 211a. Also, the control signal ATTR[1:0] is "2'b11".

[0178] In other words, if the count value reaches the upper two bits of the output data of the bit output unit 211a, the extraction circuit 260 outputs data CNT[11:4]. Similarly, if the count value reaches the upper two bits of the output data of the bit output unit 211b, the extraction circuit 260 outputs data CNT[9:2]. If the count value does not reach the upper two bits of the output data of the bit output unit 211b, the extraction circuit 260 outputs data CNT[7:0].

[0179] When the extraction circuit 260 outputs the data CNT[11:4], the value of the control signal ATTR[1:0] can be either "2'b11" or "2'b10". The processing circuit that performs subsequent processing can determine that the read data was output from the bit output unit 211a if the upper bit of the control signal ATTR[1:0] is "1". In other words, when the upper bit of the control signal ATTR[1:0] is "1", the lower bit of the control signal ATTR[1:0] is a don't care bit.

[0180] Figure 19 is a timing chart showing the operation of the pixel signal processing unit 103 in the high frame rate mode according to this embodiment. Figure 19 shows the time variation of the drive signal CNTEN and the time variation of the control pulses P_RES, P_SEL1, P_SEL2, and P_SEL3 in one row. Figure 19 also shows the time variation of the count value in each part of the pixel signal processing unit 103 and the time variation of the control signal ATTR[1:0] output from the illumination determination circuit 230. As shown in Figure 19, in the high frame rate mode, the control pulse P_SEL3 is always at a low level.

[0181] At time T60, the first frame period begins. After time T60, the control pulse P_RES becomes high, and then at time T61, the control pulse P_RES becomes low. As a result, the count value held in the counter circuit 211 is reset to "0". Consequently, the count values ​​output from the bit output units 211a, 211b, and 211c are also reset to "0".

[0182] At time T62, the drive signal CNTEN becomes high level, and the counting operation in the counter circuit 211 begins. In other words, time T62 is the start time of the exposure period. At time T63, the drive signal CNTEN becomes low level, and the counting operation in the counter circuit 211 ends. In other words, time T63 is the end time of the exposure period.

[0183] At time T63, the count value of the counter circuit 211 is "12'b1000_1100_1110". Therefore, the count value of the upper 8 bits of the counter circuit 211, bit output section 211a, is "8'b1000_1100", and the count value of the middle 8 bits of the counter circuit 211, bit output section 211b, is "8'b0011_0011". Also, the count value of the lower 8 bits of the counter circuit 211, bit output section 211c, is "8'b1100_1110".

[0184] From equations (6) to (9), the control signal A_SEL is "1", the control signal B_SEL is "0", and the control signal ATTR[1:0] is "2'b10". Therefore, selector 240 selects the count value of bit output unit 211a. Pixel output circuit 250 expands the 8-bit data output from selector 240 to 12 bits and inputs it to selector 251. At this time, the 8-bit data output from selector 240 is stored in the upper 8 bits of the expanded 12-bit data. Therefore, the expanded count value becomes "12'b1000_1100_0000". In high frame rate mode, selector 251 outputs this expanded count value to selection circuit 212.

[0185] At time T64, the control pulse P_SEL1 becomes high level, and at time T65, the control pulse P_SEL1 becomes low level. This operation causes reading to occur during the period from time T64 to time T65.

[0186] The selection circuit 212 connects the signal lines of the upper 4 bits, which are valid data from the count value "12'b1000_1100_0000" output from the selector 251, to the signal lines of bits 0 through 3 of the pixel output signal line 113, respectively. In addition, the selection circuit 212 connects the signal line of the upper 1 bit of the attribute value "2'b10" indicated by the control signal ATTR[1:0] output from the illuminance determination circuit 230 to the signal line of bit 4 of the pixel output signal line 113.

[0187] Therefore, during the period from time T64 to time T65, the pixel output signal line 113 outputs "5'b1_1000", which represents the upper 4 bits of the count value of the counter circuit 211 and the upper 1 bit of the attribute value.

[0188] At time T66, the control pulse P_SEL2 becomes high level, and at time T67, the control pulse P_SEL2 becomes low level. This operation causes reading to occur during the period from time T66 to time T67.

[0189] The selection circuit 212 connects the middle four bits of the count value "12'b1000_1100_0000" output from the selector 251, which are valid data, to the signal lines of bits 0 through 3 of the pixel output signal line 113, respectively. In addition, the selection circuit 212 connects the lower one bit of the attribute value "2'b10" indicated by the control signal ATTR[1:0] output from the illuminance determination circuit 230 to the signal line of bit 4 of the pixel output signal line 113.

[0190] Therefore, during the period from time T66 to time T67, the pixel output signal line 113 outputs "5'b0_1100", which represents the middle 4 bits of the count value and the lower 1 bit of the attribute value of the counter circuit 211.

[0191] At time T68, the first frame period ends. That is, the period from time T60 to time T68 is the first frame period. Then, the second frame period begins at time T68.

[0192] After time T68, the control pulse P_RES goes high, and then at time T69, the control pulse P_RES goes low. As a result, the count value held in the counter circuit 211 is reset to "0". Consequently, the count values ​​output from the bit output units 211a, 211b, and 211c are also reset to "0". In addition, the value of the control signal ATTR[1:0] output from the illuminance determination circuit 230 is also reset to "0".

[0193] At time T70, the drive signal CNTEN becomes high level, and the counting operation in the counter circuit 211 begins. In other words, time T70 is the start time of the exposure period. At time T71, the drive signal CNTEN becomes low level, and the counting operation in the counter circuit 211 ends. In other words, time T71 is the end time of the exposure period.

[0194] At time T71, the count value of the counter circuit 211 is "12'b0000_0011_1000". Therefore, the count value of the bit output section 211a, which is the upper 8 bits of the counter circuit 211, is "8'b0000_0011", and the count value of the bit output section 211b, which is the middle 8 bits of the counter circuit 211, is "8'b0000_1110". Also, the count value of the bit output section 211c, which is the lower 8 bits of the counter circuit 211, is "8'b0011_1000".

[0195] From equations (6) to (9), the control signal A_SEL is "0", the control signal B_SEL is "0", and the control signal ATTR[1:0] is "2'b00". Therefore, selector 240 selects the count value of bit output unit 211c. Pixel output circuit 250 expands the 8-bit data output from selector 240 to 12 bits and inputs it to selector 251. At this time, the 8-bit data output from selector 240 is stored in the upper 8 bits of the expanded 12-bit data. Therefore, the expanded count value becomes "12'b0011_1000_0000". In high frame rate mode, selector 251 outputs this expanded count value to selection circuit 212.

[0196] At time T72, the control pulse P_SEL1 becomes high level, and at time T73, the control pulse P_SEL1 becomes low level. This operation causes reading to occur during the period from time T72 to time T73.

[0197] The selection circuit 212 connects the signal lines of the upper 4 bits, which are valid data from the count value "12'b0011_1000_0000" output from the selector 251, to the signal lines of bits 0 through 3 of the pixel output signal line 113, respectively. In addition, the selection circuit 212 connects the signal line of the upper 1 bit of the attribute value "2'b00" indicated by the control signal ATTR[1:0] output from the illuminance determination circuit 230 to the signal line of bit 4 of the pixel output signal line 113.

[0198] Therefore, during the period from time T72 to time T73, the pixel output signal line 113 outputs "5'b0_0011", which represents the middle 4 bits of the count value of the counter circuit 211 and the upper 1 bit of the attribute value.

[0199] At time T74, the control pulse P_SEL2 becomes high level, and at time T75, the control pulse P_SEL2 becomes low level. This operation causes reading to occur during the period from time T74 to time T75.

[0200] The selection circuit 212 connects the middle four bits of the count value "12'b0011_1000_0000" output from the selector 251, which are valid data, to the signal lines of bits 0 through 3 of the pixel output signal line 113, respectively. In addition, the selection circuit 212 connects the lower one bit of the attribute value "2'b00" indicated by the control signal ATTR[1:0] output from the illuminance determination circuit 230 to the signal line of bit 4 of the pixel output signal line 113.

[0201] Therefore, during the period from time T74 to time T75, the pixel output signal line 113 is connected to and outputs "5'b0_1000", which represents the lower 4 bits of the count value of the counter circuit 211 and the lower 1 bit of the attribute value.

[0202] At time T76, the second frame period ends. That is, the period from time T68 to time T76 is the second frame period. Then, the third frame period begins at time T76.

[0203] After time T76, the control pulse P_RES goes high, and then at time T77, the control pulse P_RES goes low. As a result, the count value held in the counter circuit 211 is reset to "0". Consequently, the count values ​​output from the bit output units 211a, 211b, and 211c are also reset to "0". In addition, the value of the control signal ATTR[1:0] output from the illuminance determination circuit 230 is also reset to "0".

[0204] At time T78, the drive signal CNTEN becomes high level, and the counting operation in the counter circuit 211 begins. In other words, time T78 is the start time of the exposure period. At time T79, the drive signal CNTEN becomes low level, and the counting operation in the counter circuit 211 ends. In other words, time T79 is the end time of the exposure period.

[0205] At time T79, the count value of counter circuit 211 is "12'b0010_1111_0000". Therefore, the count value of bit output section 211a, which is the upper 8 bits of counter circuit 211, is "8'b0010_1111", and the count value of bit output section 211b, which is the middle 8 bits of counter circuit 211, is "8'b1011_1100". Also, the count value of bit output section 211c, which is the lower 8 bits of counter circuit 211, is "8'b1111_0000".

[0206] From equations (6) to (9), the control signal A_SEL is "0", the control signal B_SEL is "1", and the control signal ATTR[1:0] is "2'b01". Therefore, selector 240 selects the count value of bit output unit 211b. Pixel output circuit 250 expands the 8-bit data output from selector 240 to 12 bits and inputs it to selector 251. At this time, the 8-bit data output from selector 240 is stored in the upper 8 bits of the expanded 12-bit data. Therefore, the expanded count value becomes "12'b1011_1100_0000". In high frame rate mode, selector 251 outputs this expanded count value to selection circuit 212.

[0207] At time T80, the control pulse P_SEL1 becomes high level, and at time T81, the control pulse P_SEL1 becomes low level. This operation causes reading to occur during the period from time T80 to time T81.

[0208] The selection circuit 212 connects the signal lines of the upper 4 bits, which are valid data from the count value "12'b1011_1100_0000" output from the selector 251, to the signal lines of bits 0 through 3 of the pixel output signal line 113, respectively. In addition, the selection circuit 212 connects the signal line of the upper 1 bit of the attribute value "2'b01" indicated by the control signal ATTR[1:0] output from the illuminance determination circuit 230 to the signal line of bit 4 of the pixel output signal line 113.

[0209] Therefore, during the period from time T80 to time T81, the pixel output signal line 113 outputs "5'b0_1011", which represents the upper 4 bits of the count value of the counter circuit 211 and the upper 1 bit of the attribute value.

[0210] At time T82, the control pulse P_SEL2 becomes high level, and at time T83, the control pulse P_SEL2 becomes low level. This operation causes reading to occur during the period from time T82 to time T83.

[0211] The selection circuit 212 connects the middle four bits of the count value "12'b1011_1100_0000" output from the selector 251, which are valid data, to the signal lines of bits 0 through 3 of the pixel output signal line 113, respectively. In addition, the selection circuit 212 connects the lower one bit of the attribute value "2'b01" indicated by the control signal ATTR[1:0] output from the illuminance determination circuit 230 to the signal line of bit 4 of the pixel output signal line 113.

[0212] Therefore, during the period from time T82 to time T83, the pixel output signal line 113 is connected to and outputs "5'b1_1100", which represents the middle and lower 4 bits of the count value of the counter circuit 211 and the lower 1 bit of the attribute value.

[0213] At time T84, the third frame period ends. That is, the period from time T76 to time T84 is the third frame period. Further explanation of subsequent operations is omitted.

[0214] Figure 20 is a timing chart showing the operation of the pixel signal processing unit 103 according to this embodiment in non-high frame rate mode. The differences from high frame rate mode will be explained below.

[0215] The operation from time T90 to time T93 is the same as the operation from time T60 to time T63 in Figure 19, so the explanation is omitted. At time T93, the count value of the counter circuit 211 is "12'b1000_1100_1110". In non-high frame rate mode, the selector 251 outputs this count value to the selection circuit 212. That is, in non-high frame rate mode, regardless of the judgment result of the illuminance judgment circuit 230, the count value of the counter circuit 211 is output directly to the selection circuit 212.

[0216] At time T94, the control pulse P_SEL1 becomes high, and at time T95, the control pulse P_SEL1 becomes low. This operation causes the upper 4 bits to be read during the period from time T94 to time T95.

[0217] The selection circuit 212 connects the signal lines of the upper four bits of the count value "12'b1000_1100_1110" output from the selector 251 to the signal lines of bits 0 through 3 of the pixel output signal line 113, respectively. The fourth bit of the pixel output signal line 113 is the don't care bit.

[0218] Therefore, during the period from time T94 to time T95, the pixel output signal line 113 outputs "5'b*_1000", which represents the upper 4 bits of the count value of the counter circuit 211.

[0219] At time T96, the control pulse P_SEL2 becomes high, and at time T97, the control pulse P_SEL2 becomes low. This operation causes the middle 4 bits to be read during the period from time T96 to time T97.

[0220] The selection circuit 212 connects the middle four bits of the count value "12'b1000_1100_1110" output from the selector 251 to the signal lines of bits 0 through 3 of the pixel output signal line 113, respectively. Bit 4 of the pixel output signal line 113 is the don't care bit.

[0221] Therefore, during the period from time T96 to time T97, the pixel output signal line 113 outputs "5'b*_1100", which represents the middle 4 bits of the count value of the counter circuit 211.

[0222] At time T98, the control pulse P_SEL3 becomes high, and at time T99, the control pulse P_SEL3 becomes low. This operation causes the lower 4 bits to be read during the period from time T98 to time T99.

[0223] The selection circuit 212 connects the signal lines of the lower four bits of the count value "12'b1000_1100_1110" output from the selector 251 to the signal lines of bits 0 through 3 of the pixel output signal line 113, respectively. The fourth bit of the pixel output signal line 113 is the don't care bit.

[0224] Therefore, during the period from time T98 to time T99, the pixel output signal line 113 outputs "5'b*_1110", which represents the lower 4 bits of the count value of the counter circuit 211. The first frame period ends at time T100.

[0225] Similar to the first embodiment, this embodiment also provides a photoelectric converter capable of outputting a more appropriate signal according to the illuminance. Furthermore, in this embodiment, in non-high frame rate mode, each row is read three times by control pulses P_SEL1, P_SEL2, and P_SEL3. In contrast, in high frame rate mode, each row is read twice by control pulses P_SEL1 and P_SEL2. As a result, in high frame rate mode, the read time is reduced to 2 / 3 compared to non-high frame rate mode, and a read speed 1.5 times faster is achieved.

[0226] Furthermore, in this embodiment, the bit output units 211a, 211b, and 211c output data containing bits within three different ranges, and the range of bits included in the output data can be switched in three stages depending on the bit reached by the count value. As a result, in this embodiment, data containing more useful information can be output compared to the configuration of the second embodiment.

[0227] In this embodiment as well, the number of bits in the counter circuit 211 can be changed as appropriate. For example, the number of bits in the data held by the counter circuit 211 (12 bits) may be read as N bits (where N is an integer of 2 or more). Also, the number of bits in the data output by the bit output units 211a, 211b, and 211c (8 bits) may be read as M bits (where M is an integer of 1 or more and is less than N). From the viewpoint of overlapping the bit range of the data output by the bit output units 211a, 211b, and 211c, it is desirable that N ≤ 3M. Typically, as in the specific example of this embodiment, N = 1.5M. In addition, the pixel output signal line 113 may include (M / 2 + 1) or (N / 3 + 1) signal lines. The configuration and operation of this embodiment can be generalized by the above-mentioned reinterpretations.

[0228] Furthermore, the number of times each line is read in non-high frame rate mode and the number of times each line is read in high frame rate mode can be changed as appropriate. Let R be the number of times each line is read in non-high frame rate mode, and Q be the number of times each line is read in high frame rate mode. In this case, Q is an integer greater than or equal to 2, and R can be an integer greater than or equal to 3 and greater than Q.

[0229] [Fifth Embodiment] The equipment according to the fifth embodiment will be described with reference to Figure 21. Figure 21 is a block diagram showing the schematic configuration of the equipment according to this embodiment.

[0230] Figure 21 is a schematic diagram showing an instrument EQP including a photoelectric converter APR. The photoelectric converter APR has the functions of the photoelectric converter 100 of the first to fourth embodiments. All or part of the photoelectric converter APR is a semiconductor device IC. The photoelectric converter APR in this example can be used as, for example, an image sensor, an AF (Auto Focus) sensor, a photometering sensor, a distance measuring sensor, etc. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including a photoelectric conversion unit are arranged in a matrix. The semiconductor device IC may have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0231] The photoelectric converter APR may have a stacked structure (chip stacking structure) comprising a first semiconductor chip provided with multiple photoelectric conversion units and a second semiconductor chip provided with peripheral circuits. The peripheral circuits on the second semiconductor chip can each be a column circuit corresponding to a pixel row of the first semiconductor chip. Alternatively, the peripheral circuits on the second semiconductor chip can each be a matrix circuit corresponding to a pixel or pixel block of the first semiconductor chip. For connecting the first and second semiconductor chips, through-swivel electrodes (TSVs), direct bonding of conductors such as copper for inter-chip wiring, connection by microbumps between chips, or connection by wire bonding can be employed.

[0232] The photoelectric converter APR may include a semiconductor device IC as well as a package PKG that houses the semiconductor device IC. The package PKG may include a substrate on which the semiconductor device IC is fixed, a lid made of glass or the like that faces the semiconductor device IC, and connecting members such as bonding wires and bumps that connect terminals provided on the substrate to terminals provided on the semiconductor device IC.

[0233] The EQP device may further comprise at least one of the following: an optical device OPT, a control unit CTRL, a processing unit PRCS, a display unit DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric converter APR as a photoelectric converter, and is, for example, a lens, shutter, or mirror. The control unit CTRL controls the photoelectric converter APR and is, for example, a semiconductor device such as an ASIC.

[0234] The processing unit PRCS processes the signals output from the photoelectric converter APR and constitutes either the AFE (analog front end) or DFE (digital front end). The processing unit PRCS is a semiconductor device such as a CPU (central processing unit) or ASIC (application-specific integrated circuit). The display device DSPL is an EL display device, liquid crystal display device, etc., that displays the information (image) obtained from the photoelectric converter APR. The memory device MMRY is a magnetic device, semiconductor device, etc., that stores the information (image) obtained from the photoelectric converter APR. The memory device MMRY is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or hard disk drive.

[0235] The mechanical device MCHN has moving parts or propulsion parts such as motors and engines. The equipment EQP displays the signals output from the photoelectric converter APR on the display device DSPL, or transmits them to the outside using a communication device (not shown) provided by the equipment EQP. For this purpose, it is preferable that the equipment EQP further includes a memory device MMRY and a processing device PRCS, separate from the memory circuit and arithmetic circuit of the photoelectric converter APR. The mechanical device MCHN may be controlled based on the signals output from the photoelectric converter APR.

[0236] The EQP (Equipment Equipped Device) shown in Figure 21 can be electronic devices such as information terminals with imaging capabilities (e.g., smartphones and wearable devices), cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In a camera, the mechanical device MCHN can drive components of the optical device OPT for zooming, focusing, and shutter operation. The EQP can also be transportation equipment (mobile devices) such as vehicles, ships, drones, and airplanes. Furthermore, the EQP can be medical equipment such as endoscopes and CT scanners. Additionally, the EQP can be measuring instruments such as distance sensors, analytical instruments such as electron microscopes, office equipment such as photocopiers, and industrial equipment such as robots.

[0237] The mechanical device MCHN in transport equipment can be used as a mobile device. The device EQP as transport equipment is suitable for transporting the photoelectric converter APR, assisting and / or automating driving (operation) through its imaging function, etc. The processing device PRCS for assisting and / or automating driving (operation) can perform processing to operate the mechanical device MCHN as a mobile device based on information obtained from the photoelectric converter APR.

[0238] According to the first to fourth embodiments, good signal acquisition is possible. Therefore, the photoelectric converter APR according to the first to fourth embodiments can provide high value to its designers, manufacturers, distributors, buyers, and / or users. Thus, by installing the photoelectric converter APR in the EQP, the value of the EQP can also be increased. Therefore, when manufacturing and selling the EQP, deciding to install the photoelectric converter APR of this embodiment in the EQP is advantageous in increasing the value of the EQP. Increasing value here includes at least one of the following: addition of functions, improvement of performance, improvement of characteristics, improvement of reliability, improvement of manufacturing yield, reduction of environmental impact, cost reduction, miniaturization, and weight reduction.

[0239] For example, by installing the APR (Photoelectric Converter) in transportation equipment, superior performance can be obtained when photographing the outside of the transportation equipment or measuring the external environment. Therefore, when manufacturing and selling transportation equipment, deciding to install the APR (Photoelectric Converter) according to this embodiment in the transportation equipment is advantageous in improving the performance of the transportation equipment itself. In particular, the APR (Photoelectric Converter) is suitable for transportation equipment that uses information obtained from the APR to provide driving assistance and / or automatic driving.

[0240] [Sixth Embodiment] Figures 22(a) and 22(b) are block diagrams of the equipment related to the in-vehicle camera in this embodiment. Figures 22(a) and 22(b) show an example of applying the photoelectric converter to a moving object such as a vehicle. Equipment 80 includes an imaging device 800 (an example of a photoelectric converter) and a signal processing device (processing device) that processes signals from the imaging device 800. Equipment 80 includes an image processing unit 801 that performs image processing on a plurality of image data acquired by the imaging device 800, and a parallax calculation unit 802 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by equipment 80.

[0241] Here, the device 80 may include an optical system (not shown) that guides light to the imaging device 800. The optical system may include, for example, lenses, shutters, and mirrors. In addition, multiple photoelectric conversion units that are substantially conjugate to the pupil of the optical system may be arranged in pixels of the imaging device 800. For example, the multiple photoelectric conversion units may be arranged corresponding to one microlens. The multiple photoelectric conversion units receive light beams that have passed through different positions in the pupil of the optical system. As a result, the imaging device 800 outputs multiple image data corresponding to the light beams that have passed through different positions in the pupil of the optical system. The disparity calculation unit 802 may then calculate the disparity using the output multiple image data.

[0242] Furthermore, the device 80 includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 804 may use any of this distance information to determine the possibility of collision. Note that the distance information may be acquired using ToF (Time of Flight) technology. The distance information acquisition means may be implemented by specially designed hardware or by a software module. It may also be implemented by FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0243] Device 80 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Device 80 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate braking force on the vehicle based on the collision determination result of the collision determination unit 804. Furthermore, device 80 is connected to a warning device 830 that issues a warning to the driver based on the collision determination result of the collision determination unit 804. For example, if the collision determination result of the collision determination unit 804 indicates a high probability of collision, the control ECU 820 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 830 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seatbelt or steering wheel. As described above, device 80 functions as a control means that controls the actions that control the vehicle.

[0244] In this embodiment, the equipment 80 images the area around the vehicle, for example, in front of or behind it. Figure 22(b) shows the equipment when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810, acting as an imaging control means, sends instructions to the equipment 80 or imaging device 800 to perform the imaging operation. This configuration allows for further improvement of the accuracy of distance measurement.

[0245] The above example described controlling a vehicle to avoid collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles, or control systems that automatically stay within their lane. Furthermore, the equipment is not limited to vehicles such as automobiles, but can be applied to mobile objects (mobile devices) such as ships, aircraft, satellites, industrial robots, and consumer robots. In addition, it can be applied not only to mobile objects, but also to a wide range of devices that utilize object recognition or biometric recognition, such as intelligent transportation systems (ITS) and surveillance systems.

[0246] [Seventh Embodiment] The switching between the high-frame-rate mode and the non-high-frame-rate mode in the photoelectric converter 100 described above is performed by a processing circuit in the device on which the photoelectric converter 100 is installed, as described in the fifth or sixth embodiment. This processing circuit may be, for example, the processing unit PRCS of the fifth embodiment or the image processing unit 801 of the sixth embodiment. In this embodiment, a specific example of the case in which the high-frame-rate mode and the non-high-frame-rate mode are switched by feedback control from a processing circuit downstream of the photoelectric converter 100 will be described.

[0247] In this embodiment, a processing circuit that performs subsequent processing acquires information indicating the brightness of the imaged scene. The processing circuit then performs feedback control to the photoelectric converter 100 so that the high frame rate mode is applied when the brightness is below a predetermined threshold. On the other hand, the processing circuit also performs feedback control to the photoelectric converter 100 so that the non-high frame rate mode is applied when the brightness is greater than a predetermined threshold. The processing circuit switches between the high frame rate mode and the non-high frame rate mode by changing the mode setting value.

[0248] In high frame rate mode, only some bits of the counter circuit 211 are read out, resulting in less data information being read compared to non-high frame rate mode where all bits of the counter circuit 211 are read out, which can lead to a decrease in gradation. However, in this embodiment, high frame rate mode is applied only to dark scenes where the higher bits are likely to be "0," so high frame rate mode can be applied without substantially reducing gradation. On the other hand, non-high frame rate mode is applied to bright scenes, thus avoiding a decrease in gradation. Therefore, according to this embodiment, the impact of gradation reduction due to the application of high frame rate mode can be reduced.

[0249] Illuminance information is acquired, for example, by obtaining information indicating the brightness of the subject, such as the integrated value of pixel values, from the captured image. Some digital cameras, such as surveillance cameras, have an AE (Automatic Exposure) function that automatically adjusts the exposure so that the brightness of the captured image is appropriate, regardless of the actual brightness of the subject. The same technology used to acquire brightness in this AE function can be applied to acquiring illuminance information in this embodiment.

[0250] [Eighth Embodiment] This embodiment describes another example of switching between the high frame rate mode and the non-high frame rate mode as described in the seventh embodiment.

[0251] In this embodiment, a processing circuit that performs subsequent processing acquires motion information of the subject. The processing circuit then performs feedback control to the photoelectric converter 100 so that the high frame rate mode is applied when the magnitude of the subject's motion is below a predetermined threshold. On the other hand, the processing circuit also performs feedback control to the photoelectric converter 100 so that the non-high frame rate mode is applied when the magnitude of the subject's motion is greater than a predetermined threshold. For example, a method for calculating the motion vector of an image used in motion monitoring may be used to acquire the motion information of the subject.

[0252] In this embodiment, high frame rate imaging is possible in scenes with little subject movement using the high frame rate mode, and detailed imaging with high gradation is possible in scenes with significant subject movement using the non-high frame rate mode. Therefore, according to this embodiment, more appropriate imaging that takes subject movement into consideration is possible.

[0253] Examples of devices to which the photoelectric converter 100 is applied include digital cameras such as surveillance cameras. In this case, under normal conditions, high-speed imaging is possible using a high frame rate mode, and in situations where the subject is moving significantly, such as when there is a suspicious person, a non-high frame rate can be applied to capture the subject in detail. Thus, the method of this embodiment can be used in motion surveillance use cases.

[0254] The relationship between motion information and the threshold may be reversed from the example described above. That is, the processing circuit may perform feedback control to the photoelectric converter 100 so that the high frame rate mode is applied when the magnitude of the subject's movement is greater than a predetermined threshold. Alternatively, the processing circuit may perform feedback control to the photoelectric converter 100 so that the non-high frame rate mode is applied when the magnitude of the subject's movement is less than or equal to a predetermined threshold. In this example, in scenes with little subject movement, the non-high frame rate mode enables detailed imaging with high gradation, while in scenes with large subject movement, the high frame rate mode reduces blur of fast-moving subjects during imaging. This can improve the recognition efficiency in motion detection.

[0255] [Ninth Embodiment] The seventh and eighth embodiments describe examples of switching between high-frame-rate mode and non-high-frame-rate mode depending on the situation. However, the high-frame-rate mode and non-high-frame-rate mode may be switched depending on the region of the image. In this embodiment, an example is described in which the image is divided into multiple regions, and either the high-frame-rate mode or the non-high-frame-rate mode is applied to each region.

[0256] Figures 23(a), 23(b), and 23(c) show the setting areas for the high frame rate mode and non-high frame rate mode according to this embodiment. In Figures 23(a), 23(b), and 23(c), the hatched areas indicate the areas to which the high frame rate mode is applied, and the areas that are not hatched indicate the areas to which the non-high frame rate mode is applied.

[0257] Figure 23(a) shows an example where an image is divided into four regions R1, R2, R3, and R4 by dividing it in half vertically and horizontally. Of the four regions R1, R2, R3, and R4, the upper right region R2 and the lower left region R3 are to which the high frame rate mode is applied, while the upper left region R1 and the lower right region R4 are to which the non-high frame rate mode is applied. For example, the frame rate in high frame rate mode is 60fps, and the frame rate in non-high frame rate mode is 30fps. The signals corresponding to the four regions R1, R2, R3, and R4 can be processed in subsequent processing by four digital front-ends corresponding to the four regions R1, R2, R3, and R4, respectively. Note that the mode applied to each of the four regions R1, R2, R3, and R4 may be fixed, or it may be possible to dynamically switch between regions depending on the situation.

[0258] Figure 23(b) shows a modified example of the region division method. Figure 23(b) shows an example where the image is divided vertically into four sections, resulting in four regions R1, R2, R3, and R4. Of the four regions R1, R2, R3, and R4, the inner regions R2 and R3 are applied to high frame rate mode, while the upper region R1 and the lower region R4 are applied to non-high frame rate mode.

[0259] Figure 23(c) shows a modified example of the region division method. Figure 23(c) shows an example where the image is divided horizontally into four regions R1, R2, R3, and R4. Of the four regions R1, R2, R3, and R4, the inner regions R2 and R3 are applied to high frame rate mode, while the left region R1 and the right region R4 are applied to non-high frame rate mode.

[0260] As described above, this embodiment allows for the use of high-frame-rate mode and non-high-frame-rate mode for each region within an image. Furthermore, this method, applied individually to each region, is effective when the appropriate frame rate may differ depending on the location within the image.

[0261] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or an example in which a part of the configuration of one embodiment is replaced with a part of the configuration of another embodiment, is also an embodiment of the present invention.

[0262] Figures 6, 10, 14, and 16 show examples where an illuminance determination circuit 230 is provided in the pixel signal processing unit 103 of each pixel. However, it is not essential that an illuminance determination circuit 230 be provided in the pixel signal processing unit 103 of all pixels. For example, a configuration in which multiple pixel signal processing units 103 of pixels, such as 4 pixels in 2 rows and 2 rows, or 16 pixels in 4 rows and 4 rows, share one illuminance determination circuit 230. This reduces the number of illuminance determination circuits 230, thereby reducing the circuit size of the photoelectric converter 100. Furthermore, by reducing the total number of illuminance determination circuits 230, the area freed up can be used to add other circuits, thereby enhancing the functionality of the photoelectric converter 100. In this case, for example, the determination result of the illuminance determination circuit 230 in one pixel signal processing unit 103 can be applied to multiple pixel signal processing units 103, including other nearby pixel signal processing units 103.

[0263] Alternatively, multiple count values ​​may be input to a single illuminance determination circuit 230 from the bit output units 211a of multiple pixel signal processing units 103, and the illuminance determination circuit 230 may perform a determination based on these multiple count values.

[0264] Almost no light enters the photoelectric conversion unit 102 in the OB region 15 shown in Figure 2. Therefore, the illuminance determination circuit 230 does not need to be provided in the pixel signal processing unit 103 (light-shielding pixel circuit) located in region 25 in Figure 3, which corresponds to the OB region 15. For example, in the examples of the pixel signal processing unit 103 in Figures 6 and 10, no value is carried to the LSB of the data output from the bit output unit 211a in region 25. Therefore, the selector 240 may be configured to always select the count value of the bit output unit 211b without performing illuminance determination. Similarly, in the example in Figure 14, the selector 240 may be configured to always select the count value of the bit output unit 211c, and in the example in Figure 16, the selector 240 may be configured to always select the count value of the bit output unit 211b. Therefore, the illuminance determination circuit 230 is unnecessary in the pixel signal processing unit 103 located in region 25 and can be omitted. This reduces the number of illuminance determination circuits 230, thereby reducing the circuit size of the photoelectric converter 100. Furthermore, by adding other circuits in the area freed up by reducing the total number of illuminance determination circuits 230, the photoelectric converter 100 can be made more functional.

[0265] The embodiments described above can be modified as appropriate without departing from the technical concept. Furthermore, the disclosures in this specification include not only what is described herein, but also all matters that can be understood from this specification and the drawings attached thereto. In addition, the disclosures in this specification include the complement of the concepts described herein. That is, if this specification states, for example, "A is greater than B," then even if the statement "A is not greater than B" is omitted, this specification can be said to disclose that "A is not greater than B." This is because the statement "A is greater than B" presupposes that the case where "A is not greater than B" is being considered.

[0266] The disclosures in this specification include the following components: (Composition 1) An avalanche photodiode that outputs a signal corresponding to the incident light, A pulse generation circuit that generates a pulse signal based on an output signal from the avalanche photodiode; A counter that generates and holds a first count value of N bits (N is an integer of 2 or more) by counting the number of pulses included in the pulse signal; An illuminance determination circuit that generates an illuminance signal indicating illuminance based on the values of at least some bits of the first count value; A selector that outputs a second count value that is M bits (M is an integer of 1 or more and smaller than N) of the first count value; An output circuit that outputs data based on the first count value or the second count value; characterized by comprising; The selector selects a bit range of the second count value in the first count value based on the illuminance signal A photoelectric conversion device characterized by the above. (Configuration 2) In the first mode, the output circuit outputs the values of some bits of the first count value based on the second count value, In the second mode, the output circuit outputs the values of all bits of the first count value based on the first count value The photoelectric conversion device according to Configuration 1, characterized by the above. (Configuration 3) The frame rate in the first mode is higher than the frame rate in the second mode The photoelectric conversion device according to Configuration 2, characterized by the above. (Configuration 4) A plurality of the avalanche photodiodes are arranged two-dimensionally, Data based on incident light to avalanche photodiodes in a partial region of the plurality of avalanche photodiodes is output in the first mode, and data based on incident light to avalanche photodiodes in another partial region of the plurality of avalanche photodiodes is output in the second mode The photoelectric conversion device according to Configuration 2 or 3, characterized by the above. (Configuration 5) When the brightness of the imaging scene is below the threshold value, the data is output in the first mode. When the brightness is greater than the threshold value, the data is output in the second mode. The photoelectric conversion device according to Configuration 2 or 3, characterized in that. (Configuration 6) When the magnitude of the movement of the subject in the captured image is below the threshold value, the data is output in the first mode. When the magnitude of the movement of the subject is greater than the threshold value, the data is output in the second mode. The photoelectric conversion device according to Configuration 2 or 3, characterized in that. (Configuration 7) When the magnitude of the movement of the subject in the captured image is greater than the threshold value, the data is output in the first mode. When the magnitude of the movement of the subject is below the threshold value, the data is output in the second mode. The photoelectric conversion device according to Configuration 2 or 3, characterized in that. (Configuration 8) A plurality of pixel circuits each including the avalanche photodiode, the pulse generation circuit, the counter, the selector, and the output circuit are arranged in a plurality of rows. The range of bits of the second count value output by the selector of the first row among the plurality of rows is different from the range of bits of the second count value output by the selector of the second row among the plurality of rows. The photoelectric conversion device according to Configuration 1, characterized in that. (Configuration 9) In the first mode, the output circuit outputs, based on the second count values of the first row and the second row, the values of some bits of the first count value of the first row and the values of some bits of the first count value of the second row simultaneously. In the second mode, the output circuit outputs, based on the first count value of the first row, the values of all bits of the first count value of the first row. The photoelectric conversion device according to Configuration 8, characterized in that. (Composition 10) The selector selects either a first range of M bits including the most significant bit of the first count value or a second range of M bits including the least significant bit of the first count value from the first count value and outputs it as the second count value. A photoelectric conversion device according to configuration 1, characterized in that it is a photoelectric conversion device. (Composition 11) The first range and the second range do not overlap. A photoelectric conversion device according to configuration 10, characterized by the above. (Composition 12) N=2M A photoelectric conversion device according to configuration 11, characterized by the features described above. (Composition 13) In the first mode, the output circuit outputs the value of some bits of the first count value based on the second count value. In the second mode, the output circuit outputs the values ​​of all bits of the first count value in multiple steps, based on the first count value. A photoelectric conversion device according to configuration 11 or 12, characterized by the above. (Composition 14) The selector selects from the first count value one of the following: a first range of M bits including the most significant bit of the first count value, a second range of M bits including the least significant bit of the first count value, or a third range of M bits not including either the most significant or least significant bit of the first count value, and outputs it as the second count value. A photoelectric conversion device according to configuration 1, characterized in that it is a photoelectric conversion device. (Composition 15) N ≤ 3M A photoelectric conversion device according to configuration 14, characterized by the features described above. (Composition 16) The first range and a portion of the third range overlap, The second range and a portion of the third range overlap. A photoelectric conversion device according to configuration 14, characterized by the features described above. (Composition 17) In the first mode, the output circuit outputs the value of some bits of the first count value based on the second count value. In the second mode, the output circuit outputs the values ​​of all bits of the first count value in multiple steps, based on the first count value. A photoelectric conversion device according to configuration 16, characterized by the features described above. (Composition 18) In the first mode, the output circuit outputs the value of a portion of the bits of the first count value divided into Q times (where Q is an integer of 2 or more) based on the second count value. In the second mode, the output circuit outputs the value of all bits of the first count value divided into R times (where R is an integer greater than or equal to 3 and greater than Q) based on the first count value. A photoelectric conversion device according to configuration 16, characterized by the features described above. (Composition 19) The output circuit outputs an attribute value that indicates the bit range of the second count value in the first count value. A photoelectric conversion device according to any one of configurations 1 to 18, characterized by the above. (Composition 20) If the bit values ​​of the M-bit range of the first count value, including the most significant bit, are all zero, the selector selects the bit range of the second count value such that it does not include the most significant bit. A photoelectric conversion device according to any one of configurations 1 to 19, characterized by the above. (Composition 21) Multiple pixel circuits are arranged, each including the avalanche photodiode, the pulse generation circuit, the counter, the selector, and the output circuit. One of the illuminance determination circuits supplies illuminance signals to a plurality of the pixel circuits. A photoelectric conversion device according to any one of configurations 1 to 3, characterized by the above. (Composition 22) A pixel circuit including the avalanche photodiode, the pulse generation circuit, the counter, the selector, and the output circuit, A light-shielding pixel circuit including the avalanche photodiode, the pulse generation circuit, the counter, the selector, and the output circuit, wherein the avalanche photodiode is shielded from light. is arranged. The selector of the light-shielding pixel circuit selects a range of bits of the second count value so as to include the least significant bit of the first count value regardless of the illuminance signal. The photoelectric conversion device according to any one of Configurations 1 to 3, characterized in that. (Configuration 23) The photoelectric conversion device according to any one of Configurations 1 to 22, an optical device corresponding to the photoelectric conversion device, a control device for controlling the photoelectric conversion device, a processing device for processing a signal output from the photoelectric conversion device, a display device for displaying information obtained by the photoelectric conversion device, a storage device for storing information obtained by the photoelectric conversion device, and at least one of a mechanical device that operates based on information obtained by the photoelectric conversion device, and a device characterized by comprising. (Configuration 24) The processing device acquires distance information from the photoelectric conversion device to the object. The device according to Configuration 23, characterized in that.

[0267] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and causing one or more processors in a computer of the system or device to read and execute the program. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

[0268] It should be noted that the embodiments described above are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various ways without departing from its technical concept or its main features. [Explanation of symbols]

[0269] 100 Photoelectric converter 201 Avalanche Photodiode 220 pulse generation circuit 211 Counter Circuit 230 Illuminance judgment circuit 240 Selector 250-pixel output circuit< / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x>

Claims

1. An avalanche photodiode that outputs a signal corresponding to the incident light, A pulse generation circuit that generates a pulse signal based on the output signal from the avalanche photodiode, A counter that generates and stores a first count value of N bits (where N is an integer of 2 or more) by counting the number of pulses contained in the pulse signal, An illuminance determination circuit that generates an illuminance signal indicating illuminance based on the values ​​of at least some bits of the first count value, A selector that outputs a second count value which is M bits (where M is an integer greater than or equal to 1 and less than N) of the first count value, An output circuit that outputs data based on the first count value or the second count value, It has, The selector selects a range of bits in the second count value within the first count value based on the illuminance signal. A photoelectric conversion device characterized by the following features.

2. In the first mode, the output circuit outputs the value of some bits of the first count value based on the second count value. In the second mode, the output circuit outputs the values ​​of all bits of the first count value based on the first count value. The photoelectric conversion device according to feature 1.

3. The frame rate in the first mode is higher than the frame rate in the second mode. The photoelectric conversion device according to feature 2.

4. Multiple avalanche photodiodes are arranged in a two-dimensional manner. Data based on incident light on a portion of the avalanche photodiodes among the plurality of avalanche photodiodes is output in the first mode, and data based on incident light on avalanche photodiodes in other portions of the plurality of avalanche photodiodes is output in the second mode. The photoelectric conversion device according to feature 2.

5. If the brightness of the imaging scene is below a threshold, the data is output in the first mode; if the brightness is greater than the threshold, the data is output in the second mode. The photoelectric conversion device according to feature 2.

6. If the magnitude of motion of the subject in the captured image is below a threshold, the data is output in the first mode; if the magnitude of motion of the subject is greater than the threshold, the data is output in the second mode. The photoelectric conversion device according to feature 2.

7. If the magnitude of motion of the subject in the captured image is greater than a threshold, the data is output in the first mode; if the magnitude of motion of the subject is less than or equal to the threshold, the data is output in the second mode. The photoelectric conversion device according to feature 2.

8. Multiple pixel circuits, each including the avalanche photodiode, the pulse generation circuit, the counter, the selector, and the output circuit, are arranged in multiple rows. The bit range of the second count value output by the selector of the first row of the plurality of rows and the bit range of the second count value output by the selector of the second row of the plurality of rows are different from each other. The photoelectric conversion device according to feature 1.

9. In the first mode, the output circuit simultaneously outputs the values ​​of some bits of the first count value of the first row and the values ​​of some bits of the first count value of the second row, based on the second count values ​​of the first row and the second row. In the second mode, the output circuit outputs the values ​​of all bits of the first count value of the first row, based on the first count value of the first row. The photoelectric conversion device according to feature 8.

10. The selector selects either a first range of M bits including the most significant bit of the first count value or a second range of M bits including the least significant bit of the first count value from the first count value and outputs it as the second count value. The photoelectric conversion device according to feature 1.

11. The first range and the second range do not overlap. The photoelectric conversion device according to feature 10.

12. N = 2M The photoelectric conversion device according to feature 11.

13. In the first mode, the output circuit outputs the value of some bits of the first count value based on the second count value. In the second mode, the output circuit outputs the values ​​of all bits of the first count value in multiple steps, based on the first count value. The photoelectric conversion device according to feature 11.

14. The selector selects from the first count value one of the following ranges: a first range of M bits including the most significant bit of the first count value, a second range of M bits including the least significant bit of the first count value, or a third range of M bits not including either the most significant or least significant bit of the first count value, and outputs it as the second count value. The photoelectric conversion device according to feature 1.

15. N ≤ 3M The photoelectric conversion device according to feature 14.

16. The first range and a portion of the third range overlap, The second range and a portion of the third range overlap. The photoelectric conversion device according to feature 14.

17. In the first mode, the output circuit outputs the value of some bits of the first count value based on the second count value. In the second mode, the output circuit outputs the values ​​of all bits of the first count value in multiple steps, based on the first count value. The photoelectric conversion device according to feature 16.

18. In the first mode, the output circuit outputs the value of a portion of the bits of the first count value Q times (where Q is an integer of 2 or more) based on the second count value. In the second mode, the output circuit outputs the value of all bits of the first count value in R steps (where R is an integer greater than or equal to 3 and greater than Q), based on the first count value. The photoelectric conversion device according to feature 16.

19. The output circuit outputs an attribute value that indicates the bit range of the second count value in the first count value. The photoelectric conversion device according to feature 1.

20. If the bit values ​​of the M-bit range of the first count value, including the most significant bit, are all zero, the selector selects the bit range of the second count value such that it does not include the most significant bit. The photoelectric conversion device according to feature 1.

21. Multiple pixel circuits are arranged, each including the avalanche photodiode, the pulse generation circuit, the counter, the selector, and the output circuit. One of the illuminance determination circuits supplies illuminance signals to multiple of the pixel circuits. The photoelectric conversion device according to feature 1.

22. A pixel circuit including the avalanche photodiode, the pulse generation circuit, the counter, the selector, and the output circuit, A light-shielding pixel circuit comprising the avalanche photodiode, the pulse generation circuit, the counter, the selector, and the output circuit, wherein the avalanche photodiode is shielded from light, It is arranged, The selector of the light-shielding pixel circuit selects a range of bits in the second count value to include the least significant bit of the first count value, regardless of the illuminance signal. The photoelectric conversion device according to feature 1.

23. A photoelectric conversion device according to any one of claims 1 to 22, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A display device that displays information obtained by the aforementioned photoelectric converter. A storage device for storing information obtained by the aforementioned photoelectric converter, and A device characterized by comprising at least one of the following: a mechanical device that operates based on information obtained from the photoelectric converter.

24. The processing device acquires distance information from the photoelectric converter to the object. The apparatus according to claim 23.

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