Indication device
The display device addresses high power consumption and heat generation in gate drive circuits by alternating and phase-shifting gate and source signals, achieving significant reductions in power usage and heat output.
Patent Information
- Application Number
- JP2025022884
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-14
- Publication Date
- 2026-08-26
AI Technical Summary
Existing liquid crystal display devices face high power consumption and heat generation in the gate drive circuit, which is a concern in active matrix liquid crystal display devices.
A display device configuration with a matrix of transistors, including a first and second scan line group, a gate drive circuit, a source drive circuit, and a control circuit that alternates gate and source signals between multiple lines to reduce frequency and phase differences, thereby reducing power consumption and heat in the gate and source drive circuits.
This configuration effectively halves the frequency of gate and source signals, leading to reduced power consumption and heat generation in the drive circuits, as demonstrated by current consumption and temperature measurements.
Smart Images
Figure 2026136986000001_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a display device.
Background Art
[0002] Patent Document 1 discloses an active matrix liquid crystal display device. This liquid crystal display device includes a plurality of thin film transistors, a gate drive circuit, a plurality of data lines, a plurality of image signal lines, and a plurality of sampling switches. Serial-parallel conversion signals obtained by converting serial data into parallel are respectively supplied as image signals to the plurality of image signal lines. Image signals for six pixels are sequentially output in parallel to six image signal lines. Each of the plurality of data lines is connected to one of the six image signal lines via a sampling switch. Image signals are supplied to the plurality of data lines via the sampling switches.
Prior Art Documents
Patent Documents
[0003] <000,00017>
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] In a liquid crystal display device as described in Patent Document 1, it is desired to reduce the power consumption in the gate drive circuit and the amount of heat generated in the gate drive circuit.
[0005] Therefore, this disclosure has been made to solve the above problems, and an object thereof is to provide a display device capable of reducing the power consumption in the gate drive circuit and the amount of heat generated in the gate drive circuit.
Means for Solving the Problems
[0006] To solve the above problems, a display device according to one aspect of the present disclosure includes a plurality of transistors arranged in a matrix, a first scan line group including a first scan line connected to a first transistor among the plurality of transistors, and a second scan line connected to the first transistor, a source line group including a plurality of source lines connected to the plurality of transistors, a gate drive circuit that outputs a gate signal, a source drive circuit that outputs source signals to the plurality of source lines, and a control circuit that supplies a gate control signal to the gate drive circuit. The gate drive circuit selects either a first state in which it outputs the gate signal to the first scan line and does not output the gate signal to the second scan line, or a second state in which it outputs the gate signal to the first scan line and outputs a signal to the second scan line that has the same frequency as the gate signal output to the first scan line but has a different phase with respect to the gate signal. [Effects of the Invention]
[0007] According to the above configuration, it is possible to reduce the power consumption in the gate drive circuit and reduce the amount of heat generated in the gate drive circuit. [Brief explanation of the drawing]
[0008] [Figure 1] Figure 1 is a block diagram showing the schematic configuration of the display device 100 in this embodiment. [Figure 2] Figure 2 shows the configuration of a part of the gate drive circuit 1 and a part of the source drive circuit 2 in this embodiment. [Figure 3] Figure 3 is a diagram illustrating the regions R1a to R3a in the display panel 10. [Figure 4] Figure 4 is a diagram illustrating the region R1b to R3b in the display panel 10. [Figure 5] Figure 5 is a timing diagram illustrating the operation of the gate drive circuit 1 when scanning the TFT 13 within region R1a at 30 Hz. [Figure 6]Figure 6 is a timing diagram illustrating the operation of the gate drive circuit 1 when scanning the TFT 13 within region R1a at 60 Hz. [Figure 7] Figure 7 is a timing diagram illustrating the operation of the gate drive circuit 1 when scanning the TFT 13 within region R1a at 60 Hz. [Figure 8] Figure 8 is a timing diagram illustrating the operation of the gate drive circuit 1 when scanning the TFT 13 within region R1a at 120 Hz. [Figure 9] Figure 9 shows an example of a gate signal output when the TFT13 in region R1a, the TFT13 in region R2a, and the TFT13 in region R3a are operated at different frequencies. [Figure 10] Figure 10 is a timing diagram illustrating the operation of the source drive circuit 2 when a source signal is supplied at 30 Hz to the TFT 13 in region R1b. [Figure 11] Figure 11 is a timing diagram illustrating the operation of the source drive circuit 2 when a source signal is supplied to the TFT 13 in region R1b at 60 Hz. [Figure 12] Figure 12 is a timing diagram illustrating the operation of the source drive circuit 2 when a source signal is supplied at 60 Hz to the TFT 13 in region R1b. [Figure 13] Figure 13 is a timing diagram illustrating the operation of the source drive circuit 2 when a source signal is supplied at 120 Hz to the TFT 13 in region R1b. [Figure 14] Figure 14 shows an example where source signals of different frequencies are supplied to the TFT13 in region R1b, the TFT13 in region R2b, and the TFT13 in region R3b. [Figure 15] Figure 15 is a diagram illustrating the polarity of the source signal. [Figure 16] Figure 16 shows the measurement results of current consumption and temperature according to one embodiment. [Figure 17] Figure 17 shows the configuration of the display device 200 according to a first modified example of one embodiment. [Figure 18]FIG. 18 is a diagram showing the configuration of the display device 300 according to the second modification of an embodiment. [Figure 19] FIG. 19 is a diagram showing the configuration of the display device 400 according to the third modification of an embodiment. [Figure 20] FIG. 20 is a diagram showing the configuration of the display device 500 according to the fourth modification of an embodiment.
Embodiments for Carrying Out the Invention
[0009] Hereinafter, embodiments of the present disclosure will be described based on the drawings. Note that the present disclosure is not limited to the following embodiments, and design changes can be appropriately made within the scope that satisfies the configuration of the present disclosure. Also, in the following description, the same reference numerals are commonly used between different drawings for the same part or parts having the same or similar functions, and the repeated description thereof will be omitted. Further, each configuration described in the embodiments and modifications may be appropriately combined or changed without departing from the gist of the present disclosure. Also, for the sake of clarity of explanation, in the drawings referred to below, the configuration is shown in a simplified or schematic manner, or some of the constituent members are omitted.
[0010] [Overall Configuration of Display Device] FIG. 1 is a block diagram showing a schematic configuration of the display device 100 in the present embodiment. The display device 100 is a device that displays an image (video) based on an image signal supplied from a host controller (not shown). The display device 100 is, for example, a personal computer, a tablet terminal, a smartphone, a smartwatch, and a television device. The display device 100 includes a display panel 10 and a control circuit 20.
[0011] As shown in FIG. 1, the display panel 10 includes a gate driving circuit 1 and a source driving circuit 2. FIG. 2 is a diagram showing the configuration of a part of the gate driving circuit 1 and a part of the source driving circuit 2 in this embodiment. As shown in FIG. 2, the display panel 10 is provided with gate lines 11a to 11f connected to the gate driving circuit 1, source lines 12a to 12f connected to the source driving circuit 2, a TFT (Thin Film Transistor) 13, a pixel electrode 14, and a common electrode 15.
[0012] FIG. 3 is a diagram for explaining regions R1a to R3a in the display panel 10. FIG. 4 is a diagram for explaining regions R1b to R3b in the display panel 10. As shown in FIG. 3, in the display panel 10, regions R1a, region R2a, and region R3a are provided in this order in the direction in which the gate lines 11a to 11f are arranged. In region R1a, a plurality of gate lines 11a and a plurality of gate lines 11b (first scanning line group) are arranged. In region R2a, a plurality of gate lines 11c and a plurality of gate lines 11d (second scanning line group) are arranged. In region R3a, a plurality of gate lines 11e and a plurality of gate lines 11f (third scanning line group) are arranged.
[0013] As shown in FIG. 4, in the display panel 10, regions R1b, region R2b, and region R3b are provided in this order in the direction in which the source lines 12a to 12f are arranged. In region R1b, a plurality of source lines 12a and a plurality of source lines 12b (first source line group) are arranged. In region R2b, a plurality of source lines 12c and a plurality of source lines 12d (second source line group) are arranged. In region R3b, a plurality of source lines 12e and a plurality of source lines 12f (third source line group) are arranged.
[0014] As shown in Figure 2, two gate lines are connected to each row of TFT13. For example, gate lines 11a and 11b are connected to the gate electrodes of each TFT13 in region R1a. Also, gate lines 11c and 11d are connected to the gate electrodes of each TFT13 in region R2a. Gate lines 11e and 11f are connected to the gate electrodes of each TFT13 in region R3a. Furthermore, as shown in Figure 2, two source lines are connected to each row of TFT13. For example, source lines 12a and 12b are connected to the source electrodes of each TFT13 in region R1b. Also, source lines 12c and 12d are connected to the source electrodes of each TFT13 in region R2b. Source lines 12e and 12f are connected to the source electrodes of each TFT13 in region R3b.
[0015] The pixel electrode 14 is connected to the drain electrode of the TFT 13. The TFT 13 and the pixel electrode 14 are arranged within a region (pixel) demarcated by the intersection of multiple gate lines and multiple source lines. The common electrode 15 is a counter electrode positioned opposite the pixel electrode 14. The common electrode 15 is provided in common for multiple pixel electrodes 14.
[0016] In the first operational state, the gate drive circuit 1 includes a signal output unit 30, a plurality of switches 31, and conductor wires 30a and 30b connecting the signal output unit 30 and the plurality of switches 31. The signal output unit 30 supplies signal G1 to each switch 31 via conductor wire 30a. The signal output unit 30 supplies signal G2 to each switch 31 via conductor wire 30b. The source drive circuit 2 also includes a signal output unit 40, a plurality of switches 41, and conductor wires 40a and 40b connecting the signal output unit 40 and the plurality of switches 41. The signal output unit 40 supplies signal S1 to each switch 41 via conductor wire 40a. The signal output unit 40 supplies signal S2 to each switch 41 via conductor wire 40b.
[0017] The control circuit 20 supplies a gate control signal to the gate drive circuit 1. The control circuit 20 also supplies a source control signal to the source drive circuit 2. In this embodiment, the gate control signal includes a signal to operate a plurality of switches 31. The source control signal also includes a signal to operate a plurality of switches 41. As shown in Figure 2, the plurality of switches 31 include a switch SWG1 connected to gate lines 11a and 11b, a switch SWG2 connected to gate lines 11c and 11d, and a switch SWG3 connected to gate lines 11e and 11f. The plurality of switches 41 include a switch SWS1 connected to source lines 12a and 12b, a switch SWS2 connected to source lines 12c and 12d, and a switch SWS3 connected to source lines 12e and 12f.
[0018] (Operation of gate drive circuit 1) Next, the operation of the gate drive circuit 1 according to this embodiment will be described with reference to Figures 5 to 9. Figure 5 is a timing diagram illustrating the operation of the gate drive circuit 1 when scanning the TFT 13 in region R1a at 30 Hz. Figures 6 and 7 are timing diagrams illustrating the operation of the gate drive circuit 1 when scanning the TFT 13 in region R1a at 60 Hz. Figure 8 is a timing diagram illustrating the operation of the gate drive circuit 1 when scanning the TFT 13 in region R1a at 120 Hz. Figure 9 is a diagram showing an example of a gate signal output when the TFT 13 in region R1a, the TFT 13 in region R2a, and the TFT 13 in region R3a are operated at different frequencies. Figures 5 to 8 illustrate an example of the gate signal Gr supplied to the TFT13 in region R1a. However, since the TFT13 in region R2a and region R3a operate similarly to the TFT13 in region R1a, the explanation of the operation of the TFT13 in region R2a and region R3a is omitted.
[0019] In this embodiment, the multiple switches SWG1 select one of the following states in response to the gate control signal: a state in which a portion (half) of the gate signal G1 is output to the gate line 11a and the gate signals G1 and G2 are not output to the gate line 11b (see Figure 5); a state in which the gate signal G1 is output to the gate line 11a and the gate signals G1 and G2 are not output to the gate line 11b (see Figure 6); and a state in which the gate signal G1 is output to the gate line 11a and the gate signal G2, which has the same frequency as the gate signal G1 but a different phase with respect to the gate signal G1, is output to the gate line 11b (see Figure 8). As shown in Figure 2, the switch SWG1 includes a switch SWG1a that switches between a state in which the gate line 11a is connected to ground GND and a state in which the gate line 11a is connected to the conductor line 30a in response to the gate control signal. Furthermore, switch SWG1 includes a switch SWG1b that switches between a state in which the gate line 11b and the conductor line 30a are connected and a state in which the gate line 11b is open (Open state) in response to the gate control signal.
[0020] As shown in Figures 5 to 8, the gate signal input to the gate electrode of the TFT 13 is denoted as Gr. The signal output unit 30 outputs gate signals G1 and G2 to the switch SWG1. The frequency of gate signal G1 is 60 Hz. The frequency of gate signal G2 is 60 Hz, and the phase of gate signal G2 is delayed by half a period (π) relative to gate signal G1. In Figures 5 to 8, one scan is performed during the period when gate signal G1 is high once.
[0021] As shown in Figure 5, in order to set the frequency of the gate signal Gr to 30Hz, the control circuit 20 connects the switch SWG1a of the gate drive circuit 1 to ground GND at a frequency of 30Hz. As a result, the frequency of the gate signal Ga output to the gate line 11a becomes 30Hz. In addition, the control circuit 20 opens the switch SWG1b of the gate drive circuit 1. As a result, no gate signal is output to the gate line 11b. As a result of these actions, the frequency of the gate signal Gr input to the TFT 13 becomes 30Hz.
[0022] As shown in Figure 6, in order to set the frequency of the gate signal Gr to 60Hz, the control circuit 20 sets the switch SWG1a of the gate drive circuit 1 to connect the conductor wire 30a and the gate wire 11a. As a result, the frequency of the gate signal Ga output to the gate wire 11a becomes 60Hz. The control circuit 20 also sets the switch SWG1b of the gate drive circuit 1 to the open state. As a result, no gate signal is output to the gate wire 11b. As a result, the frequency of the gate signal Gr input to the TFT 13 becomes 60Hz.
[0023] Furthermore, as shown in Figure 7, as another method to set the gate signal Gr frequency to 60Hz, the control circuit 20 connects the switch SWG1a of the gate drive circuit 1 to the ground GND via the conductor wire 30a. As a result, no gate signal is output to the gate wire 11a. The control circuit 20 also connects the switch SWG1b of the gate drive circuit 1 to the conductor wire 30b via the gate wire 11b. As a result, a 60Hz gate signal Gb is output to the gate wire 11b. As a result, the frequency of the gate signal Gr input to the TFT 13 becomes 60Hz.
[0024] As shown in Figure 8, in order to set the frequency of the gate signal Gr to 120 Hz, the control circuit 20 sets the switch SWG1a of the gate drive circuit 1 to connect the conductor wire 30a and the gate wire 11a. As a result, the frequency of the gate signal Ga output to the gate wire 11a becomes 60 Hz. The control circuit 20 also sets the switch SWG1b of the gate drive circuit 1 to connect the conductor wire 30b and the gate wire 11b. As a result, a gate signal Gb of 60 Hz is output to the gate wire 11b. As a result of these actions, the frequency of the gate signal Gr input to the TFT 13 becomes 120 Hz.
[0025] According to the above configuration, two gate lines (gate lines 11a and 11b) are arranged for each row of TFT 13. As a result, when gate signal G1 is output as gate signal Ga to gate line 11a and gate signal G2 is output as gate signal Gb to gate line 11b, gate signals are supplied to the TFT 13 alternately from both gate line 11a and gate line 11b. Therefore, the frequency of the gate signal input to the TFT 13 becomes twice the frequency of gate signals G1 and G2 generated in the gate drive circuit 1. As a result, the frequency of gate signals G1 and G2 generated in the gate drive circuit 1 can be reduced to half the frequency of gate signal Gr, thereby reducing the power consumption and heat generation in the gate drive circuit 1.
[0026] Here, as shown in Figure 9, the control circuit 20 sends a gate control signal to the gate drive circuit 1 so that the frequency of the gate signal Gr input to the TFT 13 in region R1a is 30 Hz, the frequency of the gate signal Gr input to the TFT 13 in region R2a is 60 Hz, and the frequency of the gate signal Gr input to the TFT 13 in region R3a is 120 Hz. In this case, the source signal Sr is input to the TFT 13 from the source drive circuit 2 at 120 Hz. For example, the gate drive circuit 1 outputs the gate signal Gr shown in Figure 5 to the TFT 13 in region R1a, the gate signal Gr shown in Figure 6 to the TFT 13 in region R2a, and the gate signal Gr shown in Figure 8 to the TFT 13 in region R3a. With the above configuration, it is possible to change the frequency for each region on the screen.
[0027] (Operation of source drive circuit 2) Next, the operation of the source drive circuit 2 according to this embodiment will be described with reference to Figures 10 to 15. Figure 10 is a timing diagram illustrating the operation of the source drive circuit 2 when a source signal is supplied at 30 Hz to the TFT 13 in region R1b. Figures 11 and 12 are timing diagrams illustrating the operation of the source drive circuit 2 when a source signal is supplied at 60 Hz to the TFT 13 in region R1b. Figure 13 is a timing diagram illustrating the operation of the source drive circuit 2 when a source signal is supplied at 120 Hz to the TFT 13 in region R1b. Figure 14 is a diagram illustrating an example where source signals of different frequencies are supplied to the TFT 13 in region R1b, the TFT 13 in region R2b, and the TFT 13 in region R3b. Figure 15 is a diagram illustrating the polarity of the source signal. Figures 10 to 13 illustrate an example of the source signal Sr supplied to the TFT13 in region R1b. However, since the TFT13 in region R2b and region R3b operate similarly to the TFT13 in region R1b, the explanation of the operation of the TFT13 in region R2b and region R3b is omitted. Also, as shown in Figure 15, the period when the source signal is High includes the period when the source signal is positive and the period when the source signal is negative. The period when the source signal is Low is the period when the source signal is at the same potential as ground GND (neither positive nor negative).
[0028] In this embodiment, the multiple switches SWS1 select one of the following states in response to the source control signal: a state in which a portion (half) of the source signal S1 is output to the source line 12a and source signals S1 and S2 are not output to the source line 12b (see Figure 10); a state in which the source signal S1 is output to the source line 12a and source signals S1 and S2 are not output to the source line 12b (see Figure 11); and a state in which the source signal S1 is output to the source line 12a and a source signal S2, which has the same frequency as the source signal S1 but a different phase with respect to the source signal S1, is output to the source line 12b (see Figure 13). As shown in Figure 2, the switch SWS1 includes a switch SWS1a that switches between a state in which the source line 12a is connected to ground GND and a state in which the source line 12a is connected to the conductor line 40a in response to the source control signal. Furthermore, switch SWS1 includes a switch SWS1b that, in response to a source control signal, switches between a state in which the source line 12b and the conductor line 40a are connected and a state in which the source line 12b is left open (Open state).
[0029] As shown in Figures 10 to 13, the source signal input to the source electrode of the TFT 13 is denoted as Sr. The signal output unit 40 outputs source signals S1 and S2 to the switch SWS1. The frequency of source signal S1 is 60 Hz. The frequency of source signal S2 is 60 Hz, and the phase of source signal S2 is delayed by half a period (π) relative to source signal S1.
[0030] As shown in Figure 10, in order to set the frequency of the source signal Sr to 30Hz, the control circuit 20 connects the switch SWS1a of the source drive circuit 2 to ground GND at a frequency of 30Hz. As a result, the frequency of the source signal Sa output to source line 12a becomes 30Hz. The control circuit 20 also opens the switch SWS1b of the source drive circuit 2. As a result, no source signal is output to source line 12b. As a result, the frequency of the source signal Sr input to the TFT 13 becomes 30Hz.
[0031] As shown in Figure 11, in order to set the frequency of the source signal Sr to 60Hz, the control circuit 20 sets the switch SWS1a of the source drive circuit 2 to connect the conductor wire 40a and the source wire 12a. As a result, the frequency of the source signal Sa output to the source wire 12a becomes 60Hz. The control circuit 20 also sets the switch SWS1b of the source drive circuit 2 to the open state. As a result, no source signal is output to the source wire 12b. As a result, the frequency of the source signal Sr input to the TFT 13 becomes 60Hz.
[0032] Furthermore, as shown in Figure 12, as another method to set the frequency of the source signal Sr to 60Hz, the control circuit 20 connects the switch SWS1a of the source drive circuit 2 to the ground GND via the conductor wire 40a. As a result, no source signal is output to the source wire 12a. The control circuit 20 also connects the switch SWS1b of the source drive circuit 2 to the conductor wire 40b and the source wire 12b via the switch SWS1b. As a result, a 60Hz source signal Sb is output to the source wire 12b. As a result, the frequency of the source signal Sr input to the TFT 13 becomes 60Hz.
[0033] As shown in Figure 13, in order to set the frequency of the source signal Sr to 120 Hz, the control circuit 20 sets the switch SWS1a of the source drive circuit 2 to connect the conductor wire 40a and the source wire 12a. As a result, the frequency of the source signal Sa output to the source wire 12a becomes 60 Hz. The control circuit 20 also sets the switch SWS1b of the source drive circuit 2 to connect the conductor wire 40b and the source wire 12b. As a result, a 60 Hz source signal Sb is output to the source wire 12b. As a result of these actions, the frequency of the source signal Sr input to the TFT 13 becomes 120 Hz.
[0034] According to the above configuration, two source lines (source lines 12a and 12b) are arranged for each row of TFTs 13. This means that when source signal S1 is output as source signal Sa to source line 12a and source signal S2 is output as source signal Sb to source line 12b, the TFTs 13 are supplied with source signals alternately from both source lines 12a and 12b. Therefore, the frequency of the source signal input to the TFTs 13 becomes twice the frequency of source signals S1 and S2 generated in the source drive circuit 2. As a result, the frequency of source signals S1 and S2 generated in the source drive circuit 2 can be reduced to half the frequency of source signal Sr, thereby reducing power consumption and heat generation in the source drive circuit 2.
[0035] Here, as shown in Figure 14, the control circuit 20 sends a source control signal to the source drive circuit 2 so that the frequency of the source signal Sr input to the TFT 13 in region R1b is 30 Hz, the frequency of the source signal Sr input to the TFT 13 in region R2b is 60 Hz, and the frequency of the source signal Sr input to the TFT 13 in region R3b is 120 Hz. In this case, the source drive circuit 2 inputs the source signal Sr at 120 Hz to the TFT 13. For example, the source drive circuit 2 outputs the source signal Sr shown in Figure 10 to the TFT 13 in region R1b, the source signal Sr shown in Figure 11 to the TFT 13 in region R2b, and the source signal Sr shown in Figure 13 to the TFT 13 in region R3b. With the above configuration, it is possible to change the frequency for each region on the screen.
[0036] [Measurement results of current consumption and temperature change of display panel 10] Next, with reference to Figure 16, the measurement results of the current consumption and temperature change of the display panel 10 according to the embodiment of this model will be explained. Figure 16 shows the measurement results of the current consumption and temperature of the display panel 10 when the gate signal Gr input to the TFT 13 in half of the display panel 10 is changed from 60Hz to 30Hz. As shown in Figure 16, when all of the TFT 13 in the display panel 10 are operated at 60Hz, the current consumption was 1111mA. When half of the TFT 13 in the display panel 10 are operated at 60Hz and the other half at 30Hz, the current consumption was 974mA. As a result, the current consumption was reduced by 12.3%, and the temperature of the display panel 10 decreased by 1.5℃. As a result, it was found that when half of the TFTs 13 in the display panel 10 were operated at 60Hz and the other half at 30Hz, the current consumption decreased and the temperature decreased (temperature rise was smaller) compared to when all of the TFTs 13 in the display panel 10 were operated at 60Hz.
[0037] [Differentiation] Although embodiments of the invention have been described above, these embodiments are merely examples for carrying out the invention. Therefore, it is possible to carry out the invention by appropriately modifying the embodiments described above without departing from the spirit of the invention, without being limited to the embodiments described above. Modifications of the embodiments described above will be described below.
[0038] (1) In the above embodiment, an example was shown in which the signal output unit 30 and the plurality of switches 31 are configured integrally (as a gate drive circuit 1), but the disclosure is not limited thereto. As shown in the first modified display device 200 in Figure 17, the signal output unit 230 (gate drive circuit) and the plurality of switches 231 may be configured separately (as separate components).
[0039] (2) In the above embodiment, an example was shown in which the signal output unit 40 and the plurality of switches 41 are configured integrally (as a source drive circuit 2), but the disclosure is not limited thereto. As shown in the second modified display device 300 in Figure 18, the signal output unit 340 (source drive circuit) and the plurality of switches 341 may be configured separately (as separate components).
[0040] (3) In the above embodiment, an example was shown in which two gate lines and two source lines are connected to one TFT 13, but the disclosure is not limited thereto. As shown in the third modified display device 400 in Figure 19, the source drive circuit 440 (signal output section) may be configured so that one source line 412 is connected to one TFT 13 without providing a switch. Also, as shown in the fourth modified display device 500 in Figure 20, the gate drive circuit 530 (signal output section) may be configured so that one gate line 511 is connected to one TFT 13 without providing a switch. Furthermore, three or more gate lines may be connected to one TFT 13, or three or more source lines may be connected to one TFT 13.
[0041] (4) In the above embodiment, an example was shown in which the polarity of the source signal output from the source drive circuit is inverted between the positive and negative terminals, but the disclosure is not limited thereto. For example, the polarity of the source signal does not need to be inverted.
[0042] (5) In the above embodiments, 30 Hz, 60 Hz, and 120 Hz were given as examples of gate signal and source signal frequencies, but the disclosure is not limited thereto. For example, the gate drive circuit may be configured to output a gate signal with a frequency other than 30 Hz, 60 Hz, and 120 Hz, or the source drive circuit may be configured to output a source signal with a frequency other than 30 Hz, 60 Hz, and 120 Hz.
[0043] (6) In the above embodiment, an example was shown in which a gate signal G1 and a gate signal G2 that is phase-delayed by half a period (π) relative to the gate signal G1 are output from the signal output unit, but the disclosure is not limited thereto. That is, the signal output unit may output a gate signal G1 and a gate signal that is phase-delayed by a length other than half a period relative to the gate signal G1.
[0044] The above configuration can also be explained as follows:
[0045] The display device according to the first configuration includes a plurality of transistors arranged in a matrix, a first scan line group including a first scan line connected to a first transistor among the plurality of transistors, and a second scan line connected to the first transistor, a source line group including a plurality of source lines connected to the plurality of transistors, a gate drive circuit that outputs a gate signal, a source drive circuit that outputs source signals to the plurality of source lines, and a control circuit that supplies a gate control signal to the gate drive circuit, wherein the gate drive circuit selects either a first state in which it outputs the gate signal to the first scan line and does not output a gate signal to the second scan line, or a second state in which it outputs the gate signal to the first scan line and outputs a signal to the second scan line that has the same frequency as the gate signal output to the first scan line but has a different phase with respect to the gate signal (first configuration).
[0046] According to the first configuration described above, two scan lines (a first scan line and a second scan line) are connected to the first transistor. In the second state, where a gate signal is output to the first scan line and a signal with the same frequency as the gate signal output to the first scan line but with a different phase is output to the second scan line, the first transistor is supplied with gate signals of the same frequency from both the first and second scan lines at different timings. As a result, the frequency of the gate signal supplied to the first transistor is twice the frequency of the gate signal generated in the gate drive circuit. Consequently, the frequency of the gate signal generated in the gate drive circuit can be halved compared to the case where the gate signal is supplied to the first transistor via a single scan line. This reduces the power consumption and heat generated in the gate drive circuit.
[0047] In the first configuration, the gate drive circuit may be configured to select one of the following in response to the gate control signal: a first state, a second state, or a third state in which a signal with a frequency of half or less of the frequency of the gate signal output to the first scan line in the first state is output to the first scan line, and no gate signal is output to the second scan line (second configuration).
[0048] According to the second configuration described above, in the third state, the frequency at which the first transistor is driven can be reduced to half or less of the frequency at which the first transistor is driven in the first state.
[0049] In the first or second configuration, the display device may further include a second scan line group, which includes a third scan line connected to the second transistor among the plurality of transistors, and a fourth scan line connected to the second transistor. The gate drive circuit may be configured to select either the first state or the second state in response to the gate control signal, and to select either a fourth state in response to the gate control signal, in which the gate signal is output to the third scan line and the gate signal is not output to the fourth scan line, or a fifth state in which the gate signal is output to the third scan line and a signal is output to the fourth scan line at the same frequency as the gate signal output to the third scan line but with a different phase relative to the gate signal (third configuration).
[0050] According to the third configuration described above, the transistors in the area of the screen where the first scan line group is located and the transistors in the area of the screen where the second scan line group is located can be driven at different frequencies. As a result, it becomes possible to change the frequency for each area of the screen.
[0051] In the third configuration, the gate drive circuit may be configured to select either the first state or the second state in response to the gate control signal, and to select either the fourth state, the fifth state, or a sixth state in which a signal with a frequency of half or less of the frequency of the gate signal output to the third scan line in the fourth state is output to the third scan line in response to the gate control signal (fourth configuration).
[0052] According to the fourth configuration described above, in the sixth state, the frequency at which the second transistor is driven can be reduced to half or less of the frequency at which the second transistor is driven in the fourth state.
[0053] In any one of the first to fourth configurations, the source line group may include a first source line group comprising a first source line connected to a third transistor among the plurality of transistors and a second source line connected to the third transistor. The control circuit may be configured to output a source control signal to the source drive circuit. The source drive circuit may be configured to select either a seventh state in which the source signal is output to the first source line and no source signal is output to the second source line, or an eighth state in which the source signal is output to the first source line and a signal is output to the second source line at the same frequency as the source signal output to the first source line but with a different phase relative to the source signal (fifth configuration).
[0054] According to the fifth configuration described above, the third transistor is supplied with source signals of the same frequency from both the first and second source lines at different timings. Therefore, a signal with twice the frequency of the source signal generated in the source drive circuit can be supplied to the third transistor. As a result, the frequency of the source signal supplied to the third transistor becomes twice the frequency of the source signal generated in the source drive circuit. Consequently, the frequency of the source signal generated in the source drive circuit can be halved compared to the case where the source signal is supplied to the third transistor via a single source line. This reduces the power consumption and heat generation in the source drive circuit.
[0055] In the fifth configuration, the source drive circuit may be configured to select one of the following in response to the source control signal: the seventh state, the eighth state, and the ninth state in which a signal with a frequency of half or less of the frequency of the source signal output to the first source line in the seventh state is output to the first source line, and no source signal is output to the second source line (sixth configuration).
[0056] According to the sixth configuration described above, in the ninth state, the frequency at which the third transistor is driven can be reduced to half or less of the frequency at which the third transistor is driven in the seventh state.
[0057] In the fifth or sixth configuration, the display device may further include a second source line group, which includes a third source line connected to a fourth transistor among the plurality of transistors, and a fourth source line connected to the fourth transistor. The source drive circuit may be configured to select either the seventh state or the eighth state in response to the source control signal, and to select either a tenth state in response to the source control signal, which outputs the source signal to the third source line and does not output the source signal to the fourth source line, or an eleventh state in which the source signal is output to the third source line and a signal is output to the fourth source line at the same frequency as the source signal output to the third source line but with a different phase relative to the source signal (seventh configuration).
[0058] According to the seventh configuration described above, source signals of different frequencies can be supplied to the transistors in the area on the screen where the first group of source lines is located and to the transistors in the area on the screen where the second group of source lines is located. As a result, it becomes possible to change the display frequency for each area on the screen. [Explanation of Symbols]
[0059] 1: Gate drive circuit, 2: Source drive circuit, 10: Display panel, 11a~11f: Gate lines, 12a~12f: Source lines, 14: Pixel electrode, 15: Common electrode, 20: Control circuit, 30: Signal output section, 30a, 30b: Conductor wires, 31: Switch, 40: Signal output section, 40a, 40b: Conductor wires, 41: Switch, 100: Display device, 200: Display device, 230: Signal output section, 231: Switch, 300: Display device, 340: Signal output section, 341: Switch, 400: Display Device, 412: Source line, 440: Source drive circuit, 500: Display device, 511: Gate line, 530: Gate drive circuit, GND: Ground, R1a: Region, R1b: Region, R2a: Region, R2b: Region, R3a: Region, R3b: Region, SWG1: Switch, SWG1a: Switch, SWG1b: Switch, SWG2: Switch, SWG3: Switch, SWS1: Switch, SWS1a: Switch, SWS1b: Switch, SWS2: Switch, SWS3: Switch
Claims
1. Multiple transistors arranged in a matrix, A first scan line group including a first scan line connected to a first transistor among the plurality of transistors, and a second scan line connected to the first transistor, A group of source lines including multiple source lines connected to the multiple transistors, A gate drive circuit that outputs a gate signal, A source drive circuit that outputs source signals to the plurality of source lines, The system includes a control circuit that supplies a gate control signal to the gate drive circuit, The gate drive circuit, in response to the gate control signal, A first state in which the gate signal is output to the first scan line and the gate signal is not output to the second scan line, A display device that selects either a second state in which the gate signal is output to the first scan line, and a second state in which a signal with the same frequency as the gate signal output to the first scan line but with a different phase to the gate signal is output to the second scan line.
2. The display device according to claim 1, wherein the gate drive circuit selects one of the following in response to the gate control signal: a first state, a second state, and a third state in which a signal with a frequency of half or less of the frequency of the gate signal output to the first scan line in the first state is output to the first scan line, and the gate signal is not output to the second scan line.
3. The system further includes a second scan line group, which includes a third scan line connected to a second transistor among the plurality of transistors, and a fourth scan line connected to the second transistor. The gate drive circuit is, In response to the gate control signal, one of the first state and the second state is selected, The display device according to claim 1, which selects either a fourth state in which the gate signal is output to the third scan line and the gate signal is not output to the fourth scan line, or a fifth state in which the gate signal is output to the third scan line and a signal with the same frequency as the gate signal output to the third scan line but with a different phase to the gate signal is output to the fourth scan line.
4. The gate drive circuit is, In response to the gate control signal, one of the first state and the second state is selected, The display device according to claim 3, which selects one of the following in response to the gate control signal: the fourth state, the fifth state, and the sixth state in which a signal with a frequency of half or less of the frequency of the gate signal output to the third scan line in the fourth state is output to the third scan line.
5. The source line group includes a first source line group which includes a first source line connected to a third transistor among the plurality of transistors and a second source line connected to the third transistor, The control circuit outputs a source control signal to the source drive circuit. The source drive circuit, in response to the source control signal, A seventh state in which the source signal is output to the first source line and the source signal is not output to the second source line, The display device according to claim 1, which selects one of the following: outputting the source signal to the first source line, and an eighth state outputting a signal to the second source line that has the same frequency as the source signal output to the first source line but has a different phase with respect to the source signal.
6. The display device according to claim 5, wherein the source drive circuit selects one of the following in response to the source control signal: the seventh state, the eighth state, and the ninth state in which a signal with a frequency of half or less of the frequency of the source signal output to the first source line in the seventh state is output to the first source line, and no source signal is output to the second source line.
7. The system further comprises a second group of source lines including a third source line connected to a fourth transistor among the plurality of transistors, and a fourth source line connected to the fourth transistor. The source drive circuit is In accordance with the source control signal, one of the seventh state and the eighth state is selected, The display device according to claim 5, which selects either a tenth state in which the source signal is output to the third source line and the source signal is not output to the fourth source line, or an eleventh state in which the source signal is output to the third source line and a signal is output to the fourth source line at the same frequency as the source signal output to the third source line but with a different phase relative to the source signal.
Citation Information
Patent Citations
Driving circuit of electrooptical device, electrooptical device and electronic device
JP2000112437A