Thermally Enhanced Power Semiconductor Package

Abstract

A semiconductor package is provided. In one example, the power semiconductor package includes a first carrier submount, a second carrier submount, and a plurality of semiconductor dies. Each semiconductor die of the plurality of semiconductor dies has a first side and an opposite second side. Further, for each semiconductor die of the plurality of semiconductor dies, the first side is directly coupled to the first carrier submount and the second side is directly coupled to the second carrier submount.

Description

Detailed Description of the Invention

[0001] [Priority claim] This application is based on and claims the benefit of priority to U.S. Patent Application No. 18 / 456,782, filed August 28, 2023, which is a continuation-in-part of and claims the benefit of priority to U.S. Patent Application No. 18 / 154,353, filed January 13, 2023. This application claims priority to and the benefit of the entire contents of the cited applications, which are incorporated by reference. [Field]

[0002] The present disclosure relates generally to semiconductor packages. [background]

[0003] Semiconductor devices, such as transistors and diodes, are ubiquitous in modern electronic devices. Wide bandgap semiconductor material systems, such as gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC), are increasingly being utilized in semiconductor devices to push the limits of device performance in areas such as switching speed, power handling capability, and thermal conductivity. Exemplary power semiconductor devices can include metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), Schottky barrier diodes, PIN diodes, thyristors, and high-electron-mobility transistors (HEMTs). Packaging technology can play a key role in the performance of power semiconductor devices. [overview]

[0004] Aspects and advantages of embodiments of the present disclosure will be set forth in part in the description that follows, or may be learned from the description, or may be learned through practice of the embodiments.

[0005] One exemplary aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package includes a first carrier submount including one or more conductive pads. The power semiconductor package further includes a second carrier submount including one or more conductive leads. The power semiconductor package further includes a power semiconductor die having a first side and an opposite second side. The first side of the power semiconductor die may be directly coupled to the first carrier submount, and the second side of the power semiconductor die may be directly coupled to the second carrier submount.

[0006] Another exemplary aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package includes a first carrier submount, a second carrier submount, and a power semiconductor die having a first side and an opposite second side. The power semiconductor die may include source and gate contacts on the first side and a drain contact on the second side. The first side of the power semiconductor die may be directly coupled to the first carrier submount in a flip-chip configuration such that the source and gate contacts are directly coupled to the first carrier submount, and the second side of the power semiconductor die may be directly coupled to the second carrier submount.

[0007] Another exemplary aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package includes a first carrier submount and a second carrier submount. The power semiconductor package further includes a power semiconductor die having a first side and an opposite second side. The power semiconductor die may include a source contact and a gate contact on the first side and a drain contact on the second side. The power semiconductor package further includes an insulating layer on the first side of the semiconductor die and an encapsulant. The first side of the power semiconductor die may be directly coupled to the first carrier submount, and the second side of the power semiconductor die may be directly coupled to the second carrier submount.

[0008] Another exemplary aspect of the present disclosure is directed to a method of manufacturing a power semiconductor package. The method includes directly bonding a power semiconductor die to a first carrier submount to form a first assembly. The method further includes directly bonding the first assembly to a second carrier submount, the second carrier submount including one or more conductive leads. The method further includes encapsulating the first carrier submount, the second carrier submount, and at least a portion of the power semiconductor die to form an encapsulation.

[0009] Another exemplary embodiment of the present disclosure is directed to a power semiconductor package. The power semiconductor package includes a first carrier submount, a second carrier submount, and a plurality of semiconductor dies. Each semiconductor die of the plurality of semiconductor dies has a first side and an opposite second side. Further, for each semiconductor die of the plurality of semiconductor dies, the first side is directly coupled to the first carrier submount and the second side is directly coupled to the second carrier submount.

[0010] Another exemplary embodiment of the present disclosure is directed to a power semiconductor package. The power semiconductor package includes a first carrier submount, a second carrier submount, and a plurality of semiconductor dies. The first carrier submount includes a first conductive layer and a second conductive layer. Each semiconductor die of the plurality of semiconductor dies includes a first side and an opposite second side, a source contact and a gate contact on the first side, and a drain contact on the second side. Further, for each semiconductor die of the plurality of semiconductor dies, the first side is directly coupled to the first carrier submount such that the source contact is directly coupled to the first conductive layer of the first carrier submount and the gate contact is directly coupled to the second conductive layer of the first carrier submount. Further, for each semiconductor die of the plurality of semiconductor dies, the second side is directly coupled to the second carrier submount.

[0011] Another exemplary embodiment of the present disclosure is directed to a power semiconductor package. The power semiconductor package includes: a carrier submount including one or more conductive patterns; a first lead frame including one or more conductive leads; a second lead frame including one or more conductive leads; a first semiconductor die having a first side directly coupled to the carrier submount and an opposite second side directly coupled to the first lead frame; and a second semiconductor die having a first side directly coupled to the carrier submount and an opposite second side directly coupled to the second lead frame. The first semiconductor die further includes a source contact on the first side coupled to at least one of the one or more conductive patterns of the carrier submount, a gate contact on the first side coupled to at least one of the one or more conductive patterns of the carrier submount, and a drain contact on the second side coupled to at least one of the one or more conductive leads of the first lead frame. The second semiconductor die further comprises a source contact on a first surface coupled to at least one of the one or more conductive patterns of the carrier submount and to at least one of the one or more conductive leads of the first lead frame, a gate contact on the first surface coupled to at least one of the one or more conductive patterns of the carrier submount, and a drain contact on a second surface coupled to at least one of the one or more conductive leads of the second lead frame.

[0012] Another exemplary embodiment of the present disclosure is directed to a power semiconductor package. The power semiconductor package includes a first carrier submount, a second carrier submount, and a semiconductor die. The first carrier submount includes a first conductive layer, a second conductive layer, and an insulating layer between the first and second conductive layers. The semiconductor die has a first side and an opposite second side. The power semiconductor package further includes a conductive pattern that is different from the first conductive layer and the second conductive layer.

[0013] These and other features, aspects, and advantages of various embodiments will become better understood with reference to the following description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, explain related principles. [Brief explanation of the drawings]

[0014] A detailed discussion of embodiments directed to those skilled in the art is set forth herein, which refers to the accompanying drawings, in which: [Figure 1] 1 illustrates a power semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 2] 1 illustrates a flowchart of an exemplary method according to an exemplary embodiment of the present disclosure. [Figure 3] 1 illustrates an exemplary direct bonding of a power semiconductor die to a first carrier submount to form a first assembly according to an exemplary embodiment of the present disclosure. [Figure 4] 1 illustrates an exemplary first carrier submount according to an exemplary embodiment of the present disclosure. [Figure 5] 1 illustrates an exemplary semiconductor die directly bonded to a first carrier submount in a flip-chip configuration, according to an exemplary embodiment of the present disclosure. [Figure 6] 1 illustrates the formation of an exemplary insulating layer on a power semiconductor die according to an exemplary embodiment of the present disclosure. [Figure 7] 1 illustrates an exemplary singulation of a first assembly according to an exemplary embodiment of the present disclosure. [Figure 8] 1 illustrates an exemplary first assembly according to an exemplary embodiment of the present disclosure. [Figure 9] 1 illustrates an exemplary direct coupling between a first assembly and a second carrier submount according to an exemplary embodiment of the present disclosure. [Figure 10] 1 illustrates an exemplary encapsulation of a first carrier submount, a second carrier submount, and at least a portion of a power semiconductor die to form an encapsulation of a power semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 11] 1 illustrates a power semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 12] 1 illustrates a power semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 13] 1 illustrates a power semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 14] 1 illustrates a power semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 15] 1 illustrates a top view of an exemplary power semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 16] 16 illustrates a cross-sectional view of the structure of the exemplary power semiconductor package of FIG. 15, according to an exemplary embodiment of the present disclosure. [Figure 17] 16 illustrates a cross-sectional view of the structure of the exemplary power semiconductor package of FIG. 15, according to an exemplary embodiment of the present disclosure. [Figure 18] 1 illustrates a top view of an exemplary power semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 19] 1 illustrates a top view of an exemplary power semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 20] 20 illustrates a cross-sectional view of the structure of the exemplary power semiconductor package of FIG. 19, according to an exemplary embodiment of the present disclosure. [Figure 21] 20 illustrates a cross-sectional view of the structure of the exemplary power semiconductor package of FIG. 19, according to an exemplary embodiment of the present disclosure. [Figure 22] 20 illustrates a first layer of the first carrier submount of the exemplary power semiconductor package of FIG. 19, according to an exemplary embodiment of the present disclosure. [Figure 23] 20 illustrates a second layer of the first carrier submount of the exemplary power semiconductor package of FIG. 19, according to an exemplary embodiment of the present disclosure. [Figure 24] 1 illustrates a top view of an exemplary power semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 25] 1 illustrates a top view of an exemplary power semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 26] 26 illustrates a cross-sectional view of the structure of the exemplary power semiconductor package of FIG. 25, according to an exemplary embodiment of the present disclosure. [Figure 27] 26 illustrates a portion of the first lead frame and the second lead frame of the exemplary power semiconductor package of FIG. 25, according to an exemplary embodiment of the present disclosure. [Figure 28] 26 illustrates a carrier submount for the exemplary power semiconductor package of FIG. 25, according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0015] Repeat use of reference characters in the present specification and drawings is intended to represent same and / or analogous features or elements of the invention. [Detailed explanation] Reference will now be made in detail to one or more examples of the embodiments, examples of which are illustrated in the drawings. Each example is not intended to limit the disclosure, but is provided by way of explanation of the embodiments. Indeed, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments without departing from the scope or spirit of the disclosure. For example, features illustrated or described as part of one embodiment may be used with another embodiment to yield a still further embodiment. It is therefore intended that aspects of the disclosure cover such modifications and variations.

[0016] Discrete semiconductor packages containing semiconductor dies, such as MOSFETs or Schottky diodes, have been developed. Such semiconductor packages containing MOSFETs can be employed in a variety of applications to enable higher switching frequencies with associated loss reductions, higher blocking voltages, and improved avalanche capability. Exemplary applications can include high-performance industrial power supplies, server / telecom power supplies, electric vehicle charging systems, energy storage systems, uninterruptible power supplies, high-voltage DC / DC converters, electric vehicles, and battery management systems. Discrete semiconductor packages containing Schottky diodes are employed in many of the same high-performance power applications described above for MOSFETs and can sometimes also be employed in systems containing discrete power packages of MOSFETs.

[0017] Packaging technology for semiconductor devices plays a significant role in determining the performance of the semiconductor device. For example, the packaging of a power semiconductor die can limit the semiconductor die's ability to dissipate heat, conduct current, or even switch at a particular speed (e.g., due to stray inductance). Ineffective heat dissipation can create problems for semiconductor devices (e.g., small form factor semiconductor devices) or in situations where the semiconductor device is in tight contact with a housing. Excessive heat can adversely affect the operation of the semiconductor device itself and also the electronic system in which the semiconductor device is used.

[0018] Furthermore, discrete semiconductor packages may use wire bonds (e.g., aluminum wire bonds) to interconnect between a portion of the semiconductor die (e.g., the gate of the semiconductor device) and the package (e.g., the lead frame). The use of wire bonds may limit the power and current carrying capacity that can be accommodated in the package. Many solutions to improve the power and current carrying capacity capabilities of power semiconductor packages focus on the use of high thermal conductivity materials to enhance heat spreading and conductive clips or ribbons to interconnect to increase current carrying capacity. In these examples, the interconnection between the gate of the semiconductor device and the lead frame may still be by wire bond, which may act as one of the weakest points in discrete semiconductor packages.

[0019] Exemplary aspects of the present disclosure are directed to a power semiconductor package that can provide a second heat spreading path for the power semiconductor die. Additionally, in some examples, the power semiconductor package does not have any wire bonds to the power semiconductor die.

[0020] More specifically, in an exemplary embodiment, the power semiconductor package may include a first carrier submount, such as a direct bond copper (DBC) substrate or an active metal bond (AMB) substrate. The first carrier submount may include one or more conductive pads. The power semiconductor die may be directly bonded to the first carrier submount. As used herein, a power semiconductor die is directly bonded to a first carrier submount when the power semiconductor die is attached to the first carrier submount (e.g., by an adhesive material such as solder, paste, or sintered material, or without an adhesive material) without any intervening structure, such as a wire bond, wire ribbon, clip, or other structure.

[0021] In some examples, the power semiconductor die is directly bonded to the first carrier submount in a flip-chip configuration, in which the semiconductor die is "flipped" so that contacts associated with a typical outward-facing surface of the semiconductor die (e.g., source contacts, Kelvin contacts, gate contacts, etc.) are directly bonded (e.g., using an adhesive material) to the first carrier submount.

[0022] The power semiconductor die may be based on a wide bandgap semiconductor material. Wide bandgap semiconductors, such as silicon carbide and / or III-nitrides (e.g., gallium nitride), have a bandgap greater than approximately 1.40 eV. In some examples, the power semiconductor die may include semiconductor devices, such as transistors, diodes, and / or thyristors. For example, in some examples, the power semiconductor die may include a silicon carbide-based MOSFET positioned between a source contact and a drain contact to form, for example, a vertically structured power semiconductor device. Aspects of the present disclosure are discussed with reference to a silicon carbide-based MOSFET device for purposes of illustration and discussion. Using the disclosure provided herein, one skilled in the art will understand that the power semiconductor die may include other semiconductor devices, such as diodes (e.g., Schottky diodes, PIN diodes, etc.), insulated gate bipolar transistors, high electron mobility transistors, or other devices, without departing from the scope of the present disclosure.

[0023] In some examples, an insulating layer may be formed on the power semiconductor die. The insulating material may be, for example, a dielectric material. The dielectric material may, in some embodiments, be an underfill material. The underfill material may be, for example, a composite material made of a polymer (e.g., an epoxy polymer) containing fillers and / or additional components.

[0024] A semiconductor die directly bonded to a first carrier submount (e.g., in a flip-chip configuration) may form a first assembly. According to examples of the present disclosure, the first assembly may be directly bonded to a second carrier submount. For example, a surface of the semiconductor die opposite the surface directly bonded to the first carrier submount may be directly bonded to the second carrier submount. As used herein, a power semiconductor die is directly bonded to a second carrier submount when the power semiconductor die is attached to the second carrier submount (e.g., by an adhesive material such as solder, paste, or sintered material, or without an adhesive material) without any intervening structure, such as a wire bond, wire ribbon, clip, or other structure. In some examples, the second carrier submount may be a lead frame for a power semiconductor package and may include one or more conductive leads.

[0025] An encapsulation may be formed around the first carrier submount, the second carrier submount, and at least a portion of the power semiconductor die to form a power semiconductor package. In some examples, the dielectric material of the encapsulation may be the same as the dielectric material of the insulating layer on the power semiconductor die. In some examples, the dielectric material of the encapsulation may be different from the dielectric material of the insulating layer on the power semiconductor die. For example, the dielectric material of the insulating layer may have a different dielectric constant (e.g., a lower dielectric constant) than the dielectric material of the encapsulation layer. In this manner, a higher quality dielectric material may be used to form the insulating layer compared to the dielectric material of the encapsulation.

[0026] Aspects of the present disclosure provide numerous technical effects and advantages. For example, directly bonding a power semiconductor die to both the first carrier submount and the second carrier submount provides at least two heat diffusion paths for the power semiconductor die in a power semiconductor package. In addition, the power semiconductor die may be connected to a lead frame of the power semiconductor package, for example, without using any wire bonds. An insulating layer formed on the power semiconductor die (e.g., with an underfill material) may insulate different contacts (e.g., source and drain contacts) of a power semiconductor device on the power semiconductor die prior to bonding the power semiconductor die to the second carrier submount. This may reduce the risk of any electrical shorts between the source and drain contacts due to dielectric material processing during encapsulation.

[0027] Aspects of the present disclosure are discussed in connection with silicon carbide-based semiconductor structures, such as silicon carbide-based MOSFETs. Using the disclosure provided herein, one skilled in the art will understand that power semiconductor packages according to exemplary embodiments of the present disclosure can be used with any semiconductor material, such as other wide bandgap semiconductor materials, without departing from the scope of the present disclosure. Exemplary wide bandgap semiconductor materials include silicon carbide (e.g., alpha silicon carbide has a bandgap of 2.996 eV at room temperature) and Group III nitrides (e.g., gallium nitride has a bandgap of 3.36 eV at room temperature).

[0028] Although terms such as first, second, and third may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as the first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted to have a meaning consistent with their meaning in the context of the present specification and the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0031] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that the element may be directly on or extending directly onto the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, no intervening elements are present, except that in some instances an adhesive material (e.g., die attach material, solder, paste, adhesive, sintered material, or other material) may be present. When an element is referred to as being "connected" or "coupled" to another element, it will be understood that the element may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there will be no intervening elements, except that in some instances an adhesive material (e.g., die attach material, solder, paste, adhesive, sintered material, or other material) may be present.

[0032] Relative terms, such as "below" or "above," or "upper" or "lower," or "horizontal," "lateral," or "vertical," may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as shown in the figures. It will be understood that these terms are intended to encompass various orientations of the device in addition to the orientation shown in the figures.

[0033] Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments of the present disclosure. Layer thicknesses and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the drawings are naturally expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments of the present disclosure should not be construed as limiting the specific shapes of regions shown herein, and may include, for example, variations in shape due to manufacturing. Similarly, it will be understood that variations in dimensions should also be expected based on standard deviations in manufacturing procedures. As used herein, "approximately" or "about" includes values ​​within 10% of the nominal value.

[0034] Like numbers refer to like elements throughout. Thus, identical or similar numbers may be described with reference to other drawings even if they are not mentioned or described in the corresponding drawing. Also, elements not designated with a reference number may be described with reference to other drawings.

[0035] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions characterized as having a conductivity type, e.g., n-type or p-type, which refers to the majority carrier concentration in the layer and / or region. Thus, an N-type material has an equilibrium concentration of a large number of negatively charged electrons, while a P-type material has an equilibrium concentration of a large number of positively charged holes. Some materials may be designated with a "+" or "-" (e.g., N+, N-, P+, P-, N++, N--, P++, P--, etc.) to indicate a relatively high ("+") or relatively low ("-") concentration of majority carriers compared to another layer or region. However, such designations do not imply the presence of a particular concentration of majority or minority carriers in the layer or region.

[0036] In the drawings and specification, exemplary embodiments are disclosed and specific terms are employed, but they are used in a generic and descriptive sense only and not for the purpose of limiting the scope of the following claims.

[0037] FIG. 1 illustrates an exemplary power semiconductor package 100 according to an exemplary embodiment of the present disclosure. FIG. 1 illustrates the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The power semiconductor package 100 includes a first carrier submount 110. The first carrier submount 110 may be an AMB substrate, a DBC substrate, or other suitable substrate. The first carrier submount 110 may include a dielectric and / or ceramic substrate, such as alumina, aluminum nitride, silicon nitride, or other suitable dielectric material. The first carrier submount 110 may have a first side 110A and an opposite second side 110B. The first carrier submount 110 may include one or more thermal and / or electrical conductive pads on the first side 110A. For example, the first carrier submount 110 may include a first conductive pad 112 and a second conductive pad 114 on the first side 110A. The first carrier submount 110 may include a thermal conduction cooling layer 116 (e.g., a copper pad) on the second surface 110B. The first conduction pad 112, the second conduction pad 114, and / or the thermal conduction cooling layer 116 may be copper, silver, gold, titanium, or other conductive materials.

[0038] The power semiconductor package 100 includes a power semiconductor die 120. The power semiconductor die 120 may include one or more power semiconductor devices, such as one or more transistors, diodes, thyristors, or other devices. In some examples, the power semiconductor die 120 may include a silicon carbide-based MOSFET. The power semiconductor die 120 may include a first contact 122 (e.g., a source contact) disposed on a first side 120A of the power semiconductor die 120. The power semiconductor die 120 may include a second contact 124 (e.g., a drain contact) on a second side 120B of the power semiconductor die opposite the first side 120A. In this manner, the power semiconductor die 120 may include a vertical power semiconductor device between the first contact 122 and the second contact 124.

[0039] The power semiconductor die 120 may include additional contacts. For example, the power semiconductor die 120 may include one or more third contacts 126. The third contacts 126 may be on the same side (e.g., first side 120A) of the power semiconductor die 120 as the first contacts 122. The third contacts 126 may include, for example, a gate contact and / or a Kelvin contact.

[0040] The power semiconductor die 120 may be directly bonded to the first carrier submount 110. In some examples, the power semiconductor die 120 is directly bonded to the first carrier submount 110 in a flip-chip configuration. For example, a first surface 120A of the power semiconductor die 120, which includes the first contact 122 (e.g., a source contact) and the third contact 126 (e.g., a gate contact), may be directly bonded to the first carrier submount 110. A second surface 120B of the semiconductor die 120, which includes the second contact 124 (e.g., a drain contact) and is opposite to the first surface 120A, may face away from the first carrier submount 110.

[0041] More specifically, the first contact 122 (e.g., a source contact) may be directly bonded to the first conductive pad 112 of the first carrier submount 110 with or without a die attach material (e.g., solder, paste, sintered material, etc.). The first contact 122 (e.g., a source contact) may be directly bonded to the first conductive pad 112 of the first carrier submount 110 without using a wire bond. The third contact 126 (e.g., a gate contact) may be directly bonded to the second conductive pad 114 of the first carrier submount 110 with or without a die attach material (e.g., solder, paste, sintered material, etc.). The third contact 126 (e.g., a gate contact) may be directly bonded to the second conductive pad 114 of the first carrier submount 110 without using a wire bond.

[0042] The second contact 124 (e.g., a drain contact) may be directly coupled to the second carrier submount 140 with a die-attach material (e.g., solder, paste, sintered material, etc.) or without a die-attach material. The second contact 124 (e.g., a drain contact) may be directly coupled to the second carrier submount 140 without using wire bonds. The second carrier submount 140 may include or be coupled to one or more conductive leads, such as conductive lead 142 and conductive lead 144. The conductive leads 142 and 144 may facilitate connection of the power semiconductor package to external components, such as one or more circuits. The second carrier submount 140 may be, for example, a lead frame (e.g., a copper lead frame) of the power semiconductor package 100. In some embodiments, the second carrier submount 140 may be, for example, a substrate (e.g., a DBC substrate or an AMB substrate) coupled to one or more conductive leads of the power semiconductor package 100.

[0043] One or more conductive pads, such as conductive pad 112 and conductive pad 114, on the first surface 110A of the first carrier submount 110 may also be coupled to the second carrier submount 140 and / or to one or more conductive leads (e.g., conductive lead 142) associated with the second carrier submount 140. In some examples, conductive pad 114 on the first surface 110A of the first carrier submount 110 is coupled to the second carrier submount 140 and / or to one or more conductive leads of the second carrier submount 140 using interconnects 145. Interconnects 145 may, in some embodiments, include an adhesive material (e.g., solder, paste, sintered material, etc.). Conductive pad 112 on the first surface 110A of the first carrier submount 110 may similarly be coupled to the second carrier submount 140 and / or to one or more conductive leads of the second carrier submount 140 using interconnects (not shown). In some embodiments, the first conductive pad 112 may be coupled to a first conductive lead (e.g., conductive lead 142) of the second carrier submount 140. The second conductive pad 114 may be coupled to a second conductive lead of the second carrier submount 140. In this manner, the first contact 122 (e.g., source contact) and the third contact 126 (e.g., gate contact 126) of the power semiconductor die 120 are coupled to the conductive leads of the second carrier submount 140 for connection to external components.

[0044] In some examples, the power semiconductor package 100 may include an insulating layer 130 on the power semiconductor die 120. For example, the insulating layer 130 may be on the first side 120A of the power semiconductor die 120, including the first contact 122 (e.g., a source contact) and the third contact 126 (e.g., a gate contact). In some examples, the insulating layer 130 may extend between the power semiconductor die 120 and the first carrier submount 110 such that the insulating layer 130 fills any gaps between the power semiconductor die 120 and the first carrier submount 110. The insulating layer 130 may not extend onto or be present on the second side 120B of the power semiconductor die 120. In some examples, the insulating layer 130 includes an underfill material. The underfill material may be, for example, a polymer-based material, such as an epoxy polymer material. The underfill material may include fillers or other components, such as a flowing agent, an adhesive, etc.

[0045] The semiconductor package 100 may further include an encapsulant 150. The encapsulant 150 may form a housing for the power semiconductor package 100. The encapsulant 150 may be formed by a molding process such that the encapsulant is at least partially disposed around the first carrier submount 110, the power semiconductor die 120, and the second carrier submount 140. The material of the encapsulant 150 may electrically insulate the components from each other within the power semiconductor package 100. The material of the encapsulant 150 may be a dielectric material. Exemplary materials for the encapsulant 150 may include an epoxy material or an epoxy molding compound (EMC).

[0046] In some examples, the dielectric material of the encapsulation 150 may be the same as the dielectric material of the insulating layer 130. In some examples, the dielectric material of the encapsulation 150 may be different from the dielectric material of the insulating layer 130 on the power semiconductor die 120. For example, the dielectric material of the insulating layer 130 may have a different dielectric constant (e.g., a lower dielectric constant) than the dielectric material of the encapsulation 150. In this manner, a higher quality dielectric material may be used to form the insulating layer 130 compared to the dielectric material of the encapsulation 150.

[0047] 1 , the thermal conduction cooling layer 116 on the first carrier submount 110 is exposed through the encapsulation 150 of the power semiconductor package 100, for example, through an opening 148 in the encapsulation 150. In this manner, the thermal conduction cooling layer 116 may provide a second thermal conduction path for cooling the power semiconductor die 120 in the power semiconductor package 100. More specifically, a first thermal conduction path may be provided through the second carrier submount 140 and one or more conductive leads, for example, conductive lead 142 and conductive lead 144. A second thermal conduction path may be provided through the opening 148 in the encapsulation 150, which leaves at least a portion of the thermal conduction cooling layer 116 exposed through the encapsulation 150. The thermal conduction cooling layer 116 may be coupled to a heat sink and / or may provide a thermal conduction path for the power semiconductor package 100 to the ambient environment.

[0048] 2 illustrates a flowchart of an exemplary method for manufacturing a power semiconductor package according to an exemplary embodiment of the present disclosure, such as the power semiconductor packages shown in FIGS. 1, 11, and 12. FIG. 2 illustrates steps performed in a particular order for purposes of illustration and discussion. Those skilled in the art, using the disclosure provided herein, will understand that the various steps provided in the present disclosure may be omitted, rearranged, expanded, include steps not shown, and / or modified in various ways without departing from the scope of the present disclosure.

[0049] At 202, method 200 may include directly bonding a power semiconductor die to a first carrier submount to form a first assembly. For example, in some examples, a plurality of power semiconductor dies may be singulated from a semiconductor wafer to provide a plurality of individual power semiconductor dies. Each individual power semiconductor die may be, for example, power semiconductor die 120 discussed with reference to FIG. 1 . Each power semiconductor die may include one or more power semiconductor devices, such as transistors, diodes, thyristors, etc. As described above, the power semiconductor die may include a wide bandgap semiconductor. The power semiconductor die may include a vertical power semiconductor device including a first contact disposed on a first surface and a second contact disposed on a second surface opposite the power semiconductor die. As an example, the power semiconductor die may include one or more silicon carbide-based MOSFETs. In some examples, each of the plurality of power semiconductor dies may be directly bonded to a carrier sheet or card including a plurality of first carrier submounts arranged in a grid or array.

[0050] 3 illustrates direct bonding of multiple power semiconductor dies 120 to a carrier sheet including multiple first carrier submounts 110 according to an exemplary embodiment of the present disclosure. As shown, the power semiconductor dies are directly bonded (e.g., with or without an attachment material) to the first carrier submount 110 using a flip-chip structure. In the flip-chip structure, a first side 120A of the power semiconductor die including a first contact 122 (e.g., a source contact) and a third contact 126 (e.g., a gate contact) is "flipped" and directly bonded to conductive pads on the first carrier submount 110. For example, the first contact 122 (e.g., a source contact) is bonded to the first conductive pad 112. The third contact 126 (e.g., a gate contact) is bonded to the second conductive pad 114. No wire bonds are used to bond the power semiconductor dies 120 to the first carrier submount 110. The combination of the power semiconductor die 120 directly coupled to one of the plurality of first carrier submounts 110 may be referred to as a first assembly 160 .

[0051] 4 and 5 show plan views of an exemplary direct bonding between a power semiconductor die 120 and a first carrier submount 110 using a flip-chip structure according to an exemplary embodiment of the present disclosure. FIG. 4 shows a plan view of a first surface 110A of the exemplary first carrier submount 110. The first carrier submount 110 has a patterned arrangement of conductive pads, including a first conductive pad 112 and second conductive pads 114.1 and 114.2. The first conductive pad 112 may be for direct bonding with a source contact of the power semiconductor die 120. The second conductive pad 114.1 may be for direct bonding with a gate contact of the power semiconductor die 120. The second conductive pad 114.2 may be for direct bonding with another contact (e.g., a Kelvin contact) of the power semiconductor die 120.

[0052] 5 shows a plan view of a power semiconductor die 120 directly bonded to a first carrier submount 110. As shown, the power semiconductor die 120 is inverted, such that a first side 120A (not shown), which includes a first contact 122 (e.g., a source contact) and a third contact 126 (e.g., a gate contact), faces downward and is bonded to the first carrier submount 110. A second side 120B of the power semiconductor die 120, which includes a second contact (e.g., a drain contact), faces upward, pointing away from the first carrier submount 110.

[0053] 4 and 5 show, for purposes of illustration and discussion, one exemplary pattern of conductive pads for first carrier submount 110. Those skilled in the art, using the disclosure provided herein, will understand that first carrier submount 110 can have a variety of different conductive pad patterns or arrangements without departing from the scope of the present disclosure.

[0054] Referring to 204 of FIG. 2 , the method 200 may include forming an insulating layer on the power semiconductor die of the first assembly. For example, as shown in FIG. 6 , the insulating layer 130 may be formed on the first assembly 160. More specifically, the insulating layer 130 may be formed on the power semiconductor die 120 to cover at least a portion of the first contact 122 (e.g., a source contact) and the third contact 126 (e.g., a gate contact). The insulating layer 130 may fill any gaps between the power semiconductor die 120 and the first carrier submount 110. The insulating layer 130 may be present only on one side of the power semiconductor die 120, such as the first side 120A of the power semiconductor die 120 that is directly bonded to the first carrier submount 110. In some examples, the insulating layer 130 includes an underfill material. The underfill material may be, for example, a polymer-based material, such as an epoxy polymer material. The underfill material may include fillers or other components such as flow agents, adhesives, and the like.

[0055] Referring to 206 in FIG. 2, method 200 may include performing singulation of the first assemblies. For example, as shown in FIG. 7, a cutting tool 165 may be used to separate the first assemblies 160 from one another in the carrier sheet. FIG. 8 shows exemplary individual first assemblies 160 after singulation. Each individual first assembly 160 includes a power semiconductor die 120 directly bonded to a first carrier submount 110, for example, in a flip-chip configuration, with an insulating layer 130 on the power semiconductor die 120.

[0056] Referring to 208 of FIG. 2, method 200 may include directly coupling the first assembly to a second carrier submount. For example, as shown in FIG. 9, first assembly 160 is “flipped” and directly coupled to second carrier submount 140, which includes one or more conductive leads, such as conductive lead 142 and conductive lead 144. Second carrier submount 140 may, in some examples, be a lead frame for a power semiconductor package. As shown in FIG. 9, second contact 124 (e.g., drain contact) of power semiconductor die 120 may be directly coupled to the second carrier submount without using wire bonds (e.g., with or without an adhesive material). In addition, one or more conductive pads on first carrier submount 110 are also coupled to second carrier submount 140. 4 and 5, conductive pad 114.1 may be coupled to the second carrier submount 140 and / or to one or more conductive leads (e.g., conductive lead 142) of the second carrier submount 140 via an interconnect (e.g., interconnect 145, such as an adhesive material). Conductive pad 114.2 may be coupled to the second carrier submount 140 and / or to one or more conductive leads of the second carrier submount 140 via an interconnect (e.g., an adhesive material). Conductive pad 112 may be coupled to the second carrier submount 140 and / or to one or more conductive leads of the second carrier submount 140 via an interconnect (e.g., an adhesive material). In this manner, the power semiconductor die 120 is directly bonded to two different carrier submounts without wire bonds to establish connections with the conductive leads of the power semiconductor package.

[0057] Referring to 210 of FIG. 2 , method 200 may include encapsulating at least a portion of the first carrier submount, the second carrier submount, and the power semiconductor die to form an encapsulation. For example, as shown in FIG. 10 , an encapsulation 150 may be formed at least partially over the first carrier submount 110, the power semiconductor die 120, the insulating layer 130, and the second carrier submount 140. The encapsulation 150 may form a housing for the power semiconductor package 100. The encapsulation 150 may be formed by a molding process such that the encapsulation is at least partially disposed around the first carrier submount 110, the semiconductor die 120, and the second carrier submount 140. The material of the encapsulation 150 may electrically insulate the components within the encapsulation 150 from one another. The material of the encapsulation 150 may be a dielectric material. Exemplary materials for the encapsulation 150 may include an epoxy material or an epoxy molding compound (EMC).

[0058] In some examples, the dielectric material of the encapsulation 150 may be the same as the dielectric material of the insulating layer 130. In some examples, the dielectric material of the encapsulation 150 may be different from the dielectric material of the insulating layer 130 on the power semiconductor die 120. For example, the dielectric material of the insulating layer 130 may have a different dielectric constant (e.g., a lower dielectric constant) than the dielectric material of the encapsulation 150. In this manner, a higher quality dielectric material may be used to form the insulating layer 130 compared to the dielectric material of the encapsulation 150.

[0059] Variations and modifications may be made to the exemplary power semiconductor packages described herein without departing from the scope of the present disclosure. For example, FIG. 11 illustrates a power semiconductor package 300 similar to the power semiconductor package 100 of FIG. 1. FIG. 11 is intended to illustrate the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. For example, the power semiconductor package 300 includes a first carrier submount 110. The first carrier submount 110 includes one or more conductive pads (e.g., conductive pads 112 and 114) and a thermally conductive cooling layer 116. The power semiconductor package 300 includes a second carrier submount 140. The second carrier submount 140 includes one or more conductive leads (e.g., conductive lead 142 and conductive lead 144) for the power semiconductor package 300. The power semiconductor package 300 includes a power semiconductor die 120 having a first side 120A and an opposite second side 120B. A first surface 120A of the power semiconductor die 120 is directly bonded (e.g., in a flip-chip configuration) to the first carrier submount 110. A second surface 120B of the power semiconductor die 120 is directly bonded to the second carrier submount 140.

[0060] In the power semiconductor package 300, the first carrier submount 110 includes a thermal conduction cooling layer 116 on a second surface 110B opposite the first surface 110A having one or more conductive pads (e.g., conductive pads 112 and 114) of the first carrier submount 110. In the example of Figure 11, the thermal conduction cooling layer 116 is covered by the encapsulant 150 instead of being exposed through an opening in the encapsulant 150.

[0061] FIG. 12 illustrates a power semiconductor package 400 similar to the power semiconductor package 100 of FIG. 1 and the power semiconductor package 300 of FIG. 11. FIG. 12 is intended to illustrate the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The power semiconductor package 400 includes a first carrier submount 110. The first carrier submount 110 includes one or more conductive pads (e.g., conductive pads 112 and 114) and a thermally conductive cooling layer 116. The power semiconductor package 400 includes a second carrier submount 140. The second carrier submount 140 includes one or more conductive leads (e.g., conductive lead 142 and conductive lead 144) for the power semiconductor package 400. The power semiconductor package 400 includes a power semiconductor die 120 having a first side 120A and an opposite second side 120B. A first surface 120A of the power semiconductor die 120 is directly bonded (e.g., in a flip-chip configuration) to the first carrier submount 110. A second surface 120B of the power semiconductor die 120 is directly bonded to the second carrier submount 140. The power semiconductor package 400 does not include a separate insulating layer 130 on the power semiconductor die 120. Rather, the encapsulant 150 of the power semiconductor package 400 surrounds the power semiconductor die 120.

[0062] FIG. 13 illustrates a power semiconductor package 500 similar to the power semiconductor package 100 of FIG. 1. FIG. 13 is intended to illustrate the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. For example, the power semiconductor package 500 includes a first carrier submount 110. The first carrier submount 110 includes one or more conductive pads (e.g., conductive pad 112) and a thermally conductive cooling layer 116. The power semiconductor package 500 includes a second carrier submount 140. The second carrier submount 140 includes one or more conductive leads (e.g., conductive lead 142 and conductive lead 144) for the power semiconductor package 500. The power semiconductor package 500 includes a power semiconductor die 120. In the example of FIG. 13, the power semiconductor die 120 may include one or more Schottky diodes, such as one or more silicon carbide-based Schottky diodes. The power semiconductor die 120 has a first side 120A and an opposite second side 120B. The first surface 120A of the power semiconductor die 120 is directly coupled to the first carrier submount 110 (e.g., in a flip-chip configuration) such that the first contact 122 (e.g., an anode contact) is directly coupled to the first carrier submount 110. The second surface 120B of the power semiconductor die 120 is directly coupled to the second carrier submount 140 such that the second contact 124 (e.g., a cathode contact) is directly coupled to the second carrier submount 140. The power semiconductor package 500 includes an encapsulant 150. The thermally conductive cooling layer 116 is exposed through an opening 148 in the encapsulant 150.

[0063] FIG. 14 illustrates a power semiconductor package 600 similar to the power semiconductor package 500 of FIG. 13. FIG. 14 illustrates the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. For example, the power semiconductor package 600 includes a first carrier submount 110. The first carrier submount 110 includes one or more conductive pads (e.g., conductive pad 112) and a thermally conductive cooling layer 116. The power semiconductor package 600 includes a second carrier submount 140. The second carrier submount 140 includes one or more conductive leads (e.g., conductive lead 142 and conductive lead 144) for the power semiconductor package 600. The power semiconductor package 600 includes a power semiconductor die 120. In the example of FIG. 14, the power semiconductor die 120 may include one or more Schottky diodes, such as one or more silicon carbide-based Schottky diodes. The power semiconductor die 120 has a first side 120A and an opposite second side 120B. The first surface 120A of the power semiconductor die 120 is directly bonded to the first carrier submount 110 (e.g., in a flip-chip configuration) such that the first contact 122 (e.g., an anode contact) is directly bonded to the first carrier submount 110. The second surface 120B of the power semiconductor die 120 is directly bonded to the second carrier submount 140 such that the second contact 124 (e.g., a cathode contact) is directly bonded to the second carrier submount 140. The power semiconductor package 600 includes an encapsulant 150. The thermal cooling layer 116 is covered by the encapsulant 150.

[0064] Figures 15-17 illustrate an exemplary power semiconductor package 700 according to an exemplary embodiment of the present disclosure. Figure 15 illustrates a top view of the power semiconductor package 700, and Figures 16-17 illustrate cross-sectional views of the power semiconductor package 700 taken along line AA' shown in Figure 15. Figures 15-17 are intended to illustrate structures for identification and explanation purposes and are not intended to illustrate the structures to physical scale.

[0065] The power semiconductor package 700 includes a first carrier submount 710. The first carrier submount 710 may be an active metal bond (AMB) substrate, a direct bond copper (DBC) substrate, or other suitable substrate. The first carrier submount 710 may include a dielectric and / or ceramic substrate, such as alumina, aluminum nitride, silicon nitride, or other suitable dielectric material.

[0066] The first carrier submount 710 may include an insulating layer 705 having a first surface 705A and an opposite second surface 705B. The first carrier submount 710 may include one or more thermally and / or electrically conductive patterns, such as conductive patterns 712 and 714, on the first surface 705A of the insulating layer 705. In this manner, the conductive patterns 712 and 714 may be disposed on the same layer of the first carrier submount 710. However, as discussed in more detail below (e.g., FIGS. 19-23), the conductive patterns 712 and 714 may be disposed on different layers of the first carrier submount 710 without departing from the scope of the present disclosure. The one or more conductive patterns, such as conductive patterns 712 and 714, may be copper, silver, gold, titanium, or other suitable conductive materials. The first carrier submount 710 may include a thermally conductive cooling layer 716 (e.g., a copper pad) on the second surface 705B of the insulating layer 705. Thermally conductive cooling layer 716 may be copper, silver, gold, titanium, or other suitable conductive material.

[0067] Power semiconductor package 700 includes multiple semiconductor dies 720. As shown, in some embodiments, each of the multiple semiconductor dies 720 may be arranged in a parallel configuration within power semiconductor package 700. In other embodiments, however, each of the multiple semiconductor dies 720 may be arranged in a serial configuration within power semiconductor package 700 without departing from the scope of the present disclosure. As used herein, "multiple" should be understood to mean "at least two" and / or "two or more."

[0068] The semiconductor die 720 may include one or more power semiconductor devices, such as one or more transistors, diodes, thyristors, or other devices. In some embodiments, the plurality of semiconductor dies 720 may be a plurality of wide bandgap semiconductor dies 720. For example, the plurality of wide bandgap semiconductor dies 720 may include silicon carbide. More specifically, each of the plurality of wide bandgap semiconductor dies 720 may include a silicon carbide-based MOSFET. Additionally and / or alternatively, each of the plurality of wide bandgap semiconductor dies 720 may include a silicon carbide-based Schottky diode. Furthermore, the silicon carbide-based MOSFETs of the plurality of semiconductor dies and / or the silicon carbide-based Schottky diodes of the plurality of semiconductor dies may be arranged in parallel and / or series. As discussed in more detail below, the power semiconductor package 700 may not have any wire bonds to any of the plurality of semiconductor dies 720.

[0069] It should be noted that power semiconductor package 700 is shown in Figures 15-17 with two semiconductor dies 720 for purposes of illustration and discussion. For example, in some examples, the number of semiconductor dies included in plurality of semiconductor dies 720 may range from, for example, two semiconductor dies to nine semiconductor dies. However, one skilled in the art, using the disclosure provided herein, will understand that any suitable number of semiconductor dies 720 may be used without departing from the scope of the present disclosure.

[0070] Each semiconductor die 720 of the plurality of semiconductor dies 720 may include a first contact 722 (e.g., a source contact) disposed on a first side 720A of the semiconductor die 720. Each semiconductor die 720 of the plurality of semiconductor dies 720 may include a second contact 724 (e.g., a drain contact) disposed on a second side 720B of the semiconductor die 720 opposite the first side 720A. In this manner, each semiconductor die 720 may include a vertical semiconductor device between its respective first contact 722 and second contact 724.

[0071] Each semiconductor die 720 of the multiple semiconductor dies 720 may include additional contacts. For example, each semiconductor die 720 may include one or more third contacts 726. The third contacts 726 may be on the same side (e.g., first side 720A) as the first contacts 722 of the respective semiconductor die 720. The third contacts 726 may include, for example, a gate contact and / or a Kelvin contact.

[0072] The power semiconductor package 700 may further include a second carrier submount 730. The second carrier submount 730 may include or be coupled to one or more conductive leads, such as conductive lead 732. The conductive leads may facilitate connection of the power semiconductor package 700 to external components, such as one or more circuits. The second carrier submount 730 may be, for example, a lead frame (e.g., a copper lead frame) of the power semiconductor package 700. In some embodiments, the second carrier submount 730 may be, for example, a substrate (e.g., a DBC substrate or an AMB substrate) coupled to the one or more conductive leads 732 of the power semiconductor package 700.

[0073] Each semiconductor die 720 may be directly bonded to the first carrier submount 710. In some examples, each semiconductor die 720 may be directly bonded to the first carrier submount 710 in a flip-chip configuration. For example, for each semiconductor die 720, a first surface 720A (e.g., the surface including the first contact 722 and the third contact 726) may be directly bonded to the first carrier submount 710, and a second surface 720B opposite the first surface 720A (e.g., the surface including the second contact 724) may face away from the first carrier submount 710. In some embodiments, the second surface 720B of each of the multiple semiconductor dies 720 may be directly bonded to the second carrier submount 730.

[0074] More specifically, for each semiconductor die 720, the first contact 722 (e.g., source contact) may be directly coupled to at least one of the one or more conductive patterns, such as conductive pattern 712, of the first carrier submount 710 with or without a die-attach material (e.g., solder, paste, sintered material, etc.). Furthermore, for each semiconductor die 720, the first contact 722 (e.g., source contact) may be directly coupled to at least one of the one or more conductive patterns, such as conductive pattern 712, of the first carrier submount 710 without using wire bonds. Additionally, as shown in FIGS. 15-17 , each first contact 722 of each semiconductor die 720 may be coupled to the same conductive pattern (e.g., conductive pattern 712). Alternatively, as discussed in more detail below, each first contact 722 of each semiconductor die 720 may be coupled to a different conductive pattern of the one or more conductive patterns of the first carrier submount 710.

[0075] For each semiconductor die 720, the third contact 726 (e.g., a gate contact) may be directly coupled to at least one of the one or more conductive patterns, such as the conductive pattern 714, of the first carrier submount 710 with or without a die-attach material (e.g., solder, paste, sintered material, etc.). Furthermore, for each semiconductor die 720, the third contact 726 (e.g., a gate contact) may be directly coupled to at least one of the one or more conductive patterns, such as the conductive pattern 714, of the first carrier submount 710 without using wire bonds. In this manner, for each semiconductor die 720, the first contact 722 (e.g., a source contact) and the third contact 726 (e.g., a gate contact) may be coupled to different conductive patterns (e.g., the conductive pattern 712 and the conductive pattern 714, respectively) of the one or more conductive patterns. In the example of FIG. 15 , the conductive pattern 712 and the conductive pattern 714 are on the same conductive layer of the first carrier submount 710. As discussed with reference to FIGS. 19-23, the conductive pattern 712 associated with forming the source connection and the conductive pattern 714 associated with forming the gate connection may be on different layers of the first carrier submount 710.

[0076] For each semiconductor die 720, the second contact 724 (e.g., drain contact) may be directly coupled to the second carrier submount 730 with or without a die-attach material (e.g., solder, paste, sintered material, etc.). Furthermore, for each semiconductor die 720, the second contact 724 (e.g., drain contact) may be directly coupled to the second carrier submount 730 with or without a wire bond. Additionally, as shown in FIGS. 15-17 , each second contact 724 of each semiconductor die 720 may be coupled to the same conductive lead (e.g., conductive lead 732). Alternatively, as discussed in more detail below, each second contact 724 of each semiconductor die 720 may be coupled to a different conductive lead of one or more conductive leads of the second carrier submount 730.

[0077] The power semiconductor package 700 may include an insulating layer (not shown) on the plurality of semiconductor dies 720. More specifically, the power semiconductor package 700 may include an insulating layer on the plurality of semiconductor dies 720 similar to the insulating layer 130 discussed above with reference to FIG. 1 . For example, the insulating layer may be on a first surface 720A of each of the plurality of semiconductor dies 720, the first surface 720A including a first contact 722 (e.g., a source contact) and a third contact (e.g., a gate contact). Additionally, the insulating layer may extend between the plurality of semiconductor dies 720 and the first carrier submount 710 such that the insulating layer fills any gaps between the plurality of semiconductor dies 720 and the first carrier submount 710. The insulating layer may not extend to or be on a second surface 720B of each of the plurality of semiconductor dies 720. In some embodiments, the insulating layer includes an underfill material. The underfill material may be, for example, a polymer-based material, such as an epoxy polymer material. The underfill material may include fillers or other components such as flow agents, adhesives, and the like.

[0078] The power semiconductor package 700 may further include an encapsulant 750. The encapsulant 750 may form a housing for the power semiconductor package 700. The encapsulant 750 may be formed by a molding process such that the encapsulant is at least partially disposed around the first carrier submount 710, the plurality of semiconductor dies 720, and the second carrier submount 730. The material of the encapsulant 750 may electrically insulate the components from each other within the power semiconductor package 700. The material of the encapsulant 750 may be a dielectric material. Exemplary materials for the encapsulant 750 may include an epoxy material or an epoxy molding compound (EMC).

[0079] In some examples, the dielectric material of the encapsulation portion 750 may be the same as the dielectric material of the insulating layer. In some examples, the dielectric material of the encapsulation portion 750 may be different from the dielectric material of the insulating layer on the plurality of semiconductor dies 720. For example, the dielectric material of the insulating layer may have a different dielectric constant (e.g., a lower dielectric constant) than the dielectric material of the encapsulation portion 750. In this manner, a higher quality dielectric material may be used to form the insulating layer compared to the dielectric material of the encapsulation portion 750.

[0080] 16 , the thermal conduction cooling layer 716 of the first carrier submount 710 may be exposed through the encapsulation 750. More specifically, the thermal conduction cooling layer 716 may be exposed through an opening 752 in the encapsulation 750. In this manner, the thermal conduction cooling layer 716 may provide a second thermal conduction path for cooling the multiple semiconductor dies 720 in the power semiconductor package 700. More specifically, a first thermal conduction path may be provided through the second carrier submount 730 and one or more conductive leads, such as the conductive lead 732. A second thermal conduction path may be provided through the opening 752 in the encapsulation 750. The thermal conduction cooling layer 716 may be coupled to a heat sink and / or provide a thermal conduction path for the power semiconductor package 700 to the ambient environment.

[0081] 17, the thermal conduction cooling layer 716 of the first carrier submount 710 may be covered by the encapsulation 150, rather than being exposed through an opening (e.g., opening 752) in the encapsulation 150, as shown in FIG. 16. In this manner, a first thermal conduction path may be provided through the second carrier submount 730 and one or more conductive leads, such as conductive lead 732.

[0082] 15-17 , as described above, each first contact 722 (e.g., source contact) of each semiconductor die 720 may be coupled to the same conductive pattern (e.g., conductive pattern 712) of the first carrier submount 710, and each second contact 724 (e.g., drain contact) of each semiconductor die 720 may be coupled to the same conductive lead (e.g., conductive lead 732) of the second carrier submount 730. In this manner, each semiconductor die 720 of the multiple semiconductor dies 720 may be coupled to a common source terminal 760 (via its respective first contact 722) and a common drain terminal 770 (via its respective second contact 724). Similarly, each semiconductor die 720 may be coupled to a common gate terminal 780 and / or a common Kelvin terminal 790 via its respective third contact 726.

[0083] FIG. 18 illustrates a power semiconductor package 800 similar to the power semiconductor package 700 discussed above with reference to FIGS. 15-17. FIG. 18 is intended to illustrate the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The power semiconductor package 800 includes a first carrier submount 710. The first carrier submount 710 includes one or more conductive patterns (e.g., conductive pattern 712) and a thermally conductive cooling layer 716. The power semiconductor package 800 includes a second carrier submount 730. The second carrier submount 730 includes one or more conductive leads (e.g., conductive lead 732) for the power semiconductor package 800.

[0084] The power semiconductor package 800 includes a plurality of semiconductor dies 720. Each semiconductor die 720 has a first side 720A and an opposite second side 720B. The first side 720A of each of the semiconductor dies 720 is directly coupled to a first carrier submount 710 (e.g., in a flip-chip configuration) such that a first contact 722 (e.g., a source contact) and a third contact 726 (e.g., a gate contact) are directly coupled to the first carrier submount 710. The second side 720B of each of the semiconductor dies 720 is directly coupled to a second carrier submount 730 such that a second contact 724 (e.g., a drain contact) is directly coupled to the second carrier submount 730. In this manner, each of the semiconductor dies 720 of the plurality of semiconductor dies 720 may be coupled to a common source terminal 760 (via a respective first contact 722), a common drain terminal 770 (via a respective second contact 724), and a common gate terminal 780.

[0085] 18 are arranged in a side-by-side configuration for purposes of illustration and discussion. Power semiconductor package 800 may include more than two and / or fewer than two semiconductor dies 720 arranged in a side-by-side and / or series configuration without departing from the scope of this disclosure.

[0086] Power semiconductor package 800 includes an encapsulant 750. In some embodiments, thermal conduction cooling layer 716 is exposed through an opening 752 in the encapsulant. Additionally and / or alternatively, in some embodiments, thermal conduction cooling layer 716 may be covered by encapsulant 750.

[0087] 18 , the conductive patterns 714 are arranged in the power semiconductor package 800 so that the gate signal wiring lengths L for each of the semiconductor dies 720 are substantially the same. More specifically, as shown in FIG. 18 , the gate signal wiring lengths L between the gate terminals 780 and each of the semiconductor dies 720 are the same. By matching the gate signal wiring lengths L for each of the semiconductor dies 720, various electrical characteristics (e.g., resistance, inductance) along the gate signal wiring paths to each of the semiconductor dies 720 are similarly matched, which ultimately results in improved current balance among the multiple semiconductor dies 720.

[0088] For example, in some embodiments, each semiconductor die 720 may include a wide bandgap semiconductor device, such as a silicon carbide-based MOSFET, etc. In such embodiments, matching the gate signal wiring length L between the gate terminal 780 and each MOSFET improves current balancing among the MOSFETs during switching transitions (e.g., turn-on, turn-off).

[0089] FIGS. 19-23 illustrate an exemplary power semiconductor package 900 according to an exemplary embodiment of the present disclosure. FIGS. 19-23 are intended to illustrate structures for identification and explanation purposes and are not intended to depict the structures to physical scale. FIG. 19 illustrates a top view of the power semiconductor package 900, and FIGS. 20-21 illustrate cross-sectional perspective views of the power semiconductor package 900 taken along line AA′ shown in FIG. 19. The power semiconductor package 900 is similar to the power semiconductor package 700 of FIGS. 15-17. However, the power semiconductor package 900 includes one or more different conductive patterns on different layers of the first carrier submount 710. FIGS. 22-23 illustrate top views of the opposite side of the first carrier submount 710. More specifically, FIG. 22 illustrates a top view of the first side 705A of the insulating layer 705, and FIG. 23 illustrates a top view of the second side 705B of the insulating layer 705.

[0090] As mentioned above, power semiconductor package 900 is similar to power semiconductor package 700 discussed above. For example, power semiconductor package 900 includes a first carrier submount 710. First carrier submount 710 includes one or more conductive patterns (e.g., conductive pattern 712 and conductive pattern 714) disposed on opposite sides of insulating layer 705. Power semiconductor package 900 includes a second carrier submount 730 (e.g., a lead frame). Second carrier submount 730 includes one or more conductive leads (e.g., conductive lead 732) for power semiconductor package 900.

[0091] 21 , the power semiconductor package 900 may include a thermal conduction cooling layer 716. More specifically, in the example of FIG. 21 , the power semiconductor package 900 includes a second insulating layer 902 disposed between the conductive pattern 714 and the thermal conduction cooling layer 716. The power semiconductor package 900 further includes a third conductive layer (e.g., the thermal conduction cooling layer 716) on the second insulating layer 902. Furthermore, as discussed above, the thermal conduction cooling layer 716 may be exposed through the encapsulation portion 750 (e.g., through the opening 752).

[0092] The power semiconductor package 900 includes multiple semiconductor dies 720. Like the previously discussed power semiconductor packages 700 (e.g., FIGS. 15-17), the power semiconductor package 900 does not have any wire bonds to the multiple semiconductor dies 720. Furthermore, each semiconductor die 720 has a first side 720A and an opposite second side 720B. The first side 720A of each of the semiconductor dies 720 is directly coupled to a first carrier submount 710 (e.g., in a flip-chip configuration) such that a first contact 722 (e.g., a source contact) and a third contact 726 (e.g., a gate contact) are directly coupled to the first carrier submount 710. The second side 720B of each of the semiconductor dies 720 is directly coupled to a second carrier submount 730 such that a second contact 724 (e.g., a drain contact) is directly coupled to the second carrier submount 730. In this manner, each semiconductor die 720 of the plurality of semiconductor dies 720 may be coupled to a common source terminal 760 (via a respective first contact 722), a common drain terminal 770 (via a respective second contact 724), and a common gate terminal 780.

[0093] 19-23 are arranged in a parallel configuration for purposes of illustration and discussion. Power semiconductor package 900 may include more than four and / or fewer than four semiconductor dies 720 arranged in a parallel and / or serial configuration without departing from the scope of this disclosure.

[0094] The power semiconductor package 900 includes an encapsulant 750. In some embodiments (e.g., FIG. 20), the thermal conduction cooling layer 716 is exposed through an opening 752 in the encapsulant. Additionally and / or alternatively, in some embodiments (e.g., FIG. 21), the thermal conduction cooling layer 716 may be covered by the encapsulant 750.

[0095] As described above, the first carrier submount 710 of the power semiconductor package 900 may include one or more conductive patterns (e.g., conductive pattern 712, conductive pattern 714) on different layers of the first carrier submount 710. More specifically, the first carrier submount 710 may include a first conductive layer (e.g., conductive pattern 712), a second conductive layer (e.g., conductive pattern 714), and an insulating layer (e.g., insulating layer 705) between the first and second conductive layers. As shown, the first conductive layer (e.g., conductive pattern 712) may be directly coupled to first contacts 722 (e.g., source contacts) of each semiconductor die 720 of the multiple semiconductor dies 720. The first conductive layer (e.g., conductive pattern 712) may also be coupled to the second carrier submount 730. Similarly, the second conductive layer (e.g., conductive pattern 714) may be coupled to a third contact 726 (e.g., a gate contact) of each semiconductor die 720 of the plurality of semiconductor dies 720 through one or more electrically conductive vias. As discussed in more detail below, the first conductive layer (e.g., conductive pattern 712) and the second conductive layer (e.g., conductive pattern 714) may comprise different conductive patterns. For example, the first conductive layer (e.g., conductive pattern 712) may include a source pattern, and the second conductive layer (e.g., conductive pattern 714) may include a gate pattern.

[0096] FIG. 22 shows a top view of a first conductive layer of a first carrier submount 710. The first conductive layer may include one or more thermally and / or electrically conductive patterns, such as a conductive pattern 712 (e.g., a source pattern). The first conductive layer may be copper, silver, gold, titanium, or another suitable conductive material. Furthermore, as described above, the first conductive layer may be directly coupled to the first contacts 722 (e.g., source contacts) of each of the multiple semiconductor dies 720. In this manner, the first conductive layer of the first carrier submount 710 enables each semiconductor die 720 of the power semiconductor package 900 to be coupled to a common source terminal 760. The first conductive layer may further include a plurality of holes 912. As discussed in more detail below, each of the multiple holes 912 may coincide (e.g., align) with a via 922 of a second conductive layer (e.g., a conductive pattern 714).

[0097] FIG. 23 shows a top view of the second conductive layer of the first carrier submount 710. The second conductive layer may include one or more thermal and / or electrical conductive patterns, such as conductive pattern 714 (e.g., gate pattern). As such, the second conductive layer may include a conductive pattern (e.g., conductive pattern 714) that is different from the first conductive layer (e.g., conductive pattern 712). The second conductive layer may be copper, silver, gold, titanium, or another suitable conductive material. The second conductive layer may include a plurality of vias 922. The plurality of vias 922 may extend through the insulating layer 705 separating the first and second conductive layers. Each via 922 of the plurality of vias 922 may coincide (e.g., align) with one of the plurality of holes 912 in the first conductive layer (e.g., conductive pattern 712) to electrically isolate the first conductive layer (e.g., conductive pattern 712) from the second conductive layer (e.g., conductive pattern 714). Additionally, the second conductive layer (e.g., conductive layer 714) may be coupled to a third contact 726 (e.g., a gate contact) of each of the plurality of semiconductor dies 720 through a respective via 922 of the plurality of vias 922. In this manner, the plurality of vias 922 of the first carrier submount 710 allows each semiconductor die 720 of the power semiconductor package 900 to be coupled to a common gate terminal 780.

[0098] FIG. 24 shows a power semiconductor package 1000 similar to the power semiconductor package 700 of FIGS. 15-17. FIG. 24 is intended to illustrate the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The power semiconductor package 1000 includes a first carrier submount 710. The first carrier submount 710 includes one or more conductive patterns (e.g., conductive pattern 712) and a thermally conductive cooling layer 716. The power semiconductor package 1000 includes a second carrier submount 730. The second carrier submount 730 includes one or more conductive leads (e.g., conductive lead 732) for the power semiconductor package 1000. The power semiconductor package 1000 includes multiple semiconductor dies 720.

[0099] 24 , the multiple semiconductor dies 720 may include multiple Schottky diodes, such as one or more silicon carbide-based Schottky diodes. Each semiconductor die 720 has a first side 720A and an opposite second side 720B. The first side 720A of each of the semiconductor dies 720 is directly coupled to a first carrier submount 710 (e.g., in a flip-chip configuration) such that a first contact 722 (e.g., an anode contact) is directly coupled to the first carrier submount 710. The second side 720B of each of the semiconductor dies 720 is directly coupled to a second carrier submount 730 such that a second contact 724 (e.g., a cathode contact) is directly coupled to the second carrier submount 730. In this manner, each semiconductor die 720 of the plurality of semiconductor dies 720 may be coupled to a common anode terminal 1010 (via a respective first contact 722) and to a common cathode terminal 1020 (via a respective second contact 724).

[0100] The power semiconductor package 1000 includes an encapsulant 750. In some embodiments, the thermal conduction cooling layer 716 is exposed through an opening 752 in the encapsulant. Additionally and / or alternatively, in some embodiments, the thermal conduction cooling layer 716 may be covered by the encapsulant 750.

[0101] 24 are arranged in a parallel configuration for purposes of illustration and discussion. Power semiconductor package 1000 may include more than nine semiconductor dies 720 and / or fewer than nine semiconductor dies 720 arranged in a parallel configuration and / or a series configuration without departing from the scope of this disclosure.

[0102] 25-28 illustrate an exemplary power semiconductor package 1100 according to an exemplary embodiment of the present disclosure. FIGS. 25-28 are intended to illustrate structures for identification and explanation purposes and are not intended to depict the structures to physical scale. FIG. 25 illustrates a top view of the power semiconductor package 1100, and FIG. 26 illustrates a cross-sectional perspective view of the power semiconductor package 1100 taken along line AA′ shown in FIG. 25. The power semiconductor package 1100 is similar to the power semiconductor package 700 of FIGS. 15-17 and the power semiconductor package 900 of FIGS. 19-23. However, in contrast to the power semiconductor package 700 and the power semiconductor package 900, the power semiconductor package 1100 includes two semiconductor dies (e.g., semiconductor die 1120 and semiconductor die 1130) with individual (e.g., separate) source, drain, gate, and Kelvin terminals. FIG. 27 shows a first lead frame 1140 and a second lead frame 1150 of the power semiconductor package 1100, and FIG. 28 shows a carrier submount 1110 of the power semiconductor package 1100.

[0103] As shown, the power semiconductor package 1100 includes a carrier submount 1110. The carrier submount 1110 may be an active metal bond (AMB) substrate, a direct bond copper (DBC) substrate, or other suitable substrate. The carrier submount 1110 may include a dielectric and / or ceramic substrate, such as alumina, aluminum nitride, silicon nitride, or other suitable dielectric material.

[0104] The carrier submount 1110 may have a first surface 1110A and an opposite second surface 1110B. The carrier submount 1110 may include one or more thermally and / or electrically conductive patterns on the first surface 1110A, such as conductive pattern 1111, conductive pattern 1112, conductive pattern 1113, and conductive pattern 1114. The one or more conductive patterns (e.g., conductive patterns 1111, 1112, 1113, and 1114) may be made of copper, silver, gold, titanium, or other suitable conductive materials. The carrier submount 1110 may include a thermally conductive cooling layer 1116 (e.g., a copper pattern) on the second surface 1110B. The thermally conductive cooling layer 1116 may be made of copper, silver, gold, titanium, or other suitable conductive materials. Additionally, although the power semiconductor package 1100 is shown in Figures 25-28 as having one or more conductive patterns on the same layer of the carrier submount 1110, the power semiconductor package 1100 may have one or more conductive patterns on different layers of the carrier submount 1110 (e.g., similar to that described above with reference to Figures 19-23) without departing from the scope of the present disclosure.

[0105] The power semiconductor package 1100 includes multiple semiconductor dies, such as a first semiconductor die 1120 and a second semiconductor die 1130. As discussed in more detail below, the power semiconductor package 1100 does not have any wire bonds to the first semiconductor die 1120. Similarly, the power semiconductor package 1100 does not have any wire bonds to the second semiconductor die 1130. In some embodiments, the first semiconductor die 1120 and the second semiconductor die 1130 may be directly bonded to the carrier submount 1110, for example, in a flip-chip configuration. Further, as shown, in some embodiments, the multiple semiconductor dies (e.g., semiconductor die 1120, semiconductor die 1130) may be arranged in a half-bridge configuration. However, one of ordinary skill in the art, using the disclosure provided herein, will recognize that the multiple semiconductor dies (e.g., semiconductor die 1120, semiconductor die 1130) may be arranged in any suitable configuration without departing from the scope of the present disclosure.

[0106] The first semiconductor die 1120 and the second semiconductor die 1130 may each include one or more semiconductor devices, such as one or more transistors, diodes, thyristors, or other devices. In some embodiments, the first semiconductor die 1120 and the second semiconductor die 1130 may each be a wide bandgap semiconductor die. For example, the first semiconductor die 1120 and the second semiconductor die 1130 may include silicon carbide. More specifically, the first semiconductor die 1120 and the second semiconductor die 1130 may each include a silicon carbide-based MOSFET. Additionally and / or alternatively, the first semiconductor die 1120 and the second semiconductor die 1130 may each include a silicon carbide-based Schottky diode.

[0107] The power semiconductor package 1100 further includes a plurality of lead frames (e.g., copper lead frames), such as a first lead frame 1140 and a second lead frame 1150. Each of the plurality of lead frames (e.g., the first lead frame 1140, the second lead frame 1150) includes one or more conductive leads configured to facilitate connection of the power semiconductor package 1100 to external components, such as one or more circuits. For example, as shown in FIG. 26 , the first lead frame 1140 may include a conductive lead 1142, and the second lead frame 1150 may include a conductive lead 1152.

[0108] The first semiconductor die 1120 may have a first side 1120A and an opposite second side 1120B. The first side 1120A may be directly bonded to the carrier submount 1110, and the second side 1120B may be directly bonded to the first lead frame 1140. Additionally, the first semiconductor die 1120 may include a source contact 1122 and a gate contact 1124 on the first side 1120A. The first semiconductor die 1120 may further include a drain contact 1126 on the second side 1120B of the first semiconductor die 1120. More specifically, the source contact 1122 may be bonded to at least one of one or more conductive patterns of the carrier submount 1110, such as the conductive pattern 1112, without the use of wire bonds. The gate contact 1124 may be coupled to at least one of the one or more conductive patterns of the carrier submount 1110, such as conductive pattern 1111, without the use of wirebonds. The drain contact 1126 may be coupled to at least one of the one or more conductive leads of the first lead frame 1140, such as conductive lead 1142, without the use of wirebonds.

[0109] The second semiconductor die 1130 may have a first side 1130A and an opposite second side 1130B. The first side 1130A may be directly bonded to the carrier submount 1110, and the second side 1130B may be directly bonded to the second lead frame 1150. Additionally, the second semiconductor die 1130 may include a source contact 1132 and a gate contact 1134 on the first side 1130A. The second semiconductor die 1130 may further include a drain contact 1136 on the second side 1130B of the second semiconductor die 1130. More specifically, the source contact 1132 may be bonded to at least one of one or more conductive patterns of the carrier submount 1110, such as the conductive pattern 1114, without the use of wire bonds. The source contact 1132 may also be coupled, without the use of wirebonds, to at least one of the one or more conductive leads of the first lead frame 1140, such as conductive lead 1142. The gate contact 1134 may be coupled, without the use of wirebonds, to at least one of the one or more conductive patterns of the carrier submount 1110, such as conductive pattern 1113. The drain contact 1136 may be coupled, without the use of wirebonds, to at least one of the one or more conductive leads of the second lead frame 1150, such as conductive lead 1152.

[0110] In some embodiments, the first semiconductor die 1120 may include a Kelvin contact 1128 on the first side 1120A of the first semiconductor die 1120, and the second semiconductor die 1130 may include a Kelvin contact 1138 on the first side 1130A of the second semiconductor die 1130. The Kelvin contact 1128 of the first semiconductor die 1120 may be coupled to at least one of the one or more conductive patterns of the carrier submount 1110, such as conductive pattern 1115, without the use of wirebonds. The Kelvin contact 1138 of the second semiconductor die 1130 may be coupled to at least one of the one or more conductive patterns of the carrier submount 1110, such as conductive pattern 1117, without the use of wirebonds.

[0111] In some embodiments, the power semiconductor package 1100 may include an encapsulant 1160. The encapsulant 1160 may form a housing for the power semiconductor package 1100. The encapsulant 1160 may be formed by a molding process such that the encapsulant 1160 is at least partially disposed around the carrier submount 1110, the first semiconductor die 1120, the second semiconductor die 1130, the first lead frame 1140, and the second lead frame 1150. The material of the encapsulant 1160 may electrically insulate the components from each other within the power semiconductor package 1100. The material of the encapsulant 1160 may be a dielectric material. Exemplary materials for the encapsulant 1160 may include an epoxy material or an epoxy molding compound (EMC).

[0112] 26 , the thermal conduction cooling layer 1116 on the carrier submount 1110 may be exposed through the encapsulation 1160. More specifically, as shown, the thermal conduction cooling layer 1116 may be exposed through an opening 1162 in the encapsulation 1160. In this manner, the thermal conduction cooling layer 1116 may provide a third thermal conduction path for cooling multiple semiconductor dies (e.g., first semiconductor die 1120, second semiconductor die 1130) in the power semiconductor package 1100. More specifically, the first thermal conduction path may be provided through the first lead frame 1140 and one or more conductive leads, such as conductive lead 1142. The second thermal conduction path may be provided through the second lead frame 1150 and one or more conductive leads, such as conductive lead 1152. The third thermal conduction path may be provided through the opening 1162 in the encapsulation 1160. The thermal conduction cooling layer 1116 may be coupled to a heat sink and / or may provide a thermal conduction path for the power semiconductor package 1100 to the ambient environment.

[0113] 17, the thermal conduction cooling layer 1116 on the carrier submount 1110 may be covered by the encapsulant 1160, rather than being exposed through an opening (e.g., opening 1162) in the encapsulant 1160 as shown in FIG. 26. In such an embodiment, a first thermal conduction path may be provided through the first lead frame 1140 and one or more conductive leads, such as conductive lead 1142, and a second thermal conduction path may be provided through the second lead frame 1150 and one or more conductive leads, such as conductive lead 1152.

[0114] 25-28 , as described above, the first semiconductor die 1120 and the second semiconductor die 1130 may be coupled to different source terminals of the power semiconductor package 1100. For example, the source contact 1122 of the first semiconductor die 1120 may be coupled to the source terminal 1172, and the source contact 1132 of the second semiconductor die 1130 may be coupled to the source terminal 1182. The first semiconductor die 1120 and the second semiconductor die 1130 may be coupled to different gate terminals of the power semiconductor package 1100. For example, the gate contact 1124 of the first semiconductor die 1120 may be coupled to the gate terminal 1174, and the gate contact 1134 of the second semiconductor die 1130 may be coupled to the gate terminal 1184. The first semiconductor die 1120 and the second semiconductor die 1130 may be coupled to different drain terminals of the power semiconductor package 1100. For example, the drain contact 1126 of the first semiconductor die 1120 may be coupled to the drain terminal 1176, and the drain contact 1136 of the second semiconductor die 1130 may be coupled to the drain terminal 1186. Furthermore, in embodiments in which the first semiconductor die 1120 and the second semiconductor die 1130 are arranged in a half-bridge configuration, the drain terminal 1176 of the first semiconductor die 1170 may be coupled to the source terminal 1182 of the second semiconductor die 1130, for example, via the first lead frame 1140.

[0115] Furthermore, in embodiments in which the first semiconductor die 1120 includes a Kelvin contact 1128 and the second semiconductor die 1130 includes a Kelvin contact 1138, the first semiconductor die 1120 and the second semiconductor die 1130 may be coupled to different Kelvin terminals. More specifically, the Kelvin contact 1128 of the first semiconductor die 1120 may be coupled to the Kelvin contact 1178, and the Kelvin contact 1138 of the second semiconductor die 1130 may be coupled to the Kelvin terminal 1188.

[0116] Exemplary aspects of the present disclosure are provided in the following paragraphs, which examples may be combined to form various different embodiments of the present disclosure.

[0117] One exemplary aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package includes a first carrier submount including one or more conductive pads. The power semiconductor package further includes a second carrier submount including one or more conductive leads. The power semiconductor package further includes a power semiconductor die having a first side and an opposite second side. The first side of the power semiconductor die may be directly coupled to the first carrier submount, and the second side of the power semiconductor die may be directly coupled to the second carrier submount.

[0118] In some examples, the power semiconductor die includes a first contact on a first surface and a second contact on a second surface.

[0119] In some examples, the first contact is directly coupled to at least one of the one or more conductive pads of the first carrier submount, and the second contact is directly coupled to the second carrier submount.

[0120] In some examples, the power semiconductor die includes a third contact on the first surface.

[0121] In some examples, the one or more conductive pads of the first carrier submount include a first conductive pad and a second conductive pad, the first contact is directly coupled to the first conductive pad, and the third contact is directly coupled to the second conductive pad.

[0122] In some examples, the first carrier submount is coupled to one or more second conductive leads of the power semiconductor package.

[0123] In some examples, the power semiconductor die is directly bonded to the first carrier submount in a flip-chip configuration.

[0124] In some examples, the first carrier submount includes a direct bond copper (DBC) substrate or an active metal bond (AMB) substrate.

[0125] In some examples, the second carrier submount includes a lead frame for a power semiconductor package.

[0126] In some examples, the first carrier submount has a first surface and an opposite second surface, one or more conductive pads are on the first surface of the first carrier submount, and the first carrier submount includes a thermally conductive cooling layer on the second surface.

[0127] In some examples, the thermal conduction cooling layer is exposed through the encapsulation of the power semiconductor package.

[0128] In some examples, the thermal conduction cooling layer is covered by an encapsulation of the power semiconductor package.

[0129] In some examples, the power semiconductor package further comprises an insulating layer over the first contact of the power semiconductor die.

[0130] In some examples, the insulating layer includes a first dielectric material.

[0131] In some examples, the power semiconductor package further comprises an encapsulant, the encapsulant including a second dielectric material.

[0132] In some instances, the first dielectric material is different from the second dielectric material.

[0133] In some examples, the first dielectric material has a first dielectric constant and the second dielectric material has a second dielectric constant, the first dielectric constant being different from the second dielectric constant.

[0134] In some instances, the first dielectric material is the same as the second dielectric material.

[0135] In some examples, the first dielectric material is an underfill material.

[0136] In some examples, the power semiconductor die includes a wide bandgap semiconductor.

[0137] In some examples, the wide bandgap semiconductor is silicon carbide.

[0138] In some instances, the power semiconductor package does not have any wire bonds to the power semiconductor die.

[0139] In some examples, the power semiconductor die includes a silicon carbide-based MOSFET.

[0140] In some examples, the power semiconductor die includes a silicon carbide-based Schottky diode.

[0141] Another exemplary aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package includes a first carrier submount, a second carrier submount, and a power semiconductor die having a first side and an opposite second side. The power semiconductor die may include source and gate contacts on the first side and a drain contact on the second side. The first side of the power semiconductor die may be directly coupled to the first carrier submount in a flip-chip configuration such that the source and gate contacts are directly coupled to the first carrier submount, and the second side of the power semiconductor die may be directly coupled to the second carrier submount.

[0142] In some instances, the power semiconductor package does not have any wire bonds to the power semiconductor die.

[0143] In some examples, the first carrier submount includes a direct bond copper (DBC) substrate or an active metal bond (AMB) substrate.

[0144] In some examples, the second carrier submount includes a lead frame for a power semiconductor package.

[0145] In some examples, the power semiconductor package further comprises an insulating layer on the first surface of the power semiconductor die.

[0146] In some examples, the power semiconductor package further comprises an encapsulation portion.

[0147] In some examples, the insulating layer comprises a first dielectric material and the encapsulation comprises a second dielectric material.

[0148] In some instances, the first dielectric material is different from the second dielectric material.

[0149] In some instances, the first dielectric material is the same as the second dielectric material.

[0150] In some examples, the first carrier submount includes a thermal conduction cooling layer exposed through the encapsulation.

[0151] In some examples, the first carrier submount comprises a thermal conduction cooling layer covered by an encapsulant.

[0152] Another exemplary aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package includes a first carrier submount and a second carrier submount. The power semiconductor package further includes a power semiconductor die having a first side and an opposite second side. The power semiconductor die may include a source contact and a gate contact on the first side and a drain contact on the second side. The power semiconductor package further includes an insulating layer on the first side of the semiconductor die and an encapsulant. The first side of the power semiconductor die may be directly coupled to the first carrier submount, and the second side of the power semiconductor die may be directly coupled to the second carrier submount.

[0153] In some examples, the insulating layer comprises a first dielectric material and the encapsulation comprises a second dielectric material.

[0154] In some instances, the first dielectric material is different from the second dielectric material.

[0155] In some instances, the first dielectric material is the same as the second dielectric material.

[0156] In some examples, the first carrier submount includes a thermal conduction cooling layer exposed through the encapsulation.

[0157] In some examples, the first carrier submount comprises a thermal conduction cooling layer covered by an encapsulant.

[0158] Another exemplary aspect of the present disclosure is directed to a method of manufacturing a power semiconductor package. The method includes directly bonding a power semiconductor die to a first carrier submount to form a first assembly. The method further includes directly bonding the first assembly to a second carrier submount, the second carrier submount including one or more conductive leads. The method further includes encapsulating the first carrier submount, the second carrier submount, and at least a portion of the power semiconductor die to form an encapsulation.

[0159] In some examples, directly coupling the power semiconductor die to the first carrier submount includes directly coupling the power semiconductor die to the first carrier submount in a flip-chip configuration.

[0160] In some examples, directly coupling the first assembly to the second carrier submount includes directly coupling the first assembly to the second carrier submount without wire bonds.

[0161] In some examples, the method further includes forming an insulating layer over the power semiconductor die.

[0162] In some examples, forming the insulating layer over the power semiconductor die includes forming the insulating layer over the power semiconductor die prior to directly bonding the first assembly to the second carrier submount.

[0163] In some examples, the insulating layer comprises a first dielectric material and the encapsulation comprises a second dielectric material.

[0164] In some instances, the first dielectric material is different from the second dielectric material.

[0165] In some instances, the first dielectric material is the same as the second dielectric material.

[0166] In some examples, the first carrier submount comprises a thermally conductive cooling layer.

[0167] In some examples, encapsulating the first carrier submount, the second carrier submount, and at least a portion of the power semiconductor die to form an encapsulation includes leaving at least a portion of the thermal conduction cooling layer exposed through the encapsulation.

[0168] In some examples, encapsulating the first carrier submount, the second carrier submount, and at least a portion of the power semiconductor die to form an encapsulation includes covering a thermal conduction cooling layer with the encapsulation.

[0169] In some examples, the first carrier submount includes a direct bond copper (DBC) substrate or an active metal bond (AMB) substrate.

[0170] In some examples, the second carrier submount includes a lead frame for a power semiconductor package.

[0171] In some examples, the power semiconductor die includes a wide bandgap semiconductor.

[0172] In some examples, the wide bandgap semiconductor is silicon carbide.

[0173] In some examples, the power semiconductor die includes a silicon carbide-based MOSFET.

[0174] In some examples, the power semiconductor die includes a silicon carbide-based Schottky diode.

[0175] Another exemplary embodiment of the present disclosure is directed to a power semiconductor package. The power semiconductor package includes a first carrier submount, a second carrier submount, and a plurality of semiconductor dies. Each semiconductor die of the plurality of semiconductor dies has a first side and an opposite second side. Further, for each semiconductor die of the plurality of semiconductor dies, the first side is directly coupled to the first carrier submount and the second side is directly coupled to the second carrier submount.

[0176] In some examples, each semiconductor die of the plurality of semiconductor dies includes a first contact on a first surface and a second contact on a second surface.

[0177] In some examples, the first carrier submount includes one or more conductive patterns, and further, for each semiconductor die of the plurality of semiconductor dies, the first contact is directly coupled to at least one of the one or more conductive patterns of the first carrier submount, and the second contact is directly coupled to the second carrier submount.

[0178] In some examples, each semiconductor die further comprises a third contact on the first surface.

[0179] In some examples, for each semiconductor die of the plurality of semiconductor dies, the third contact is directly coupled to at least one of the one or more conductive patterns of the first carrier submount, and the first contact and the third contact are coupled to different conductive patterns of the first carrier submount.

[0180] In some examples, for each semiconductor die of the plurality of semiconductor dies, the first contact is a source contact, the second contact is a drain contact, and the third contact is at least one of a gate contact or a Kelvin contact.

[0181] In some examples, each semiconductor die of the plurality of semiconductor dies is coupled to a common source terminal.

[0182] In some examples, the second carrier submount comprises a plurality of conductive leads, and each drain contact of the plurality of semiconductor dies is coupled to a different one of the plurality of conductive leads.

[0183] In some examples, each semiconductor die of the plurality of semiconductor dies is coupled to a common drain terminal.

[0184] In some examples, each source contact of the plurality of semiconductor dies is coupled to a different conductive pattern of the one or more conductive patterns.

[0185] In some examples, each semiconductor die of the plurality of semiconductor dies is coupled to a common gate terminal.

[0186] In some examples, the power semiconductor package further comprises an encapsulant, the encapsulant including a dielectric material.

[0187] In some examples, the multiple semiconductor dies are directly bonded to the first carrier submount in a flip-chip configuration.

[0188] In some examples, the first carrier submount includes a direct bond copper (DBC) substrate or an active metal bond (AMB) substrate.

[0189] In some examples, the second carrier submount includes a lead frame for a power semiconductor package.

[0190] In some examples, the first carrier submount comprises a first conductive layer, a second conductive layer, and an insulating layer between the first conductive layer and the second conductive layer.

[0191] In some examples, the first conductive layer comprises a source pattern and a gate pattern.

[0192] In some examples, the first conductive layer and the second conductive layer have different conductive patterns.

[0193] In some examples, the power semiconductor package further includes a plurality of vias extending through the insulating layer connecting the second conductive layer with the plurality of semiconductor dies.

[0194] In some examples, the second conductive layer is a thermally conductive cooling layer.

[0195] In some examples, the thermal conduction cooling layer is exposed through the encapsulation of the power semiconductor package.

[0196] In some examples, the thermal conduction cooling layer is covered by an encapsulation of the power semiconductor package.

[0197] In some examples, the first carrier submount comprises a second insulating layer on the second conductive layer and a third conductive layer on the second insulating layer.

[0198] In some examples, the third conduction cooling layer is a thermal conduction cooling layer.

[0199] In some examples, the plurality of semiconductor dies includes a plurality of wide bandgap semiconductor dies.

[0200] In some examples, the plurality of wide bandgap semiconductor dies include silicon carbide.

[0201] In some instances, the power semiconductor package does not have any wire bonds to the multiple semiconductor dies.

[0202] In some examples, each semiconductor die of the plurality of semiconductor dies includes a silicon carbide-based MOSFET.

[0203] In some examples, the silicon carbide-based MOSFETs of multiple semiconductor dies are arranged in parallel.

[0204] In some examples, each semiconductor die of the plurality of semiconductor dies includes a silicon carbide-based Schottky diode.

[0205] In some examples, the silicon carbide-based Schottky diodes of multiple semiconductor dies are arranged in parallel.

[0206] In some examples, the number of semiconductor dies in the plurality of semiconductor dies is in the range of two semiconductor dies to nine semiconductor dies.

[0207] Another exemplary embodiment of the present disclosure is directed to a power semiconductor package. The power semiconductor package includes a first carrier submount, a second carrier submount, and a plurality of semiconductor dies. The first carrier submount includes a first conductive layer and a second conductive layer. Each semiconductor die of the plurality of semiconductor dies has a first side and an opposite second side, and includes a source contact and a gate contact on the first side and a drain contact on the second side. Further, for each semiconductor die of the plurality of semiconductor dies, the first side is directly coupled to the first carrier submount such that the source contact is directly coupled to the first conductive layer of the first carrier submount and the gate contact is directly coupled to the second conductive layer of the first carrier submount. Further, for each semiconductor die of the plurality of semiconductor dies, the second side is directly coupled to the second carrier submount.

[0208] In some examples, for each semiconductor die of the plurality of semiconductor dies, the gate contact is coupled to the second conductive layer of the first carrier submount through a via.

[0209] In some instances, the power semiconductor package does not have any wire bonds to the multiple semiconductor dies.

[0210] In some examples, the first carrier submount includes a direct bond copper (DBC) substrate or an active metal bond (AMB) substrate.

[0211] In some examples, the second carrier submount includes a lead frame for a power semiconductor package.

[0212] In some examples, the first layer of the first carrier submount is coupled to a plurality of semiconductor dies and to a lead frame.

[0213] In some examples, each semiconductor die of the plurality of semiconductor dies is coupled to a common source terminal.

[0214] In some examples, the second carrier submount comprises a plurality of conductive leads, and each drain contact of the plurality of semiconductor dies is coupled to a different one of the plurality of conductive leads.

[0215] In some examples, each semiconductor die of the plurality of semiconductor dies is coupled to a common drain terminal.

[0216] In some examples, the first carrier submount comprises a plurality of conductive patterns, and each source contact of the plurality of semiconductor dies is coupled to a different conductive pattern of the plurality of conductive patterns.

[0217] In some examples, each semiconductor die of the plurality of semiconductor dies is coupled to a common gate terminal.

[0218] In some examples, each semiconductor die of the plurality of semiconductor dies further comprises a Kelvin contact on the first surface.

[0219] In some examples, each semiconductor die of the plurality of semiconductor dies is coupled to a common Kelvin terminal.

[0220] In some examples, the power semiconductor package further comprises an encapsulation portion.

[0221] In some examples, the first carrier submount includes a thermal conduction cooling layer exposed through the encapsulation.

[0222] In some examples, the first carrier submount comprises a thermal conduction cooling layer covered by an encapsulant.

[0223] In some examples, the multiple semiconductor dies are directly bonded to the first carrier submount in a flip-chip configuration.

[0224] In some examples, the plurality of semiconductor dies includes a plurality of wide bandgap semiconductor dies.

[0225] In some examples, the plurality of wide bandgap semiconductor dies are silicon carbide-based semiconductor dies.

[0226] In some examples, the multiple semiconductor dies include multiple silicon carbide-based MOSFETs.

[0227] In some examples, multiple silicon carbide-based MOSFETs are arranged in parallel.

[0228] In some examples, the plurality of semiconductor dies includes a plurality of silicon carbide-based Schottky diodes.

[0229] In some examples, multiple silicon carbide-based Schottky diodes are arranged in parallel.

[0230] In some examples, the number of semiconductor dies in the plurality of semiconductor dies is in the range of two semiconductor dies to nine semiconductor dies.

[0231] Another exemplary embodiment of the present disclosure is directed to a power semiconductor package. The power semiconductor package includes: a carrier submount including one or more conductive patterns; a first lead frame including one or more conductive leads; a second lead frame including one or more conductive leads; a first semiconductor die having a first side directly coupled to the carrier submount and an opposite second side directly coupled to the first lead frame; and a second semiconductor die having a first side directly coupled to the carrier submount and an opposite second side directly coupled to the second lead frame. The first semiconductor die further includes a source contact on the first side coupled to at least one of the one or more conductive patterns of the carrier submount, a gate contact on the first side coupled to at least one of the one or more conductive patterns of the carrier submount, and a drain contact on the second side coupled to at least one of the one or more conductive leads of the first lead frame. The second semiconductor die further comprises a source contact on the first surface coupled to at least one of the one or more conductive patterns of the carrier submount and to at least one of the one or more conductive leads of the first lead frame, a gate contact on the first surface coupled to at least one of the one or more conductive patterns of the carrier submount, and a drain contact on the second surface coupled to at least one of the one or more conductive leads of the second lead frame.

[0232] In some examples, the carrier submount includes a thermal conduction cooling layer exposed through the encapsulation of the power semiconductor package.

[0233] In some examples, the carrier submount includes a thermal conduction cooling layer that is covered by the encapsulation of the power semiconductor package.

[0234] In some examples, the source contact of the first semiconductor die and the source contact of the second semiconductor die are coupled to different source terminals of the power semiconductor package.

[0235] In some examples, the gate contact of the first semiconductor die and the gate contact of the second semiconductor die are coupled to different gate terminals of the power semiconductor package.

[0236] In some examples, the drain contact of the first semiconductor die and the drain contact of the second semiconductor die are coupled to different drain terminals of the power semiconductor package.

[0237] In some examples, the first semiconductor die further comprises a Kelvin contact on the first surface, the Kelvin contact coupled to at least one of the one or more conductive patterns of the carrier submount, and the second semiconductor die further comprises a Kelvin contact on the first surface, the Kelvin contact coupled to at least one of the one or more conductive patterns of the carrier submount.

[0238] In some examples, the Kelvin contact of the first semiconductor die and the Kelvin contact of the second semiconductor die are coupled to different Kelvin terminals of the power semiconductor package.

[0239] In some examples, the power semiconductor package does not have any wire bonds to the first semiconductor die.

[0240] In some examples, the power semiconductor package does not have any wire bonds to the second semiconductor die.

[0241] In some examples, the carrier submount includes a direct bond copper (DBC) substrate or an active metal bond (AMB) substrate.

[0242] In some examples, the first semiconductor die and the second semiconductor die are directly bonded to the carrier submount in a flip-chip configuration.

[0243] In some examples, the first semiconductor die includes a first wide bandgap semiconductor die and the second semiconductor die includes a second wide bandgap semiconductor die.

[0244] In some examples, the first wide bandgap semiconductor die and the second wide bandgap semiconductor die are silicon carbide-based semiconductor dies.

[0245] In some examples, the first wide bandgap semiconductor is a silicon carbide-based MOSFET and the second wide bandgap semiconductor is a silicon carbide-based MOSFET.

[0246] In some examples, the first wide bandgap semiconductor is a silicon carbide-based Schottky diode and the second wide bandgap semiconductor is a silicon carbide-based Schottky diode.

[0247] In some examples, the first semiconductor die and the second semiconductor die are arranged in a half-bridge configuration.

[0248] Another exemplary embodiment of the present disclosure is directed to a power semiconductor package. The power semiconductor package includes a first carrier submount, a second carrier submount, and a semiconductor die. The first carrier submount includes a first conductive layer, a second conductive layer, and an insulating layer between the first and second conductive layers. The semiconductor die has a first side and an opposite second side. The power semiconductor package further includes a conductive pattern that is different from the first conductive layer and the second conductive layer.

[0249] In some examples, the first conductive layer comprises a source pattern and the second conductive layer comprises a gate pattern.

[0250] In some examples, the first carrier submount further includes a via extending through the insulating layer connecting the second conductive layer with the semiconductor die.

[0251] In some examples, the semiconductor die includes a source contact on a first side and a drain contact on a second side.

[0252] In some examples, the semiconductor die further comprises a gate contact on the first surface.

[0253] In some examples, the power semiconductor package further comprises an encapsulant, the encapsulant including a dielectric material.

[0254] In some examples, the semiconductor die is directly bonded to the first carrier submount in a flip-chip configuration.

[0255] In some examples, the first carrier submount includes a direct bond copper (DBC) substrate or an active metal bond (AMB) substrate.

[0256] In some examples, the semiconductor die includes a wide bandgap semiconductor die.

[0257] In some examples, the wide bandgap semiconductor die includes silicon carbide.

[0258] In some examples, the wide bandgap semiconductor die includes a silicon carbide-based MOSFET.

[0259] In some examples, the wide bandgap semiconductor die includes a silicon carbide-based Schottky diode.

[0260] In some instances, the power semiconductor package does not have any wire bonds to the semiconductor die.

[0261] While the present subject matter has been described in detail with reference to certain exemplary embodiments thereof, it will be recognized that those skilled in the art, once they have achieved the above understanding, may readily produce alterations, variations, and equivalents of such embodiments. Accordingly, the scope of the present disclosure is intended to be illustrative rather than limiting, and the disclosure of the subject matter does not exclude the inclusion of such modifications, variations, and / or additions to the present subject matter as would be readily apparent to those skilled in the art.

Claims

1. 1. A power semiconductor package, comprising: a first carrier submount, the first carrier submount comprising one or more conductive pads; a second carrier submount, the second carrier submount comprising one or more conductive leads; a power semiconductor die having a first side and an opposite second side; Equipped with the first surface of the power semiconductor die is directly coupled to the first carrier submount; the second surface of the power semiconductor die is directly coupled to the second carrier submount. Power semiconductor package.

2. 2. The power semiconductor package of claim 1, wherein the power semiconductor die comprises a first contact on the first side and a second contact on the second side.

3. 3. The power semiconductor package of claim 2, wherein the first contact is directly coupled to at least one of the one or more conductive pads of the first carrier submount, and the second contact is directly coupled to the second carrier submount.

4. The power semiconductor package of claim 3 , wherein the power semiconductor die comprises a third contact on the first surface.

5. 5. The power semiconductor package of claim 4, wherein the one or more conductive pads of the first carrier submount include a first conductive pad and a second conductive pad, the first contact is directly coupled to the first conductive pad, and the third contact is directly coupled to the second conductive pad.

6. The power semiconductor package of claim 1 , wherein the first carrier submount is coupled to one or more second conductive leads of the power semiconductor package.

7. 10. The power semiconductor package of claim 1, wherein the power semiconductor die is directly bonded to the first carrier submount in a flip-chip structure.

8. 10. The power semiconductor package of claim 1, wherein the first carrier submount comprises a direct bond copper (DBC) substrate or an active metal bond (AMB) substrate.

9. 10. The power semiconductor package of claim 1, wherein the second carrier submount comprises a lead frame for the power semiconductor package.

10. 2. The power semiconductor package of claim 1, wherein the first carrier submount has a first side and an opposite second side, the one or more conduction pads are on the first side of the first carrier submount, and the first carrier submount includes a thermal conduction cooling layer on the second side.

11. The power semiconductor package of claim 10 , wherein the thermal conduction cooling layer is exposed through an encapsulation of the power semiconductor package.

12. The power semiconductor package of claim 10 , wherein the thermal conduction cooling layer is covered by an encapsulation of the power semiconductor package.

13. The power semiconductor package of claim 1 , further comprising an insulating layer on the first contact of the power semiconductor die.

14. The power semiconductor package of claim 13 , wherein the insulating layer comprises a first dielectric material.

15. The power semiconductor package of claim 14 , further comprising an encapsulant, said encapsulant comprising a second dielectric material.

16. 16. The power semiconductor package of claim 15, wherein the first dielectric material is different from the second dielectric material.

17. 17. The power semiconductor package of claim 16, wherein the first dielectric material has a first dielectric constant and the second dielectric material has a second dielectric constant, the first dielectric constant being different from the second dielectric constant.

18. 16. The power semiconductor package of claim 15, wherein the first dielectric material is the same as the second dielectric material.

19. 15. The power semiconductor package of claim 14, wherein the first dielectric material is an underfill material.

20. 10. The power semiconductor package of claim 1, wherein the power semiconductor die comprises a wide bandgap semiconductor.

21. 21. The power semiconductor package of claim 20, wherein the wide bandgap semiconductor is silicon carbide.

22. 10. The power semiconductor package of claim 1, wherein the power semiconductor package does not have any wire bonds to the power semiconductor die.

23. 10. The power semiconductor package of claim 1, wherein the power semiconductor die comprises a silicon carbide based MOSFET.

24. 10. The power semiconductor package of claim 1, wherein the power semiconductor die comprises a silicon carbide based Schottky diode.

25. 1. A power semiconductor package, comprising: a first carrier submount; a second carrier submount; and a power semiconductor die having a first side and an opposite second side, the power semiconductor die including a source contact and a gate contact on the first side, and the power semiconductor die including a drain contact on the second side; Equipped with the first surface of the power semiconductor die is directly coupled to the first carrier submount in a flip-chip configuration such that the source contact and the gate contact are directly coupled to the first carrier submount; the second surface of the power semiconductor die is directly coupled to the second carrier submount. Power semiconductor package.

26. 26. The power semiconductor package of claim 25, wherein the power semiconductor package does not have any wire bonds to the power semiconductor die.

27. 26. The power semiconductor package of claim 25, wherein the first carrier submount comprises a direct bond copper (DBC) substrate or an active metal bond (AMB) substrate.

28. 26. The power semiconductor package of claim 25, wherein the second carrier submount comprises a lead frame for the power semiconductor package.

29. 26. The power semiconductor package of claim 25, further comprising an insulating layer on the first surface of the power semiconductor die.

30. 30. The power semiconductor package of claim 29, further comprising an encapsulation.

31. 31. The power semiconductor package of claim 30, wherein the insulating layer comprises a first dielectric material and the encapsulant comprises a second dielectric material.

32. 32. The power semiconductor package of claim 31, wherein the first dielectric material is different from the second dielectric material.

33. 32. The power semiconductor package of claim 31, wherein the first dielectric material is the same as the second dielectric material.

34. 31. The power semiconductor package of claim 30, wherein the first carrier submount comprises a thermal conduction cooling layer exposed through the encapsulation.

35. 31. The power semiconductor package of claim 30, wherein the first carrier submount comprises a thermal conduction cooling layer covered by the encapsulation.

36. 1. A power semiconductor package, comprising: a first carrier submount; a second carrier submount; and a power semiconductor die having a first side and an opposite second side, the power semiconductor die including a source contact and a gate contact on the first side, and the power semiconductor die including a drain contact on the second side; an insulating layer on the first surface of the semiconductor die; A sealing portion; Equipped with the first surface of the power semiconductor die is directly coupled to the first carrier submount; the second surface of the power semiconductor die is directly coupled to the second carrier submount. Power semiconductor package.

37. 37. The power semiconductor package of claim 36, wherein the insulating layer comprises a first dielectric material and the encapsulant comprises a second dielectric material.

38. 38. The power semiconductor package of claim 37, wherein the first dielectric material is different from the second dielectric material.

39. 38. The power semiconductor package of claim 37, wherein the first dielectric material is the same as the second dielectric material.

40. 37. The power semiconductor package of claim 36, wherein the first carrier submount comprises a thermal conduction cooling layer exposed through the encapsulation.

41. 37. The power semiconductor package of claim 36, wherein the first carrier submount comprises a thermal conduction cooling layer covered by the encapsulation.

42. 1. A method for manufacturing a power semiconductor package, comprising: directly bonding the power semiconductor die to a first carrier submount to form a first assembly; directly coupling the first assembly to a second carrier submount, the second carrier submount comprising one or more conductive leads; encapsulating the first carrier submount, the second carrier submount, and at least a portion of the power semiconductor die to form an encapsulation; A method comprising:

43. 43. The method of claim 42, wherein directly coupling the power semiconductor die to the first carrier submount comprises directly coupling the power semiconductor die to the first carrier submount in a flip-chip configuration.

44. 43. The method of claim 42, wherein directly coupling the first assembly to the second carrier submount comprises directly coupling the first assembly to the second carrier submount without wire bonds.

45. 43. The method of claim 42, further comprising forming an insulating layer over the power semiconductor die.

46. 46. ​​The method of claim 45, wherein forming an insulating layer over the power semiconductor die comprises forming the insulating layer over the power semiconductor die prior to directly bonding the first assembly to the second carrier submount.

47. 46. ​​The method of claim 45, wherein the insulating layer comprises a first dielectric material and the encapsulation comprises a second dielectric material.

48. 48. The method of claim 47, wherein the first dielectric material is different from the second dielectric material.

49. 48. The method of claim 47, wherein the first dielectric material is the same as the second dielectric material.

50. 43. The method of claim 42, wherein the first carrier submount comprises a thermal conduction cooling layer.

51. 51. The method of claim 50, wherein encapsulating the first carrier submount, the second carrier submount, and at least a portion of the power semiconductor die to form an encapsulation comprises leaving at least a portion of the thermal conduction cooling layer exposed through the encapsulation.

52. 51. The method of claim 50, wherein encapsulating the first carrier submount, the second carrier submount, and at least a portion of the power semiconductor die to form an encapsulation comprises covering the thermal conduction cooling layer with the encapsulation.

53. 43. The method of claim 42, wherein the first carrier submount comprises a direct bond copper (DBC) substrate or an active metal bond (AMB) substrate.

54. 43. The method of claim 42, wherein the second carrier submount comprises a lead frame for the power semiconductor package.

55. 43. The method of claim 42, wherein the power semiconductor die comprises a wide bandgap semiconductor.

56. 56. The method of claim 55, wherein the wide bandgap semiconductor is silicon carbide.

57. 43. The method of claim 42, wherein the power semiconductor die includes a silicon carbide based MOSFET.

58. 43. The method of claim 42, wherein the power semiconductor die comprises a silicon carbide based Schottky diode.

59. 1. A power semiconductor package, comprising: a first carrier submount; a second carrier submount; and a plurality of semiconductor dies, each semiconductor die of the plurality of semiconductor dies having a first side and an opposite second side; Equipped with for each semiconductor die of the plurality of semiconductor dies, the first surface is directly coupled to the first carrier submount and the second surface is directly coupled to the second carrier submount; Power semiconductor package.

60. 60. The power semiconductor package of claim 59, wherein each semiconductor die of the plurality of semiconductor dies comprises a first contact on the first surface and a second contact on the second surface.

61. the first carrier submount comprises one or more conductive patterns; For each semiconductor die of the plurality of semiconductor dies: the first contact is directly coupled to at least one of the one or more conductive patterns of the first carrier submount; the second contact is directly coupled to the second carrier submount; 61. The power semiconductor package of claim 60.

62. 62. The power semiconductor package of claim 61, wherein each semiconductor die further comprises a third contact on the first surface.

63. For each semiconductor die of the plurality of semiconductor dies: the third contact is directly coupled to at least one of the one or more conductive patterns of the first carrier submount; the first contact and the third contact are coupled to different conductive patterns of the first carrier submount; 63. The power semiconductor package of claim 62.

64. For each semiconductor die of the plurality of semiconductor dies: the first contact is a source contact; the second contact is a drain contact; 64. The power semiconductor package of claim 63, wherein the third contact is at least one of a gate contact or a Kelvin contact.

65. 65. The power semiconductor package of claim 64, wherein each semiconductor die of the plurality of semiconductor dies is coupled to a common source terminal.

66. 66. The power semiconductor package of claim 65, wherein the second carrier submount comprises a plurality of conductive leads, and wherein each drain contact of the plurality of semiconductor dies is coupled to a different one of the plurality of conductive leads.

67. 65. The power semiconductor package of claim 64, wherein each semiconductor die of the plurality of semiconductor dies is coupled to a common drain terminal.

68. 68. The power semiconductor package of claim 67, wherein each source contact of the plurality of semiconductor dies is coupled to a different conductive pattern of the one or more conductive patterns.

69. 65. The power semiconductor package of claim 64, wherein each semiconductor die of the plurality of semiconductor dies is coupled to a common gate terminal.

70. 60. The power semiconductor package of claim 59, further comprising an encapsulant, said encapsulant comprising a dielectric material.

71. 60. The power semiconductor package of claim 59, wherein the plurality of semiconductor dies are directly bonded to the first carrier submount in a flip-chip configuration.

72. 60. The power semiconductor package of claim 59, wherein the first carrier submount comprises a direct bond copper (DBC) substrate or an active metal bond (AMB) substrate.

73. 60. The power semiconductor package of claim 59, wherein the second carrier submount comprises a lead frame for the power semiconductor package.

74. The first carrier submount comprises: a first conductive layer; a second conductive layer; and an insulating layer between the first conductive layer and the second conductive layer; 60. The power semiconductor package of claim 59, comprising:

75. 75. The power semiconductor package of claim 74, wherein the first conductive layer comprises a source pattern and a gate pattern.

76. 75. The power semiconductor package of claim 74, wherein the first conductive layer and the second conductive layer comprise different conductive patterns.

77. the first conductive layer comprises a source pattern; the second conductive layer comprises a gate pattern; 77. The power semiconductor package of claim 76.

78. 78. The power semiconductor package of claim 77, further comprising a plurality of vias extending through said insulating layer connecting said second conductive layer with said plurality of semiconductor dies.

79. 75. The power semiconductor package of claim 74, wherein the second conductive layer is a thermally conductive cooling layer.

80. 80. The power semiconductor package of claim 79, wherein the thermal conduction cooling layer is exposed through an encapsulation of the power semiconductor package.

81. 80. The power semiconductor package of claim 79, wherein the thermal conduction cooling layer is covered by an encapsulation of the power semiconductor package.

82. The first carrier submount comprises: a second insulating layer on the second conductive layer; a third conductive layer on the second insulating layer; 75. The power semiconductor package of claim 74, comprising:

83. 83. The power semiconductor package of claim 82, wherein the third conduction cooling layer is a thermal conduction cooling layer.

84. 60. The power semiconductor package of claim 59, wherein the plurality of semiconductor dies includes a plurality of wide bandgap semiconductor dies.

85. 85. The power semiconductor package of claim 84, wherein the plurality of wide bandgap semiconductor dies comprise silicon carbide.

86. 60. The power semiconductor package of claim 59, wherein the power semiconductor package does not have any wire bonds to the plurality of semiconductor dies.

87. 60. The power semiconductor package of claim 59, wherein each semiconductor die of the plurality of semiconductor dies includes a silicon carbide based MOSFET.

88. 88. The power semiconductor package of claim 87, wherein the silicon carbide-based MOSFETs of the plurality of semiconductor dies are arranged in parallel.

89. 60. The power semiconductor package of claim 59, wherein each semiconductor die of the plurality of semiconductor dies includes a silicon carbide based Schottky diode.

90. 90. The power semiconductor package of claim 89, wherein the silicon carbide based Schottky diodes of the plurality of semiconductor dies are arranged in parallel.

91. 60. The power semiconductor package of claim 59, wherein the number of semiconductor dies in the plurality of semiconductor dies is in the range of two semiconductor dies to nine semiconductor dies.

92. a first carrier submount comprising a first conductive layer and a second conductive layer; a second carrier submount; and a plurality of semiconductor dies, each semiconductor die of the plurality of semiconductor dies comprising: a first surface and an opposite second surface; a source contact and a gate contact on the first surface; a drain contact on the second surface; a plurality of semiconductor dies, Equipped with For each semiconductor die of the plurality of semiconductor dies: the first surface is directly coupled to the first carrier submount such that the source contact is directly coupled to the first conductive layer of the first carrier submount and the gate contact is directly coupled to the second conductive layer of the first carrier submount; the second surface is directly coupled to the second carrier submount; Power semiconductor package.

93. 93. The power semiconductor package of claim 92, wherein for each semiconductor die of the plurality of semiconductor dies, the gate contact is coupled to the second conductive layer of the first carrier submount through a via.

94. 93. The power semiconductor package of claim 92, wherein the power semiconductor package does not have any wire bonds to the plurality of semiconductor dies.

95. 93. The power semiconductor package of claim 92, wherein the first carrier submount comprises a direct bond copper (DBC) substrate or an active metal bond (AMB) substrate.

96. 93. The power semiconductor package of claim 92, wherein the second carrier submount comprises a lead frame for the power semiconductor package.

97. 97. The power semiconductor package of claim 96, wherein the first layer of the first carrier submount is coupled to the plurality of semiconductor dies and to the lead frame.

98. 93. The power semiconductor package of claim 92, wherein each semiconductor die of the plurality of semiconductor dies is coupled to a common source terminal.

99. 100. The power semiconductor package of claim 98, wherein the second carrier submount comprises a plurality of conductive leads, and wherein each drain contact of the plurality of semiconductor dies is coupled to a different one of the plurality of conductive leads.

100. 93. The power semiconductor package of claim 92, wherein each semiconductor die of the plurality of semiconductor dies is coupled to a common drain terminal.

101. 101. The power semiconductor package of claim 100, wherein the first carrier submount comprises a plurality of conductive patterns, and each source contact of the plurality of semiconductor dies is coupled to a different conductive pattern of the plurality of conductive patterns.

102. 93. The power semiconductor package of claim 92, wherein each semiconductor die of the plurality of semiconductor dies is coupled to a common gate terminal.

103. 93. The power semiconductor package of claim 92, wherein each semiconductor die of the plurality of semiconductor dies further comprises a Kelvin contact on the first surface.

104. 104. The power semiconductor package of claim 103, wherein each semiconductor die of the plurality of semiconductor dies is coupled to a common Kelvin terminal.

105. 93. The power semiconductor package of claim 92, further comprising an encapsulation portion.

106. 106. The power semiconductor package of claim 105, wherein the first carrier submount comprises a thermal conduction cooling layer exposed through the encapsulation portion.

107. 106. The power semiconductor package of claim 105, wherein the first carrier submount comprises a thermal conduction cooling layer covered by the encapsulation.

108. 93. The power semiconductor package of claim 92, wherein the plurality of semiconductor dies are directly bonded to the first carrier submount in a flip-chip configuration.

109. 93. The power semiconductor package of claim 92, wherein the plurality of semiconductor dies includes a plurality of wide bandgap semiconductor dies.

110. 110. The power semiconductor package of claim 109, wherein the plurality of wide bandgap semiconductor dies are silicon carbide based semiconductor dies.

111. 111. The power semiconductor package of claim 110, wherein the plurality of semiconductor dies includes a plurality of silicon carbide based MOSFETs.

112. 112. The power semiconductor package of claim 111, wherein the plurality of silicon carbide based MOSFETs are arranged in parallel.

113. 111. The power semiconductor package of claim 110, wherein the plurality of semiconductor dies includes a plurality of silicon carbide based Schottky diodes.

114. 114. The power semiconductor package of claim 113, wherein the plurality of silicon carbide based Schottky diodes are arranged in parallel.

115. 93. The power semiconductor package of claim 92, wherein the number of semiconductor dies in the plurality of semiconductor dies is in the range of two semiconductor dies to nine semiconductor dies.

116. 1. A power semiconductor package, comprising: a carrier submount comprising one or more conductive patterns; a first lead frame having one or more conductive leads; a second lead frame having one or more conductive leads; a first semiconductor die having a first surface directly coupled to the carrier submount and an opposite second surface directly coupled to the first leadframe; a source contact on the first surface coupled to at least one of the one or more conductive patterns of the carrier submount; a gate contact on the first surface coupled to at least one of the one or more conductive patterns of the carrier submount; a drain contact on the second surface coupled to at least one of the one or more conductive leads of the first lead frame; a first semiconductor die further comprising: a second semiconductor die having a first surface directly coupled to the carrier submount and an opposite second surface directly coupled to the second leadframe; a source contact on the first surface coupled to at least one of the one or more conductive patterns of the carrier submount and to at least one of the one or more conductive leads of the first lead frame; a gate contact on the first surface coupled to at least one of the one or more conductive patterns of the carrier submount; a drain contact on the second surface coupled to at least one of the one or more conductive leads of the second lead frame; a second semiconductor die further comprising: A power semiconductor package comprising:

117. 117. The power semiconductor package of claim 116, wherein the carrier submount comprises a thermal conduction cooling layer exposed through an encapsulation portion of the power semiconductor package.

118. 117. The power semiconductor package of claim 116, wherein the carrier submount comprises a thermal conduction cooling layer covered by an encapsulation portion of the power semiconductor package.

119. 117. The power semiconductor package of claim 116, wherein the source contact of the first semiconductor die and the source contact of the second semiconductor die are coupled to different source terminals of the power semiconductor package.

120. 117. The power semiconductor package of claim 116, wherein the gate contact of the first semiconductor die and the gate contact of the second semiconductor die are coupled to different gate terminals of the power semiconductor package.

121. 117. The power semiconductor package of claim 116, wherein the drain contact of the first semiconductor die and the drain contact of the second semiconductor die are coupled to different drain terminals of the power semiconductor package.

122. the first semiconductor die further comprising a Kelvin contact on the first surface, the Kelvin contact coupled to at least one of the one or more conductive patterns of the carrier submount; the second semiconductor die further comprising a Kelvin contact on the first surface, the Kelvin contact coupled to at least one of the one or more conductive patterns of the carrier submount.

117. The power semiconductor package of claim 116.

123. 123. The power semiconductor package of claim 122, wherein the Kelvin contact of the first semiconductor die and the Kelvin contact of the second semiconductor die are coupled to different Kelvin terminals of the power semiconductor package.

124. 117. The power semiconductor package of claim 116, wherein the power semiconductor package does not have any wire bonds to the first semiconductor die.

125. 117. The power semiconductor package of claim 116, wherein the power semiconductor package does not have any wire bonds to the second semiconductor die.

126. 117. The power semiconductor package of claim 116, wherein the carrier submount comprises a direct bond copper (DBC) substrate or an active metal bond (AMB) substrate.

127. 117. The power semiconductor package of claim 116, wherein the first semiconductor die and the second semiconductor die are directly bonded to the carrier submount in a flip-chip configuration.

128. 117. The power semiconductor package of claim 116, wherein the first semiconductor die comprises a first wide bandgap semiconductor die and the second semiconductor die comprises a second wide bandgap semiconductor die.

129. 129. The power semiconductor package of claim 128, wherein the first wide bandgap semiconductor die and the second wide bandgap semiconductor die are silicon carbide based semiconductor dies.

130. 130. The power semiconductor package of claim 129, wherein the first wide bandgap semiconductor is a silicon carbide based MOSFET and the second wide bandgap semiconductor is a silicon carbide based MOSFET.

131. 130. The power semiconductor package of claim 129, wherein the first wide bandgap semiconductor is a silicon carbide based Schottky diode and the second wide bandgap semiconductor is a silicon carbide based Schottky diode.

132. 117. The power semiconductor package of claim 116, wherein the first semiconductor die and the second semiconductor die are arranged in a half-bridge configuration.

133. 1. A power semiconductor package, comprising: a first carrier submount, a first conductive layer; a second conductive layer; and an insulating layer between the first conductive layer and the second conductive layer; a first carrier submount comprising: a second carrier submount; and a semiconductor die having a first side and an opposite second side; Equipped with the first conductive layer and the second conductive layer have different conductive patterns; Power semiconductor package.

134. the first conductive layer comprises a source pattern; the second conductive layer comprises a gate pattern; 134. The power semiconductor package of claim 133.

135. 135. The power semiconductor package of claim 134, wherein the first carrier submount further comprises a via extending through the insulating layer connecting the second conductive layer with the semiconductor die.

136. 136. The power semiconductor package of claim 135, wherein the semiconductor die comprises a source contact on the first side and a drain contact on the second side.

137. 137. The power semiconductor package of claim 136, wherein the semiconductor die further comprises a gate contact on the first surface.

138. 134. The power semiconductor package of claim 133, further comprising an encapsulant, the encapsulant comprising a dielectric material.

139. 134. The power semiconductor package of claim 133, wherein the semiconductor die is directly bonded to the first carrier submount in a flip-chip configuration.

140. 134. The power semiconductor package of claim 133, wherein the first carrier submount comprises a direct bond copper (DBC) substrate or an active metal bond (AMB) substrate.

141. 134. The power semiconductor package of claim 133, wherein the semiconductor die comprises a wide bandgap semiconductor die.

142. 142. The power semiconductor package of claim 141, wherein the wide bandgap semiconductor die comprises silicon carbide.

143. 143. The power semiconductor package of claim 142, wherein the wide bandgap semiconductor die includes a silicon carbide based MOSFET.

144. 143. The power semiconductor package of claim 142, wherein the wide bandgap semiconductor die comprises a silicon carbide based Schottky diode.

145. 134. The power semiconductor package of claim 133, wherein the power semiconductor package does not have any wire bonds to the semiconductor die.

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