Characterization of quantum logic gates by dynamic decoupling

Abstract

One exemplary aspect of the present disclosure is directed to a method for characterizing a multi-qubit logic gate operating on a pair of qubits. The method includes repeatedly performing a set of serial operations on the pair of qubits via a multi-qubit quantum circuit. The multi-qubit quantum circuit includes a multi-qubit logic gate, a first single-qubit logic gate operating on a first qubit, and a second single-qubit logic gate operating on a second qubit. After repeatedly performing the set of serial operations on the pair of qubits, a first quantum state of the first qubit and a second quantum state of the second qubit are measured. A first set of expectation values ​​for the first qubit and a second set of expectation values ​​for the second qubit are determined. A value of a first parameter of the set of parameters of the multi-qubit logic gate is determined.

Description

[Technical Field]

[0001] Priority claims This application claims priority to U.S. Provisional Application No. 63 / 436,320, entitled "CHARACTERIZATION OF QUANTUM LOGIC GATES VIA DYNAMICAL DECOUPLING," filed December 30, 2023, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates generally to quantum computing systems, and more particularly to calibrating complex quantum gates (eg, two-qubit quantum gates) within quantum computing systems. [Background technology]

[0003] Quantum computing is a computing method that exploits quantum effects, such as superposition of basis states and entanglement, to perform certain calculations more efficiently than classical digital computers. In contrast to digital computers, which store and manipulate information in the form of bits, e.g., "1" or "0," quantum computing systems can manipulate information using quantum bits ("qubits"). A qubit can refer to a quantum device that allows for a superposition of multiple states, e.g., data in both "0" and "1" states, and / or the superposition of multiple states itself. Following conventional terminology, the superposition of "0" and "1" states in a quantum system can be represented, for example, as a|0〉 + b|1〉. The "0" and "1" states of a digital computer are analogous to the |0〉 and |1〉 basis states of the qubit, respectively. Summary of the Invention

[0004] Aspects and advantages of embodiments of the present disclosure will be set forth in part in the description that follows, or may be learned from the description, or may be learned by practice of the embodiments.

[0005] One exemplary aspect of the present disclosure is directed to a method for characterizing a multi-qubit logic gate, e.g., a fermion simulation (fSim) gate. The multi-qubit logic gate is enabled to operate on a pair of qubits. The pair of qubits includes a first qubit and a second qubit. The method includes repeatedly performing a set of serial operations on the pair of qubits. The set of serial operations may be performed by a multi-qubit quantum circuit. The multi-qubit quantum circuit may be included in a quantum computing system. The multi-qubit quantum circuit includes at least a multi-qubit logic gate, a first single-qubit logic gate (e.g., a first Pauli gate) enabled to operate on the first qubit, and a second single-qubit logic gate (e.g., a second Pauli gate) enabled to operate on the second qubit. The set of serial operations includes at least a first operation and a second operation. The first operation includes the multi-qubit logic gate operating on the pair of qubits. The second operation includes a first single-qubit logic gate operating on the first qubit. The second operation also includes a second single-qubit logic gate operating on the second qubit. The first single-qubit logic gate operating on the first qubit and the second single-qubit logic gate operating on the second qubit may be performed in parallel. After repeatedly performing the set of serial operations on the pair of qubits, a first quantum state of the first qubit may be measured in the quantum computing system. After repeatedly performing the set of serial operations on the pair of qubits, a second quantum state of the second qubit may be measured in the quantum computing system. A first set of expectation values ​​for the first qubit may be determined in the quantum computing system. The first set of expectation values ​​for the first qubit may be determined based on the first quantum state of the first qubit. A second set of expectation values ​​for the second qubit may be determined in the quantum computing system.A second set of expectation values ​​for the second qubit may be determined based on a second quantum state of the second qubit. A value of at least a first parameter (e.g., a control phase, a swap angle, or a Z-phase) of the set of parameters of the multi-qubit logic gate is determined in the quantum computing system. Determining the value of the first parameter may be based on the first set of expectation values ​​for the first qubit and the second set of expectation values ​​for the second qubit.

[0006] Other aspects of the present disclosure are directed to various systems, methods, apparatus, non-transitory computer-readable media, computer-readable instructions, and computing devices.

[0007] These and other features, aspects, and advantages of various embodiments of the present disclosure will become better understood with reference to the following detailed description and the appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present disclosure and, together with the detailed description, explain associated principles.

[0008] Detailed descriptions of embodiments directed to those skilled in the art are set forth herein with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0009] [Figure 1] 1 illustrates an exemplary quantum computing system according to an exemplary embodiment of the present disclosure. [Figure 2A] 1 illustrates the operation of a generalized multi-qubit logic gate that can be characterized via various embodiments of the present disclosure. [Figure 2B] 2B illustrates a quantum state measurement that allows for the determination of matrix elements of the sub-matrix of FIG. 2A, according to various embodiments. [Figure 3-1]3A illustrates a quantum state measurement that enables determination of control phase parameters of a multi-qubit logic gate (e.g., an fSim gate) via dynamic decoupling, according to various embodiments, and FIG. 3B illustrates a mathematical representation of the operation of the multi-qubit quantum logic circuit of FIG. 3A, according to various embodiments. [Figure 3-2] FIG. 1C shows a multi-qubit quantum logic circuit for determining the control phase parameters of an fSim gate, with a depth of 4, according to various embodiments. [Figure 4] 10 illustrates quantum state measurements that enable determination of exchange angle parameters of multi-qubit logic gates (e.g., fSim gates) via dynamic decoupling, according to various embodiments. [Figure 5] FIG. 1 shows a flow diagram of an exemplary method for characterizing a multi-qubit logic gate capable of operating on a pair of qubits including a first qubit and a second qubit, according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] Exemplary aspects of the present disclosure are directed to enhanced systems and methods for characterizing (e.g., calibrating) multi-qubit quantum logic gates (e.g., two-qubit quantum gates) in quantum computing systems. Quantum gates can be building blocks of quantum circuits implemented by quantum computing systems for quantum computing and quantum information processing. Quantum computer operations can require characterization (or calibration) of experimentally realizable quantum logic gates. Characterization (or calibration) of a quantum logic gate can include determining values ​​of a set of parameters (e.g., a set of gate parameters) that characterize the quantum logic gate. Various embodiments enable the determination of values ​​of the set of gate parameters to be more accurate, precise, more efficient, and less prone to noise and errors than conventional methods of calibrating (quantum) logic gates.

[0011] Robust and efficient quantum gate characterization provides information about realized quantum gates, which can then be used for subsequent quantum control calibration in quantum computing systems. Quantum control calibration can include, for example, calibration of control pulses for implementing quantum gates on quantum systems with multiple qubits. Quantum gate characterization and calibration are useful for achieving high-fidelity quantum computing and large-scale deployment.

[0012] A composite gate characterizable by various embodiments may be a generalized fermion simulation (fSim) gate operating on a pair of qubits (e.g., a first qubit and a second qubit). As used throughout, an fSim gate may be an example of a multi-qubit (quantum) logic gate. A generalized fSim gate may implement at least two quantum logic operations for an input two-qubit pair: (a) an exchange operation that “exchanges” the qubit pair by an arbitrary exchange angle (θ), and (b) a control phase operation that generates an arbitrary phase (e.g., a control phase (φ)) between the qubit pair. The set of two quantum operations: {exchange, control phase} may form a functionally complete (or nearly functionally complete) set of quantum logic operations for the qubit pair. Thus, an fSim gate may be characterized by determining values ​​for a set of gate parameters including at least the exchange angle (θ) parameter and the control phase (φ) parameter. In some embodiments, the value of another gate parameter, the common Z phase of the pair of qubits, may also be determined. Determining values ​​for the parameters of the set of gate parameters may include determining a value for each parameter as a function of an operating frequency of the gate.

[0013] Conventional methods for calibrating fSim gates (e.g., determining the value of at least one of a Z-phase parameter, an exchange angle parameter, and the gate's control phase) are prone to noise and other instabilities due to fluctuations in the single-qubit Z-phase gates conventionally employed to determine the values ​​of a set of (gate) parameters. More particularly, such fluctuations in the Z-phase gates manifest as noise when conventionally determining (or measuring) the exchange angle parameter. Furthermore, such conventional methods may not be generalizable to determining the control phase and may be employed to calibrate only specialized instances of fSim gates (e.g., controlled-Z gates).

[0014] Embodiments address these and other drawbacks associated with conventional gate calibration methods by employing various enhanced quantum measurement circuits to perform a set of enhanced quantum measurements. These enhanced measurements enable the determination of parameter values ​​for a generalized fSim gate. That is, the enhanced quantum circuit and enhanced quantum measurements enable the determination of values ​​for at least the control phase and the exchange angle. More specifically, the circuits and measurements decouple multiple noise parameters, making the determination of gate parameters independent of the noise parameters. Due to the decoupling of noise parameters, the determination of gate parameter values ​​is insensitive to noise in the quantum measurements. The decoupling of noise parameters can be achieved by repeatedly applying π pulses to each of the qubits, with successive π pulses interleaved by the repeated application of fSim gates. The π pulses can be implemented via Pauli gates (e.g., X-gates and / or Y-gates). In some embodiments, the π pulses provided to each of the first and second qubits can be in-phase π pulses (e.g., implemented by a pair of parallel X-gates). In other embodiments, the π pulses provided to each of the first and second qubits may be out-of-phase π pulses (e.g., implemented by a parallel pair of Pauli gates including an X gate operating on the first qubit and a Y gate operating on the second qubit). Measurements allow for the determination of various expectation values ​​(e.g., as encoded in operator matrix elements). Such noise-insensitive expectation values ​​may be employed to determine values ​​for a set of gate parameters. Quantum circuits and quantum measurements, as well as the determination of expectation values ​​and parameter values, are discussed below.

[0015] Aspects of the present disclosure provide several technical effects and advantages. For example, conventional methods may be constrained to calibrating only controlled-Z gates, which are specialized instances of fSim gates. In contrast, various embodiments enable determining values ​​for a full set of gate parameters that fully characterize a fully generalized fSim gate. Because they are constrained to controlled-Z gates, conventional methods may be capable of determining the value of only a single gate parameter (e.g., exchange angle). That is, these conventional embodiments may not be able to determine the value of the control phase of a generalizable fSim gate. In contrast, embodiments enable determining values ​​for at least both the exchange angle and the control phase of a generalized fSim gate. Furthermore, various embodiments require less circuitry (or equivalently, a shallower circuit depth) for the same accuracy in determining the exchange angle compared to those conventional methods that provide similar accuracy. Furthermore, conventional methods may require the use of physical Z gates to determine the value of the exchange angle. The use of physical Z gates requires additional calibration and introduces noise into the equivalent circuit depth. Because various embodiments do not require the use of physical Z-gates to determine the values ​​of the parameters, various embodiments are associated with a smaller amount of noise and / or calibration. Various embodiments may employ one or more X-gates and / or one or more Y-gates rather than a Z-gate.

[0016] 1 illustrates an exemplary quantum computing system 100. System 100 is one example of a system of one or more classical computers and / or quantum computing devices, at one or more locations, that may implement the systems, components, and techniques described herein below. Using the disclosure provided herein, one skilled in the art will understand that other quantum computing devices or systems may be used without departing from the scope of the present disclosure.

[0017] System 100 includes quantum hardware 102 in data communication with one or more classical processors 104. Classical processor 104 may be configured to execute computer-readable instructions stored in one or more memory devices to perform operations, such as any of the operations described herein. Quantum hardware 102 includes components for performing quantum computations. For example, quantum hardware 102 includes quantum system 110, control device(s) 112, and readout device(s) 114 (e.g., readout resonator(s)). Quantum system 110 may include one or more multilevel quantum subsystems, such as a register of qubits (e.g., qubit 120). In some implementations, multilevel quantum subsystems may include superconducting qubits, such as flux qubits, charge qubits, transmon qubits, gmon qubits, and spin-based qubits.

[0018] The type of multilevel quantum subsystem utilized by system 100 may vary. For example, in some cases it may be advantageous to include one or more readout device(s) 114 attached to one or more superconducting qubits, e.g., transmon, flux, gmon, xmon, or other qubits. In other cases, ion traps, photonic devices, or superconducting cavities (e.g., that may prepare states without the need for qubits) may be used. Further examples of implementations of multilevel quantum subsystems include fluxmon qubits, silicon quantum dots, or phosphorus impurity qubits.

[0019] Quantum circuits may be constructed and applied to a register of qubits included in quantum system 110 via multiple control lines coupled to one or more control devices 112. An exemplary control device 112 operating on a register of qubits can be used to implement a quantum circuit having a quantum gate or multiple quantum gates, e.g., Pauli gates, Hadamard gates, controlled-NOT (CNOT) gates, controlled phase gates, T-gates, multi-qubit quantum gates, coupler quantum gates, etc. One or more control devices 112 may be configured to operate on quantum system 110 with each of one or more control parameters (e.g., one or more physical control parameters). For example, in some implementations, the multilevel quantum subsystem may be a superconducting qubit, and control device 112 may be configured to provide control pulses to the control lines to generate magnetic fields to tune the frequency of the qubit.

[0020] The quantum hardware 102 may further include a readout device 114 (e.g., a readout resonator). Measurements 108 obtained via the measurement device may be provided to a classical processor 104 for processing and analysis. In some embodiments, the quantum hardware 102 may include quantum circuits, and the control device(s) 112 and readout device(s) 114 may implement one or more quantum logic gates that operate on the quantum system 110 through physical control parameters (e.g., microwave pulses) transmitted over wires included in the quantum hardware 102. Further examples of control devices include arbitrary waveform generators, in which a DAC (digital-to-analog converter) produces a signal.

[0021] The readout device(s) 114 may be configured to perform quantum measurements on the quantum system 110 and send the measurement results 108 to the classical processor 104. Additionally, the quantum hardware 102 may be configured to receive data from the classical processor 104 specifying physical control qubit parameter values ​​106. The quantum hardware 102 may use the received physical control qubit parameter values ​​106 to update the actions of the control device(s) 112 and the readout device(s) 114 on the quantum system 110. For example, the quantum hardware 102 may receive data specifying new values ​​representing voltage magnitudes of one or more DACs included within the control device 112 and may update the actions of the DACs on the quantum system 110 accordingly. The classical processor 104 may be configured to initialize the quantum system 110 to an initial quantum state, e.g., by sending data to the quantum hardware 102 specifying an initial set of parameters 106.

[0022] In some implementations, readout device(s) 114 may utilize the difference in impedance for the |0> and |1> states of an element of a quantum system, such as a qubit, to measure the state of the element (e.g., the qubit). For example, the resonant frequency of the readout resonator may be different when the qubit is in the |0> or |1> state due to the nonlinearity of the qubit. Thus, microwave pulses reflected from readout device 114 convey amplitude and phase shifts that depend on the qubit state. In some implementations, a Purcell filter may be used in conjunction with readout device(s) 114 to prevent microwave propagation at the qubit frequency.

[0023] In some embodiments, quantum system 110 may include multiple qubits 120 arranged, for example, in a two-dimensional grid 122. For clarity, two-dimensional grid 122 depicted in FIG. 1 includes 4x4 qubits, although in some implementations, system 110 may include a fewer or greater number of qubits. In some embodiments, multiple qubits 120 may interact through multiple qubit couplers, such as qubit coupler 124. The qubit coupler may define nearest-neighbor interactions between multiple qubits 120. In some implementations, the strength of the multiple qubit couplers is a tunable parameter. In some cases, the multiple qubit couplers included in quantum computing system 100 may be couplers with fixed coupling strengths.

[0024] In some embodiments, the plurality of qubits 120 may include data qubits, such as qubit 126, and measurement qubits, such as qubit 128. A data qubit is a qubit that participates in a computation being performed by system 100. A measurement qubit is a qubit that can be used to determine the outcome of a computation performed by a data qubit. That is, during a computation, the unknown state of a data qubit is conveyed to a measurement qubit using an appropriate physical operation and measured via an appropriate measurement operation performed on the measurement qubit.

[0025] In some implementations, each qubit of plurality of qubits 120 may operate using a respective operating frequency, such as an idle frequency, an interaction frequency, a readout frequency, and / or a reset frequency. The operating frequency may vary from qubit to qubit. For example, each qubit may idle at a different operating frequency. The operating frequency of qubit 120 may be selected before a computation is performed.

[0026] 1 illustrates an example of a quantum computing system that can be used to implement methods and operations according to exemplary aspects of the present disclosure. Other quantum computing systems may be used without departing from the scope of the present disclosure.

[0027] 2A illustrates the operation of a generalized multi-qubit logic gate (e.g., an fSim gate) that can be characterized via various embodiments of the present disclosure. More specifically, unitary matrix 200 encodes the unitary operation of an fSim gate (e.g., an fSim gate operating on a two-qubit system) for any exchange angle (θ) and any control phase (φ). In addition to being a function of the exchange angle and control phase parameters, the operation of the fSim gate is also a function of the Z-phase parameter (γ). The Z-phase parameter is a phase angle common to both qubits in a qubit pair. Note that unitary matrix 200 is a block diagonal matrix with diagonal elements: a scalar identity element 202, a 2×2 submatrix 204, and a scalar phase element 206. Submatrix 202 is a block diagonal matrix with four complex matrix elements: {u 11 ,u 12 ,u 21 ,u 22 ,}. Phase component 206 is a function of both the common Z phase and the control phase. Equation 208 shows that the common Z phase can be calculated from the determinant of submatrix 204.

[0028] FIG. 2B illustrates a quantum state measurement that enables the determination of matrix elements of submatrix 204 of FIG. 2A , according to various embodiments. As discussed above, equation 208 of FIG. 2A indicates that the common Z phase of two qubits operated by an fSim gate (e.g., fSim gate 212 of FIG. 2B ) can be calculated from the determinant of submatrix 204 of FIG. 2A . More specifically, FIG. 2B illustrates two separate experimental setups: a first experimental setup 220 and a second experimental setup 230. Both first experimental setup 220 and second experimental setup employ qubit pair 210, fSim gate 212, and a pair of quantum measurement devices 214. In the following description, the first qubit of qubit pair 210 will be referred to as the “upper” qubit, and the second qubit of qubit pair 210 will be referred to as the “lower” qubit (e.g., upper and lower are terms relative to the vertical axis of the plane of FIG. 2A ). A first quantum measurement device 216 of pair of quantum measurement devices 214 is capable of measuring (or observing) the quantum state of a first (or upper) qubit of qubit pair 210. A second quantum measurement device 218 of pair of quantum measurement devices 214 is capable of measuring (or observing) the quantum state of a second (or lower) qubit of qubit pair 210. Each of first quantum measurement device 216 and second quantum measurement device 218 is capable of selectively measuring (or observing) the quantum state of their corresponding qubit for either two “X” observable states (or eigenstates) or two “Y” observable states (or eigenstates), where X and Y are basis states corresponding to the respective Pauli matrices.

[0029] In the first experimental setup 220, the upper qubit is in a first Hadamard state 222 (e.g., in the {|0〉,|1〉} basis

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[0030] Each of the eight measurements yielded four expected values ​​with sufficient statistical significance for each of the first experimental setup 220 and the second experimental setup 230:

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[0031] 3A illustrates quantum state measurements that enable the determination of control phase parameters of a multi-qubit logic gate (e.g., an fSim gate) via dynamic decoupling, according to various embodiments. FIG. 3A includes an experimental setup having a multi-qubit quantum logic circuit 300. The multi-qubit quantum logic circuit 300 includes a first qubit line 302 and a second qubit line 304. The multi-qubit quantum logic circuit 300 further includes at least two fSim gates, i.e., a first fSim gate 306 and a second fSim gate 308, and at least two pairs of corresponding X gates, i.e., a first pair of X gates 316 and a second pair of X gates 318, where the X gates are quantum NOT gates (e.g., Pauli matrices in the {|0〉,|1〉} basis).

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[0032] Note that the first fSim gate 306 and the second fSim gate 308 need not be separate physical gates. Rather, the first fSim gate 306 and the second fSim gate 308 can be the same physical fSim gate. Similarly, the first pair of X gates 316 and the second pair of X gates 318 need not be separate pairs of X gates. Rather, the first pair of X gates 316 and the second pair of X gates 318 can be the same physical pair of X gates. A multi-qubit quantum logic gate 300 may "loop" back on itself in a feedback direction. A multi-qubit quantum logic circuit 300 with the same physical gate can be programmed to iteratively feedback on itself.

[0033] In other embodiments of multi-qubit quantum logic circuit 300 (e.g., multi-qubit quantum logic circuit 340 of FIG. 3C), additional (or alternative) copies of the fSim gate and X gate may be positioned on a pair of qubit lines. In some embodiments, a pair of X gates may be positioned to the right of each fSim gate so that a π pulse is applied to each qubit after it has been operated on by the corresponding fSim gate. Although not explicitly shown in FIG. 3A, a pair of quantum measurement devices (e.g., pair of quantum measurement devices 214 of FIG. 2B) may be positioned on a pair of qubit lines of multi-qubit quantum logic circuit 300 so that the quantum state of each qubit may be measured after it has been processed by the alternative series of fSim and X gates.

[0034] The π pulse applied to each qubit after it is acted upon by the fSim gate serves to dynamically decouple the noise parameter for the determination of the control phase parameter (φ). Each π pulse serves to further decouple the noise parameter. Thus, the greater the number of alternate fSim and X gate pairs, the greater the noise reduction in the measurement of the control phase parameter. The “depth” of the quantum logic circuit can be increased to provide a higher level of noise suppression in the determination of the control phase parameter, where depth refers to the number of alternate fSim gate pairs and X gate pairs. The depth of the multi-qubit quantum logic circuit 300 is two. Briefly focusing on FIG. 3C , FIG. 3C illustrates a multi-qubit quantum logic circuit 340 for determining the control phase parameter of an fSim gate, with a depth of four, according to various embodiments. The multi-qubit quantum logic circuit 340 is similar to the multi-qubit quantum logic circuit 300 of FIG. 3A , except that the multi-qubit quantum logic circuit 340 has a depth of four, while the multi-qubit quantum logic circuit 300 has a depth of two. Multi-qubit quantum logic circuit 340 may provide greater noise suppression when determining the control phase parameters compared to multi-qubit quantum logic circuit 300. The depth parameter may indicate the number of times the quantum logic circuit is programmed to feed back into itself to repeatedly apply alternate sequences of fSim gates and X gates. For example, for a depth of 4, the quantum logic circuit may be programmed to feed back into itself three times.

[0035] FIG. 3B shows a mathematical representation of the operation of the multi-qubit quantum logic circuit 300 of FIG. 3A , according to various embodiments. Equation 320 shows the matrix operations of the multi-qubit quantum logic circuit 300 operating on pairs of qubits. The dashed lines with arrows between FIGS. 3A-3B indicate the correspondence between the quantum circuit elements of the multi-qubit quantum logic circuit 300 and the various factors in Equation 320. Note that each factor in Equation 320 is a 4×4 matrix. The product of the four factors in Equation 320 yields a unitary (and block diagonal) matrix 322. Similar to matrix 200 of FIG. 2A , the “center” element of matrix 322 is a 2×2 submatrix 324. The elements of submatrix 324 may be determined similarly to the measurements and equations of FIG. 2B . Thus, the four elements of submatrix 323 may be experimentally measured by repeated measurements that provide sufficient statistical significance. Equation 320 can be updated to accommodate quantum logic circuits of depth greater than two (eg, multi-qubit quantum logic circuit 340 of FIG. 3C) by inserting more factors into equation 320.

[0036] Note that matrix 322 (and submatrix 324) includes a common phase factor 326 that depends on both the common Z-phase parameter (γ) and the control phase parameter (φ). Thus, when determining the control phase parameter (as described in conjunction with FIGS. 2A-2B), the control phase parameter can be determined by the common phase factor 326, which itself is determined by measuring the matrix elements of submatrix 324.

[0037] FIG. 4 illustrates quantum state measurements that enable determination of the exchange angle parameter of an fSim gate via dynamical decoupling, according to various embodiments. FIG. 4 illustrates first and second experimental setups employed to determine the exchange angle of the fSim gate. The first experimental setup includes a first multi-qubit quantum logic circuit 400, and the second experimental setup includes a second multi-qubit quantum logic circuit 440. The first multi-qubit quantum logic circuit 400 is enabled to operate on a qubit pair 402. The pair of qubits 402 includes a first qubit (e.g., q1) and a second qubit (e.g., q2). The first multi-qubit quantum logic circuit 400 includes a multi-qubit logic gate (e.g., an fSim gate 404) and a first pair of single-qubit logic gates 406. The multi-qubit logic gate 404 is enabled to operate on each of the qubits in the pair of qubits 402. As shown in the schematic diagram of the first multi-qubit quantum logic circuit 400, the multi-qubit logic gate operates as a CZ (eg, a controlled Z gate).

[0038] The first pair of single-qubit logic gates 406 includes a first single-qubit logic gate (e.g., a first X gate) that is enabled to operate on the first qubit of the qubit pair 402, and a second single-qubit logic gate (e.g., a second X gate) that is enabled to operate on the second qubit of the qubit pair 402. The depth of the multi-qubit quantum circuit is two. Thus, two instantiations of the multi-qubit logic gate 404 and two instantiations of the first pair of single-qubit logic gates 402 are shown in the schematic diagram of the first multi-qubit quantum logic circuit 400.

[0039] In some embodiments, a first qubit is initially prepared in a first excited state (e.g., |1〉) and a second qubit is initially prepared in a vacuum state (e.g., |0〉) such that the initial state of the pair of qubits 402 is represented by the state vector |10〉. Similar to the description in FIGS. 3A-3C, the effect of the first pair of single-qubit logic gates 406 is to apply a π pulse to the qubits of the qubit pair 402. In the first pair of single-qubit logic gates 406, both single-qubit logic gates are X gates, so the π pulses are in phase. Also shown in FIG. 4 is a first Bloch sphere representation 410 of the qubit pair 402, where the initial preparation of the qubit pair 402 is along the Z axis of the first Bloch sphere representation 410. Repeated application of a CZ gate (e.g., a multi-qubit logic gate 404) and the pair of single-qubit logic gates 406 preserves the number of excited states of the qubit pair 402. Thus, first Bloch sphere representation 410 covers the entire 2D subspace available to qubit pair 402, since qubit pair 402 is initially prepared in the |10> state.

[0040] The first pair of single-qubit logic gates 406 tend to dynamically decouple the noise parameter of the measurement of the exchange angle. As indicated by arrow 412, the dynamic decoupling operation of the first pair of single-qubit logic gates 406 tends to rotate the state vector |10〉 toward the |10〉 + |01〉 axis of the first Bloch sphere representation 410. The dynamic decoupling of the noise parameter achieved by the dynamic decoupling operation of the first pair of single-qubit logic gates 406 tends to damp other rotations of the state vector. Note that the exchange angle may be complex-valued, and the real value of the exchange angle may be determined by the first multi-qubit quantum logic circuit 400, through repeated measurements similar to those described in conjunction with FIG. 2B .

[0041] Similar to the first multi-qubit quantum logic circuit 400, the second multi-qubit quantum logic circuit 440 is enabled to operate on the qubit pair 402. The second multi-qubit quantum logic circuit 440 may be similar to the first multi-qubit quantum logic circuit 400, except that rather than the first pair of single-qubit logic gates 406, the second multi-qubit quantum logic circuit 440 includes a second pair of single-qubit logic gates 408. The second pair of single-qubit logic gates 408 includes a first single-qubit logic gate (e.g., a first X gate) enabled to operate on the first qubit of the qubit pair 402 and a second single-qubit logic gate (e.g., a first Y gate) enabled to operate on the second qubit of the qubit pair 402. The depth of the multi-qubit quantum circuit is two. Thus, two instantiations of multi-qubit logic gate 404 and two instantiations of a second pair of single-qubit logic gates 402 are shown in the schematic diagram of second multi-qubit quantum logic circuit 440.

[0042] Similar to the description above, in some embodiments, a first qubit is initially prepared in a first excited state (e.g., |1〉) and a second qubit is initially prepared in a vacuum state (e.g., |0〉) such that the initial state of the pair of qubits 402 is represented by the state vector |10〉. Similar to the description in FIGS. 3A-3C, the effect of the second pair of single-qubit logic gates 406 is to apply π pulses to the qubits of the qubit pair 402. In the second pair of single-qubit logic gates 408, the first single-qubit logic gate is an X gate and the second single-qubit gate is a Y gate, so the π pulses are not in phase. Also shown in FIG. 4 is a second Bloch sphere representation 414 of the qubit pair 402, with the initial preparation of the qubit pair 402 along the Z axis of the second Bloch sphere representation 414. Repeated application of a CZ gate (e.g., multi-qubit logic gate 404) and a second pair of single-qubit logic gates 408 preserves the number of excited states of qubit pair 402. Thus, second Bloch sphere representation 414 covers the entire 2D subspace available to qubit pair 402, since qubit pair 402 is initially prepared in the |10〉 state.

[0043] The second pair of single-qubit logic gates 408 tend to dynamically decouple the noise parameter of the measurement of the exchange angle. As indicated by arrow 416, the dynamic decoupling operation of the second pair of single-qubit logic gates 408 tends to rotate the state vector |10〉 toward the |10〉+i|01〉 axis of the second Bloch sphere representation 414. The dynamic decoupling of the noise parameter achieved by the dynamic decoupling operation of the second pair of single-qubit logic gates 408 tends to damp other rotations of the state vector. Note that the exchange angle may be complex-valued, and the imaginary value of the exchange angle may be determined by the first multi-qubit quantum logic circuit 400, through repeated measurements similar to those described in conjunction with FIG. 2B .

[0044] 5 depicts operations occurring in a particular order for purposes of illustration and explanation. Using the disclosure provided herein, one skilled in the art will understand that the operations of any of the methods described herein may be extended in various ways, may include steps not shown, may be omitted, may be rearranged, and / or may be modified without departing from the scope of the disclosure. Various portions or steps of method 500 of FIG. 5 may be implemented by a quantum computing system (e.g., quantum computing system 100 of FIG. 1).

[0045] FIG. 5 shows a flow diagram of an exemplary method 500 for characterizing a multi-qubit logic gate (e.g., an fSim gate) capable of operating on a pair of qubits including a first qubit and a second qubit, according to an exemplary embodiment of the present disclosure. Method 500 begins at block 502, where a set of serial operations is performed on the pair of qubits. The set of serial operations may be performed by a multi-qubit quantum circuit included in a quantum computing system. The multi-qubit quantum circuit may include at least a multi-qubit logic gate, a first single-qubit logic gate capable of operating on the first qubit, and a second single-qubit logic gate capable of operating on the second qubit. The set of serial operations may include a first operation having a multi-qubit logic gate operating on the pair of qubits. The set of serial operations may further include a second operation having a first single-qubit logic gate operating on the first qubit in parallel to a second single-qubit logic gate operating on the second qubit.

[0046] At block 504, a first quantum state of a first qubit may be measured in the quantum computing system after iteratively performing the set of serial operations on the pair of qubits. At block 506, a second quantum state of a second qubit may be measured in the quantum computing system after iteratively performing the set of serial operations on the pair of qubits.

[0047] In block 508, a first set of expectation values ​​for a first qubit may be determined in the quantum computing system. The determination of the first set of expectation values ​​for the first qubit may be determined based on a first quantum state of the first qubit. In block 510, a second set of expectation values ​​for a second qubit may be determined in the quantum computing system. The determination of the second set of expectation values ​​for the second qubit may be determined based on a second quantum state of the second qubit. In block 512, a value of at least a first parameter of the set of parameters of the multi-qubit logic gate may be determined in the quantum computing system. Determining the value of the first parameter may be based on the first set of expectation values ​​for the first qubit and the second set of expectation values ​​for the second qubit.

[0048] In some embodiments, the multi-qubit logic gate is a fermion simulation (fSim) gate and the first parameter corresponds to a control phase of the fSim gate, hi other embodiments, the multi-qubit logic gate is a fermion simulation (fSim) gate and the first parameter corresponds to an exchange angle of the fSim gate.

[0049] The first parameter may correspond to a control phase of a multi-qubit logic gate. In such embodiments, the method may include preparing an initial quantum state of a first qubit in a vacuum state in a quantum computing system before iteratively performing the set of serial operations on the pair of qubits. Prior to iteratively performing the set of serial operations on the pair of qubits, an initial quantum state of a second qubit may be prepared in a first Hadamard state in the quantum computing system.

[0050] The first parameter may correspond to a swap angle of the multi-qubit logic gate. In such embodiments, the method may further include preparing an initial quantum state of the first qubit in a vacuum state in the quantum computing system before iteratively performing the set of serial operations on the pair of qubits. Prior to iteratively performing the set of serial operations on the pair of qubits, an initial quantum state of the second qubit may be prepared in a first excited state in the quantum computing device.

[0051] Each of the first single-qubit logic gate and the second single-qubit logic gate is a Pauli gate. The first parameter may correspond to a control phase of the multi-qubit logic gate, wherein the first single-qubit logic gate is a first instantiation of a Pauli X-gate and the second single-qubit logic gate is a second instantiation of a Pauli X-gate. In other embodiments, the first parameter corresponds to an exchange angle of the multi-qubit logic gate, wherein the first single-qubit logic gate is a first instantiation of a Pauli X-gate and the second single-qubit logic gate is a first instantiation of a Pauli Y-gate.

[0052] The first quantum state of the first qubit may correspond to an eigenstate of the X observable of the first qubit, and the second quantum state of the second qubit corresponds to an eigenstate of the X observable of the second qubit. In other embodiments, the first quantum state of the first qubit corresponds to an eigenstate of the X observable of the first qubit, and the second quantum state of the second qubit corresponds to an eigenstate of the Y observable of the second qubit. The first parameter corresponds to a swap angle of the multi-qubit logic gate, and the multi-qubit logic gate operates as a controlled Z gate (CZ gate).

[0053] Implementations of the digital, classical, and / or quantum subject matter, and digital functional and quantum operations described herein may be implemented in digital electronic circuitry, suitable quantum circuitry, or more generally, quantum computing systems, tangibly embodied digital and / or quantum computer software or firmware, digital and / or quantum computer hardware, including the structures disclosed herein and their structural equivalents, or one or more combinations thereof. The term "quantum computing system" may include, but is not limited to, a quantum computer / computing system, a quantum information processing system, a quantum cryptography system, or a quantum simulator.

[0054] Embodiments of the digital and / or quantum subject matter described herein may be implemented as one or more digital and / or quantum computer programs, i.e., as one or more modules of digital and / or quantum computer program instructions encoded on a tangible, non-transitory storage medium for execution by or control the operation of a data processing device. The digital and / or quantum computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubits / qubit structures, or a combination of one or more thereof. Alternatively or additionally, the program instructions may be encoded on an artificially generated propagated signal (e.g., a machine-generated electrical, optical, or electromagnetic signal) capable of encoding digital and / or quantum information, generated to encode the digital and / or quantum information for transmission to a suitable receiver device for execution by a data processing device.

[0055] The terms quantum information and quantum data refer to information or data conveyed by, held by, or stored within a quantum system, with the smallest nontrivial system being a qubit, i.e., a system defining a unit of quantum information. The term "qubit" is understood to encompass all quantum systems that can be appropriately approximated as a two-level system in a corresponding context. Such quantum systems may include, for example, multi-level systems having two or more levels. By way of example, such systems may include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the computational basis states are specified as the ground state and the first excited state, although it is understood that other devices are possible in which the computational states are specified as higher-level excited states (e.g., qubits).

[0056] The term "data processing apparatus" refers to digital and / or quantum data processing hardware and encompasses all types of apparatus, devices, and machines for processing digital and / or quantum data, including, by way of example, a programmable digital processor, a programmable quantum processor, a digital computer, a quantum computer, or multiple digital and quantum processors or computers, as well as combinations thereof. An apparatus may also be or include special-purpose logic circuits, such as FPGAs (field-programmable gate arrays), ASICs (application-specific integrated circuits), or quantum simulators, i.e., quantum data processing apparatuses designed to simulate or generate information about specific quantum systems. In particular, quantum simulators are special-purpose quantum computers that do not have the capability to perform universal quantum computations. In addition to hardware, an apparatus may also optionally include code that creates an execution environment for digital and / or quantum computer programs, such as code constituting processor firmware, protocol stacks, database management systems, operating systems, or one or more combinations thereof.

[0057] A digital or classical computer program may also be referred to or written as a program, software, software application, module, software module, script, or code, and may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a digital computing environment. A quantum computer program may also be referred to as a program, software, software application, module, software module, script, or code, and may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and may be converted to or written in a suitable quantum programming language, such as QCL, Quipper, Cirq, etc.

[0058] A digital and / or quantum computer program may correspond to a file in a file system, but this is not necessarily the case. A program may be stored in a portion of a file holding other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program, or in multiple linked files, e.g., files storing one or more modules, subprograms, or code portions. A digital and / or quantum computer program may be deployed to run on one digital or quantum computer, or on multiple digital and / or quantum computers located at one location, or on multiple computers distributed across multiple locations and interconnected by a digital and / or quantum data communication network. A quantum data communication network is understood to be a network capable of transmitting quantum data using quantum systems, e.g., qubits. While digital data communication networks generally cannot transmit quantum data, quantum data communication networks can transmit both quantum data and digital data.

[0059] The processes and logic flows described herein may be performed by one or more programmable digital and / or quantum computers equipped with one or more digital and / or quantum processors, as appropriate, executing one or more digital and / or quantum computer programs that perform functions by operating on input digital and quantum data to generate output. The processes and logic flows may also be implemented by special purpose logic circuitry, e.g., FPGAs or ASICs, or quantum simulators, or a combination of special purpose logic circuitry or quantum simulators with one or more programmed digital and / or quantum computers.

[0060] A system of one or more digital and / or quantum computers or processors is "configured" or "operable" to perform a particular operation or action means that the system has installed thereon software, firmware, hardware, or a combination thereof that causes the system to perform the operation or action when in operation. One or more digital and / or quantum computer programs are configured to perform a particular operation or action means that the program or programs contain instructions that, when executed by a digital and / or quantum data processing device, cause the device to perform the operation or action. A quantum computer may receive instructions from a digital computer that, when executed by a quantum computing device, cause the device to perform the operation or action.

[0061] A digital and / or quantum computer suitable for executing a digital and / or quantum computer program may be based on a general-purpose or dedicated digital and / or quantum microprocessor, or both, or any other kind of central digital and / or quantum processing unit. Typically, the central digital and / or quantum processing unit receives instructions and digital and / or quantum data from a read-only memory, or a random access memory, or a quantum system suitable for transmitting quantum data, e.g., photons, or a combination thereof.

[0062] Some exemplary elements of a digital and / or quantum computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and digital and / or quantum data. The central processing unit and memory may be supplemented by or incorporated into special-purpose logic circuitry or a quantum simulator. Generally, a digital and / or quantum computer includes one or more mass storage devices for storing digital and / or quantum data, such as, for example, magnetic, magneto-optical, optical disks, or quantum systems suitable for storing quantum information, or is operably coupled to receive digital and / or quantum data from them, transfer digital and / or quantum data to them, or both. However, a digital and / or quantum computer need not have such devices.

[0063] Digital and / or quantum computer-readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include, by way of example, all forms of non-volatile digital and / or quantum memories, media, and memory devices, including semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices, magnetic disks, e.g., internal hard disks or removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks, and quantum systems, e.g., trapped atoms or electrons. Quantum memory is understood to be a device capable of long-term storage of quantum data with high fidelity and efficiency, such as, for example, a light-matter interface where light is used for transmission and matter is used for storage and preservation of quantum properties of the quantum data, such as superposition or quantum coherence.

[0064] Control of the various systems described herein, or portions thereof, may be implemented in a digital and / or quantum computer program product stored on one or more tangible, non-transitory, machine-readable storage media and including instructions executable on one or more digital and / or quantum processing devices. The systems described herein, or portions thereof, may each be implemented as an apparatus, method, or electronic system that may include one or more digital and / or quantum processing devices and memory for storing executable instructions for performing the operations described herein.

[0065] While this specification contains many details of specific embodiments, these should not be construed as limiting the scope of what may be claimed, but rather as descriptions of features that may be inherent in particular embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features of the invention that are described in the context of a single embodiment may also be provided in multiple embodiments separately or in any suitable subcombination. Furthermore, while features may be described above as operating in a particular combination and may initially be claimed as such, one or more features from a claimed combination may, in some cases, be deleted from the combination, and the claimed combination may be directed to a subcombination or a variation of the subcombination.

[0066] Similarly, while operations are shown in the figures in a particular order, this should not be understood as requiring that such operations be performed in the particular order or sequence shown, or that all of the illustrated operations be performed, to achieve desirable results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the above-described program components and systems may generally be integrated together in a single software product or packaged in multiple software products.

[0067] Specific embodiments of the present invention have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims may be performed in a different order and still produce desirable results. By way of example, the processes depicted in the accompanying figures do not necessarily require the particular order shown or sequential order to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. 1. A method for characterizing a multi-qubit logic gate operable to operate on a pair of qubits including a first qubit and a second qubit, comprising: iteratively performing a set of serial operations on the pair of qubits by a multi-qubit quantum circuit included in a quantum computing system, the multi-qubit quantum circuit including at least the multi-qubit logic gate, a first single-qubit logic gate enabled to operate on the first qubit, and a second single-qubit logic gate enabled to operate on the second qubit, the set of serial operations including a first operation having the multi-qubit logic gate operating on the pair of qubits and a second operation having the first single-qubit logic gate operating on the first qubit in parallel to the second single-qubit logic gate operating on the second qubit; measuring a first quantum state of the first qubit in the quantum computing system after repeatedly performing the set of serial operations on the pair of qubits; measuring a second quantum state of the second qubit in the quantum computing system after repeatedly performing the set of serial operations on the pair of qubits; determining, in the quantum computing system, a first set of expectation values ​​for the first qubit based on the first quantum state of the first qubit; determining, in the quantum computing system, a second set of expectations for the second qubit based on the second quantum state of the second qubit; determining, in the quantum computing system, a value for at least a first parameter of a set of parameters of the multi-qubit logic gate based on the first set of expectation values ​​for the first qubit and the second set of expectation values ​​for the second qubit; A method comprising:

2. 2. The method of claim 1, wherein the multi-qubit logic gate is a fermion simulation (fSim) gate, and the first parameter corresponds to a control phase of the fSim gate.

3. 2. The method of claim 1, wherein the multi-qubit logic gate is a fermion simulation (fSim) gate and the first parameter corresponds to an exchange angle of the fSim gate.

4. The first parameter corresponds to a control phase of the multi-qubit logic gate, and the method further comprises: preparing an initial quantum state of the first qubit in a vacuum state in the quantum computing system before iteratively performing the set of serial operations on the pair of qubits; preparing an initial quantum state of the second qubit in the quantum computing system at a first Hadamard state before repeatedly performing the set of serial operations on the pair of qubits; The method of claim 1 , comprising:

5. The first parameter corresponds to a swap angle of the multi-qubit logic gate, and the method further comprises: preparing an initial quantum state of the first qubit in a vacuum state in the quantum computing system before iteratively performing the set of serial operations on the pair of qubits; preparing an initial quantum state of the second qubit in the quantum computing system at a first excited state before repeatedly performing the set of serial operations on the pair of qubits; The method of claim 1 , comprising:

6. 10. The method of claim 1, wherein each of the first single-qubit logic gate and the second single-qubit logic gate is a Pauli gate.

7. 7. The method of claim 6, wherein the first parameter corresponds to a control phase of the multi-qubit logic gate, the first single-qubit logic gate being a first instantiation of a Pauli X-gate, and the second single-qubit logic gate being a second instantiation of the Pauli X-gate.

8. 7. The method of claim 6, wherein the first parameter corresponds to an exchange angle of the multi-qubit logic gate, the first single-qubit logic gate being a first instantiation of a Pauli X-gate, and the second single-qubit logic gate being a first instantiation of a Pauli Y-gate.

9. 2. The method of claim 1 , wherein the first quantum state of the first qubit corresponds to an eigenstate of an X observable of the first qubit, and the second quantum state of the second qubit corresponds to an eigenstate of an X observable of the second qubit.

10. 2. The method of claim 1 , wherein the first quantum state of the first qubit corresponds to an eigenstate of a Y observable for the first qubit, and the second quantum state of the second qubit corresponds to an eigenstate of a Y observable for the second qubit.

11. 2. The method of claim 1 , wherein the first quantum state of the first qubit corresponds to an eigenstate of an X observable of the first qubit, and the second quantum state of the second qubit corresponds to an eigenstate of a Y observable of the second qubit.

12. 2. The method of claim 1, wherein the first parameter corresponds to a swap angle of the multi-qubit logic gate, and the multi-qubit logic gate operates as a controlled Z gate (CZ gate).

13. 1. A quantum computing system, comprising: a pair of qubits including a first qubit and a second qubit; a multi-qubit quantum circuit including a multi-qubit gate, a first single-qubit logic gate, and a second single-qubit logic gate, wherein the multi-qubit logic gate is operable on the pair of qubits, the first single-qubit logic gate is operable on the first qubit, and the second single-qubit logic gate is operable on the second qubit; one or more processors; one or more memory devices storing computer-readable instructions that, when executed by the one or more processors, cause the one or more processors to perform operations for characterizing the multi-qubit logic gate, the operations comprising: iteratively performing, by the multi-qubit quantum circuit, a set of serial operations on the pair of qubits, the multi-qubit quantum circuit including at least the multi-qubit logic gate, a first single-qubit logic gate enabled to operate on the first qubit, and a second single-qubit logic gate enabled to operate on the second qubit, the set of serial operations including a first operation with the multi-qubit logic gate operating on the pair of qubits and a second operation with the first single-qubit logic gate operating on the first qubit in parallel to the second single-qubit logic gate operating on the second qubit; measuring a first quantum state of the first qubit after repeatedly performing the set of serial operations on the pair of qubits; measuring a second quantum state of the second qubit after repeatedly performing the set of serial operations on the pair of qubits; determining a first set of expectation values ​​for the first qubit based on the first quantum state of the first qubit; determining a second set of expectation values ​​for the second qubit based on the second quantum state of the second qubit; determining a value for at least a first parameter of a set of parameters of the multi-qubit logic gate based on the first set of expected values ​​for the first qubit and the second set of expected values ​​for the second qubit; Including, the system.

14. 14. The system of claim 13, wherein the multi-qubit logic gate is a fermion simulation (fSim) gate, and the first parameter corresponds to a control phase of the fSim gate.

15. 14. The system of claim 13, wherein the multi-qubit logic gate is a fermion simulation (fSim) gate, and the first parameter corresponds to an exchange angle of the fSim gate.

16. The first parameter corresponds to a control phase of the multi-qubit logic gate, and the method further comprises: preparing an initial quantum state of the first qubit in a vacuum state before iteratively performing the set of serial operations on the pair of qubits; preparing an initial quantum state of the second qubit in a first Hadamard state before iteratively performing the set of serial operations on the pair of qubits; The system of claim 13 , comprising:

17. The first parameter corresponds to a swap angle of the multi-qubit logic gate, and the method further comprises: preparing an initial quantum state of the first qubit in a vacuum state before iteratively performing the set of serial operations on the pair of qubits; preparing an initial quantum state of the second qubit in a first excited state before repeatedly performing the set of serial operations on the pair of qubits; The system of claim 13 , comprising:

18. 14. The system of claim 13, wherein each of the first single-qubit logic gate and the second single-qubit logic gate is a Pauli gate.

19. 19. The system of claim 18, wherein the first parameter corresponds to a control phase of the multi-qubit logic gate, the first single-qubit logic gate being a first instantiation of a Pauli X-gate, and the second single-qubit logic gate being a second instantiation of the Pauli X-gate.

20. 20. The system of claim 18, wherein the first parameter corresponds to an exchange angle of the multi-qubit logic gate, the first single-qubit logic gate being a first instantiation of a Pauli X-gate, and the second single-qubit logic gate being a first instantiation of a Pauli Y-gate.

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