Method and apparatus for stochastic analog-to-digital conversion

Abstract

The ADC includes an input, multiple quantizers, multiple feedback loops, and multiple filters. The input receives an input signal. The multiple quantizers include an Nth quantizer, which has an Nth quantizer input and an Nth quantizer output. The Nth quantizer input is connected to the input. A loop is formed around the Nth quantizer output and the Nth quantizer input and is configured to reduce the difference between the Nth quantizer output signal and the Nth reference signal in the Nth frequency domain. The multiple filters include an Nth filter. The Nth filter selects the Nth frequency domain. The feedback loop provides a means to control non-ideal effects such as comparator offset.

Description

[Technical Field]

[0001] This invention relates generally to electrical systems and electronic devices, and more particularly to analog-to-digital conversion systems and devices. [Background technology]

[0002] Some analog-to-digital converters (ADCs) use the offset of a comparator, which operates as a single-bit quantizer, as a reference signal for multi-bit quantization. This stochastic ADC based on comparator offset is reported, for example, by T. Sundstrom and A. Alvandpour in “Utilizing Process Variations for Reference Generation in a Flash ADC,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 5, pp. 364–368, May 2009, doi: 10.1109 / TCSII.2009.2019165. Using the comparator offset as a reference signal allows for the use of smaller transistors in the comparator, which is advantageous for increasing comparator speed and reducing power consumption. However, the mismatch in comparator offsets generally follows a Gaussian distribution and is therefore determined solely by probability. Because this reference signal is not linearly distributed, this type of stochastic ADC often suffers from poor linearity. Furthermore, because the placement of comparator offsets is random, an unfavorable set of comparator offsets can significantly degrade linearity performance. A similar type of stochastic ADC is found in U.S. Patent Application Publication No. US2022 / 0140835 A1 (U.S. Patent Application No. 17 / 431,888), which employs a feedback-based architecture to reduce the effective signal amplitude at the input of a set of comparators. U.S. Patent No. US 7,564,391 B2 discloses an ADC designed to handle large comparator offsets, also using a feedback loop.

[0003] Another type of stochastic ADC introduces a dithering signal as a comparison reference signal, as shown, for example, in JL Ceballos, I. Galton and GC Temes, “Stochastic analog-to-digital conversion,” 48th Midwest Symposium on Circuits and Systems, 2005, pp. 855–858 Vol. 1, doi: 10.1109 / MWSCAS.2005.1594236. The stochastic characteristics of the dithering signal are predetermined, but the dithering signal is not constant and is determined only probabilistically. It is known that linearity can be improved by using a dithering signal as a reference signal instead of the comparator offset. For example, see H. Sun, K. Sobue, K. Hamashita, and U.-K. Moon, “An Oversampling Stochastic ADC Using VCO-Based Quantizers,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 12, pp. 4037–4050, December 2018, doi: 10.1109 / TCSI.2018.2836466. However, this type of stochastic ADC requires the comparator offset to be small enough so that it does not interfere with the dithering signal. This limitation makes it difficult for a stochastic ADC using a dithering signal to take advantage of the small transistors of the comparator. A sigma-delta ADC using a stochastic ADC with a dithering signal can also be found in U.S. Patent No. 7,420,494 B1. Summary of the Invention [Problem to be solved by the invention] [Means for solving the problem]

[0004] The ADC according to the disclosed technology includes an input, multiple quantizers, multiple feedback loops, and multiple filters. The input receives an input signal. The multiple quantizers include an Nth quantizer, which has an Nth quantizer input and an Nth quantizer output. The Nth quantizer input is connected to the input. N is an integer between 1 and M, inclusive, where M is an integer greater than or equal to 2. The multiple feedback loops include an Nth feedback loop, which is formed around the Nth quantizer output and the Nth quantizer input and is configured to reduce a difference between a signal at the Nth quantizer output and an Nth reference signal in the Nth frequency domain. The multiple filters include an Nth filter, which is not located on any path that sends the input signal forward from the input to the Nth quantizer input, but is located on the Nth feedback loop. The Nth filter selects the Nth frequency domain.

[0005] Since the Nth feedback loop is configured to reduce the difference between the signal at the Nth quantizer output and the Nth reference signal in the Nth frequency domain, even if the signal at the Nth quantizer output is affected by non-ideal conditions such as a comparator offset, the signal at the Nth quantizer output can be controlled by the Nth reference signal and the Nth feedback loop. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an ADC 1 according to the first embodiment. [Figure 2] FIG. 2 is a flowchart showing the analog-to-digital conversion method according to the first embodiment. [Figure 3] FIG. 3 is a diagram illustrating the ADC 2 according to the second embodiment. [Figure 4] FIG. 4 is a diagram illustrating the ADC 3 according to the third embodiment. [Figure 5] FIG. 5 is a diagram illustrating the sigma-delta ADC 4 according to the fourth embodiment. [Figure 6] FIG. 6 is a circuit diagram of a global DAC 403 according to the fourth embodiment. [Figure 7] FIG. 7 is a diagram illustrating an ADC 6 in accordance with an embodiment of the present technology. [Figure 8] FIG. 8 is a diagram illustrating a sigma-delta ADC in accordance with an embodiment of the present technology. DETAILED DESCRIPTION OF THE INVENTION

[0007] First Embodiment 1 (an example of an analog-to-digital converter) has an input 10, an output 11, multiple quantizers 12, multiple feedback loops 13, multiple filters 14, multiple summing sections 15, an output stage 16, multiple digital-to-analog converters (DACs) 17, and multiple forward paths 18. The number of quantizers 12 is M, where M is an integer equal to or greater than 2. N is an integer equal to or greater than 1 and equal to or less than M. That is, 1≦N≦M and 2≦M.

[0008] The input 10 (an example of an input) is configured to receive an analog signal to be converted into a corresponding digital signal. The analog signal may be either a continuous signal or a discrete signal. For example, if an analog signal is sampled and held at a fixed clock period, the sampled and held signal is a discrete signal but is still an analog signal. The output 11 is configured as a terminal or a group of terminals from which a digital signal is output. The multiple quantizers 12 (an example of a multiple quantizer) include first through Mth quantizers. That is, the first quantizer 120b, the Nth quantizer 120a (an example of the Nth quantizer), and the Mth quantizer 120c are all included in the multiple quantizers 12. In this embodiment, each of the multiple quantizers 12 is a single-bit quantizer. The Nth quantizer 120a has an Nth quantizer input 121a (an example of the Nth quantizer input) and an Nth quantizer output 122a (an example of the Nth quantizer output). The Nth quantizer input 121a is connected to the input 10 via an adder 15a. The first quantizer 120b has a first quantizer input 121b and a first quantizer output 122b, and the Mth quantizer 120c has an Mth quantizer input 121c and an Mth quantizer output 122c. The multiple quantizers 12 quantize the signals at their quantizer inputs every clock period defined by the clock signal. The output signals of the multiple quantizers 12 are binary. In the Nth quantizer 120a, if the signal at the Nth quantizer input 121a is greater than a particular threshold, i.e., a reference value, the signal at the Nth quantizer output 122a is high; otherwise, the output signal is low. The other quantizers operate in a similar manner. In this embodiment, the thresholds of the multiple quantizers 12 are nominally zero, but consider the case where the thresholds are different due to random offsets. The plurality of feedback loops 13 (an example of a plurality of feedback loops) includes a first feedback loop 13b to an M-th feedback loop 13c.The Nth feedback loop 13a (an example of an Nth feedback loop) is formed around the Nth quantizer output 122a and the Nth quantizer input 121a, and is configured to reduce the difference between the Nth quantizer output 122a and the Nth reference signal 19a (an example of an Nth reference signal) in the low-frequency domain (an example of an Nth frequency domain). In this embodiment, the Nth feedback loop 13a includes an Nth quantizer 120a, an Nth DAC 17a, an Nth filter 14a, and an Nth adder 15a. The first feedback loop 13b to the Mth feedback loop 13c are all formed in the same manner as the Nth feedback loop 13a. The multiple filters 14 (an example of multiple filters) include the first filter 14b to the Mth filter 14c. The Nth filter 14a (an example of an Nth filter) is arranged on the Nth feedback loop 13a and is located between the Nth quantizer output 122a and the Nth quantizer input 121a. The Nth filter 14a is not on the forward path 18a or any other path that forwards the input signal from the input 10 to the Nth quantizer input 121a. The Nth filter 14a is configured to select the Nth frequency region. That is, in this embodiment, the Nth filter 14a is a low-pass filter that acts to reduce the difference between the Nth reference signal and the single-bit output signal of the Nth quantizer output 122a in the low-frequency region. The gain of the Nth filter 14a is high in the low-frequency region and low in other frequency regions, thereby selecting the low-frequency region. In this embodiment, the first filter 14b through the Mth filter 14c are also low-pass filters and are associated with the first feedback loop 13b through the Mth feedback loop 13c, respectively. These filters are arranged in the same manner as the Nth filter 14a with respect to the first reference signal 19b through the Mth reference signal 19c, respectively. The plurality of adder units 15 (an example of a plurality of adder units) includes a first adder unit 15b to an M-th adder unit 15c. The N-th adder unit 15a (an example of an N-th adder unit) is disposed on the N-th feedback loop 13a and is configured to provide the difference between the signal at the input 10 (an example of an input signal and an analog signal) and the signal coming from the N-th filter 14a to the N-th quantizer input 121a.In the Nth adder 15a, the signal from the Nth filter 14a is subtracted from the signal at the input 10, thus closing the Nth feedback loop 13a. A summing amplifier or transconductance stage can be used to create the adder 15a. It is also possible to create the Nth adder 15a as part of a comparator, as described in U.S. Patent Application Publication No. US Pat. No. 2022 / 0140835 A1. The first adder 15b through the Mth adder 15c are arranged similarly to the Nth adder 15a with respect to the signals from the first filter 14b through the Mth filter 14c, respectively. The output stage 16 connects the first through Mth quantizers to the output 11 and is configured to generate the output signal of the ADC 1. Specifically, in this embodiment, the output stage 16 averages the outputs of the first through Mth quantizers to generate the output signal at the output 11. In this embodiment, the outputs of the first to Mth quantizers are single-bit signals, so averaging is performed in the digital domain. As a result, the output signal is obtained as a digital signal. The multiple DACs 17 include a first DAC 17b to an Mth DAC 17c. Each of the multiple DACs 17 is a single-bit DAC, and may use a known topology such as a current steering DAC or a resistive DAC.

[0009] The signal flow in ADC 1 can also be seen from FIG. 1. ADC 1 has multiple forward paths 18, which are configured to connect input 10 and output 11. The multiple forward paths 18 include forward path 18b through forward path 18c. An Nth quantizer 120a is located on forward path 18a (an example of a path that sends the input signal forward from the input to the Nth quantizer input), quantizer 120b is located on forward path 18b, and quantizer 120c is located on forward path 18c, and so on. Multiple quantizers 12 are connected in parallel to input 10 along multiple forward paths 18, and the signal at input 10 is individually quantized by the multiple quantizers 12. The signal at Nth quantizer output 122a is converted to an analog signal by an Nth DAC 17a, and then an Nth reference signal 19a is subtracted from the output signal of the Nth DAC 17a. The difference signal between the signal at the Nth quantizer output 122a and the Nth reference signal 19a is filtered by the Nth filter 14a and processed again by the Nth quantizer 120a. The signal flow around the Nth quantizer output 122a and the Nth quantizer 121a forms the Nth feedback loop 13a, which reduces the difference between the signal at the Nth quantizer output 122a and the Nth reference signal 19a in the frequency domain determined by the Nth filter 14a. In this embodiment, the Nth filter 14a is not on the Nth forward path 18a. The loop gain of the Nth feedback loop 13a is provided by the Nth quantizer 120a and / or the filter 14a.

[0010] In this embodiment, each of the multiple quantizers 12 is a single-bit quantizer, and therefore the multiple quantizers 12 can be implemented with comparators. Comparators are typically implemented using transistors, and modern semiconductor technology is utilized to realize these transistors and other components. The threshold voltage of a comparator typically contains a random offset or deviation from its target value due to limitations in the precision of the semiconductor manufacturing process. This offset can cause the quantization results to vary from quantizer to quantizer, even if the exact same input signal is applied to each quantizer. In ADC1, this effect of the offset on quantization in the Nth quantizer 120a is controlled by feedback loop 13a.

[0011] A method for converting an analog signal to a digital signal using the techniques disclosed herein is shown in FIG. 2. In step S1001, an input 10 receives an analog signal. In step S1002, a plurality of quantizers 12 perform quantization. In step S1003, an Nth feedback loop 13a formed around the Nth quantizer output 122a and the Nth quantizer output 121a is used to reduce the difference between the Nth quantizer output 122a and the Nth reference signal 19a in the Nth frequency domain. In step S1004, an Nth frequency domain is selected using an Nth filter 14a disposed on the Nth feedback loop 13a and positioned between the Nth quantizer output 122a and the Nth quantizer input 121a. It should be noted that steps S1003 and S1004 are typically performed as a single process because the Nth filter 14a is on the Nth feedback loop 13a. In step S1005, the difference between the signal at input 10, which is the analog signal to be converted, and the signal coming from the Nth filter 14a is applied to the Nth quantizer input 121a via the Nth adder 15a arranged on the Nth feedback 13a. The Nth quantizer 120a performs quantization on this signal applied via the Nth adder 15a in step S1001.

[0012] Second Embodiment FIG. 3 shows an ADC2 (an example of an analog-to-digital converter) according to a second embodiment. The ADC2 has an input 20 (an example of an input), an output 21, and common components with the ADC1, and these common components are designated by the same reference numerals as the ADC1. Only differences from the ADC1 will be described in detail. The ADC2 also has a DAC 22 (an example of a signal converter) that converts the signals from the first through Mth quantizer outputs into analog signals (an example of converted signals). The signals from the first through Mth quantizer outputs are averaged when converted by the DAC 22. Specifically, the signals from the first quantizer output 122b through the Mth quantizer output 122c are added together and divided by M. This averaging process is primarily performed in the analog domain in this embodiment, i.e., after digital-to-analog conversion. However, this averaging process may also be performed in the digital domain, or in both the digital and analog domains. The analog signals generated by converting the signals from the first through Mth quantizer outputs are used as the Nth reference signal 29a and all other reference signals. This means that all of the first reference signal 29a to the Mth reference signal 29c are this common analog signal through conversion.

[0013] As mentioned above, the signals output from the first through Mth quantizers tend to differ from one another due to mismatches in the offsets of the multiple quantizers 12. The first through Mth feedback loops operate to reduce the differences between these signals output from the first through Mth quantizers. For example, the input offset of a comparator used as the Nth quantizer 120a is specific to this quantizer, and if the Nth feedback loop 13a did not exist, the same offset value would always be added to the input signal at the first quantizer input. The Nth feedback loop 13a operates to equalize the effect of this offset of the Nth quantizer 120a with the effect of the offsets of the other quantizers in the Nth frequency region selected by the Nth filter 14a. This action distributes the effect of the offset of the Nth quantizer 120a to the other quantizers, causing the offset to appear as a random pseudo-dithering signal.

[0014] <Third embodiment> An ADC3 according to a third embodiment is shown in FIG. 4. The ADC3 has an input 30 (an example of an input), an output 31, and common components with the ADC1, and these common components are designated by the same reference numerals as the ADC1. As with the previous embodiments, the quantization is governed by a clock signal, but the clock signal is omitted from FIG. 4. The ADC3 is shown with M=4. In the ADC3, the reference signal is one of the signals output by the other quantizers, or a delayed version of the same. Specifically, the Nth reference signal 39a is the signal from the first quantizer output 122b. Meanwhile, the first reference signal 39b is the signal from the Mth quantizer output 122c. Similarly, the Mth reference signal 39c is the signal from the output of an adjacent quantizer.

[0015] Because the quantizer output signal is cyclically used as a reference signal for other feedback loops, the effects of the offsets of the multiple quantizers 12 are distributed evenly in the frequency range selected by the filter 14. As a result, the offsets that were originally inherent to the quantizers are perturbed to appear as random pseudo-dithering signals, just as in the ADC 2.

[0016] <Fourth embodiment> A sigma-delta ADC 4 (an example of a sigma-delta analog-to-digital converter) according to a fourth embodiment is shown in FIG. 5. The sigma-delta ADC 4 includes the ADC 2 according to the second embodiment, a global input 401, a global output 402, a global DAC 403, a global adder 404, a loop filter 405, and a high-speed path 406. The global input 401 (an example of a global input) receives an analog signal to be converted into a corresponding digital signal. The global output 402 is a terminal connected to the output 21 of the ADC 2 and is configured to output a digital output signal. The global DAC 403 (an example of a global digital-to-analog converter) is configured to generate a feedback signal in response to signals from the outputs of the multiple quantizers 12. More specifically, the signals from the first quantizer output 122b to the Mth quantizer output 122c are converted into analog signals by the global DAC 403 and averaged. The global DAC 403 may include a signal delay. This delay accounts for a portion of the excess loop delay of the sigma-delta ADC 4. This excess loop delay includes delays due to the quantization process by the multiple quantizers 12, delays due to signal buffering, delays due to digital-to-analog conversion, and sometimes intentionally added delays. The fast path 406 is added to compensate for this excess loop delay. The global summer 404 (an example of a global summer) is coupled to the global input 401 and configured to provide the difference between the signal at the global input 401, i.e., the global input signal, and the feedback signal generated by the global DAC 403. The global summer 404 may be implemented, for example, as part of the first integrator in the loop filter 405. The loop filter 405 is coupled between the global summer 404 and the input 20 of the ADC 2 and operates in response to the global summer 404. The loop filter 405 is used to define the signal bandwidth of the sigma-delta ADC 4. Loop filter 405 is also used to provide the loop gain for the sigma-delta ADC 4, but could alternatively be a passive loop filter.The loop filter 405 may be, for example, a cascade-of-integrators feedback / feedforward type, a cascade-of-resonators feedback / feedforward type, or a mixture thereof.

[0017] To implement the global DAC 403, a single-element DAC can be used, as shown in FIG. 6. In this embodiment, the global DAC 403 is a current-steering DAC, consisting of M elements (current-steering units) of equal size arranged side by side, with the ON / OFF states of the elements controlled by the output signals of multiple quantizers 12. The signals from the first quantizer output 122b through the Mth quantizer output 122c are applied to the switches of the corresponding current-steering units of the global DAC 403 without being coded or decoded. The currents from the elements of the global DAC 403 are collected by resistors, and the output voltage is obtained as a differential signal at DAC outputs 403a and 403b. The currents of the elements of the global DAC 403 are generally different from each other because the current sources constituting each element are not completely identical due to variations in conditions such as process, bias voltage, and temperature. Variations in the feedback DAC elements in a sigma-delta ADC often degrade the linearity performance of the DAC. In the ADC2, an Nth feedback loop 13a is formed around the Nth quantizer output 122a and the Nth quantizer input 121a and is configured to reduce the difference between the signal at the Nth quantizer output 122a and the Nth reference signal 29a in an Nth frequency region selected by an Nth filter 14a. Furthermore, the ADC2 includes a DAC 22 configured to convert the signals at the first through Mth quantizer outputs into transformed signals, and the Nth reference signal is this transformed signal. This configuration encourages the signals at the first through Mth quantizer outputs 122b through 122c to be similar in the low-frequency region. This low-frequency region is selected by multiple filters 14 in this embodiment. This means that the elements of the global DAC 403 are driven by input signals that are similar to each other in the low-frequency region. As a result, variations among elements of the DAC 403 are averaged in accordance with the frequency characteristics of the Nth filter 14a (1≦N≦M), suppressing degradation of linearity in the sigma-delta ADC 4. In other words, mismatch shaping can be achieved in the sigma-delta ADC 4.The advantageous effect of mismatch shaping can be obtained regardless of the type of DAC 403, and other types of DACs such as a resistive DAC or a capacitive DAC may also be used as the DAC 403.

[0018] The ADC 2 used in the sigma-delta ADC 4 includes an Nth filter 14a. The Nth filter 14a is not connected in series or cascade with the loop filter 405. In other words, the Nth filter 14a and the loop filter 405 are not on a common forward path starting from the global input 401 and ending at the global output 402. More specifically, the Nth adder 15a is on the Nth feedback loop 13a and configured to provide the difference between the signal at the input 20 of the ADC 2 and the signal from the Nth filter 14a to the Nth quantizer input 121a. The Nth adder 15a is on the forward path where the loop filter 405 is located. However, the Nth filter 14a is on the Nth feedback loop 13a but is located before the Nth adder 15a, and therefore is not on the forward path of the sigma-delta ADC 4. If the Nth filter 14a and the loop filter 405 are in the same forward path, the Nth filter 14a will have a greater effect on the noise transfer function of the sigma-delta ADC 4, which will degrade the stability of the sigma-delta ADC 4. In the ADC 2, the Nth filter 14a is not cascaded with the loop filter 405, which reduces the degradation of stability.

[0019] <Other embodiments> The configuration of the present invention shown here is not limited to the above-described embodiment, and may be modified as long as it achieves the same purpose as intended by the present invention.

[0020] The Nth filter 14a is not limited to a low-pass filter and may be other types of filters, such as a band-pass filter or a lead-lag filter. Furthermore, the bands of the first filter 14b through the Mth filter 14c do not necessarily have to be the same and may be different from each other. For example, if the multiple filters 14 are low-pass filters such as single-pole amplifiers, their poles define the first through Mth frequency ranges. In this case, the pole locations of the first through Mth filters may be the same or may be selected to be different from each other. As in the ADC 6 shown in FIG. 7, a replica of the first filter 14a may be used for the Nth reference signal 19a. The ADC 6 includes a filter 601 (an example of a part that selects the Nth frequency range for the Nth reference signal instead of the Nth filter), which replicates the Nth filter 14a. This allows the signal summation point to be moved to the output of the Nth filter 14a. The filter 601 does not need to be exactly the same as the Nth filter 14a. For example, the filter 601 may have different poles and / or zeros than the Nth filter 14a. The Nth quantizer 120a is not limited to a single-bit quantizer and may be a multi-bit quantizer. This is because, when the technology disclosed herein is applied to a sigma-delta ADC equipped with multiple multi-bit quantizers, mismatch shaping occurs between the multi-bit quantizers, similar to that occurring between single-bit quantizers. Although not explicitly shown in the figure, the multiple feedback loops 13 may include signal delays. This signal delay is partially due to delays caused by processes such as quantization by the multiple quantizers 12, signal buffering, and digital-to-analog conversion by the multiple DACs 17. In the above-described embodiment, a comparator offset due to process variations is used to achieve multi-bit analog-to-digital conversion. However, this offset may be intentionally added. The effect of this intentionally applied offset is equalized by the Nth feedback loop 13a (1≦N≦M), similar to what happened to the comparator's inherent offset in the previous embodiment, where the intentionally applied offset results in a dither-like behavior.In the ADC 2 of the second embodiment, the averaging weights in the DAC 22 are uniform. However, averaging may be performed using other types of weights, such as non-uniform weights. Here, averaging also includes simple summation. In the above-described embodiments, the signal is not limited to voltage, but may be other types such as current, pulse width, count, phase, etc. It is also possible to use a signal different from that in the above-described embodiments as the Nth reference signal 19a. One example is shown in FIG. 8 as a sigma-delta ADC 7. The sigma-delta ADC 7 has a global input 701, a global output 702, a sample-and-hold circuit 703, a delay 704, and an ADC1. Components common to the sigma-delta ADC 4 are denoted by the same reference numerals. The input signal of the global input 701 is sampled and held by the sample-and-hold circuit 703, delayed by one cycle of the sampling clock by the delay 704, and then used as the first to Mth reference signals 19b to 19c. [Industrial Applicability]

[0021] The techniques disclosed herein can be applied to analog-to-digital converters where high speed sampling is required.

Claims

1. An analog-to-digital converter, an input for receiving an input signal; a plurality of quantizers including an Nth quantizer having an Nth quantizer output and an Nth quantizer input coupled to said input, where M is an integer greater than or equal to 2 and N is an integer greater than or equal to 1 and less than or equal to M; a plurality of feedback loops including an N-th feedback loop formed around the N-th quantizer output and the N-th quantizer input, which reduces a difference between the N-th quantizer output signal and an N-th reference signal in an N-th frequency domain; a plurality of filters including an Nth filter that is not positioned on any path forwarding the input signal from the input to the Nth quantizer input, but is positioned on the Nth feedback loop and selects the Nth frequency region; An analog-to-digital converter having:

2. 2. The analog-to-digital converter according to claim 1, further comprising a signal converter that converts the signals of the first to Mth quantizer outputs into converted signals, and the Nth reference signal is at least one of the converted signals and delayed versions of the converted signals.

3. a signal converter that converts the signals output from the first to M-th quantizers into converted signals, and the N-th reference signal is at least one of the converted signal and a delayed version of the converted signal; 2. The analog-to-digital converter according to claim 1, wherein the signals of the first through Mth quantizer outputs are averaged when converted by the signal converter.

4. 2. The analog-to-digital converter of claim 1, wherein the N filters are low-pass filters.

5. 2. The analog-to-digital converter of claim 1, wherein the N quantizers are single-bit quantizers.

6. 2. The analog-to-digital converter of claim 1, further comprising a section for selecting the Nth frequency region for the Nth reference signal in place of the Nth filter.

7. 1. A sigma-delta analog-to-digital converter, comprising: an analog-to-digital converter having: (a) an input for receiving an input signal; (b) a plurality of quantizers, including an Nth quantizer, where M is an integer greater than or equal to 2 and N is an integer greater than or equal to 1 and less than or equal to M, having an Nth quantizer output and an Nth quantizer input connected to the input; (c) a plurality of feedback loops, including an Nth feedback loop, formed around the Nth quantizer output and the Nth quantizer input, reducing a difference between a signal at the Nth quantizer output and an Nth reference signal in an Nth frequency domain; and (d) a plurality of filters, including an Nth filter, not located on any path forwarding the input signal from the input to the Nth quantizer input, but located on the Nth feedback loop and selecting the Nth frequency domain; a global input for receiving a global input signal; a global digital-to-analog converter that generates a feedback signal in response to the first to Mth quantizer output signals; a global adder providing the difference between the global input signal and the feedback signal; a loop filter coupled between the global summer and the input of the analog-to-digital converter and operative in response to the global summer; A sigma-delta analog-to-digital converter having

8. 8. The sigma-delta analog-to-digital converter according to claim 7, further comprising a signal converter that converts the signals of the first to Mth quantizer outputs into converted signals, and the Nth reference signal is at least one of the converted signals and delayed versions of the converted signals.

9. a signal converter that converts the signals output from the first to M-th quantizers into converted signals, and the N-th reference signal is at least one of the converted signal and a delayed version of the converted signal; 8. The sigma-delta analog-to-digital converter according to claim 7, wherein the signals of the first through Mth quantizer outputs are averaged when converted by the signal converter.

10. 8. The sigma-delta analog-to-digital converter of claim 7, wherein the N filter is a low-pass filter.

11. 8. The sigma-delta analog-to-digital converter of claim 7, wherein the N quantizers are single-bit quantizers.

12. 8. The sigma-delta analog-to-digital converter of claim 7, further comprising a portion for selecting the Nth frequency region for the Nth reference signal in place of the Nth filter.

13. 1. A method for converting an analog signal to a digital signal, comprising: receiving the analog signal via an input; performing quantization with a plurality of quantizers, including an Nth quantizer having an Nth quantizer output and an Nth quantizer input coupled to said input, where M is an integer greater than or equal to 2 and N is an integer greater than or equal to 1 and less than or equal to M; Reducing the difference between the signal at the Nth quantizer output and an Nth reference signal in the Nth frequency domain using an Nth feedback loop formed around the Nth quantizer output and the Nth quantizer input; selecting the Nth frequency region using an Nth filter that is not positioned on any path forwarding the input signal from the input to the Nth quantizer input, but is positioned on the Nth feedback loop; A method for converting an analog signal to a digital signal, comprising:

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