Liquid-cooled compact power system

Abstract

The apparatus may include a device having a metal structure, a metal element, a metal pedestal, and a transistor. The metal structure, the metal element, and the metal pedestal each have a first surface and a second surface that are substantially flat and facing each other. The transistor may have a first terminal and a second terminal, each having a substantially flat and facing first surface and a second surface. The first surface of the metal pedestal may be sintered to the second surface of the metal element. The first and second surfaces of the first and second terminals, respectively, may be sintered to the first and second surfaces of the metal structure and the metal pedestal, respectively. The second surface of the metal structure may be electrically and thermally connected to a bus bar.

Description

[Background technology]

[0001] Power systems use power semiconductors, including power transistors and power diodes. A power converter is an example of a power system. A power converter converts power. An "inverter" is a type of power converter. An inverter converts direct current (DC) power to alternating current (AC) power. A "rectifier" is another type of power converter. A rectifier converts AC power to DC power. A DC-DC converter (e.g., a buck, boost, or buck-boost converter) converts DC power at one voltage level to DC power at another voltage level. An AC-AC converter (e.g., a variable frequency drive, matrix converter, etc.) converts AC power in one form to AC power in another form. Some AC-AC converters include a DC link electrically connected between the rectifier and the inverter, converting AC power at one frequency to AC power at another frequency.

[0002] The present technology may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. [Brief explanation of the drawings]

[0003] [Figure 1A] FIG. 2 illustrates relevant components of an example three-phase inverter. [Figure 1B] FIG. 4 is a timing diagram illustrating an example of a gate control signal. [Figure 1C] FIG. 1 illustrates relevant components of an example three-phase rectifier. [Figure 2A-1] FIG. 1 illustrates a top view of an example packaged switch. [Figure 2A-2] FIG. 1 illustrates a bottom view of an example packaged switch. [Figure 2A-3] FIG. 1 is a side view of an example packaged switch. [Figure 2B-1] FIG. 1 illustrates a top view of an example packaged switch. [Figure 2B-2]FIG. 1 illustrates a bottom view of an example packaged switch. [Figure 2B-3] FIG. 1 is a side view of an example packaged switch. [Figure 2C-1] FIG. 1 illustrates a top view of an example packaged switch. [Figure 2C-2] FIG. 1 illustrates a bottom view of an example packaged switch. [Figure 2C-3] FIG. 1 is a side view of an example packaged switch. [Figure 2D-1] FIG. 1 illustrates a top view of an example packaged switch. [Figure 2D-2] FIG. 1 illustrates a bottom view of an example packaged switch. [Figure 2D-3] FIG. 1 is a side view of an example packaged switch. [Figure 2E-1] FIG. 1 is a top view of an example packaged diode. [Figure 2E-2] FIG. 1 is a bottom view of an example packaged diode. [Figure 2E-3] FIG. 1 is a side view of an example of a packaged diode. [Figure 2F] FIG. 1 is a top view illustrating a portion of an example of a transistor. [Figure 2G] FIG. 1 is a side view illustrating a portion of an example of a transistor. [Figure 2H] FIG. 2 is a side view showing a portion of an example of a laminate sheet. [Figure 3A] FIG. 1 illustrates an example of a packaged switch. [Figure 3B] FIG. 1 illustrates an example of a packaged switch. [Figure 3C] FIG. 1 illustrates an example of a packaged switch. [Figure 3D] FIG. 1 illustrates an example of a packaged switch. [Figure 3E] FIG. 1 illustrates an example of a packaged switch. [Figure 3F] FIG. 1 illustrates an example of a packaged switch. [Figure 3G]FIG. 1 illustrates an example of a packaged switch. [Figure 3H] FIG. 1 illustrates an example of a packaged switch. [Figure 3I] FIG. 1 illustrates an example of a packaged switch. [Figure 3J] FIG. 1 illustrates an example of a packaged switch. [Figure 3K] FIG. 1 illustrates an example of a packaged switch. [Figure 3L] FIG. 1 illustrates an example of a packaged switch. [Figure 3M] FIG. 1 illustrates an example of a packaged diode. [Figure 3N] FIG. 1 illustrates an example of a packaged diode. [Figure 3O] FIG. 1 illustrates an example of a packaged switch. [Figure 3P] FIG. 1 illustrates an example of a packaged switch. [Figure 4A-1] 1A and 1B are top and side views of an example die substrate. [Figure 4A-2] 1A and 1B are top and side views of an example die substrate with an example transistor. [Figure 4A-3] 1A and 1B are top and side views of an example die substrate with an example transistor and a pedestal. [Figure 4A-4] 1A and 1B are top and side views of an example die clip. [Figure 4A-5] 1A and 1B are top and side views of an example switch module. [Figure 4A-6] 1A and 1B are top and side views of an example die substrate with an example transistor and a pedestal. [Figure 4A-7] 1A and 1B are top and side views of an example switch module. [Figure 4A-8] 1A and 1B are top and side views of an example die substrate with an example transistor and a pedestal. [Figure 4A-9] 1A and 1B are top and side views of an example switch module. [Figure 4B-1] 1A and 1B are top and side views of an example die substrate with an example transistor. [Figure 4B-2] 1A and 1B are top and side views of an example die substrate with an example transistor and a pedestal. [Figure 4B-3] 1A and 1B are top and side views of an example switch module. [Figure 4B-4] 1A and 1B are top and side views of an example die substrate with an example transistor and a pedestal. [Figure 4B-5] 1A and 1B are top and side views of an example switch module. [Figure 4C-1] 1A and 1B are top and side views of an example die clip with an example transistor. [Figure 4C-2] 1A and 1B are top and side views of an example switch module. [Figure 4D-1] 1A and 1B are top and side views of an example die clip with an example transistor and pedestal. [Figure 4D-2] 1A and 1B are top and side views of an example paddle. [Figure 4D-3] 1A and 1B are top and side views of an example switch module. [Figure 4E-1] 1A and 1B are top and side views of an example die substrate with an example transistor. [Figure 4E-2] 1A and 1B are top and side views of an example die clip with an example transistor. [Figure 4E-3] 1A and 1B are top and side views of an example switch module. [Figure 4F-1] 1A and 1B are top and side views of an example die substrate with an example transistor. [Figure 4F-2] 1A and 1B are top and side views of an example die substrate with an example transistor and a pedestal. [Figure 4F-3] 1A and 1B are top and side views of an example switch module. [Figure 4G-1] 1A and 1B are a top view and a side view of an example of a transistor. [Figure 4G-2]1A and 1B are top and side views of an example transistor with an example signal frame. [Figure 4G-3] 1A and 1B are top and side views of an example transistor with an example signal frame and pedestal. [Figure 4G-4] FIG. 4G-3 is a side view of the structure shown in FIG. [Figure 4G-5] FIG. 4G-3 is a cross-sectional view of the structure shown in FIG. [Figure 4G-6] 1A and 1B are top and side views of an example die substrate with an example transistor. [Figure 4G-7] 1A and 1B are top and side views of an example switch module. [Figure 4G-8] FIG. 1 is a top view of an example transistor with an example signal frame and pedestal. [Figure 4G-9] FIG. 1 is a top view of an example die substrate with an example transistor. [Figure 4G-10] FIG. 1 is a side view of an example die substrate with an example transistor. [Figure 4G-11] FIG. 2 is a side view of an example of a switch module. [Figure 4G-12] FIG. 2 is a top view of an example of a switch module. [Figure 4H] 1A and 1B are top and side views of an example of a diode module. [Figure 5A-1] FIG. 1 is a front view of an example converter without tubes. [Figure 5A-2] FIG. 1 is a side view of an example of a converter without a tube. [Figure 5A-3] FIG. 1 is a cross-sectional view of an example of a tube. [Figure 5A-4] FIG. 1 is a cross-sectional view of an example of a tube. [Figure 5A-5] FIG. 1 is a cross-sectional view of an example of a tube. [Figure 5A-6] FIG. 1 is a cross-sectional view of an example of a tube. [Figure 5A-7] FIG. 1 is a cross-sectional view of an example of a tube. [Figure 5A-8] FIG. 1 is a cross-sectional view of an example of a tube. [Figure 5A-9]FIG. 1 is a cross-sectional view of an example of a tube. [Figure 5A-10] FIG. 2 is a side view of an example of a tube. [Figure 5A-11] FIG. 2 is a side view of an example of a tube. [Figure 5A-12] FIG. 2 is a side view of an example of a tube. [Figure 5A-13] FIG. 2 is a side view of an example of a tube. [Figure 5A-14] FIG. 2 is a side view of an example of a tube. [Figure 5A-15] FIG. 2 is a side view of an example of a tube. [Figure 5A-16] FIG. 1 is a cross-sectional view of an example of a tube insert and a tube. [Figure 5A-17] FIG. 1 is a cross-sectional view of an example of a tube insert and a tube. [Figure 5A-18] FIG. 2 is a front view of an example converter. [Figure 5A-19] FIG. 2 is a side view of an example of a converter. [Figure 5A-20] FIG. 2 is a side view of an example of a converter. [Figure 5A-21] FIG. 2 is a side view of an example of a converter. [Figure 5A-22] FIG. 2 is a side view of an example of a converter. [Figure 5A-23] FIG. 2 is a side view of an example of a converter. [Figure 5A-24] FIG. 2 is a side view of an example of a converter. [Figure 5A-25] FIG. 2 is a front view of an example converter. [Figure 5A-26] FIG. 2 is a front view of an example converter. [Figure 5A-27] FIG. 2 is a side view of an example of a converter. [Figure 5B-1] FIG. 2 is a front view of an example converter. [Figure 5B-2] FIG. 2 is a side view of an example of a converter. [Figure 5C] FIG. 2 is a front view of an example converter. [Figure 5D-1] FIG. 2 is a front view of an example converter. [Figure 5D-2] FIG. 2 is a rear view of an example of a converter. [Figure 5D-3] FIG. 2 is a side view of an example of a converter. [Figure 5E-1] FIG. 2 is a front view of an example converter. [Figure 5E-2] FIG. 2 is a side view of an example of a converter. [Figure 5E-3] FIG. 2 is a side view of an example of a converter. [Figure 5F-1] FIG. 2 is a front view of an example converter. [Figure 5F-2] FIG. 2 is a side view of an example of a converter. [Figure 5F-3] FIG. 2 is a side view of an example of a converter. [Figure 5G-1] FIG. 2 is a front view of an example converter. [Figure 5G-2] FIG. 2 is a side view of an example of a converter. [Figure 5H] FIG. 2 is a front view of an example converter. [Figure 5I-1] FIG. 2 is a front view of an example converter. [Figure 5I-2] FIG. 2 is a rear view of an example of a converter. [Figure 5I-3] FIG. 2 is a side view of an example of a converter. [Figure 5J] FIG. 2 is a front view of an example converter. [Figure 5K] FIG. 2 is a front view of an example converter. [Figure 5L] FIG. 2 is a front view of an example converter. [Figure 5M] Figures 5M-1 and 5M-2 are front and side views of an example of a solid-state circuit breaker. [Figure 5N] Figures 5N-1 and 5N-2 are front and side views of an example of a solid-state circuit breaker. [Figure 5O-1] FIG. 2 is a front view of an example converter. [Figure 5O-2] FIG. 2 is a side view of an example of a converter. [Figure 5O-3] FIG. 2 is a side view of an example of a converter. [Figure 5P-1]FIG. 2 is a front view of an example converter. [Figure 5P-2] FIG. 2 is a side view of an example of a converter. [Figure 5P-3] FIG. 10 is a front view of an example of connected bus bars. [Figure 5P-4] FIG. 1 is a side view of an example of connected bus bars. [Figure 5P-5] FIG. 1 is a front view of an example of a bus. [Figure 5P-6] FIG. 2 is a side view of an example of a bus bar. DETAILED DESCRIPTION OF THE INVENTION

[0004] The use of the same reference numeral in different figures indicates the same item. A reference numeral without a letter and / or number following it generally refers to any or all elements having that reference numeral. For example, the reference numeral "204" refers to 204, 204L, 204H, 204L-1, etc., and the reference numeral "204L" refers to 204L, 204L-1, etc.

[0005] Power systems include power converters, solid-state circuit breakers (SSCBs), etc. Power converters include inverters, rectifiers, DC / DC converters, variable frequency drives, etc. SSCBs are devices that can switch an electrical circuit on or off. For example, SSCBs may be used in the electrical path between a voltage source, such as a battery, and a power converter, such as an inverter. While this disclosure is primarily described with respect to converters and SSCBs, the disclosure is applicable to other power systems.

[0006] The inverters and rectifiers of the present disclosure may be bidirectional. A bidirectional inverter can convert DC power to AC power during forward operation and AC power to DC power during reverse operation. A bidirectional rectifier can convert AC power to DC power during forward operation and DC power to AC power during reverse operation.

[0007] Inverters and rectifiers may vary in design. For example, inverters and rectifiers may have one or more phases. Each phase may include one or more legs or half-bridges. Each leg or half-bridge may include a "high-side switch" electrically connected to a "low-side switch." When a switch is turned on (i.e., activated), it conducts current between its current terminals.

[0008] FIG. 1A shows relevant components of a three-phase inverter 100 for converting DC power from a battery into three-phase AC power for an electric motor. Each phase includes a high-side switch connected to a low-side switch. Each high-side switch includes a high-side transistor THx connected in parallel with a high-side diode DHx, and each low-side switch includes a low-side transistor TLx connected in parallel with a low-side diode DLx. In FIG. 1A, each transistor T is an insulated gate bipolar transistor (IGBT).

[0009] The high-side transistors TH1 to TH3 are connected in series to the low-side transistors TL1 to TL3 via nodes N1 to N3, respectively, which are connected to the terminals of the inductive elements Wa to Wc. For illustrative purposes, the inductive elements Wa to Wc are configured as stator windings of a synchronous or asynchronous motor of an electric vehicle (EV).

[0010] The collector terminals of TH1 to TH3 and the cathode terminals of DH1 to DH3 are connected to each other and to the V+ input terminal. Meanwhile, the emitter terminals of TL1 to TL3 and the anode terminals of diodes DL1 to DL3 are connected to each other and to the V- input terminal. A DC voltage Vdc is supplied between the V+ input terminal and the V- input terminal by a battery or other DC power source.

[0011] High-side transistors TH1-TH3 and low-side transistors TL1-TL3 are controlled by microcontroller 110 via gate drivers H101-H103 and L101-L103, respectively. A driver is a device that receives low-power input signals from a device (e.g., a microcontroller) and generates corresponding high-power output signals required to operate the transistors.

[0012] Control of transistor T is relatively simple. High-side gate drivers H101-H103 and low-side gate drivers L101-L103 receive driver control signals (e.g., pulse-width modulation signals PWM-H1-PWM-H3 and PWM-L1-PWM-L3) from microcontroller 110. When the high-side gate drivers H101-H103 receive the PWM-H1-PWM-H3 signals, they apply high-power gate control signals VgH1-VgH3 to operate high-side transistors TH1-TH3, respectively. When the low-side gate drivers L101-L103 receive the PWM-L1-PWM-L3 signals, they apply high-power gate control signals VgL1-VgL3 to operate low-side transistors TL1-TL3, respectively. Each of the transistors TH1-TH3 and TL1-TL3 supplies or draws current to or from the stator winding W to which it is connected when in operation.

[0013] By operating transistors TH1-TH3 and TL1-TL3 in a coordinated manner, the direction of current flow in the stator windings can be controlled, allowing current to flow in or out of the windings. FIG. 1B shows an example timing diagram of gate control signals VgH1-VgH3 and VgL1-VgL3. This timing diagram is provided solely to facilitate a basic understanding of inverter control. In practice, more complex timing patterns are typically used to control the inverter.

[0014] Microcontroller 110 controls high-side transistors TH1-TH3 and low-side transistors TL1-TL3 via PWM-H1-PWM-H3 and PWM-L1-PWM-L3 signals, respectively. Microcontrollers such as microcontroller 110 and other similar data processing devices may include a central processing unit (CPU), memory for storing CPU-executable instructions, and peripherals such as timers and input / output (I / O) ports. Microcontroller 110 generates the PWM-H1-PWM-H3 and PWM-L1-PWM-L3 signals based on the CPU-executable instructions stored in the memory. Gate drivers H101-H103 generate VgH1-VgH3 signals based on the PWM-H1-PWM-H3 signals, and gate drivers L101-L103 generate VgL1-VgL3 signals based on the PWM-L1-PWM-L3 signals. The microcontroller 110 can adjust the duty cycle and / or period of the pulse width modulated (PWM) signal according to instructions stored in memory.

[0015] FIG. 1C illustrates the relevant components of a three-phase rectifier 150 that can be used to convert three-phase AC power from a power grid to DC power for charging an EV battery. The inverter 100 and the rectifier 150 are similar. Like the inverter 100, each phase of the rectifier 150 includes a high-side switch connected to a low-side switch. Each high-side switch includes a transistor THx connected in parallel with a diode DHx, and each low-side switch includes a transistor TLx connected in parallel with a diode DLx. High-side transistors TH1-TH3 are connected in series with low-side transistors TL1-TL3, respectively, via nodes N1-N3, which are connected to respective terminals of inductive elements La-Lc. For illustrative purposes, the inductive elements La-Lc are configured as inductors of an LCL filter 162, which is connected to a three-phase AC power source 164.

[0016] The collector terminals of TH1 to TH3 and the cathode terminals of DH1 to DH3 are connected to each other and also to the V+ output terminal, while the emitter terminals of TL1 to TL3 and the anode terminals of diodes DL1 to DL3 are connected to each other and also to the V- output terminal.

[0017] The high-side transistors TH1-TH3 and the low-side transistors TL1-TL3 are controlled by a rectifier controller 160 via gate drivers H101-H103 and L101-L103, respectively. Through coordinated operation of the high-side and low-side IGBTs, the rectifier 150 supplies a rectified DC voltage Vrdc to output terminals V+ and V−, which may be connected to another device, such as an isolated DC / DC converter, that can employ one or more aspects of the present disclosure. Although not shown, a filter may be connected between the output terminals V+ and V− to smooth Vrdc before supplying it to another device, such as an isolated DC / DC converter.

[0018] While inverter 100 and rectifier 150 are similar, there is at least one difference. Rectifier 150 includes a controller 160, which may include a phase-locked loop (PLL) or other components for synchronizing control of high-side transistors TH1-TH3 and low-side transistors TL1-TL3 to the frequency (e.g., 60 Hz) of three-phase AC input power provided by power supply 164. Controller 160 may also include a CPU and memory for storing CPU-executable instructions, although these CPU-executable instructions may differ from the CPU-executable instructions stored in the memory of microcontroller 110 of inverter 100. Like microcontroller 110, controller 160 generates PWM-H1-H3 and PWM-L1-L3 signals. The gate drivers H101 to H103 generate the VgH1 to VgH3 signals based on the PWM-H1 to PWM-H3 signals, and the gate drivers L101 to L103 generate the VgL1 to VgL3 signals based on the PWM-L1 to PWM-L3 signals. The controller 160 can adjust the duty cycle and / or period of the PWM signals.

[0019] EVs, DC fast chargers, industrial machinery (e.g., industrial pumps, fans, compressors, etc.), and electric vertical take-off and landing (eVTOL) vehicles use large and heavy power converters. There is a demand for smaller, lighter power converters with higher power density (i.e., power / volume). For example, the October 2017 "Electrical and Electronics Engineering Team (EETT) Roadmap," published in part by the U.S. Department of Energy, sets a 2025 power density target of 100 kW / L for EV inverters. The 2017 EETT Roadmap states, "Achieving the 2025 EETT R&D goals requires a power density increase of more than 800% compared to the 2015 EETT R&D technology goals and more than 450% compared to current commercial technologies."

[0020] A "power module" is disclosed. The power module may comprise a "switch module" and a "diode module." A "packaged power module" is disclosed. The packaged power module may comprise a packaged switch module and a packaged diode module. A power converter may use packaged switches and / or packaged diodes.

[0021] The switch module may include a "power stack." The power stack includes a "switch" that is electrically and thermally connected (e.g., sintered, soldered, etc.) to and sandwiched between a "die substrate" and a "die clip." The switch may be bidirectional or capable of controlling forward and reverse current. The switch may include one, two, or more power transistors (hereinafter "transistors"). The transistors within a switch may be connected in parallel, anti-parallel, or back-to-back. The switch may also include one or more power diodes (hereinafter "diodes") connected in parallel with one or more transistors. Depending on the configuration, the switch may carry 10, 20, 50, 100, 200, 400 amperes (A), or more of current during operation or upon power input. The switch module may include one or more additional components, such as a transistor control terminal driver (hereinafter "driver," e.g., a gate driver or base driver), resistors, capacitors, current sensors, temperature sensors, voltage sensors, voltage regulators, etc.

[0022] The diode module may include a power stack. The power stack includes one or more diodes that are electrically and thermally connected (e.g., sintered, soldered, etc.) and sandwiched between the die substrate and the die clip. Multiple diodes may be connected in parallel. The diode module may also include one or more additional components, such as resistors, capacitors, current sensors, temperature sensors, voltage sensors, etc.

[0023] The die substrate and die clip are electrically and thermally conductive elements. The die substrate and die clip may have die substrate terminals and die clip terminals, respectively. Current may be transmitted along a linear path between the die substrate terminal containing the active switch or diode and the die clip terminal. Heat generated in the switch or diode and current conducted by the switch or diode may simultaneously be transmitted through the die substrate terminal and / or die clip terminal. The die substrate terminal and die clip terminal may be thermally and electrically connected to a bus bar, a heat sink, or a bus bar that also functions as a heat sink.

[0024] A packaged switch module (hereinafter also referred to as a packaged switch) may include one or more switch modules. Packaged switch modules may be used in converters, SSCBs, etc. A packaged switch module having only one switch module is called a "packaged switch." A packaged switch module having two switch modules is called a "packaged half-bridge." The switches may or may not be electrically connected within the packaged half-bridge.

[0025] A packaged diode module (hereinafter also referred to as a packaged diode) may include one or more diode modules. The packaged diode module may be used in a converter or other power system.

[0026] A compact power converter (hereinafter also referred to as a power converter) including an inverter is disclosed. The power converter may use packaged switches and / or packaged diodes. The power converter of the present disclosure may have several advantages over conventional power converters. For example, the power density of one or more of the disclosed inverters may meet or exceed the 100 kW / L power density target set in the aforementioned 2017 EETT Roadmap. Current density may also be an important advantage of the power converter of the present disclosure. For example, the inverter of the present disclosure may be able to carry the same amount of continuous current with fewer transistors than a prior art inverter with a larger volume. The power converter of the present disclosure may use a heat sink or bus bar with embedded tubes that carry a cooling fluid. The cooling fluid can remove heat from the transistors and / or diodes electrically and thermally connected to the bus bar.

[0027] Although the present disclosure will be described primarily with respect to inverters and rectifiers, it should be understood that one or more aspects of the present disclosure may also be applicable to other power converters, such as DC / DC converters, matrix converters, AC / AC converters, and other power systems, such as SSCBs.

[0028] Packaged Switches and Packaged Diodes Packaged switches and packaged diodes may have a cube shape with six sides: top, bottom, front, back, left side, and right side. Some packaged switches may conform to industry standard packaging aspects, such as the TO-247 package.

[0029] FIGS. 2A-1, 2A-2, and 2A-3 are top, bottom, and side views, respectively, of an exemplary packaged switch 247p. FIGS. 2B-1, 2B-2, and 2B-3 are top, bottom, and side views, respectively, of an exemplary packaged switch 247q. FIGS. 2C-1, 2C-2, and 2C-3 are top, bottom, and side views, respectively, of an exemplary packaged switch 247s. FIGS. 2D-1, 2D-2, and 2D-3 are top, bottom, and side views, respectively, of an exemplary packaged switch 247d. Packaged switches 247s and 247d are examples that conform to one or more aspects of the TO-247 packaging standard. FIGS. 2E-1, 2E-2, and 2E-3 are top, bottom, and side views, respectively, of an exemplary packaged diode 245.

[0030] case The packaged switch and packaged diode may have a case. FIGS. 2A-1 through 2A-3 show an example case 248p. FIGS. 2B-1 through 2B-3 show an example case 248q. FIGS. 2C-1 through 2C-3 show an example case 248s. FIGS. 2D-1 through 2D-3 show an example case 248d. FIGS. 2E-1 through 2E-3 show an example case 249.

[0031] The case may insulate, protect, and / or support switch module or diode module components, such as a power stack. The case may be composed of glass, plastic, ceramic, etc. For purposes of illustration, the case will be composed of a plastic, such as a molding compound like an epoxy resin. Modern molding compounds have evolved into complex formulations containing up to 20 different raw materials. Fillers such as alumina can be added to increase the thermal conductivity of the molding compound, which may aid in cooling the switch module and diode module components, including the transistors and diodes. The case may be formed around the switch module and diode module using any of a variety of packaging techniques, such as transfer molding.

[0032] The packaged switches and packaged diodes may be small. For example, the length lp, width wp, and height hp of the packaged diode 245, packaged switch 247q, packaged switch 247s, and / or packaged switch 247d, excluding connector leads 288, may be approximately 21 mm, 16 mm, and 5 mm, respectively. However, the size (e.g., 21 mm × 16 mm × 5 mm) and shape (e.g., cubic) of these packaged switches and packaged diodes are not limited to the disclosed subject matter and may vary. The length lp, width wp, and height hp of the packaged switch 247p, excluding connector leads 288, may be approximately 21 mm, 16 mm, and 12 mm, respectively. However, the size (e.g., 21 mm × 16 mm × 12 mm) and shape (e.g., cubic) of the packaged switch 247p are not limited to the disclosed subject matter and may vary. For example, the exemplary length, width, and / or height of the above packaged switches 247p, 247q, 247s, or 247d may be doubled depending on the nature of the internal components, such as the power stack or those contained therein.

[0033] The size and shape of the packaged switch may depend on one or more factors, such as the number and / or type of transistors in the packaged switch. For example, a packaged switch 247d with six metal-oxide semiconductor field-effect transistors (MOSFETs) connected in parallel may be longer and / or wider than a packaged switch 247d with four MOSFETs connected in parallel. Or, a packaged switch 247q with two MOSFETs connected in parallel may be thinner than a packaged switch 247q with two MOSFETs connected back-to-back. Some transistors, such as IGBTs, may be wider and / or longer than other transistors, such as MOSFETs. A packaged switch 247d with four IGBTs connected in parallel may be longer and / or wider than a packaged switch 247d with four MOSFETs connected in parallel.

[0034] The exterior surface of the case may be substantially flat. "Substantially" is used to describe a feature such as flatness. The term "substantially" means that the feature has a variation within an acceptable tolerance. For example, a substantially flat surface refers to a surface whose flatness varies within an acceptable tolerance, such as 10.0 μm.

[0035] Switch Modules and Diode Modules Connection elements Switch modules and diode modules may include metal traces, bond wires, straps, leads, tabs, signal frames, etc., or other metal connection elements used to form an electrical path between two or more devices. Electrical connection elements may be used to transmit signals, including voltage signals and current signals.

[0036] Traces have flat surfaces and can be formed on rigid printed circuit boards (PCBs), flexible PCBs, direct bond copper (DBC) substrates, etc. Bond wires are small in diameter (e.g., 10 μm or less, up to several hundred micrometers). Straps, leads, tabs, and signal frames can be thicker than traces and bond wires and rated to carry significantly more current.

[0037] Straps, leads, bond wires, signal frames, etc. may be attached, bonded, connected, or adhered together or to traces, die clips, die substrates, paddles, control terminal pads, etc. Components may be attached, bonded, connected, or adhered via electrically conductive attaching, bonding, connecting, or adhesive materials such as solder or silver sinter paste. Components may be attached, bonded, connected, or adhered via dielectric or electrically insulating attaching, bonding, connecting, or adhesive materials. When a strap, lead, or other connecting element is attached, bonded, connected, or adhered to a device (e.g., die substrate) via a dielectric material, the device is electrically isolated from the strap, lead, or other connecting element.

[0038] The leads may be cylindrical "pins" and may have a square or rectangular cross section. For purposes of discussion, the straps, signal frames, tabs, and leads will be considered to have a square or rectangular cross section. The straps, tabs, signal frames, and leads may be formed (e.g., by cutting, sawing, dicing, stamping, etc.) from a sheet of electrically conductive material such as metal.

[0039] A switch module or diode module may include a DBC substrate. For example, the DBC substrate may be thermally attached (e.g., soldered) to the flat surface of a die substrate or die clip. A DBC substrate is a ceramic tile (typically alumina) with copper sheets bonded to both sides using a high-temperature oxidation process. (The copper and substrate are heated to a precisely controlled temperature in a nitrogen atmosphere containing approximately 30 ppm oxygen; under these conditions, a copper-oxygen eutectic mixture forms, successfully bonding both the copper and the oxide used as the substrate.) The upper copper layer is pre-formed before firing or chemically etched using PCB technology to form traces. Meanwhile, the lower copper layer is typically left bare when thermally attached to the flat surface of a die substrate or die clip. When used in a switch module or diode module, DBC substrates may have thermal advantages over rigid PCBs. For example, much of the heat generated by a device (e.g., a gate driver) can be dissipated through the DBC substrate on which the device is mounted.

[0040] The switch module or diode module may include a PCB. For example, the PCB may be attached to a flat surface of a die substrate or die clip. The PCB has flat conductor traces etched from one or more thin metal sheet layers laminated on and / or between non-conductive substrate sheet layers. Metal vias through the non-conductive substrate layers may electrically connect different levels of wiring. Exemplary packaged diode 245, packaged switch 247p, packaged switch 247q, packaged switch 247s, and packaged switch 247d do not include a PCB or DBC substrate.

[0041] Connection elements (e.g., traces, bond wires, signal frames, etc.) may transmit signals (e.g., gate control signals, temperature sensor output signals, current terminal voltage levels, etc.) between leads and components (e.g., transistors, temperature sensors, etc.) within the packaged switches and packaged diodes. Connection elements may transmit signals between components within the packaged switches and packaged diodes. Bond wires may transmit signals between transistor control terminals within the packaged switches and packaged diodes and straps or DCB substrates. Traces on the PCB or DCB substrate may transmit signals (e.g., PWM signals, gate control signals, temperature sensor signals, etc.), voltages (e.g., DC supply voltages), etc. Traces on the PCB or DCB substrate may transmit signals in an electrical path between components within the switch module or diode module (e.g., temperature sensors) and components external to the switch or diode module (e.g., microcontrollers). Flexible PCB traces may be used in converters to facilitate communication between data processing devices such as MCUs and other components such as drivers, voltage sensors, current sensors, etc., as described in more detail below.

[0042] A packaged diode or packaged switch may include one or more "connector leads." Ends of some connector leads may be electrically connected to a die substrate, paddle, die clip, etc. These may further be electrically connected to current terminals of a transistor or diode. Ends of some connector leads may be electrically connected to wires, straps, signal frames, etc. These may further be electrically connected to transistor control terminals. A packaged switch may include connector leads having ends electrically connected to straps via bond wires, and the straps may be connected to the die clip, paddle, or die substrate via material that electrically insulates the straps from the die clip, paddle, or die substrate.

[0043] Connector leads may extend laterally from the case. The connector leads of the packaged switch or packaged diode may mate with a "connector" external to the packaged switch or packaged diode. The connector may be attached to an external PCB (e.g., a driver PCB or control PCB, described in more detail below) on which a microcontroller, driver, voltage regulator, and / or other components may be mounted. The connector leads may transmit signals between components of the switch module or diode module and components on the external PCB.

[0044] 2A-1 to 2A-3 show connector leads 288g1, 288g2, 288c, 288dc, and 288ds. 2B-1 to 2B-3 show connector leads 288g1, 288g2, 288dc, and 288ds. 2C-1 to 2C-3 and 2D-1 to 2D-3 show connector leads 288g, 288dc, and 288ds. 2E-1 to 2E-3 show connector leads 288ds and 288dc.

[0045] Although not shown in FIGS. 2A-1 and 2B-1, connector lead 288g1 may be electrically connected to one or more first control terminals (e.g., gate terminals) of one or more first transistors within packaged switch 247p or 247q. Also, connector lead 288g2 may be electrically connected to one or more second control terminals (e.g., gate terminals) of one or more second transistors within packaged switch 247p or 247q. In some cases, connector leads 288g1 and 288g2 may be connected to respective control terminals of a transistor (e.g., a bidirectional bipolar junction transistor) within packaged switch 247q. Although not shown in FIGS. 2C-1 and 2D-1, connector lead 288g may be electrically connected to one or more control terminals (e.g., gate terminals) of one or more transistors within packaged switches 247s and 247d. Connector leads 228ds and 228dc may be electrically connected to the die substrate and the die clip, respectively. The connector lead 288c may be electrically connected to a paddle, which will be described below.

[0046] Power Stack The power stack may include a switch or diode that is electrically and thermally connected and disposed between the die substrate and the die clip, which may be formed from an electrically and thermally conductive material (e.g., a metal), as described below.

[0047] The die substrate and die clip may include die substrate terminals and die clip terminals, respectively. The packaged switch and packaged diode of Figures 2A-1 through 2E-3 show exemplary die substrate terminals 230 and die clip terminals 344.

[0048] The die substrate terminal 230 may have a width wds of approximately 13.5 mm and a length lds of approximately 16.5 mm. The die clip terminal 344 may have a width wdc of approximately 13.0 mm and a length ldc of approximately 16.0 mm. The length and width of the die substrate terminal 230 and the die clip terminal 344 may depend on the number and / or type of transistors in the switch disposed therebetween. For example, a packaged switch 247q having six metal-oxide semiconductor field-effect transistors (MOSFETs) connected in parallel may have die substrate terminals 230 and die clips 344, respectively, that are wider and / or longer than the die clip terminals 230 and 344, respectively, of a packaged switch 247q having only four MOSFETs connected in parallel. The packaged switch 247d having two IGBTs connected in parallel may have die clip terminals 230 and 344, respectively, which are wider and / or longer than the die clip terminals 230 and 344, respectively, of the packaged switch 247d having only two MOSFETs connected in parallel.

[0049] The length and width of the die substrate terminal 230 and die clip terminal 344 of the diode package 245 may depend on the number and / or type of diodes therebetween. A packaged diode 245 with four diodes connected in parallel may have die clip terminals 230 and 344, respectively, that are wider and / or longer than the die clip terminals 230 and 344, respectively, of a packaged diode 245 with only two diodes connected in parallel.

[0050] 2A-1 through 2E-3 can be electrically connected to the die substrate terminal 230 and the die clip terminal 344, respectively. The connector leads 288ds and 288dc can carry a large amount of current (e.g., 1, 5, 10, 25, 50, 100 amperes (A) or more). Although the connector leads 288 in FIGS. 2A-3, 2B-3, 2C-3, 2D-3, and 2E-3 are shown as being disposed in a common plane for purposes of illustration, the connector leads 288 need not be disposed in a common plane.

[0051] The switch module may include power stacks. Each power stack may include a switch thermally and electrically connected and disposed between a die substrate and a die clip. The die substrate may be directly connected (e.g., sintered) to the switch or indirectly connected to the switch through one or more electrically and thermally conductive components, such as a pedestal (described below). Similarly, the die clip may be directly connected (e.g., sintered) to the switch or indirectly connected to the switch through one or more electrically and thermally conductive components, such as a pedestal.

[0052] Two articles can be directly or indirectly connected, attached, bonded, or coupled. Two articles (e.g., a transistor and a die substrate, or a bus bar and a die substrate terminal) that are thermally and electrically connected, attached, bonded, or coupled can simultaneously conduct large amounts of current (e.g., 1, 5, 10, 50, 100, 200, 400 A or more) and large amounts of heat (e.g., 1, 2, 5, 10, 20, 40, 80, 100, 200, 400, 800, 1200, 1400 Watts or more) between them, directly or indirectly. Two articles that are thermally and electrically connected, attached, bonded, or coupled can simultaneously conduct large amounts of current and large amounts of heat between them via a direct connection, attachment, bond, or bond (e.g., a silver sintered connection, attachment, bond, or bond). Two items that are indirectly thermally and electrically connected, attached, joined, or coupled can simultaneously conduct large amounts of current and heat between them through one or more intervening items, such as a base. The surface areas of two items can be directly connected, attached, joined, or coupled by pressing the surface areas together using mechanical structures, such as clamps, screws, etc.

[0053] The thermal and / or electrical connection may be more than a simple point-to-point connection. Two items that are thermally and / or electrically connected, joined, attached, or coupled may be separated by more than one surface area (e.g., 1, 5, 10, 20, 50, 100, 200, 400 mm 2 (or more) may be directly connected, attached, bonded, or joined through a layer of connecting, attaching, bonding, or joining material, i.e., a flat surface-to-flat surface connection. A thermal and / or electrical connection, attachment, bonding, or joint that directly connects, attaches, bonds, or joins two items may directly fill substantially the entire space between the respective surface areas of the two opposing items.

[0054] The diode module may include power stacks. Each power stack may include at least one diode electrically and thermally connected and disposed between a die substrate and a die clip. The diode may be directly connected (e.g., sintered) to the die substrate or indirectly connected to the die substrate via one or more electrically and thermally conductive components, such as a pedestal. The diode may be directly connected (e.g., sintered) to the die clip or indirectly connected to the die clip via one or more electrically and thermally conductive components, such as a pedestal.

[0055] Sintering can be a process of forming connections, bonds, connections, or attachments by applying heat and / or pressure without melting the sintering material to its liquidus point. Prior to sintering a pair of articles, such as a die substrate and a transistor, a thin layer of sintering material (e.g., silver, a silver alloy, etc.) may be applied to one or both surfaces of the articles to be sintered. During the sintering process, atoms in the sintering material diffuse across the boundaries of the articles to be sintered, fusing them together and effectively forming a single solid article. The sintering temperature need not reach the melting point of the sintering material, nor does the sintering process need to reach the melting point of the articles (e.g., the die substrate and the transistor) being sintered together. Unlike soldering, sintering should not create bubbles or other voids that adversely affect thermal and electrical conductivity between the articles. While other methods of attaching articles can be used, sintering may be preferred because it can form a mechanically strong bond, especially compared to soldering. A strong bond is particularly important when subjected to extreme environmental stresses (e.g., thermal and / or mechanical stresses). For example, the joints may be subjected to severe mechanical stresses due to road vibrations while the electric vehicle is in motion. The joints may also be subjected to severe thermal stresses due to temperature cycling. Furthermore, the melting point of the sintered material is higher than the temperatures used in soldering, brazing, epoxy bonding, sintering, or other processes used in the manufacture of packaged switches, diodes, or converters, so these processes do not disturb the sintered connection.

[0056] The die clips and die substrates of the power stack may be substantially identical or may vary significantly in size, shape, and / or composition. The die substrate may vary in size, shape, and composition for different versions of the power stack. Similarly, the die clips may vary in size, shape, and / or composition for different versions of the power stack.

[0057] The switch may comprise one or more semi-controlled and / or fully controlled transistors (e.g., insulated gate bipolar transistors (IGBTs), reverse-blocking IGBTs (RB-IGBTs), non-punch-through IGBTs (NPT-IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), silicon-controlled rectifiers (SCRs), thyristors, symmetric-gate turn-off thyristors (GTO thyristors), bidirectional thyristors (BTs), bidirectional triode thyristors or TRIACs, bidirectionally controlled thyristors (BCTs), bipolar junction transistors (BJTs), bidirectional BJTs (BBJTs (also known as BTrans)), etc.). The switch may also comprise one or more diodes (e.g., normal diodes, Zener diodes, etc.) connected in parallel or anti-parallel with the one or more transistors. The transistors and / or diodes may be composed of any of a variety of semiconductor materials, such as Si, SiC, GaN, GaO, cubic boron arsenide, etc.

[0058] A transistor has two current terminals (e.g., collector and emitter terminals of an IGBT or BJT, source and drain terminals of a MOSFET, cathode and anode terminals of a thyristor, collector / emitter terminals of a BBJT, cathode / anode terminals of a BT, etc.) through which current can flow when the transistor is in an active or on-state. A diode may have two current terminals (e.g., cathode and anode terminals). The current terminals may comprise one or more pads, each of which may have a substantially flat surface. A first current terminal (e.g., drain terminal, collector, cathode, etc.) of a switch may be electrically and thermally connected to a die substrate terminal, such as die substrate terminal 230 shown in FIGS. 2A-2E, via the body of the die substrate. A second current terminal (e.g., source, emitter, anode, etc.) may be electrically and thermally connected to a die clip terminal, such as die clip terminal 344 shown in FIGS. 2A-2E, via the body of the die clip.

[0059] A transistor has a control terminal (e.g., a gate terminal of a MOSFET or IGBT, a base terminal of a BJT or BBJT, etc.). The transistor is controlled (operated or deactivated) by a signal received at its control terminal. Some transistors may be purely unidirectional, or capable of controllably allowing current to flow from a first terminal to a second current terminal when activated, and blocking current in the reverse direction (i.e., from the second current terminal to the first current terminal) when deactivated. Some transistors (e.g., MOSFETs) may be quasi-unidirectional, or capable of controllably allowing current to flow from a first terminal to a second current terminal when activated, but not capable of controlling current flow in the reverse direction when deactivated. A transistor may be bidirectional, or capable of controllably allowing current to flow in both directions between a first and second current terminal when activated, and blocking current flow in both directions between the first and second current terminals when deactivated. A BBJT is an example of a bidirectional transistor.

[0060] As described above, the current terminal may include one or more pads, each of which may have a substantially flat surface. There may be a low-resistance path between the current terminal pad and the die substrate terminal 230. There may also be a low-resistance path between the current terminal pad and the die clip terminal 344. The low-resistance path between the current terminal pad and the die substrate terminal 230 or the die clip terminal 344 may have a thermal resistance of 0.3, 0.2, 0.1, 0.05, 0.03, or 0.02°C / W or less and an electrical resistance of 16, 12, 10, 8, 6, 5, 4, or 3 ohms or less. The low-resistance path between the current terminal pad and the die substrate terminal 230 or the die clip terminal 344 should be free of dielectrics. The low-resistance path may include one or more connections, attachments, bonds, or joints (e.g., one or more sintered connections, attachments, bonds, or joints) between the current terminal pad and the die substrate or die clip. The low resistance path may further include a pedestal or other metal component between the current terminal pad and the die substrate or die clip. A low resistance path may mean that the cross-sectional area of ​​the path parallel to the surface of the current terminal pad does not substantially decrease from the current terminal pad to the die substrate terminal 230 or the die clip terminal 344. The cross-sectional area of ​​some low resistance paths parallel to the surface of the current terminal pad may increase from the current terminal pad to the die substrate terminal 230 or the die clip terminal 344, thereby improving heat spreading from the current terminal pad to the die substrate terminal 230 or the die clip terminal 344. A large amount of heat (e.g., 1, 2, 5, 10, 20, 50, 100, 200, 300, 750 watts or more) and current (e.g., 1, 5, 10, 50, 100, 200, 400 amps or more) can simultaneously flow from the current terminal pad to the die substrate terminal 230 or the die clip terminal 344 via the low resistance path. Ideally, the cross-sectional area of ​​the low resistance path between the current terminal pad and the die substrate terminal 230 or die clip terminal 344 should decrease as current and heat are conducted from the current terminal pad to the die substrate terminal 230 or die clip terminal 344. Ideally, the low resistance path between the current terminal pad and the die substrate terminal 230 or die clip terminal 344 should have a cross-sectional area equal to or greater than the surface area of ​​the current terminal pad.

[0061] The transistors in a switch may be connected in parallel (i.e., first current terminals are electrically connected and second current terminals are electrically connected). The transistors in a switch may be connected back-to-back (e.g., two transistors are connected in series, but their first current terminals or second current terminals are connected). The transistors in a switch may be connected in anti-parallel (e.g., two transistors are connected in parallel, but the first and second current terminals of the first transistor are connected to the second and first current terminals of the second transistor, respectively). A switch may be bidirectional or capable of controlling current flow in both directions. A switch may be bidirectional if it includes quasi-unidirectional transistors such as MOSFETs connected back-to-back. A switch may be bidirectional if it includes pure unidirectional transistors such as BJTs or IGBTs, including NPT-IGBTs or RB-IGBTs, connected anti-parallel. A switch may be bidirectional if it includes only one bidirectional transistor such as a BBJT or multiple bidirectional transistors connected in parallel.

[0062] The switches may be hybrids or mixtures of different types of transistors connected in parallel, back-to-back, or anti-parallel. For example, a hybrid switch may include one or more MOSFETs and one or more IGBTs connected in parallel (i.e., the drains and collectors are electrically connected and the sources and emitters are electrically connected). Other hybrid switches are also contemplated.

[0063] Different types of drivers may be required to control different types of transistors. Some gate drivers can activate or deactivate IGBTs but not MOSFETs, or vice versa. However, other drivers can control different types of transistors simultaneously. For example, some gate drivers can independently generate separate signals to control the gates of the MOSFETs and IGBTs in a switch. The independently controlled signals can be turned on at different times. For example, the independently controlled signals for each transistor can be asserted at different times.

[0064] Multiple transistors in a switch may be connected in parallel and controlled by a common signal received at their control terminals. Parallel-connected transistors in a switch may be controlled by respective independent control signals received at their control terminals. Groups of parallel-connected transistors in a switch may be controlled by respective independent control signals. All or some (e.g., one, two, or more, but less than all) parallel-connected transistors in a switch may be simultaneously in an operating state when controlled by respective independent control signals.

[0065] A pair of transistors in a switch may be connected in anti-parallel, or two groups of parallel-connected transistors in a switch may be connected in anti-parallel. Each pair of anti-parallel transistors may be controlled by its own independent signal, or two groups of parallel-connected anti-parallel transistors may be controlled by its own independent control signal. Only one pair of anti-parallel-connected transistors must be active at a time, and only one group of parallel-connected anti-parallel-connected transistors must be active at a time.

[0066] A pair of transistors in a switch may be connected back-to-back, or two groups of parallel-connected transistors in a switch may be connected back-to-back. A pair of back-to-back connected transistors may be controlled by independent signals, or two groups of parallel-connected back-to-back connected transistors may be controlled by independent control signals. Only one pair of back-to-back connected transistors in a switch must be active at a time, and only one group of parallel-connected back-to-back connected transistors must be active at a time.

[0067] The transistor or diode may be a vertically structured semiconductor device or die. A vertically structured transistor may have a trench-like structure with a first current terminal (e.g., drain terminal, collector terminal, collector / emitter terminal, etc.) on or near a first surface (e.g., bottom surface) of the die and a second current terminal (e.g., source terminal, emitter terminal, collector / emitter terminal, etc.) on or near an opposite second surface (e.g., top surface) of the die. A vertically structured transistor may have a control terminal (e.g., base terminal or gate terminal) on or near the top surface of the die. Some transistors, such as BBJTs or BCTs, may have a second control terminal on or near the bottom surface of the die. The cathode and anode terminals of a vertically structured diode may be on or near the opposite top and bottom surfaces, respectively.

[0068] The current terminals may comprise one or more electrically and thermally conductive (e.g., metallic) contact pads (hereinafter, pads), each of which may be in electrical or ohmic contact with an underlying doped semiconductor region (e.g., source, drain, emitter, collector, emitter / collector, anode, cathode, etc.). The control terminals may also comprise one or more pads. The control terminal pads may or may not be in ohmic contact with the underlying doped semiconductor region (e.g., gate, base, etc.). In an IGBT or MOSFET, a dielectric layer may electrically insulate the gate terminal pad from the underlying gate. The base terminal pad of a BJT or BBJT may be in electrical or ohmic contact with the underlying base.

[0069] The current terminal pad and the control terminal pad may be formed on the same side or surface of the transistor. The current terminal pad in the transistor may have a larger flat surface area than the control terminal pad of the transistor. The current terminal pad may have a flat surface that may be exposed to and configured for direct connection (e.g., sintered connection) with a corresponding flat surface of the die clip, die substrate, paddle, pedestal, etc. The current terminal pad may have a surface area sized to allow heat transfer to the thermally and electrically connected (e.g., sintered) die clip, paddle, pedestal, etc., with the larger surface area allowing for more heat transfer. The first current terminal pad surface (e.g., the drain and collector terminal pad surfaces of the MOSFET and IGBT (or BJT), respectively) may be 1, 2, 3, 4, 5, 6, 8, 10, 15, or 20 mm 2 The second current terminal pad surfaces (e.g., source and emitter terminal pad surfaces of a MOSFET and an IGBT (or BJT), respectively) may have a flat surface area of ​​1, 2, 3, 4, 6, 8, 10, 15 mm 2 The planar surfaces of the current terminal pads exposed on one side of the transistor may be contained within a common plane.

[0070] The exposed planar surfaces of the control terminal pads in a transistor (e.g., a BBJT, as described below) may be contained within a common plane. The control terminal pads may also have planar surfaces that are connected (e.g., by wire bonding, soldering, sintering, etc.) to bond wires, signal frames, etc.

[0071] The flat surfaces of the control terminal pads and the current terminal pads in the transistor may be in the same plane. The surfaces of the current terminal pads in the transistor may be contained in a plane that is higher than and parallel to a plane containing the surfaces of the control terminal pads. The current terminal pads in the transistor may be fabricated with a height higher than the control terminal pads, allowing the flat surface of the die substrate or die clip to be directly connected (e.g., sintered) to the flat surface of the current terminal pads while avoiding contact with the control terminal pads. An etched layer of photoresist may be formed on the wafer to cover the control terminal (gate terminal) pads while exposing the current terminal (e.g., source terminal) pads. Metal may then be deposited to increase the height of the current terminal pads. The photoresist layer may then be removed, leaving the exposed surfaces of the current terminal pads in a common plane that is higher than the common plane containing the surfaces of the control terminal pads. The additional height imparted to the current terminal pads may be considered a "pedestal."

[0072] The flat surfaces of the upper and lower terminal pads of a transistor or diode may face in opposite directions. In general, the outward normal vector to the average height of a first surface of a pair of opposing surfaces may point in the opposite direction to the outward normal vector to the average height of a second surface of the pair of opposing surfaces.

[0073] FIG. 2F shows a partial top or overhead view of an exemplary vertical structure BBJT 250. FIG. 2G shows a partial cross-sectional side view of the BBJT 250 taken along line 1-1 in FIG. 2F. Exemplary current and control terminal pads are shown in FIGS. 2G and 2F. With reference to FIG. 2G, the BBJT includes a first (e.g., upper) generally planar surface 252 and an oppositely facing second (e.g., lower) generally planar surface 254.

[0074] FIG. 2G shows collector / emitter regions 256 on one side, which may form a junction with a drift or bulk substrate 258, and collector / emitter terminal pads 262 electrically connected to each collector / emitter region 256. Collector / emitter terminal pads 262 define exposed planar surfaces 280. FIG. 2G shows base regions 260 disposed between collector / emitter regions 256 and base terminal pads 264 electrically connected to base region 260. Base terminal pads 264 define planar surfaces 282. Surfaces 280 and 282 are contained within a common plane, although it will be understood that surface 280 may be contained within a plane higher or lower than the plane containing surface 282. FIG. 2G shows collector / emitter regions 270 on the opposite side, which may form junctions with the bulk substrate 258, and collector / emitter terminal pads 272 electrically connected to each collector / emitter region 270. Collector / emitter terminal pads 272 define a planar surface 284. FIG. 2G shows base regions 276 and base terminal pads 278 electrically connected to base region 276. Base terminal pads 278 define a planar surface 286. Surfaces 284 and 286 are contained within a common plane, although it will be understood that surface 284 may be contained within a plane higher or lower than the plane containing surface 286. Although not shown in FIG. 2G, a BBJT may include multiple collector / emitter regions and multiple base regions on both sides. 2G shows only two collector / emitter terminal pads and one base terminal pad on each side, more than one collector / emitter terminal pad may be implemented on each side of the BBJT, and more than one base terminal pad may be implemented on each side of the BBJT. The terminal pads may be formed by depositing a metal material through a window in an insulating material (not shown) covering one side of a transistor such as a BBJT.

[0075] The exemplary BBJT 250 is of NPN construction, meaning that the collector / emitter regions 256 and 270 are N-type, the base regions 260 and 276 are P-type, and the bulk substrate 258 is P-type. Note that PNP-type BBJTs are also contemplated, but are not specifically shown to avoid unnecessarily lengthening this description.

[0076] 2F, collector / emitter region 256 defines a plurality of undoped interior regions 290. Within each exemplary interior region 290 is defined a base region 260.

[0077] The switch can transmit high levels of current (e.g., 1, 5, 10, 50, 100, 200, 400 amperes, or more) between the die clip and die substrate without failure, depending on the size (e.g., width and length of the current terminals), type (e.g., MOSFET), semiconductor material (e.g., GaN), and number of transistors connected in parallel and in operation. The transistor can transmit high levels of current (e.g., 1, 5, 10, 50, 100, 200, 400 amperes, or more) between its current terminals at high switching speeds (e.g., 100 kHz or more for Si IGBTs, 500 kHz or more for SiC MOSFETs, 1.0 GHz or more for GaN MOSFETs, etc.). When thermally connected to and cooled by a heat sink or a bus bar that also functions as a heat sink, the transistor can transmit more current at higher switching speeds without breaking, delaminating, or degrading. Similarly, when thermally connected to and cooled by a heat sink or a bus bar that also functions as a heat sink, a diode can transmit more current without breaking.

[0078] The switch may be electrically and thermally connected to and sandwiched between the die substrate and the die clip. The first current terminal (e.g., collector terminal, drain terminal, etc.) pad and the second current terminal (e.g., emitter terminal, source terminal, etc.) pad of the transistor in the switch may be directly or indirectly connected to the die substrate and the die clip, respectively, or vice versa. The flat surfaces of the first current terminal pad and the flat surfaces of the second current terminal pad of the transistor in the switch may be indirectly connected to the flat surfaces of the die substrate and the die clip, respectively, or vice versa. The flat surfaces of the first current terminal pad of the transistor may be directly connected to the flat surface of the die substrate, and the flat surfaces of the second current terminal pad may be indirectly connected to the flat surface of the die clip, or vice versa. The flat surfaces of the first current terminal pad of the transistor may be directly connected to the flat surface of the die clip, and the flat surfaces of the second current terminal pad of the transistor may be directly connected to the flat surface of the die substrate, or vice versa. A direct connection involves only sintering or other types of bonding material between the current terminal pad surface and the surface of the die substrate or die clip. The current terminal pad may be indirectly connected to the die clip or die substrate via an electrically and thermally conductive pedestal having a flat end face sintered to the flat surface of the current terminal pad.

[0079] The switch may include multiple transistors, each electrically and thermally connected to and sandwiched between a die clip and a die substrate. The flat surfaces of the first and second current terminal pads of the parallel-connected transistors in the switch may be directly or indirectly connected to the flat surfaces of the die substrate and die clip, respectively, or vice versa. The flat surfaces of the first and second current terminal (e.g., collector) pads of a first transistor (e.g., a first RB-IGBT) in the switch and the flat surfaces of the second current terminal (e.g., emitter) pads of a second transistor (e.g., a second RB-IGBT) in the switch may be directly or indirectly connected to the flat surfaces of the die substrate, and the flat surfaces of the second and second current terminal (e.g., emitter) pads of the first and second transistors may be directly or indirectly connected to the flat surfaces of the die clip, or vice versa. The planar surfaces of the first current terminal (e.g., drain) pads of the first and second transistors in the switch may be directly or indirectly connected to the planar surfaces of the die substrate and the die clip, respectively, and the second current terminal (e.g., source) pads of the first and second transistors may be indirectly connected to each other.

[0080] The control terminal (e.g., gate terminal, base terminal, etc.) pads of one or more transistors in the switch may be controlled by a voltage or current signal from a driver, and the control terminals of each transistor or each group of transistors in the switch may be controlled by a respective voltage or current signal from a respective driver. Effective control of different types of transistors may require different types of drivers. The drivers may be configured to control the different types of transistors separately. The control terminals of the BBJTs may be controlled by separate signals from the drivers or by separate control signals from their respective drivers.

[0081] The control terminal pads may be located on only one side of some transistors (e.g., MOSFETs and IGBTs), while on opposing sides of other transistors (e.g., BBJTs). The control terminal pads may be located adjacent to current terminal (e.g., source or emitter) pads of some transistors (e.g., MOSFETs or IGBTs), while they may be interspersed between current terminal (e.g., collector / emitter) pads of other transistors (e.g., BBJTs).

[0082] The transistor control signals may be transmitted from the drivers to the control terminal pads in electrical paths that include leads, wires, straps, bond wires, signal frames, etc., or a series combination of two or more thereof. In some switch modules, bond wires may be wire-bonded to the control terminal pads. In some switch modules, signal frames may be soldered to one or more control terminal pads.

[0083] One or more pedestals in a power stack may be electrically and thermally connected and positioned between the transistor and the die clip, paddle, bridge, or die substrate. The pedestals may be configured to provide space for bond wires below the die clip, paddle, or die substrate. In some power stacks, one or more pedestals are electrically and thermally connected and positioned between the transistor and the die clip, and one or more pedestals are electrically and thermally connected between the transistor and the paddle or die substrate. The pedestals may be configured to allow liquid molding compound (e.g., liquid resin) to flow around them during transfer molding packaging of the switch module or diode module, thereby forming a package in which the molding compound (e.g., resin) electrically insulates the exposed surfaces of the facing die clip and die substrate. The molding compound may also cover exposed bond wires, straps, signal frames, current terminal pads, and / or control terminal pads.

[0084] One or more diodes may be electrically and thermally connected to and sandwiched between the die substrate and the die clip. The flat surfaces of the first current terminal (e.g., anode terminal) pad and the flat surfaces of the second current terminal (e.g., cathode terminal) pad of the diode may be directly or indirectly connected to the die substrate and the die clip, respectively, or vice versa. Similar to a switch, the current terminal pad of the diode may be indirectly connected to the die substrate or the die clip via a pedestal sintered to the pad, or a direct connection may include sintering or other types of bonding material between the current terminal pad and the die substrate or the die clip. Because the diode does not have a control terminal, it does not need to accommodate bond wires. The first current terminal pad and the second current terminal pad of the diode may be directly connected (e.g., sintered) to the flat surfaces of the die clip and the die substrate, respectively.

[0085] The die clip can pass a large amount of current into or out of the packaged switch or packaged diode through its die clip terminals while simultaneously dissipating a large amount of heat from the packaged switch or packaged diode through its die clip terminals. The die substrate can pass a large amount of current into or out of the packaged switch or packaged diode through its die substrate terminals while simultaneously dissipating a large amount of heat from the packaged switch or packaged diode through its die substrate terminals.

[0086] The pedestal can allow a large amount of current to flow into or out of a current terminal pad electrically and thermally attached (e.g., sintered) to the pedestal, while simultaneously dissipating a large amount of heat from the current terminal pad electrically and thermally attached to the pedestal. The flat end surface of the pedestal may be directly connected (e.g., sintered) to the flat surface of only one current terminal pad, or the flat end surface of the pedestal may be directly connected (e.g., sintered) to the surfaces of multiple current terminal pads in a transistor or diode. The pedestals in a switch module or diode module may be structurally identical. Some switch modules may not use a pedestal, and opposing current terminal pad surfaces of a transistor or diode may be directly connected (e.g., sintered) to the respective surfaces of the die clip and die substrate. Similarly, some packaged diodes may not use a pedestal, and opposing current terminal pad surfaces may be directly connected (e.g., sintered) to the respective surfaces of the die clip and die substrate.

[0087] The power stack may include additional electrically and thermally conductive components, such as bridges and paddles, as described below. Pedestals and other components (e.g., bridges) may provide low-resistance electrical and thermal paths between the current terminal pads and the die clip or die substrate. The flat end faces of the pedestal may be directly attached (e.g., sintered) to the flat surfaces of the current terminal pads, and the opposing flat end faces of the pedestal may be directly attached (e.g., sintered) to the flat surfaces of the die clip, paddle, or die substrate. Alternatively, the opposing flat end faces of the pedestal may be indirectly attached to the flat surfaces of the die substrate, paddle, or die clip via one or more intermediate components, such as bridges, as described below. In other versions, the opposing end faces of the pedestal may be directly attached to the current terminal (e.g., source) pads of a pair of back-to-back connected transistors.

[0088] The die substrate, die clip, pedestal, paddle, and bridge may be formed using different methods. The die substrate, die clip, pedestal, paddle, and bridge may be formed by 3D printing. The die substrate, die clip, paddle, pedestal, and bridge may be formed by extrusion molding. The die substrate, die clip, paddle, pedestal, and bridge may be formed by a sintering process in which pressure and heat are applied to sintered powder in a mold to form a solid mass without melting it to the liquidus point. The die substrate, die clip, pedestal, paddle, and bridge may be formed from a thin sheet of highly conductive material. Before or after forming the die substrate, die clip, paddle, pedestal, or bridge, a layer of sintering-facilitating material (e.g., silver or a silver alloy) may be formed on the surface of the die substrate, die clip, paddle, pedestal, or bridge (e.g., by electrolytic plating). Barrel plating may be used to form a thin layer of sintered material on the surface of the die substrate, die clip, paddle, pedestal, etc. The barrel plating process involves placing an article (e.g., a pedestal) in a barrel-shaped cage made of non-conductive material. The cage is then submerged in a tank filled with the appropriate chemical solution and slowly rotated to initiate the plating process. The die substrate, pedestal, die clip, bridge, paddle, etc. must not contain any dielectric elements.

[0089] Die clips, die substrates, paddles, pedestals, bridges, etc. may be formed (e.g., by machining, cutting, punching, sawing, dicing, etc.) from thin (e.g., 0.1 mm to 3.0 mm) sheets of one or more metal layers. The term metal includes pure metals (e.g., copper, iron, aluminum, gold, silver, molybdenum, etc.) or metal composites. Metal composites are made by combining two or more different materials, at least one of which is a pure metal.

[0090] Thin (e.g., 3.0, 2.0, 1.0, 0.5, 0.3, 0.2, 0.1 mm or less) sheets from which die substrates, die clips, paddles, pedestals, or bridges are formed (e.g., by machining, cutting, punching, sawing, dicing, etc.) may be stacked. Two or more layers of the stacked sheets may be substantially uniform in thickness. Each layer of the stacked sheets may be metal, or each layer of the stacked sheets may be a metal composite. One or more layers of the stacked sheets may be metal, or one or more layers of the stacked sheets may be a metal composite.

[0091] For purposes of explanation, this disclosure will refer to die substrates, die clips, paddles, pedestals, and bridges formed from sheets of highly conductive material. For purposes of explanation, die substrates, die clips, paddles, pedestals, and bridges that are directly connected (e.g., sintered) to the current terminal pad surfaces of transistors or diodes will refer to die substrates, die clips, paddles, pedestals, and bridges that are directly connected (e.g., sintered) to the current terminal pad surfaces of transistors or diodes as being formed from laminated sheets unless otherwise specified.

[0092] FIG. 2H shows a side view of a portion of an exemplary laminate sheet 265 from which a pedestal, paddle, bridge, die clip, die substrate, or other component can be formed. The laminate sheet 265 may be 0.5 to 1.16 mm between opposing first and second flat surfaces 275 and 277. Section 271 may be comprised of a central layer 266 of metal (e.g., molybdenum, which may be suitable for attaching a die substrate or pedestal to a low CTE (e.g., SiC)-based device such as a MOSFET or diode) or metal composite (copper / diamond, copper / molybdenum, copper / tungsten, etc.) between layers 267 of metal (e.g., copper) or metal composite. Note that layers 266 may be made of materials other than molybdenum. Section 271 may be sandwiched between layers 268 of metal (e.g., nickel) or metal composite, as shown. The nickel layer 268 may prevent copper from migrating to the silver layer 269. Layer 268 may be formed (e.g., by electroplating) on ​​layer 267. Section 273 may be sandwiched between layer 269 of a sintering-facilitating material (e.g., silver) as shown. Layer 269 may be formed (e.g., by electroplating) on ​​layer 268. For purposes of illustration, layers 268 and 269 are formed before the pedestal, paddle, bridge, die clip, die substrate, or other component is formed from the sheet. In other versions, one or both of layers 268 and 269 may be added to the pedestal, paddle, bridge, die clip, die substrate, or other component after the pedestal, paddle, bridge, die clip, die substrate, or other component is formed from a sheet consisting only of layers 266 and 267.

[0093] Layer 266 may have a thickness tc that is approximately equal to thickness t1 of layer 267. For example, tc and t1 may both be 0.30 to 0.35 mm. Layer 266 may have a thickness that is greater than or less than thickness t1 of layer 267. For example, layer 266 may be twice or four times as thick as layer 267, or layer 266 may be half or less thick than layer 267. Layers 268 and 269 may have approximately the same thickness. For example, each of t2 and t3 may be 0.005 to 0.015 mm.

[0094] The properties, such as thicknesses tc and t1, and composition of planar layers 266 and 267 can be varied. Layer 267 may have a higher thermal conductivity compared to layer 266, providing more efficient heat spreading properties. Center layer 266 may have a lower coefficient of thermal expansion (CTE) than layer 267. As discussed below, CTE can be a factor that affects the mechanical integrity of connections between bridges, pedestal edges, die substrates, paddles, die clip surfaces, etc., and transistors or diodes.

[0095] The flat surfaces of the current terminal pads may be electrically and thermally connected (e.g., sintered) directly to flat surfaces (i.e., 275 or 277) of the bridge, pedestal edge, die substrate, paddle, die clip surface, etc. formed from sheet 265. The sintered connection may be formed, for example, using silver or copper sinter paste, film, or preform. Components with different CTEs may expand and contract at different rates with temperature changes. The composition and / or thickness of layers 266 and 277 may be selected so that the CTE of the die substrate, die clip, pedestal, paddle, bridge, etc. is close to or substantially equal to the CTE of the transistor or diode to which the die substrate, die clip, pedestal, paddle, bridge, etc. is connected (e.g., sintered). Similar CTEs can reduce the likelihood of, for example, the drain terminal pad of a MOSFET peeling or delaminating from the die substrate surface due to mechanical stress or strain caused by differences in expansion or contraction rates between the die substrate and the MOSFET as the MOSFET is cycled between high and low temperatures. The composition and / or thickness of layers 266 and 267, such as the bridge, pedestal edge, die substrate, paddle, and die clip surface, may be selected based on one or more factors, such as the type of transistor or diode to which it is attached. For example, providing a molybdenum or molybdenum / copper layer 266 between copper layers 267 of the die substrate results in a CTE that is close to or approximately equal to the CTE of a Si CMOSFET to which the die substrate is attached by silver sintering.

[0096] The die substrate, die clip, bridge, or paddle may be formed with an integral pedestal. A bridge with an integral pedestal (hereinafter "integral bridge") may be formed (by machining, cutting, stamping, sawing, dicing, etc.) from a sheet of metal or metal composite, or a laminated sheet as shown in Figure 2H.

[0097] The die substrate may have only one terminal exposed through the case of the packaged switch or packaged diode, through which heat and current are transmitted. The die substrate terminal may have a flat surface for mechanically, electrically, and thermally mating with a flat surface of, for example, a bus bar. The surface of the die substrate terminal may be completely flat.

[0098] The die clip may have only one terminal exposed through the case of the packaged switch or packaged diode, through which heat and current are transmitted. The die clip terminal may have a flat surface for mechanically, electrically, and thermally mating with a flat surface of, for example, a bus bar. The surface of the die clip terminal may be completely flat.

[0099] The die substrate terminals or die clip terminals may have completely flat surfaces that are generally flush or coplanar with the case surface of the packaged switch or packaged diode in which they are housed. In other versions, the surfaces of the die substrate terminals or die clip terminals may be completely flat and generally parallel to and recessed from the case surface, or parallel to and protruding from the case surface. Some die clip terminals may not be exposed through the case of the packaged switch (e.g., packaged switch 247s).

[0100] 2A-1 through 2E-2 illustrate exemplary die substrate terminals 230 and exemplary die clip terminals 344. FIGS. 2C-1 through 2C-3 illustrate an example packaged switch 247s in which the die clip terminals are not exposed through the case 248s. While FIGS. 2A-1 through 2E-2 show that the die substrate terminals 230 and die clip terminals 344 are rectangular, have perfectly flat surfaces, and are parallel and slightly above, parallel and slightly below, or nearly flush with the flat case surface of the packaged switch 247 and packaged diode 245, the terminals 230 and 344 may appear to be flush with the case surface.

[0101] The size and shape of the die substrate terminals or die clip terminals should not be limited to those shown in the drawings. In other words, the die substrate terminals and die clip terminals may have different forms, shapes, and sizes. The die clip terminals or die substrate terminals may have one or more recesses that can mate with similarly shaped protrusions on an external device (e.g., a phase bus bar, a V+ bus bar, a V- bus bar, etc., as described below), thereby facilitating electrical, thermal, and / or mechanical connection therebetween. Alternatively, the die clip terminals or die substrate terminals may have one or more protrusions that can mate with similarly shaped recesses on an external device (e.g., a phase bus bar, a V+ bus bar, a V- bus bar, etc.), thereby facilitating electrical, thermal, and / or mechanical connection therebetween.

[0102] Current can flow into the packaged switch or packaged diode through the die substrate terminal and then out through the die clip terminal. Or, current can flow in the reverse direction through the packaged switch or packaged diode. For example, current can flow into the packaged switch 247d through the die substrate terminal 230 of the die substrate, through the die substrate, the switch, the die clip, and then out through the die clip terminal 344 of the packaged switch 247d. Or, current (e.g., freewheeling diode current) can flow in the reverse direction. Current can flow into the packaged diode 245 through the die substrate terminal 230 of the die substrate, through the die substrate, the diode, the die clip, and then out through the packaged diode 245 through the die clip terminal 344. Or, current (e.g., reverse recovery current) can flow in the reverse direction.

[0103] The die substrate and die clip can transmit a large amount of current to or from the respective connected switches or diodes while simultaneously dissipating a large amount of heat from the respective connected switches or diodes. The die substrate terminals and die clip terminals can transmit a large amount of current into or out of the packaged switches or diodes while simultaneously dissipating a large amount of heat from the packaged switches or diodes. For example, the die substrate terminals 230 in FIG. 2A-1, 2B-1, 2C-1, 2D-1, or 2E-1 can be flat, have a width wds of about 14.5 mm and a length lds of about 17.5 mm, and can be electrically connected to the flat surface of a bus bar. The die substrate can transmit 50, 100, 200, 400 A, or more of current between the connected switches or diodes and the bus bar through the die substrate terminals 230. The die clip terminal 344 of Figures 2A-2, 2B-2, 2D-2, or 2E-2 may have a width wdc of approximately 14.0 mm and a length ldc of approximately 17.0 mm and may be thermally and electrically connected to a flat surface of a bus bar. The die clip may transmit currents of 50, 100, 200, 400 A, or more between the connected switch or diode and the bus bar through the die clip terminal 344. The connector leads 288ds or 288dc of Figures 2A-1 through 2E-3 may transmit currents of 10, 40, 80, 100, 200 A, or more, to or from the packaged switch or packaged diode.

[0104] Transistors in switches can become hot due to conduction and switching losses, especially when carrying high currents at high switching speeds. Diodes can also become hot when carrying current. Depending on their dimensions, the die substrate can conduct a large amount of heat generated by the transistor or diode to the exterior of the packaged switch or diode through the die substrate terminals. For example, the die substrate terminals 230 in FIG. 2A-1, 2B-1, 2C-1, 2D-1, or 2E-1 may be approximately 14.5 mm wide and approximately 17.5 mm long. The flat surfaces of the die substrate terminals 230 may be electrically and thermally connected to a heat sink or to the flat surfaces of a bus bar that also functions as a heat sink. The die substrate terminals 230 can dissipate 0 to 750 watts or more of heat from the packaged switch 247p, 247q, 247s, or 247d or packaged diode 245. In other words, the die substrate terminals 230 can conduct 10, 20, 50, 100, 200, 300, 750 watts or more of heat. The die substrate may have a thickness (e.g., 0.5, 0.8, 1.0, 2.0, 4.0, 8.0 mm or more when measured between opposing surfaces), the greater the thickness, the greater the heat capacity, which may be important in absorbing sudden heat gains from an attached switch or diode.

[0105] Like the die substrate, the die clip can conduct a large amount of heat generated by the transistor or diode to the exterior of the packaged switch or packaged diode through the die clip terminals. For example, the die clip terminals 344 of FIG. 2A-2, 2B-2, 2D-2, or 2E-2 may be approximately 14.0 mm wide and approximately 17.0 mm long and may be electrically and thermally connected to a heat sink or a flat surface of a bus bar that also functions as a heat sink. The die clip terminals 344 can dissipate heat from 0 to 750 watts or more from the packaged switch 247p, 247q, 247d, or packaged diode 245. In other words, the die clip terminals 344 can conduct 10, 20, 50, 100, 200, 300, 750 watts, or more. The die clip may have a thickness (e.g., 0.5, 0.8, 1.0, 2.0, 4.0, 8.0 mm or more when measured between opposing surfaces), the greater the thickness, the greater the thermal capacity, which may be important in absorbing sudden heat gains from the attached switch or diode.

[0106] Although not shown in FIGS. 2A-1 through 2E-3, the packaged switches 247p, 247q, 247d, and 247s or the packaged diode 245 may include one or more pedestals. The pedestals may have different sizes, shapes, and compositions. For illustrative purposes, each pedestal or integrated bridge is formed from a laminated sheet as shown in FIG. 2H, and layer 266 may be a metal other than molybdenum if the pedestal or integrated bridge is directly attached (e.g., sintered) to a non-SiC-based device (e.g., a transistor) (e.g., a GaN-based MOSFET). Each pedestal may have opposing first and second substantially flat (e.g., within a 0.01 mm tolerance) end faces. The first and second end faces may be completely flat. Multiple pedestals in a power stack may be substantially identical in size, shape, and composition. Groups of one or more pedestals in a power stack may be substantially different in size, shape, and composition.

[0107] The pedestal may have a uniform cross-section between the first and second opposing flat end faces. Alternatively, the pedestal may have a non-uniform cross-section between the first and second opposing flat end faces. For example, the cross-sectional width near the first flat end face that is directly connected (e.g., sintered) to the flat surface of the current terminal pad may be smaller than the cross-sectional width near the second flat end face.

[0108] A first flat end surface of the pedestal may be directly thermally and electrically connected (e.g., sintered) to a flat surface of a current terminal pad of each of the transistors in the power stack, and a second flat end surface of the pedestal may be directly thermally and electrically connected (e.g., sintered) to a flat surface of the die substrate or die clip opposite the side having the die substrate terminals 230 or die clip terminals 344. Alternatively, the second flat end surface of the pedestal may be directly thermally and electrically connected (e.g., sintered) to a flat surface of a bridge, the bridge comprising an opposing flat surface that is directly thermally and electrically connected (e.g., sintered) to a flat surface of the die substrate or die clip opposite the side having the die clip terminals 344 or die substrate terminals 230.

[0109] A first flat end face of the single pedestal may be directly thermally and electrically connected (e.g., sintered) to a flat surface of a current terminal pad of a transistor in the power stack, and a second flat end face of the pedestal may be directly thermally and electrically connected (e.g., sintered) to a flat surface of the die substrate or die clip opposite the side having the die substrate terminal 230 or die clip terminal 344. Alternatively, the second flat end face of the single pedestal may be directly thermally and electrically connected (e.g., sintered) to a flat surface of a bridge, the bridge comprising an opposing flat surface that is directly thermally and electrically connected (e.g., sintered) to a flat surface of the die substrate or die clip opposite the side having the die clip terminal 344 or die substrate terminal 230.

[0110] The one or more first transistors may be electrically connected back-to-back to one or more second transistors in the power stack. The first flat end surface of the pedestal may be electrically and thermally connected (e.g., sintered) to a respective flat current terminal (e.g., source) pad of the first transistor, and the second flat end surface of the pedestal may be electrically and thermally directly connected (e.g., sintered) to a respective flat current terminal (e.g., source) pad of the second transistor in the power stack. Alternatively, the first flat end surface of the pedestal may be electrically and thermally directly connected (e.g., sintered) to a respective pair of flat current terminal (e.g., source) pads of the first transistor, and the second flat end surface of the pedestal may be electrically and thermally directly connected (e.g., sintered) to a respective pair of flat current terminal (e.g., source) pads of the second transistor in the power stack.

[0111] The pedestal may be integrally formed from and extend from a surface of the die substrate or die clip opposite the side having the die substrate terminals 230 or die clip terminals 344, respectively. Alternatively, the pedestal may be integrally formed from and extend from a flat surface of the bridge opposite the side that is connected (e.g., sintered) to the die substrate or die clip. In this alternative version, a first flat end face of the pedestal may be directly electrically and thermally connected (e.g., sintered) to a respective flat surface or respective pair of current terminal pads of one or more transistors in the power stack.

[0112] The first flat end face of the pedestal may have a shape substantially equal to the shape of the flat surface of the connected current terminal pad. The first end of the pedestal may have a flat surface area configured to connect to the flat surface of a pair of adjacent current terminal pads in the transistor. The flat surface of the current terminal pad may be connected to the first flat surface of the pedestal, paddle, die clip, die substrate, etc. using any of a variety of attachment techniques (e.g., sintering, soldering, transient liquid phase bonding, conductive adhesive processes, etc.). The second opposing flat end face of the pedestal may be connected to the flat surface of the paddle, die clip, die substrate, etc. using any of a variety of attachment techniques (e.g., sintering, soldering, transient liquid phase bonding, conductive adhesive processes, etc.).

[0113] In the past, bond wires have been used to transmit large currents (1 A or greater) in power converters. The connections from N1 to TL1, N2 to TL2, and N3 to TL3, and from V+ to TH1, TH2, and TH3 in FIGS. 1A and 1C, may consist of one or more bond wires (not shown) wire-bonded to the current terminal pads of the IGBTs. These bond wires are prone to failure during temperature cycling. For example, the bond wires or bond wire connections often crack or break during temperature cycling. Lift-off of the bond wires can also occur. This failure may be due to relatively high current densities and low heat capacity in the bond wires themselves or in the connections between the bond wires and the current terminal pads. In contrast, the pedestal has a large cross-sectional area, resulting in a lower current density and a higher heat capacity compared to the bond wires. Additionally, the connection (e.g., a sintered connection) between the flat surface of the current terminal pad and the flat surface of the connected pedestal may experience low current densities. Such bond wire-related failures are less likely to occur when the end face of the pedestal is connected (e.g., sintered) to the current terminal pad surface. Pedestals have additional advantages over bond wires, such as low parasitic parameters (e.g., inductance, resistance, and capacitance). The parasitic inductance in the electrical path between the die substrate terminal and the die clip terminal in the packaged switch, including the pedestal, may be 0.15 nH or less. Low parasitic inductance may improve the operational behavior of the packaged switch.

[0114] A pair of components may be directly or indirectly connected, attached, bonded, or coupled. A pair of components may be directly connected, attached, bonded, or coupled by soldering, sintering, brazing, adhesive bonding, etc. Materials used to solder, sinter, braze, adhesively, etc. a pair of components may be electrically and / or thermally conductive. A pair of components may be directly connected, attached, bonded, or coupled by pressing (i.e., "press-fit") the surfaces of the components together using mechanical structures such as clamps and bolts. Thus, a pair of components may be directly connected, attached, bonded, or coupled without an intervening material (e.g., solder, sintered material, conductive adhesive, thermal interface material (TIM), electrically insulating adhesive, etc.) between them. A pair of components may be indirectly connected, attached, bonded, or coupled through one or more additional components (e.g., die substrate, die clip, pedestal, transistor, wire, ribbon, lead, wiring, etc.).

[0115] Packaging Switch 247 Example With continued reference to Figures 2A-1-2A-3, 2B-1-2B-3, and 2D-1-2D-3, Figures 3A-3L, 3O, and 3P illustrate example packaged switches 247p, 247q, or 247d from a side view. In Figures 3A-3L, 3O, and 3P, the case (e.g., case 248) is shown as transparent to facilitate a better understanding of the packaged switch components, their interactions, and relative positions. Additionally, connector leads 288ds and 288dc are not shown for ease of understanding.

[0116] The example packaged switch 247 shown in Figures 3A-3L, 3O, and 3P includes switch modules 376A-376L, 376O, and 376P, respectively, each including a power stack with a switch 304 electrically and thermally connected between a die substrate 360 ​​and a die clip 372, both shown symbolically. Die substrate terminals 230 and die clip terminals 344 are also shown symbolically. Figure 3K also includes a paddle 361, shown symbolically. Although not shown in Figure 3K, paddle 361 may include opposing flat surfaces to which the flat ends of the respective pedestals are directly connected (e.g., sintered).

[0117] The surfaces of die substrate terminals 230 and die clip terminals 344 may be completely flat and flush with the respective surfaces of case 248. Alternatively, the surfaces of die substrate terminals 230 and die clip terminals 344 may be completely flat and recessed or protruding from the surface of case 248. The switch module components, including die substrate 360 ​​and die clip 372, may vary in size, shape, composition, etc., between packaged switches 247 of Figures 3A-3L, 3O, and 3P.

[0118] 3A-3L, 3O, and 3P, each power stack may include one or more pedestals, each of which may have completely flat opposing first and second end faces. The first flat end face of the pedestal may be directly connected (e.g., by sintering, soldering, transient liquid phase bonding, a conductive adhesive process, etc.) to one or more current terminal pads of the transistors of switch 304, and the second flat end face of the pedestal may be directly connected (e.g., by sintering, soldering, transient liquid phase bonding, a conductive adhesive process, etc.) to a flat surface of die substrate 360 ​​or die clip 372 opposite the side having die substrate terminal 230 or die clip terminal 344. Alternatively, the second flat end face of the pedestal may be directly connected to a flat surface of the bridge, with the bridge having an opposing flat surface that is directly connected (e.g., by sintering, soldering, transient liquid phase bonding, conductive adhesive process, etc.) to the flat surface of the die substrate 360 ​​or die clip 372 opposite the side having the die clip terminal 344 or die substrate terminal 230. Alternatively, the second flat end face of the pedestal may be directly connected to one or more current terminals of another transistor. The pedestal may be integrally formed and extend from the flat surface of the bridge, with the bridge having an opposing flat surface that is directly connected to the flat surface of the die substrate 360 ​​or die clip 372 opposite the side having the die clip terminal 344 or die substrate terminal 230.

[0119] 3A-3P illustrate the relative positioning of the components. The die substrate 360, switch 304, and die clip 372 may be stacked as shown. In one sense, stacking the first and second components means that the first and second components are disposed in first and second planes, respectively, that are separated but parallel to each other. The first component in the first plane may be disposed directly above the second component in the second plane, or the first component may be laterally offset within the first plane, such that the second component is not directly below the first component. Current may be transmitted between the die clip terminal 344 and the die substrate terminal 230 through the actuated switch 304.

[0120] The switch module 376 may include connector leads 288g, 288ds, 288c, and 288dc, although connector leads 288dc and 288ds are not shown in FIGS. 3A-3P for ease of illustration. Connector lead 288g may be electrically connected to the control terminal pads of each transistor of the switch 304 of FIGS. 3A-3D and 3O. Connector lead 288g1 may be electrically connected to the control terminal pads of one or more first transistors of the switch 304 of FIGS. 3E-3L and 3P. Connector lead 288g2 may be electrically connected to the control terminal pads of one or more second transistors of the switch 304 of FIGS. 3E-3L and 3P. In FIGS. 3G and 3L, the one or more first transistors are identical to the one or more second transistors.

[0121] Die substrate 360 ​​and die clip 372 can direct large currents (e.g., 1, 5, 10, 50, 100, 200, 400 A, or more) to and from packaged switches 247q, 247d, and 247p via die substrate terminals 230 and die clip terminals 344, respectively. Switch 304 can become hot. Die substrate 360 ​​and die clip 372 can dissipate large amounts of switch heat from packaged switch 247 via die substrate terminals 230 and die clip terminals 344, respectively, while die substrate terminals 230 and die clip terminals 344 can carry large currents.

[0122] FIG. 3A shows an example of a packaged switch 247dA. In FIG. 3A, switch 304dA includes an IGBT electrically connected in parallel with a diode D. Each collector terminal of the IGBT and each cathode terminal of the diode may have one or more conductive pads with perfectly flat surfaces that can be electrically and thermally directly connected (e.g., sintered) to a flat surface of the die substrate, for example. For purposes of explanation, each collector terminal of the IGBT and each cathode terminal of the diode will have only one conductive pad unless otherwise noted. Each emitter terminal of the IGBT may have multiple conductive pads with perfectly flat surfaces that can be electrically and thermally directly connected (e.g., sintered) to a flat surface of a respective pedestal or to a flat surface of a single pedestal. Each anode terminal of the diode may have a pad with perfectly flat surfaces that can be electrically and thermally directly connected (e.g., sintered) to a flat surface of the pedestal. In other versions, the flat surfaces of the emitter and anode terminal pads may be directly connected (e.g., sintered) to a flat surface of the die clip.

[0123] 3A may be directly connected (e.g., sintered) to the flat surface of the die substrate 360, and the flat surfaces of the emitter and anode terminal pads may be directly connected (e.g., sintered) to the first flat end face of the pedestal. A second flat surface at the opposite end of the pedestal (i.e., the second flat end face) may be directly connected (e.g., sintered) to the flat surface of the die clip 372. The pad surface connections (e.g., sintered connections) enable thermal and electrical transmission.

[0124] The connector lead 288g may be electrically connected to the gate terminal g of the IGBT. Although not shown in FIG. 3A , the switch module 376A may include a strap attached to the same surface of the die substrate 360 ​​to which the collector terminal c and cathode terminal pads are connected. The strap may be electrically insulated from the die substrate 360. One or more bond wires may electrically connect the strap to the gate terminal g pad. For purposes of explanation, each IGBT in this disclosure has only one gate terminal pad unless otherwise noted. The connector lead 288g may be electrically connected to the strap. The end of the connector lead 288g may be directly connected (e.g., soldered) to the strap. Alternatively, one or more bond wires may electrically connect the strap to the end of the connector lead 288g.

[0125] FIG. 3B is an example of a packaged switch 247dB. In FIG. 3B, switch 304dB includes four n-channel MOSFETs connected in parallel. Each drain terminal of the MOSFETs may have one or more conductive pads with perfectly flat surfaces that can be electrically and thermally directly connected (e.g., sintered) to a flat surface of the die substrate, for example. For purposes of explanation, each drain terminal in this disclosure will have only one conductive pad unless otherwise specified. Each source terminal of the MOSFETs may have multiple conductive pads with perfectly flat surfaces that can be electrically and thermally directly connected (e.g., sintered) to a flat surface of each pedestal or to a flat surface of one pedestal, for example. In another version, the flat surface of the source terminal pads may be directly connected (e.g., sintered) to a flat surface of the die clip.

[0126] In FIG. 3B, the flat surfaces of the pads for the drain terminals d1-d4 may be directly connected (e.g., sintered) to the flat surface of the die substrate 360, and the flat surfaces of the pads for the source terminals s1-s4 may be directly connected (e.g., sintered) to the first flat end faces of the respective pedestals. The second flat surfaces (i.e., the second flat end faces) at the opposite ends of the pedestals may be directly electrically and thermally connected (e.g., sintered) to the flat surface of the die clip 372. A connector lead 288g may be electrically connected to the gate terminal of each MOSFET. For purposes of explanation, each MOSFET in this disclosure has only one gate terminal pad unless otherwise noted. Although not shown in FIG. 3B, the switch module 376B may include a strap attached to the same surface of the die substrate 360 ​​to which the pads for the drain terminals d1-d4 are connected. The strap may be electrically insulated from the die substrate 360. One or more bond wires may electrically connect the straps to the pads of the gate terminals of each MOSFET. Connector leads 288g may be electrically connected to the straps. The ends of the connector leads 288g may be directly connected (e.g., soldered) to the straps. Alternatively, one or more bond wires may electrically connect the straps to the ends of the connector leads 288g.

[0127] In FIG. 3C, switch 304dC comprises a symmetric GTO thyristor. The cathode terminal of the symmetric GTO thyristor may have one or more conductive pads with perfectly flat surfaces that can be electrically and thermally directly connected (e.g., sintered) to the flat surface of the die substrate, for example. For purposes of explanation, the cathode terminal of a symmetric GTO thyristor in this disclosure will have only one conductive pad unless otherwise noted. The anode terminal of the symmetric GTO thyristor may have one or more conductive pads with perfectly flat surfaces that can be electrically and thermally directly connected (e.g., sintered) to the flat surface of a single pedestal. In other versions, the flat surface of the anode terminal pad may be directly connected (e.g., sintered) to the flat surface of the die clip.

[0128] 3C may be directly connected (e.g., sintered) to a flat surface of the die substrate 360, and the flat surface of the anode termination pad may be directly connected (e.g., sintered) to a first flat end face of the pedestal. A second flat surface at the opposite end of the pedestal may be directly electrically and thermally connected (e.g., sintered) to a flat surface of the die clip 372.

[0129] For purposes of explanation, each symmetric GTO thyristor in this disclosure has only one gate terminal pad unless otherwise noted. Connector lead 288g may be electrically connected to the gate terminal of the GTO thyristor. Although not shown in FIG. 3C , switch module 376C may include a strap attached to the same surface of die substrate 360 ​​to which the cathode terminal pad is connected. The strap may be electrically insulated from die substrate 360. One or more bond wires may electrically connect the strap to the gate terminal pad of the symmetric GTO thyristor. Connector lead 288g may be electrically connected to the strap. The end of connector lead 288g may be directly connected (e.g., soldered) to the strap. Alternatively, one or more bond wires may electrically connect the strap to the end of connector lead 288g.

[0130] In FIG. 3D , switch 304dD includes a TRIAC. The first current terminal Anode-1 of the TRIAC may have one or more conductive pads with perfectly flat surfaces that can be electrically and thermally directly connected (e.g., sintered) to a flat surface of, for example, a die substrate. For purposes of explanation, each first current terminal Anode-1 in this disclosure has only one conductive pad unless otherwise noted. The second current terminal Anode-2 of the TRIAC may have one or more conductive pads with perfectly flat surfaces that can be electrically and thermally directly connected (e.g., sintered) to a flat surface of a single pedestal. In one version, the flat surface of the Anode-2 pad may be electrically and thermally directly connected (e.g., sintered) to a flat surface of a die clip.

[0131] 3D may be directly connected (e.g., sintered) to the flat surface of the die substrate 360, and the flat surface of the anode-2 may be directly connected (e.g., sintered) to the first flat end face of the pedestal. The flat surface at the opposite end of the pedestal may be directly electrically and thermally connected (e.g., sintered) to the flat surface of the die clip 372.

[0132] For purposes of illustration, each TRIAC in this disclosure has only one gate terminal pad unless otherwise noted. Connector lead 288g may be electrically connected to the gate terminal pad of the TRIAC. Although not shown in FIG. 3D , switch module 376D may include a strap attached to the same surface of die substrate 360 ​​to which the anode-1 pad is connected. The strap may be electrically insulated from die substrate 360. One or more bond wires may electrically connect the strap to the gate terminal pad of the TRIAC. Connector lead 288g may be electrically connected to the strap. The end of connector lead 288g may be directly connected (e.g., soldered) to the strap. Alternatively, one or more bond wires may electrically connect the strap to the end of connector lead 288g.

[0133] FIG. 3E illustrates an example of a packaged switch 247qE. The switch 304qE includes four n-channel MOSFETs connected in parallel. The flat surfaces of the pads for the drain terminals d1-d4 may be directly connected (e.g., sintered) to the flat surface of the die substrate 360, and the flat surfaces of the pads for the source terminals s1-s4 may be directly connected (e.g., sintered) to the first flat end surface of the pedestal. The flat surface at the opposite end of the pedestal (i.e., the second flat end surface) may be directly electrically and thermally connected (e.g., sintered) to the flat surface of the die clip 372. The connector lead 288g1 may be electrically connected to the gate terminals of the first pair of MOSFETs as shown, and the connector lead 288g2 may be electrically connected to the gate terminals of the other pair of MOSFETs. Although not shown in FIG. 3E, the switch module 376E may include first and second separate straps attached to the same surface of the die substrate 360 ​​to which the pads for the drain terminals d1-d4 are connected. The straps may be electrically insulated from the die substrate 360. One or more bond wires may electrically connect a first strap to the pads of the gate terminals of the first pair of MOSFETs shown, and one or more bond wires may electrically connect a second strap to the pads of the gate terminals of the other pair of MOSFETs. Connector lead 288g1 may be electrically connected to the first strap, and connector lead 288g2 may be electrically connected to the second strap. An end of connector lead 288g1 may be directly connected (e.g., soldered) to the first strap, and an end of connector lead 288g2 may be directly connected (e.g., soldered) to the second strap. Alternatively, one or more bond wires may electrically connect the first strap to the end of connector lead 288g1, and one or more bond wires may electrically connect the second strap to the end of connector lead 288g2.

[0134] FIG. 3F shows an example of a packaged switch 247qF. The switch 304qF includes three MOSFETs connected in parallel with an IGBT. The flat surfaces of the pads for the collector terminal c and the drain terminal d may be directly connected (e.g., sintered) to the flat surface of the die substrate 360, and the flat surfaces of the pads for the emitter terminal e and the source terminal s may be directly connected (e.g., sintered) to the first flat end surface of the pedestal. The flat surface at the opposite end of the pedestal (i.e., the second flat end surface) may be directly electrically and thermally connected (e.g., sintered) to the flat surface of the die clip 372. The connector lead 288g1 may be electrically connected to the gate terminal g of the MOSFET, and the connector lead 288g2 may be electrically connected to the gate terminal g of the IGBT. Although not shown in FIG. 3F, the switch module 376F may include first and second separate straps attached to the same surface of the die substrate 360 ​​to which the pads for the drain terminal d and the collector terminal c are connected. The straps may be electrically insulated from the die substrate 360. One or more bond wires may electrically connect the first strap to the pad of the gate terminal of the IGBT as shown, and one or more bond wires may electrically connect the second strap to the pad of the gate terminal g of the MOSFET. A connector lead 288g1 may be electrically connected to the first strap, and a connector lead 288g2 may be electrically connected to the second strap. An end of the connector lead 288g1 may be directly connected (e.g., soldered) to the first strap, and an end of the connector lead 288g2 may be directly connected (e.g., soldered) to the second strap. Alternatively, one or more bond wires may electrically connect the first strap to an end of the connector lead 288g1, and one or more bond wires may electrically connect the second strap to an end of the connector lead 288g2.

[0135] FIG. 3G shows an example of a packaged switch 247qG including a BBJT. Each current terminal c / e of the BBJT may have multiple conductive pads with completely flat surfaces that can be electrically and thermally directly connected (e.g., sintered) to the flat surface of the respective pedestal. The flat surface of the pad of the first current terminal c / e1 may be directly connected (e.g., sintered) to the first flat surface of each of the first pedestals, and the second flat surface on the opposite side of the first pedestal may be electrically and thermally directly connected (e.g., sintered) to the flat surface of the die substrate 360. The flat surface of the pad of the second current terminal c / e2 may be directly connected (e.g., sintered) to the first flat end face of each of the second pedestals. The flat surface on the opposite end of the second pedestal may be electrically and thermally directly connected (e.g., sintered) to the flat surface of the die clip 372.

[0136] Connector lead 288g1 may be electrically connected to base terminal b1 of the BBJT, and connector lead 288g2 may be electrically connected to base terminal b2. For purposes of illustration, each base terminal b of the BBJT of the present disclosure is assumed to have multiple base terminal pads unless otherwise noted. The base terminal pads on the BBJT are arranged in groups, and each group may have multiple linearly arranged base terminal pads, each with an exposed flat surface. For purposes of illustration, no dielectric or other material is present between the base terminal pads within a group of linearly arranged base terminal pads. Although not shown in FIG. 3G , switch module 376G may include a first signal frame having a surface electrically connected (e.g., soldered) to the surface of the pad of base terminal b1 and a second signal frame having a flat surface electrically connected (e.g., soldered) to the surface of the pad of base terminal b2. The signal frames may be electrically isolated from each other. Connector lead 288g1 may be electrically connected to a first signal frame, and connector lead 288g2 may be electrically connected to a second signal frame. An end of connector lead 288g1 may be directly connected (e.g., soldered) to the first signal frame, and an end of connector lead 288g2 may be directly connected (e.g., soldered) to the second signal frame. Alternatively, one or more bond wires may electrically connect the first signal frame to an end of connector lead 288g1, and one or more bond wires may electrically connect the second signal frame to an end of connector lead 288g2.

[0137] 3H shows an example of a packaged switch 247ph. Switch 304ph includes a MOSFET connected in parallel with a BBJT. In alternative versions of packaged switch 247ph, two or more MOSFETs may be electrically connected in parallel with the BBJT, and these combinations may be connected between die substrate 360 ​​and die clip 372.

[0138] 3H may be directly connected (e.g., sintered) to a first flat surface of the respective first pedestal, and a second flat surface opposite the first pedestal may be directly electrically and thermally connected (e.g., sintered) to a flat surface of the die substrate 360. The flat surface of the pad of the second current terminal c / e2 may be directly connected (e.g., sintered) to a first flat end face of the respective second pedestal. A flat surface at the opposite end of the second pedestal may be directly electrically and thermally connected (e.g., sintered) to a flat surface of the die clip 372. The connector lead 288g1 may be electrically connected to the base terminal b1 of the BBJT, and the connector lead 288g2 may be electrically connected to the base terminal b2. Although not shown in FIG. 3H , the switch module 376H may include a first signal frame having a surface electrically connected (e.g., soldered) to the surface of the pad of the base terminal b1 and a second signal frame having a flat surface electrically connected (e.g., soldered) to the surface of the pad of the base terminal b2. The signal frames may be electrically insulated from each other. The connector lead 288g1 may be electrically connected to the first signal frame, and the connector lead 288g2 may be electrically connected to the second signal frame. An end of the connector lead 288g1 may be directly connected (e.g., soldered) to the first signal frame, and an end of the connector lead 288g2 may be directly connected (e.g., soldered) to the second signal frame. Alternatively, one or more bond wires may electrically connect the first signal frame to the end of connector lead 288g1, and one or more bond wires may electrically connect the second signal frame to the end of connector lead 288g2.

[0139] In FIG. 3H , the flat surface of the pad for the drain terminal d may be directly connected (e.g., sintered) to the flat surface of the die substrate 360, and the flat surface of the pad for the source terminal s may be directly connected (e.g., sintered) to the first flat end face of the pedestal. The flat surface at the opposite end of the pedestal (i.e., the second flat end face) may be directly electrically and thermally connected (e.g., sintered) to the flat surface of the die clip 372. A connector lead 288c may be electrically connected to the gate terminal pad of the MOSFET. Although not shown in FIG. 3H , the switch module 376H may include a strap attached to the same surface of the die substrate 360 ​​to which the pad for the drain terminal d is connected. The strap may be electrically insulated from the die substrate 360. One or more bond wires may electrically connect the strap to the pad for the gate terminal. The connector lead 288c may be electrically connected to the strap. An end of the connector lead 288c may be directly connected (e.g., soldered) to the strap. Alternatively, one or more bond wires may electrically connect the strap to the end of connector lead 288c.

[0140] FIG. 3I shows an example of a packaged switch 247qI that may be bidirectional. The switch 304qI includes first and second groups of RB-IGBTs connected in anti-parallel. Each group of RB-IGBTs includes two RB-IGBTs connected in parallel. In alternative versions, the RB-IGBTs may be replaced with NPT-IGBTs or BJTs. Each collector terminal c1 of the first group of RB-IGBTs and each collector terminal c2 of the second group of RB-IGBTs may have one conductive pad with a completely flat surface. Each emitter terminal e1 of the first group of RB-IGBTs and each emitter terminal e2 of the second group of RB-IGBTs may have a conductive pad with a completely flat surface. The flat surfaces of the pads of collector terminals c1-1 and c1-2 may be directly connected (e.g., sintered) to the flat surface of the die substrate 360, and the surfaces of the pads of collector terminals c2-1 and c2-2 may be directly connected (e.g., sintered) to the flat surface of the die clip 372. The flat surfaces of the pads of each emitter terminal e may be directly connected (e.g., sintered) to a first flat end face of the pedestal. The flat surfaces of the opposite ends of the pedestals connected to the pads of emitter terminals e2-1 and e2-2 may be directly electrically and thermally connected (e.g., sintered) to the flat surface of the die substrate 360, and the flat surfaces of the opposite ends of the pedestals connected to the pads of emitter terminals e1-1 and e1-2 may be directly electrically and thermally connected (e.g., sintered) to the flat surface of the die clip 372. Connector lead 288g1 may be electrically connected to gate terminal g2, and connector lead 288g2 may be electrically connected to gate terminal g1. Although not shown in FIG. 3I, switch module 376I may include a first strap attached to the same surface of die substrate 360 ​​to which pads for collector terminal c1 and emitter terminal e2 are connected, and a second strap attached to the same surface of die clip 372 to which pads for collector terminal c2 and emitter terminal e1 are connected. The first and second straps may be electrically insulated from die substrate 360 ​​and die clip 372, respectively.One or more bond wires may electrically connect the first strap to the pad of the gate terminal g2, and one or more bond wires may electrically connect the second strap to the pad of the gate terminal g1. A connector lead 288g1 may be electrically connected to the first strap, and a connector lead 288g2 may be electrically connected to the second strap. An end of the connector lead 288g1 may be directly connected (e.g., soldered) to the first strap, and an end of the connector lead 288g2 may be directly connected (e.g., soldered) to the second strap. Alternatively, one or more bond wires may electrically connect the first strap to an end of the connector lead 288g1, and one or more bond wires may electrically connect the second strap to an end of the connector lead 288g2.

[0141] FIG. 3J shows an example of a packaged switch 247qJ that can be bidirectional. In FIG. 3J, switch 304qJ includes first and second groups of MOSFETs connected back-to-back. Each group includes four MOSFETs. Each source terminal s of the MOSFETs may have a completely flat conductive pad. Each drain terminal d of the MOSFETs may have a completely flat conductive pad. The flat surfaces of the pads of drain terminals d1 and d2 may be directly connected (e.g., sintered) to the flat surfaces of the die substrate 360 ​​and die clip 372, respectively. The flat surfaces of the pads of source terminal s1 may be directly connected (e.g., sintered) to the first flat end surface of the respective pedestal. The flat surfaces at the opposite end of the pedestal may be directly electrically and thermally connected (e.g., sintered) to the flat surfaces of the pads of the respective source terminal s2. Connector lead 288g1 may be electrically connected to gate terminal g1, and connector lead 288g2 may be electrically connected to gate terminal g2. Although not shown in FIG. 3J , the switch module 376J may include first and second separate straps attached to the die substrate 360 ​​and the die clip 372, respectively. The first strap may be attached to the same surface of the die substrate 360 ​​to which the pad for the drain terminal d1 is connected, and the second strap may be attached to the same surface of the die clip 372 to which the pad for the drain terminal d2 is connected. The first and second straps may be electrically isolated from each other and from the die substrate 360 ​​and the die clip 372. One or more bond wires may electrically connect the first strap to the pad for the gate terminal g1, and one or more bond wires may electrically connect the second strap to the pad for the second gate terminal g2. A connector lead 288g1 may be electrically connected to the first strap, and a connector lead 288g2 may be electrically connected to the second strap. The end of connector lead 288g1 may be directly connected (eg, soldered) to a first strap, and the end of connector lead 288g2 may be directly connected (eg, soldered) to a second strap.Alternatively, one or more bond wires may electrically connect the first strap to the end of connector lead 288g1, and one or more bond wires may electrically connect the second strap to the end of connector lead 288g2.

[0142] FIG. 3K shows an example of a packaged switch 247pK that may be bidirectional. In addition to the components of the packaged switch 247qJ of FIG. 3J, the packaged switch 247pK of FIG. 3K includes a paddle 361 and a connector lead 288c. The paddle 361 is shown symbolically. Although not shown, the paddle 361 has first and second flat surfaces that face each other. In FIG. 3K, the switch 304pK includes first and second groups of MOSFETs connected back-to-back. Each group includes four MOSFETs connected in parallel. Each source terminal s of the MOSFETs may have a completely flat conductive pad. Each drain terminal d of the MOSFETs may have a completely flat conductive pad. The flat surfaces of the pads of the drain terminals d1 and d2 may be directly connected (e.g., sintered) to the flat surfaces of the die substrate 360 ​​and the die clip 372, respectively. The flat surface of the pad of the source terminal s1 may be directly connected (e.g., sintered) to the first flat end face of the respective first pedestal. The flat surface at the opposite end of the first pedestal may be electrically and thermally directly connected (e.g., sintered) to the first flat surface of the paddle 361. The flat surface of the pad of the source terminal s2 may be directly connected (e.g., sintered) to the first flat end face of the respective second pedestal. The flat surface at the opposite end of the second pedestal may be electrically and thermally directly connected (e.g., sintered) to the second flat surface of the paddle 361. The connector lead 288g1 may be electrically connected to the gate terminal g1, and the connector lead 288g2 may be electrically connected to the gate terminal g2. Although not shown in FIG. 3K, the switch module 376K may include first and second separate straps attached to the die substrate 360 ​​and the die clip 372, respectively. The first strap may be attached to the same surface of the die substrate 360 ​​to which the pad of the drain terminal d1 is connected, and the second strap may be attached to the same surface of the die clip 372 to which the pad of the drain terminal d2 is connected. The first and second straps may be electrically isolated from each other and from the die substrate 360 ​​and the die clip 372 .One or more bond wires may electrically connect the first strap to the pad of the gate terminal g1, and one or more bond wires may electrically connect the second strap to the pad of the second gate terminal g2. Connector lead 288g1 may be electrically connected to the first strap, and connector lead 288g2 may be electrically connected to the second strap. An end of connector lead 288g1 may be directly connected (e.g., welded) to the first strap, and an end of connector lead 288g2 may be directly connected (e.g., welded) to the second strap. Alternatively, one or more bond wires may electrically connect the first strap to the end of connector lead 288g1, and one or more bond wires may electrically connect the second strap to the end of connector lead 288g2. Connector lead 288c is electrically connected to paddle 361.

[0143] Figure 3L shows a packaged switch 247ql that can be bidirectional. Figure 3L shows a switch 304ql having four BBJTs connected in parallel. The flat surface of the pad of the first current terminal c / e1 of each BBJT may be directly connected (e.g., sintered) to the first flat surface of the respective first pedestal, and the opposite second flat surface of each BBJT's first pedestal may be directly electrically and thermally connected (e.g., sintered) to the flat surface of the die substrate 360. The flat surface of the pad of the second current terminal c / e2 may be directly connected (e.g., sintered) to the first flat end face of the respective second pedestal. The flat surface of the opposite end of the second pedestal may be directly electrically and thermally connected (e.g., sintered) to the flat surface of the die clip 372.

[0144] Connector lead 288g1 may be electrically connected to the base terminal b1 of each BBJT, and connector lead 288g2 may be electrically connected to the base terminal b2 of each BBJT. Although not shown in FIG. 3L, switch module 376L may include a first signal frame having a surface electrically connected (e.g., welded) to the surface of a pad of base terminal b1 of each BBJT, and a second signal frame having a flat surface electrically connected (e.g., welded) to the surface of a pad of base terminal b2 of each BBJT. The signal frames may be electrically insulated from each other. Connector lead 288g1 may be electrically connected to the first signal frame, and connector lead 288g2 may be electrically connected to the second signal frame. An end of connector lead 288g1 may be directly connected (e.g., welded) to the first signal frame, and an end of connector lead 288g2 may be directly connected (e.g., welded) to the second signal frame. Alternatively, one or more bond wires may electrically connect the first signal frame to the end of connector lead 288g1, and one or more bond wires may electrically connect the second signal frame to the end of connector lead 288g2.

[0145] FIG. 3O is an example of a packaged switch 247dO. In FIG. 3O, switch 304dO includes four IGBTs connected in parallel. Each collector terminal of the IGBT may have one or more conductive pads with perfectly flat surfaces that can be electrically and thermally directly connected (e.g., sintered) to a flat surface of the die substrate, for example. For purposes of explanation, each collector terminal in this disclosure has only one conductive pad unless otherwise noted. Each emitter terminal of the IGBT may have multiple conductive pads with perfectly flat surfaces that can be electrically and thermally directly connected (e.g., sintered) to a flat surface of a respective pedestal or to a flat surface of a single pedestal, for example. In another version, the flat surfaces of the emitter terminal pads may be directly connected (e.g., sintered) to a flat surface of the die clip.

[0146] In FIG. 3O, the flat surfaces of the pads for the collector terminals c1-c4 may be directly connected (e.g., sintered) to the flat surface of the die substrate 360, and the flat surfaces of the pads for the emitter terminals e1-e4 may be directly connected (e.g., sintered) to the first flat end surface of the pedestal. The second flat end surface at the opposite end of the pedestal (i.e., the second flat end surface) may be directly electrically and thermally connected (e.g., sintered) to the flat surface of the die clip 372. A connector lead 288g may be electrically connected to the gate terminal of each IGBT. For purposes of explanation, each IGBT in this disclosure has only one gate terminal pad unless otherwise noted. Although not shown in FIG. 3O, the switch module 376O may include a strap attached to the same surface of the die substrate 360 ​​to which the pads for the collector terminals c1-c4 are connected. The strap may be electrically insulated from the die substrate 360. One or more bond wires may electrically connect the straps to the pads of the gate terminals of each IGBT. Connector leads 288g may be electrically connected to the straps. The ends of the connector leads 288g may be directly connected (e.g., welded) to the straps. Alternatively, one or more bond wires may electrically connect the straps to the ends of the connector leads 288g.

[0147] FIG. 3P illustrates an example of a packaged switch 247qP. The switch 304qP includes two MOSFETs connected in parallel with two IGBTs. The flat surfaces of the pads for the collector terminal c and the drain terminal d may be directly connected (e.g., sintered) to the flat surface of the die substrate 360, and the flat surfaces of the pads for the emitter terminal e and the source terminal s may be directly connected (e.g., sintered) to the first flat end surface of the pedestal. The flat surface at the opposite end of the pedestal (i.e., the second flat end surface) may be directly electrically and thermally connected (e.g., sintered) to the flat surface of the die clip 372. The connector lead 288g1 may be electrically connected to the gate terminal g of the IGBT, and the connector lead 288g2 may be electrically connected to the gate terminal g of the MOSFET. Although not shown in FIG. 3P, the switch module 376P may include first and second separate straps attached to the same surface of the die substrate 360 ​​to which the pads for the drain terminal d and the collector terminal c are connected. The straps may be electrically insulated from the die substrate 360. One or more bond wires may electrically connect the first strap to the pad of the gate terminal of the illustrated IGBT, and one or more bond wires may electrically connect the second strap to the pad of the gate terminal g of the MOSFET. Connector lead 288g1 may be electrically connected to the first strap, and connector lead 288g2 may be electrically connected to the second strap. An end of connector lead 288g1 may be directly connected (e.g., welded) to the first strap, and an end of connector lead 288g2 may be directly connected (e.g., welded) to the second strap. Alternatively, one or more bond wires may electrically connect the first strap to the end of connector lead 288g1, and one or more bond wires may electrically connect the second strap to the end of connector lead 288g2. The packaged switch 304qP should not be limited to two MOSFETs connected in parallel with two IGBTs.In alternative versions, three or four MOSFETs may be connected in parallel with two IGBTs, three or four IGBTs may be connected in parallel with two MOSFETs, three MOSFETs may be connected in parallel with three IGBTs, and four MOSFETs may be connected in parallel with four IGBTs. To accommodate these alternative versions of packaged switch 304qP, the size (i.e., length and width) of die substrate 360 ​​and die clip 372 must be increased.

[0148] Example of a packaged diode 245 2E-1 through 2E-3, Figures 3M and 3N show an example of a packaged diode 245 from a side view. The case (e.g., case 249) is shown transparent in Figures 3M and 3N to allow a better understanding of the packaged diode's components, their interactions, and their relative positions.

[0149] The example packaged diode 245 shown in Figures 3M and 3N includes diode modules 378M and 378N, respectively. Each diode module includes a power stack, which includes one or more diodes D disposed in electrical and thermal connection between a die substrate 360 ​​and a die clip 372, all of which are symbolically shown. Die substrate terminals 230 and die clip terminals 344 are also symbolically shown. The surfaces of the die substrate terminals 230 and die clip terminals 344 are completely flat and may be located below, above, or flush with the respective surfaces of the case 249. The diode module components, including the die substrate 360 ​​and die clip 372, may vary in size, shape, composition, etc. between the packaged diodes 245 of Figures 3M and 3N.

[0150] Although not shown in Figures 3M and 3N, each power stack may include one or more pedestals, each of which may have completely flat, opposing first and second end faces. The first flat end face of each of the one or more pedestals may be electrically and thermally connected (e.g., sintered) to a flat surface of a current terminal pad of a respective diode D. The second flat end face of each of the one or more pedestals may be electrically and thermally connected (e.g., sintered) to a flat surface of the die substrate 360 ​​or die clip 372 opposite the side having the die substrate terminal 230 or die clip terminal 344. In an alternative version, the power stacks of Figures 3M and 3N do not use pedestals, and the current terminals are directly connected (e.g., sintered) to the flat surfaces of the die clip 372 and die substrate 360, respectively.

[0151] Figures 3M and 3N show the relative positions of the components. The die substrate 360, one or more diodes D, and die clip 372 may be stacked as shown. Current can be transmitted between the die clip terminal 344 and the die substrate terminal 230 through the one or more diodes D. Diode modules 376M and 376N may include connector leads 288ds and 288dc, although for simplicity, neither are shown in Figures 3M and 3N. In many packaged diode versions, connector leads 288ds and 288dc are unnecessary and are omitted.

[0152] Die substrate 360 ​​and die clip 372 can conduct large currents (e.g., 1, 5, 10, 50, 200, 400 amperes, or more) to and from packaged diode 245 via die substrate terminals 230 and die clip terminals 344, respectively. Diodes generate heat. Die substrate 360 ​​and die clip 372 can conduct large amounts of heat generated by one or more diodes D to the exterior of packaged diode 245 via die substrate terminals 230 and die clip terminals 344, respectively.

[0153] 3M and 3N show examples of packaged diodes 245 that can be cooled via the die substrate terminal and the die clip terminal, respectively. In FIGS. 3M and 3N, each cathode terminal of one or more diodes D may have one or more completely flat conductive pads. Each anode terminal of one or more diodes D may have one or more completely flat conductive pads. The flat surface of the pad of the cathode terminal may be directly connected (e.g., sintered) to the flat surface of the die substrate 360, and the flat surface of the pad of the anode terminal may be directly connected (e.g., sintered) to the first flat end face of the respective pedestal. The flat surface of the opposite end of the pedestal (i.e., the second flat end face) may be electrically and thermally connected (e.g., sintered) to the flat surface of the die clip 372. Alternatively, the flat surface of the pad of the anode terminal may be directly connected (e.g., sintered) to the flat surface of the die clip 372.

[0154] Power Stack Terminal Example A power stack is formed by electrically and thermally connecting transistors and / or diodes between the die clip and the die substrate. The first current terminal (e.g., collector terminal, drain terminal, cathode terminal, etc.) pad of each transistor and / or diode may be sintered to the die substrate (or die clip) using a layer of highly conductive sintered material including silver, copper, etc. No dielectric exists between the transistor and / or diode and the die substrate terminal of the connected die substrate (or the die clip terminal of the connected die clip). The second current terminal (e.g., emitter terminal, source terminal, anode terminal, etc.) pad of each transistor and / or diode may be sintered to the die clip (or die substrate) via a layer of highly conductive sintered material including silver, copper, etc. No dielectric exists between the transistor and / or diode and the die clip terminal of the connected die clip (or the die substrate terminal of the die substrate). Therefore, no dielectric should exist between the die substrate terminal and the die clip terminal in a power stack.

[0155] The die substrate terminals and die clip terminals may have rectangular flat surfaces exposed through the case, for example, for connection to a bus bar. The dimensions (e.g., width and length) of the exposed terminals are configured to transmit a large amount of current and heat. The die substrate terminals may be parallel to and opposite (i.e., 180 degrees from) at least one flat surface of the die substrate to which a first current terminal (e.g., collector terminal, drain terminal, etc.) pad is sintered. The die clip terminals may be parallel to and opposite (i.e., 180 degrees from) at least one flat surface of the die clip to which a second current terminal (e.g., collector terminal, drain terminal, etc.) pad is sintered.

[0156] 2A-1 through 2E-3 may be electrically connected to one or more first current terminals (e.g., drains) and one or more second current terminals (e.g., sources) of one or more transistors in packaged switches 247p, 247q, 247s, and 247d, respectively. Alternatively, die substrate terminal 230 and die clip terminal 344 may be electrically connected to one or more first current terminals (e.g., cathodes) and one or more second current terminals (e.g., anodes) of diodes in packaged diode 245, respectively.

[0157] The die substrate terminals and die clip terminals may be configured for direct electrical and / or thermal connection to a device. The die substrate terminals 230 or die clip terminals 344 may be electrically and / or thermally connected to a heat sink, a bus bar, or the surface of a bus bar that also functions as a heat sink. For example, the die substrate terminals 230 or die clip terminals 344 may have a V+ terminal and be electrically and / or thermally connected to the flat surface of a “V+ bus bar” that is electrically connectable to the V+ terminal of a battery, fuel cell, DC / DC converter, etc. The die substrate terminals 230 or die clip terminals 344 may have a V− terminal and be electrically and / or thermally connected to a “V− bus bar” that is electrically connectable to the V− terminal of a battery, fuel cell, DC / DC converter, etc. The die substrate terminals 230 or die clip terminals 344 may have AC terminals and be electrically and / or thermally connected to an AC bus bar, also known as a “phase bus bar,” that is electrically connectable to the stator winding W of a motor, the inductor L of a filter, or the terminals of other devices. The heat sink or bus bar may have a flat surface that can be press-fit, welded, sintered, or otherwise connected to a flat surface of the die substrate terminal 230 or the die clip terminal 344, thereby forming an electrical and thermal connection between the two. A press-fit or soldered connection can reduce or eliminate problems due to differences in thermal expansion coefficients, as described below.

[0158] Busbars can have a variety of configurations depending on the design of the power converter in which they are used. Busbars may be assembled from several components. Typically, busbars are metallic elements that distribute high currents (e.g., 10, 20, 50, 100, 200, 400, 800 amperes, or more). The material composition (e.g., copper, aluminum, etc.) and cross-sectional area of ​​the busbar or its elements determine the maximum allowable current and parasitic parameters. Busbars with larger cross-sectional areas have smaller parasitic parameters, such as parasitic inductance, which affect voltage overshoots (also known as voltage spikes). The inductance of the disclosed busbars may be 1.0, 0.8, 0.6, 0.4 nH, or less, between the busbar terminals (e.g., V+, V-, or phase busbar terminals) and the die substrate terminals or die clip terminals of the packaged switch to which the busbar is directly connected.

[0159] The busbar or heat sink may have one or more channels. Cooling air supplied by a fan may flow through the channels. Alternatively, the channels may house tubes, as described below. Cooling fluid may flow through the tubes. The tubes may be in fluid communication with a pump and a radiator through interconnected manifolds and hoses. The manifold may be connected to each end of the channel or tubes within the channel.

[0160] The tube may be formed (e.g., extruded) from a metal such as copper or aluminum. The entire inner and / or outer surface of the metal tube may be coated with one or more layers of a thermally conductive and electrically insulating dielectric material. The outer dielectric layer may electrically insulate the metal tube from the heat sink or bus bar in which the tube is housed. The inner dielectric layer may electrically insulate the cooling fluid flowing within the metal tube. The outer surface of the metal tube may be selectively coated with a dielectric material. In other words, the outer surface of the metal tube may be partially coated with a dielectric material. In another version, there is no dielectric between the cooling fluid (e.g., a dielectric fluid such as oil) flowing within the metal tube and the heat sink or bus bar in which the tube is housed. In this alternative version, the outer surface of the metal tube may be electrically and thermally connected to the heat sink or bus bar in which the tube is housed. The tube may take the form of a concentric metal (e.g., copper) tube. A fluid may flow within the inner tube of the concentric tubes. A dielectric material may be disposed between the concentric tubes (i.e., between the outer surface of the inner tube and the inner surface of the outer tube) to electrically insulate the concentric tubes from one another.

[0161] The tube may be formed (e.g., extruded) from a thermally conductive and electrically insulating material, such as aluminum nitride or beryllium oxide. For purposes of illustration, the thermally conductive and electrically insulating tube is formed from aluminum nitride, but it is understood that the tube may be formed from other electrically insulating and thermally conductive materials. The entire inner and / or outer surface of the aluminum nitride tube may be coated with one or more layers of metal. Alternatively, the metal layer may be formed only on selected portions of the outer surface of the aluminum nitride tube. In other words, the aluminum nitride tube may be partially coated with metal. A single aluminum nitride tube may be housed in separate bus bars, and only those portions of the tube may be coated with an outer metal layer. A thin metal layer may be formed only on the ends of the tube (dielectric-coated metal tube or aluminum nitride tube), which improves the seal between the tube end and the fluid manifold. The bus bar may be cast around the aluminum nitride tube. The aluminum nitride tube in the cast bus bar does not need to be coated with a thin metal layer, except for the ends that connect to the manifold.

[0162] In general, heat sinks or bus bars may be formed (e.g., extruded, 3D printed, cast, etc.) in whole or in part from a conductive metal such as copper or aluminum, and may have a variety of shapes, sizes, and dimensions (e.g., length, width, height, etc.) to suit different design purposes. Heat sinks or bus bars that also function as heat sinks may be formed by casting aluminum, copper, or other materials around a tube. Casting is a process in which liquid metal is poured into a mold that has a negative impression (i.e., a three-dimensional negative image) of the intended shape. A bare metal tube or a metal tube completely or partially coated with a thin layer of a dielectric material or other material may be placed in the mold before the liquid metal is poured. A bare aluminum nitride tube or an aluminum nitride tube completely or partially coated with a thin layer of a metal or other material may be placed in the mold before the liquid metal is poured. In other words, the bus bar may be cast around the tube. A heat sink or busbar that also functions as a heat sink may be formed by sandwiching a bare, fully, or partially coated metal or aluminum nitride tube between two metal halves, positioning them in aligned grooves, and then joining (e.g., welding, soldering, sintering, brazing, etc.) the two metal halves. The two halves may be formed by extrusion, 3D printing, casting, etc. Before joining the halves, a thin layer of thermal paste (also known as thermal compound, thermal grease, thermal interface material (TIM), thermal gel, heat paste, heat sink compound, heat sink paste, or CPU grease) may be applied to the exterior surface of the tube to eliminate voids or spaces at the interface between the tube and the heat sink or busbar that also functions as a heat sink, forming a better thermal connection. In yet another version, the heat sink or bus bar containing the bare, fully or partially coated tube may be heated to reflow the metal of the heat sink or bus bar, eliminating voids or spaces at the interface between the tube and the heat sink or bus bar and forming a better thermal bond.

[0163] Examples of switch modules and diode modules 3A-3P, FIGS. 4A-1-4H illustrate an example switch module 376, an example diode module 378, and their components. Each example switch module 376 and diode module 378 includes a switch or diode sandwiched between a die substrate and a die clip.

[0164] FIG. 4A-1 shows top and side views of an example die substrate 360, connector leads 288ds, and connector leads 288g. The die substrate is formed (e.g., by stamping, cutting, sawing, dicing, etc.) from a thin (e.g., 0.7 mm to 1.5 mm) metal sheet, which may or may not be electroplated with silver. Alternatively, the die substrate can be formed (e.g., by stamping, cutting, sawing, dicing, etc.) from a thin (e.g., 0.7 mm to 1.5 mm) laminate sheet, as shown in FIG. 2H. An example die substrate 360 ​​and collector leads 288ds can be formed from a thin (e.g., 0.7 mm to 1.5 mm) laminate sheet, as shown in FIG. 2H. The connector leads 288ds can be integrally connected to the die substrate 360 ​​as shown. In another version, the connector leads 288ds can be formed separately and then attached (e.g., welded) to the die substrate 360. In yet another version, connector leads 288ds may not be connected to die substrate 360.

[0165] Die substrate 360 ​​comprises opposing, completely flat, and substantially equal-area surfaces, one of which is designated as 362, the other of which defines an example of die substrate terminal 230. Die substrate terminal 230 may be configured to be thermally and electrically connected to a planar surface of a device, such as a bus bar, as described below.

[0166] Die substrate 360 ​​may have a width wds of about 13.5 mm and a length lds of about 16.5 mm. Connector leads 288ds may have a width of about 1.2 mm and a length of about 20 mm. Connector leads 288g may have a width of about 1.2 mm and a length of about 18 mm. Bond area 367 provides a surface onto which bond wires can be wirebonded.

[0167] The current terminal (e.g., drain terminal, collector terminal, cathode terminal, etc.) pad surface of the transistor and / or diode may be electrically and thermally directly attached to surface 362 of die substrate 360. For example, the flat first current terminal (e.g., drain terminal, collector terminal, cathode terminal, anode 2 terminal, etc.) pad surface of switch 304 or diode D shown in Figures 3A-3F, 3H-3K, and 3M-3P may be electrically and thermally directly attached (e.g., sintered) to surface 362.

[0168] The size of the die substrate 360 ​​(i.e., widths wds and lengths lds) may depend on the number and / or type of transistors in the switch 304 connected to it. For example, assuming IGBT dies are larger in size than MOSFET dies, the area of ​​the surface 362 required to accommodate four BBJTs or four IGBTs connected in parallel may be larger than the area of ​​the surface 362 required to accommodate four MOSFETs connected in parallel, or the area required to accommodate four MOSFETs connected in parallel may be smaller than the area of ​​the surface 362 required to accommodate two MOSFETs and two IGBTs connected in parallel. For ease of explanation and illustration, the size (length and width) of the transistor die will be assumed to be equal regardless of transistor type, unless otherwise indicated.

[0169] FIG. 4A-2 shows the die substrate 360 ​​of FIG. 4A-1 after four transistors T1-T4 have been electrically and thermally attached to the surface 362. More specifically, the flat surfaces of the first current terminal (e.g., drain terminal, collector terminal, etc., not shown) pads of transistors T1-T4 may be sintered to the surface 362. A low-resistance path may exist between the die substrate terminal 230 and each first current terminal pad. Each die-substrate bond (e.g., a sintered bond, not shown) of FIG. 4A-2 connecting the first current terminal pad surface to the surface 362 may conduct 1, 2, 5, 10, 20, 50, 100, 200, 300, 750 watts or more of heat while simultaneously conducting 1, 5, 10, 50, 100, 200, 400 amperes or more of current. Each die-substrate bond may have a length and width approximately equal to the length and width of the respective first current terminal pad surface.

[0170] T1 through T4 may be the same type of transistor, or T1 through T4 may be a mixture of different types of transistors. For example, T1 through T4 may be MOSFETs, and the flat surfaces of the drain terminal pads of T1 through T4 may be sintered to surface 362. T1 through T4 may be IGBTs, and the flat surfaces of the collector terminal pads of T1 through T4 may be sintered to surface 362. In another example, T1 and T2 may be MOSFETs, and T3 and T4 may be IGBTs. In this version, the flat surfaces of the drain terminal pads of T1 and T2 may be sintered to surface 362, and the flat surfaces of the collector terminal pads of T3 and T4 may be sintered to surface 362. In another version, one of the transistors (e.g., T1) may be replaced with a diode, and the other three transistors (e.g., T2 through T4) may be IGBTs. In this version, the flat surfaces of the collector terminal pads of the three IGBTs and the flat surfaces of the cathode terminal pads of the diodes may be sintered to surface 362.

[0171] Each of transistors T1-T4 may include a pair of second current terminal (e.g., source terminal, emitter terminal, etc.) pads, although it is understood that a transistor may have fewer or more than one pair of second current terminal pads. Each second current terminal pad may have a flat surface. An example of a flat surface 395 of a second current terminal pad is shown. Each of transistors T1-T4 includes a control terminal (e.g., gate terminal) pad having a flat surface. An example of a surface 384 of a control terminal pad is shown. Pads are not shown in the side view of FIG. 4A-2.

[0172] 4A-2 also shows examples of gate strap 364, bond wire 365, and bond wire 366. Gate strap 364 may be formed of a conductive metal such as copper and attached to surface 362 via an electrically insulating material (not shown), thereby electrically isolating gate strap 364 from die substrate 360. Connector lead 288g may be electrically connected to gate strap 364 via bond wire 365. Multiple bond wires 366 of approximately equal length may electrically connect gate strap 364 to respective surfaces 384 of the control terminal pads. Each bond wire 366 may be wire bonded to strap 364 at a location on strap 364 approximately equidistant from the point on strap 364 to which bond wire 365 is wire bonded. In an alternative version, the end of connector lead 288g with an extended length may be attached (e.g., welded) to strap 364. In yet another alternative version, the ends of the extended length connector leads 288g may be attached to the surface 362 via an electrically insulating layer, thereby electrically isolating the extended length connector leads 288g from the die substrate 360. Multiple bond wires of approximately equal length may electrically connect the extended length connector leads 288g to the respective surfaces 384 of the control terminal pads.

[0173] 4A-3 shows the structure of FIG. 4A-2 after an exemplary pedestal 1104 has been electrically and thermally attached (e.g., sintered) directly to the surface 395 of each of the second current terminal pads of transistors T1-T4. The pedestal, including pedestal 1104, may be formed from a thin (e.g., 1.0 mm to 1.2 mm) laminate sheet as shown in FIG. 2H. Pedestal 1104 may be approximately 1.65 mm wide and approximately 2.8 mm long.

[0174] The pedestal may have first and second end faces that are completely flat and facing each other. Only the flat first end face 1101 is shown in FIG. 4A-3. The flat end faces of the pedestal, such as pedestal 1104, may have the same size and shape. The second flat end face of pedestal 1104 may be directly electrically and thermally attached (e.g., sintered) to the flat surface 395 of each second current terminal pad. The second flat end faces of pedestal 1104 may have a shape (e.g., approximately rectangular) and size (e.g., approximately 2.8 mm x 1.65 mm) that is substantially the same as, but slightly smaller than, the shape and size of the flat surface 395 of each second current terminal pad to which they are electrically and thermally attached. This may ensure that pedestal 1104 does not contact transistors T1-T4 outside the area occupied by the second current terminal (e.g., source terminal) pad. The second flat end surface of pedestal 1104 can distribute mechanical stress more evenly. Pedestals such as pedestal 1104 can reduce the current flux through source terminal pad surface 395 compared to the current flux (i.e., current density) through a small area on the source terminal pad surface connected to a bond wire. Each second joint (e.g., a sintered joint) connecting second current terminal pad surface 395 to the second flat end surface of pedestal 1104, and each pedestal 1104, can conduct 1, 2, 5, 10, 20, 50, 100, 200, 350 watts or more of heat while simultaneously conducting 1, 5, 10, 20, 50, 100, 200, 350 watts or more of current. Each of these second joints can have a length and width approximately equal to the length and width of the respective second flat end surface of pedestal 1104. The first flat end faces of the pedestals, such as surface 1101 in Figure 4A-3, can be arranged in a common plane for attachment to, for example, the flat surface of a die clip. Pedestals, such as pedestal 1104 in a switch, can have different thicknesses between their flat end faces to accommodate transistors having current terminal pad surfaces with different heights measured relative to surface 362, and the first end faces of the pedestals can be arranged in a common plane for electrical and thermal attachment to, for example, the flat surface of a die clip.

[0175] The transistors and / or diodes can be electrically and thermally connected to the die clip. FIGS. 4A-4 show top and side views of an example die clip 372 and an example connector lead 288dc. The die clip 372 can be formed (e.g., by stamping, cutting, sawing, dicing, etc.) from a thin (e.g., 0.7 mm to 1.5 mm) metal or metal composite sheet. Alternatively, the die clip 372 can be formed (e.g., by stamping, cutting, sawing, dicing, etc.) from a thin (e.g., 0.7 mm to 1.5 mm) laminate sheet as shown in FIG. 2H. Unless otherwise noted, the die clip 372 is formed from a thin copper sheet. The die clip 372 can include an outer layer of an electroplated sintering-facilitating material (e.g., silver). The connector lead 288dc can be integrally connected to the die clip 372 as shown. In another version, the connector lead 288dc may be formed separately and then attached (e.g., welded) to the die clip 372. In yet another version, the connector lead 288dc may not be connected to the die clip 372.

[0176] Die clip 372 includes opposing, substantially equal-area, substantially flat surfaces 344 and 375. Surfaces 344 and 375 may be completely flat. Surface 344 defines an example die clip terminal 344 and may be configured to be thermally and electrically connected to a flat surface of a device, such as a bus bar, as described below. Surface 375 may be electrically and thermally attached (e.g., sintered) directly to a pedestal, current terminal pad, or the like.

[0177] In one version, the die clip 372 may have a width wdc of approximately 13.0 mm and a length ldc of approximately 16.0 mm. The connector leads 288dc may have a width of approximately 1.2 mm and a length of approximately 20 mm. As with the die substrate, the size of the die clip 372 may need to be adjusted depending on the number and / or type of transistors in the switch 304 connected to it. For example, the area of ​​the surface 375 required to accommodate a switch having four IGBTs connected in parallel or four BBJTs connected in parallel may be larger or smaller than the area of ​​the surface 375 required to accommodate a switch having four MOSFETs connected in parallel. Also, the area required to accommodate a switch having four MOSFETs connected in parallel may be smaller than the area 375 required to accommodate a switch having two MOSFETs and two IGBTs connected in parallel, assuming the IGBT die is larger than the MOSFET die.

[0178] A surface of a component, such as a pedestal including pedestal 1104, can be electrically and thermally directly attached to a flat surface of the die clip. For example, a first flat end surface of the pedestal, such as surface 1101, can be electrically and thermally directly connected (e.g., sintered) to surface 375. In some versions, flat surfaces of current terminal pads of transistors and / or diodes can be electrically and thermally directly connected (e.g., sintered) to surface 375. For example, the flat pad surface of the drain terminal d2 shown in FIG. 3J or 3K can be sintered to surface 375 of a die clip 372 formed from a thin (e.g., 0.7 mm to 1.5 mm) laminate sheet as shown in FIG. 2H. The width wdc and / or length ldc dimensions can be increased or decreased depending on the number of transistors connected in parallel or anti-parallel to the die clip 372.

[0179] 4A-5 shows top and side views of the structure of FIG. 4A-3 after the flat surface 375 of the die clip 372 has been electrically and thermally attached (e.g., sintered) directly to the flat surface 1101 of the pedestal 1104. Each die clip joint (e.g., sintered joint) connecting a first flat surface of the pedestal, such as surface 1101, to surface 375 can conduct 1, 2, 5, 10, 20, 50, 100, 300, 600 watts or more of heat while simultaneously conducting 1, 5, 10, 20, 50, 100, 200, 400 amps or more of current. Each die clip joint can have a length and width approximately equal to the length and width of a respective first flat end face of the pedestal, such as surface 1101. A low-resistance path can exist between the die clip terminal 344 and each second current terminal pad, such as pad 395.

[0180] If T1-T4 take the form of MOSFETs, the structure shown in FIG. 4A-5 can be a version of switch module 376B shown in FIG. 3B. If T1-T4 take the form of IGBTs, the structure shown in FIG. 4A-5 can be a version of switch module 376O shown in FIG. 3O. After die clip 372 is electrically and thermally attached to base 1104, a case can be formed around the switch module of FIG. 4A-5, for example, using transfer molding, to produce the example packaged switch 247s shown in FIGS. 2C-1-2C-3. Alternatively, a case can be formed around the switch module of FIG. 4A-5, for example, using transfer molding, to produce the example packaged switch 247dB or 247dO shown in FIGS. 3B and 3O, respectively, which are examples of packaged switch 247d shown in FIGS. 2D-1-2D-3. Prior to case formation, some or all of the connector leads 288 can be bent to place the case exterior ends of the connector leads 288 in a common plane, as shown in Figures 2C-3 and 2D-3. In alternative versions, connector leads 288ds and / or 288dc can be omitted to create alternative versions of packaged switch 247d.

[0181] In FIG. 4A-3, the pedestals 1104 are electrically and thermally directly connected (e.g., sintered) to each second current terminal pad. The pedestals can be connected to adjacent second current terminal pads in the transistor. FIG. 4A-6 shows the structure of FIG. 4A-2, with exemplary pedestals 1108 electrically and thermally directly attached (e.g., sintered) to each pair of second terminals. The pedestals 1108 are longer than the pedestals 1104 and may be formed from a thin (e.g., 1.0 mm to 1.2 mm) laminate sheet as shown in FIG. 2H, although it is understood that the pedestals 1108 should not be limited thereto. The pedestals 1108 may be approximately 2.8 mm wide and approximately 3.3 mm long.

[0182] Like pedestal 1104, pedestal 1108 may have first and second flat end faces that face each other. Only first flat end face 1107 is shown in FIGS. 4A-6 . Each second flat end face is directly electrically and thermally attached (e.g., sintered) to the flat surface 395 of an adjacent second current terminal pad in a respective transistor. The flat second end face (not shown) of each pedestal 1108 may have a shape (e.g., substantially rectangular) and size (e.g., approximately 2.8 mm × 3.3 mm) that is generally the same as the shape and size of the surface 395 of an adjacent second current terminal pad in a transistor and the area that separates the adjacent second current terminal pads. Each second joint (e.g., a sintered joint) connecting a pair of adjacent second current terminal pad surfaces 395 to the flat second end face of the pedestal 1108, and each pedestal 1108, may conduct 10, 20, 50, 100, 300, 700 watts or more of heat while simultaneously conducting 10, 20, 50, 100, 200, 400 amps or more of current. Each second joint may have a length and width approximately equal to the length and width of the flat second end face of the pedestal 1108.

[0183] FIG. 4A-7 shows top and side views of the structure of FIG. 4A-6 after the flat surface 375 of the die clip 372 of FIG. 4A-4 has been electrically and thermally attached (e.g., sintered) directly to the flat surface 1107 of the base 1108. A low-resistance path can exist between the die clip terminal 344 and each second current terminal pad 395. Each die clip joint (e.g., a sintered joint) connecting surface 1107 to surface 375 can conduct 10, 20, 50, 100, 300, 700 watts or more of heat while simultaneously conducting 10, 20, 50, 100, 200, 400 amperes or more of current. Each die clip joint (not shown) in FIG. 4A-7 can have a length and width approximately equal to the length and width of the respective first flat end surface 1107.

[0184] If T1-T4 take the form of MOSFETs, the structure shown in FIG. 4A-7 can be a version of switch module 376B shown in FIG. 3B. If T1-T4 take the form of IGBTs, the structure shown in FIG. 4A-7 can be a version of switch module 376O shown in FIG. 3O. After die clip 372 is attached, a case may be formed around the switch module of FIG. 4A-7, for example, using transfer molding, to produce an example of packaged switch 247s shown in FIGS. 2C-1-2C-3. Alternatively, a case may be formed around the switch module of FIG. 4A-7, for example, using transfer molding, to produce an example of packaged switch 247dB or 247dO shown in FIGS. 3B and 3O, respectively, which is an example of packaged switch 247d shown in FIGS. 2D-1-2D-3. Prior to case formation, some or all of the connector leads 288 can be bent to place the case exterior ends of the connector leads 288 in a common plane, as shown in Figures 2C-3 and 2D-3. In an alternative version, connector leads 288ds and / or 288dc are not included, thereby creating an alternative version of packaged switch 247d.

[0185] In yet another version of the switch module 376B, the pedestal may be integrally formed with the bridge (i.e., an integral bridge). Figure 4A-8 illustrates the structure of Figure 4A-2, where each of the exemplary integral bridges 371 is directly electrically and thermally attached (e.g., sintered) to the second current terminal of the respective adjacent transistor. The integral bridges 371 may have a generally flat surface 383 that is approximately 10.8 mm long and 2.8 mm wide.

[0186] The integral bridge 371 may be formed (e.g., cut) from a thin (e.g., 0.7 mm to 1.5 mm) laminate sheet as shown in FIG. 2H. The integral pedestals 1110 may be created by cutting grooves into the laminate sheet. The flat end surface of each integral pedestal 1110 may have the same size and shape as the flat end surface 1107 of the pedestal 1108. Each flat end surface may be directly electrically and thermally attached (e.g., sintered) to the surface 395 of an adjacent current terminal pad in the respective transistor. Each second joint (e.g., sintered joint) connecting a pair of adjacent second current terminal pad surfaces 395 to the flat second end surface of the integral pedestal 1110, and each pedestal 1110, may conduct 10, 20, 50, 100, 300, 700 watts or more of heat while simultaneously conducting 10, 20, 50, 100, 200, 400 amperes or more of current. Each of these second joints may have a length and width approximately equal to the length and width of the flat second end face of the base 1110. Each bridge 371 may have a flat surface 383 that can be sintered to the flat surface of the die clip 372.

[0187] The grooves of the integral bridge 371 may extend across its entire width and span between pairs of adjacent transistors. For example, the groove of the integral bridge 371-1 may span between transistors T1 and T2, and the groove of the integral bridge 371-2 may span between transistors T3 and T4. The grooves may be formed by cutting into the laminated sheet using, for example, a rotary burr (also called a die grinder bit) of a rotary tool. The grooves may be deep enough to allow liquid molding compound to flow freely between the pedestals 1110 when the flat end faces of the pedestals 1110 are electrically and thermally attached (e.g., sintered) directly to the second current terminal (e.g., source terminal) pad surfaces 395 of the respective transistors. The grooves may be rectangular with three sides (i.e., rectangular grooves) as shown in side views in FIGS. 4A-8, or they may be inverted V-shaped with two sides (i.e., V-grooves). In a V-groove, the cross-sectional width of the pedestals 1110 widens toward the bridge side to which they are integrally connected. V-grooves may provide better heat dissipation compared to rectangular grooves, but rectangular grooves may allow liquid mold compound to flow better between the pedestals 1110 during transfer molding.

[0188] FIG. 4A-9 shows a top view and a side view of the structure of FIG. 4A-8 after the die clip 372 of FIG. 4A-4 has been added. Specifically, FIG. 4A-9 shows the structure after the flat surface 375 of the die clip 372 has been electrically and thermally attached (e.g., sintered) directly to the flat surface 383 of the integral bridge 371. A low-resistance path can exist between the die clip terminal 344 and each second current terminal pad 395. Each die clip joint (e.g., a sintered joint) connecting surface 383 to surface 375 can conduct 10, 20, 50, 100, 300, 700, 1400 watts or more of heat while simultaneously conducting 10, 20, 50, 100, 200, 400, 800 amperes or more of current. Each die clip joint (not shown) in FIG. 4A-9 can have a length and width approximately equal to the length and width of the respective surface 383.

[0189] If T1-T4 are MOSFETs, the structure shown in FIG. 4A-9 can be a version of switch module 376B shown in FIG. 3B. If T1-T4 are IGBTs, the structure shown in FIG. 4A-9 can be a version of switch module 376O shown in FIG. 3O. After die clip 372 is electrically and thermally attached to integral bridge 371, a case can be formed around the switch module of FIG. 4A-9, for example, using transfer molding, to produce an example of packaged switch 247s shown in FIGS. 2C-1-2C-3. Alternatively, a case can be formed around the switch module of FIG. 4A-9, for example, using transfer molding, to produce a version of packaged switch 247dB or 247dO shown in FIGS. 3B and 3O, respectively, which is an example of packaged switch 247d shown in FIGS. 2D-1-2D-3. Prior to case formation, some or all of the connector leads 288 can be bent to place the case exterior ends of the connector leads 288 in a common plane, as shown in Figures 2C-3 and 2D-3. In an alternative version, connector leads 288ds and / or 288dc are not included, thereby creating an alternative version of packaged switch 247d.

[0190] Returning to FIG. 4A-2, all control terminals of transistors T1-T4 are electrically connected to gate strap 364. In an alternative version, the control terminals of the transistors in the switch may be electrically connected to individual gate straps. FIG. 4B-1 shows the structure of FIG. 4A-2 in which gate strap 364 is replaced with a pair of gate straps 359-1 and 359-2, which are attached to the surface 362 of the die substrate 360 ​​via an electrically insulating material (not shown). Gate straps 359-1 and 359-2 may be narrower than gate strap 364. Otherwise, gate straps 359-1 and 359-2 are substantially identical to gate strap 364. FIG. 4B-1 also shows that connector lead 288g of FIG. 4A-2 has been replaced with a pair of connector leads 288g-1 and 288g-2. Connector lead 288g is substantially identical to connector leads 288g-1 and 288g-2.

[0191] Bond wires 366-1 and 366-2 of approximately the same length may electrically connect gate strap 359-1 (or extended length connector lead 288g-1) to the surface 384 of the control terminal (e.g., gate terminal) pad of transistors T1 and T2, respectively. Bond wires 366-3 and 366-4 of approximately the same length may electrically connect gate strap 359-2 (or extended length connector lead 288g-2) to the surface 384 of the control terminal pad of transistors T3 and T4, respectively. Connector leads 288g-1 and 288g-2 are electrically connected to gate straps 359-1 and 359-2, respectively, by bond wires 365-1 and 365-2, respectively. In an alternative version, the ends of extended length connector leads 288g-1 and 288g-2 may be connected (e.g., welded) to gate straps 359-1 and 359-2, respectively. In yet another version, the ends of extensions 288g-1 and 288g-2 may be attached to surface 362 via an electrically insulating material. In this alternative version, bond wires 366-1 and 366-2 of approximately the same length may electrically connect extended connector lead 288g-1 to surface 384 of the control terminal pads of transistors T1 and T2, and bond wires 366-3 and 366-4 of approximately the same length may electrically connect extended connector lead 288g-2 to surface 384 of the control terminal pads of transistors T3 and T4.

[0192] Transistors T1-T4 in FIG. 4B-1 may be the same type, or transistors T1-T4 may be a mix of different types. For example, T1-T4 may all be MOSFETs or IGBTs. T1 and T2 may be MOSFETs and T3 and T4 may be IGBTs, or T1 and T3 may be MOSFETs and T2 and T4 may be IGBTs. In a mixed-transistor version, the flat surfaces of the first current terminal (e.g., drain and collector) pads of T1-T4 may be electrically and thermally attached (e.g., sintered) directly to surface 362. In yet another version, one of the transistors (e.g., T1) may be replaced with a diode, and transistors T2-T4 may take the form of an IGBT. In a mixed IGBT / diode version, the flat collector terminal pad of the IGBT and the flat cathode terminal pad of the diode may be electrically and thermally attached (e.g., sintered) directly to surface 362. A low resistance path may exist between the die substrate terminal 230 and the drain or collector terminal pad of each transistor T or diode.

[0193] FIG. 4B-2 shows the structure of FIG. 4B-1 after the pedestal 1108 has been electrically and thermally directly attached (e.g., sintered) to the adjacent surface 395 within each transistor. FIG. 4B-3 shows top and side views of the structure of FIG. 4B-2 after the die clip 372 of FIG. 4A-4 has been added. Specifically, in FIG. 4B-3, the flat surface 375 of the die clip 372 is electrically and thermally directly attached (e.g., sintered) to the flat surface 1107 of the pedestal 1108. A low-resistance path may exist between the die clip terminal 344 and each second current terminal pad 395. Transistors T1 and T2 may be controlled by a first control terminal signal received via connector lead 288g-1, and transistors T3 and T4 may be independently controlled by a separate second terminal control signal received via connector lead 288g-2.

[0194] If transistors T1-T4 are MOSFETs, the structure shown in FIG. 4B-3 can be a version of switch module 376E in FIG. 3E. If transistors T1 and T2 are IGBTs and T3 and T4 are MOSFETs, the structure shown in FIG. 4B-3 can be a version of switch module 376P in FIG. 3P. In another version, transistors T1-T4 may each be an IGBT. After die clip 372 is attached to base 1108, a case may be formed around the switch module shown in FIG. 4B-3, using, for example, transfer molding, to produce a version of packaged switch 247qE or 247qP shown in FIGS. 3E and 3P, respectively, which is an example of packaged switch 247q shown in FIGS. 2B-1-2B-3. Prior to case formation, some or all of connector leads 288 may be bent to position the case exterior ends of connector leads 288 in a common plane, as shown in FIG. 2B-3. In an alternative version, connector leads 288ds and / or 288dc are not included, creating an alternative version of packaged switch 247q.

[0195] FIG. 4B-4 illustrates the structure of FIG. 4B-2, with bond wires 366-1 through 366-3 electrically connecting gate strap 359-1 to control terminal pad surface 384 of transistors T1 through T3, and bond wire 366-4 electrically connecting gate strap 359-2 to control terminal pad surface 384 of transistor T4. Transistors T1 through T4 in FIG. 4B-4 may be the same type, or transistors T1 through T4 may be a mix of different types. Transistors T1 through T3 may be controlled by a control terminal signal received via connector lead 288g-1, and transistor T4 may be independently controlled by a separate terminal control signal received via connector lead 288g-2. FIG. 4B-5 illustrates top and side views of the structure of FIG. 4B-4 after the die clip 372 of FIG. 4A-4 has been added. Specifically, FIG. 4B-5 shows the structure after the flat surface 375 of the die clip 372 has been electrically and thermally attached (e.g., sintered) directly to the flat surface 1107 of the base 1108. If transistors T1-T3 are MOSFETs and transistor T4 is an IGBT, the structure shown in FIG. 4B-5 can be a version of the switch module 376F of FIG. 3F. After the die clip 372 is electrically and thermally attached to the base 1108, a case can be formed around the switch module shown in FIG. 4B-5, using, for example, transfer molding, to produce an example of the packaged switch 247qF shown in FIG. 3F, which is an example of the packaged switch 247q shown in FIGS. 2B-1-2B-3. Prior to case formation, some or all of the connector leads 288 can be bent to position the case exterior ends of the connector leads 288 in a common plane, as shown in FIG. 2B-3. In an alternative version, connector leads 288ds and / or 288dc are not included, creating an alternative version of packaged switch 247q.

[0196] The surfaces of the transistor current terminal pads may be electrically and thermally attached to the die clip. FIG. 4C-1 shows the die clip 372 after the surfaces of the first current terminal (e.g., drain, collector, etc.) pads of transistors T5-T8 have been electrically and thermally attached (e.g., sintered) directly to surface 375. A low-resistance path may exist between the die clip terminal 344 and each first current terminal pad of transistors T5-T8. Each joint (e.g., a sintered joint) connecting the first current terminal pad surface to surface 375 in FIG. 4C-1 may conduct 10, 20, 50, 100, 200, 300, 750 watts or more of heat while simultaneously carrying 50, 100, 200, 400 amps or more of current. Each of these joints (not shown in FIG. 4C-1) may have a length and width approximately equal to the length and width of the respective first current terminal pad surface. In FIG. 4C-1, die clip 372 may be formed from a thin (e.g., 0.7 mm to 1.5 mm) laminate sheet, as shown in FIG. 2H. T5-T8 may be the same type of transistor, or T5-T8 may be a mix of different types of transistors. For example, T5 and T6 may be MOSFETs, and T7 and T8 may be IGBTs. In this version, the flat surfaces of the drain terminal pads of T5 and T6 and the flat surfaces of the collector terminal pads of T7 and T8 may be sintered to surface 375. In another version, one of the transistors (e.g., T5) may be replaced with a diode, and transistors T6-T8 may take the form of IGBTs. In this version, the flat collector terminal pads of the three IGBTs and the flat cathode terminal pads of the diodes may be electrically and thermally attached (e.g., sintered) directly to surface 375.

[0197] Each of transistors T5-T8 may include a pair of second current terminal (e.g., source terminal, emitter terminal, etc.) pads. Each second current terminal pad may have a flat surface 395. Each of transistors T5-T8 includes a control terminal (e.g., gate terminal) pad having a flat surface 384. The pads are not shown in the side view of FIG. 4C-1.

[0198] FIG. 4C-1 also shows an example of a gate strap 364-2, bond wires 365-2, and bond wires 366. The gate strap 364-2 may be formed of a conductive metal such as copper and may be attached to the surface 375 via an electrically insulating layer (not shown), thereby electrically insulating the gate strap 364-2 from the die clip 372. A connector lead 288g-2 may be electrically connected to the gate strap 364-2 via the bond wires 365-2. Multiple bond wires 366 of approximately equal length may electrically connect the gate strap 364-2 to the surface 384 of each of the control terminal pads. Each bond wire 366 may be wire bonded to the strap 364-2 at a location on the strap 364-2 approximately equidistant from the point on the strap 364-2 to which the bond wire 365-2 is wire bonded. In an alternative version, the end of the extended length connector lead 288g-2 may be attached (e.g., welded) to the strap 364-2. In yet another alternative version, the ends of the extended length connector leads 288g-2 may be attached to the surface 375 via an electrically insulating layer, thereby electrically insulating the extended length connector leads 288g-2 from the die clip 372. Multiple bond wires of approximately equal length may electrically connect the extended length connector leads 288g-2 to respective surfaces 384 of the control terminal pads.

[0199] 4A-6, FIG. 4C-2 shows the structure of FIG. 4C-1 after the second current terminals of transistors T5-T8 have been thermally and electrically attached (e.g., sintered) directly to respective end surfaces 1107 of pedestal 1108, pedestal 1108 has been thermally and electrically attached (e.g., sintered) directly to respective second terminals of transistors T1-T4, and transistors T1-T4 have been electrically connected back-to-back with transistors T5-T8, respectively. For illustrative purposes, gate strap 364, bond wire 365, and surface region 367 of FIG. 4A-6 have been relabeled gate strap 364-1, bond wire 365-1, and surface region 367-1 in FIG. 4C-2. Transistors T1-T4 may be controlled by a first control terminal signal received via connector lead 288g-1, and transistors T5-T8 may be independently controlled by a separate second terminal control signal received via connector lead 288g-2.

[0200] If T1-T8 are MOSFETs, the structure shown in FIG. 4C-2 can be a version of switch module 376J in FIG. 3J. In this case, the source terminals of MOSFETs T1-T4 are electrically connected to the source terminals of MOSFETs T5-T8, respectively. After die clip 372 is attached to base 1108, a case may be formed around the switch module shown in FIG. 4C-2, for example, using transfer molding, to produce an example of packaged switch 247qJ shown in FIG. 3J, which is an example of packaged switch 247q shown in FIGS. 2B-1-2B-3. Prior to case formation, some or all of connector leads 288 can be bent to position the case exterior ends of connector leads 288 in a common plane, as shown in FIG. 2B-3. In an alternative version, connector leads 288ds and / or 288dc are not included, thereby producing an alternative version of packaged switch 247q.

[0201] FIG. 4D-1 shows the structure of FIG. 4C-1 after the second flat end surface of the pedestal 1108 has been electrically and thermally attached to the adjacent second current terminal (e.g., source terminal, emitter terminal, anode terminal, etc.) pad surface 395 of each transistor T5-T8.

[0202] The switch module may include a paddle disposed between the die substrate and the die clip. The paddle may be formed (e.g., by stamping, cutting, sawing, dicing, etc.) from a thin (e.g., 0.7 mm to 1.5 mm) metal or composite sheet. Alternatively, the paddle may be formed (e.g., by stamping, cutting, sawing, dicing, etc.) from a thin (e.g., 0.7 mm to 1.5 mm) laminate sheet as shown in FIG. 2H. FIG. 4D-2 shows top and side views of an example paddle 361 and an example connector lead 288c. The paddle 361 may be formed from a thin (e.g., 0.7 mm to 1.5 mm) copper sheet. The paddle 361 may have the same size, shape, and composition as the die clip 372 shown in FIG. 4A-4, except that a connector lead (e.g., connector lead 288c) is positioned intermediate the paddle 361 as shown. The connector lead 288c may be integrally connected to the paddle 361 as shown. In another version, the connector lead 288c may be electrically and thermally attached (eg, welded) to the paddle.

[0203] Paddle 361 has substantially flat surfaces 332 and 334 facing each other, although these surfaces may be completely flat. These surfaces may be electrically and thermally connected to the current terminal pad surfaces of the transistors. For example, flat surface 332 may be directly electrically and thermally attached (e.g., sintered) to a first flat end surface of a first pedestal, and a second flat end surface of the first pedestal may be directly electrically and thermally attached (e.g., sintered) to the second current terminals of each of the first group of transistors. Meanwhile, flat surface 344 may be directly electrically and thermally attached (e.g., sintered) to a first flat end surface of a second pedestal, and a second flat end surface of the second pedestal may be directly electrically and thermally attached (e.g., sintered) to the second current terminals of each of the second group of transistors. This electrically connects the second current terminals of the first group of transistors to each other and to the second current terminals of the second group of transistors, connecting the first group and the second group back-to-back.

[0204] Figure 4D-3 shows the paddle 361 of Figure 4D-2 after the paddle 361 has been thermally and electrically attached to the structure shown in Figures 4A-6 and 4D-1. Specifically, Figure 4D-3 shows the structure of Figures 4A-6 and 4D-1 after the end face 1107 of the pedestal 1108 of Figure 4A-6 has been electrically and thermally attached (e.g., sintered) directly to the flat surface 334 of the paddle 361, and after the end face 1107 of the pedestal 1108 of Figure 4D-1 has been electrically and thermally attached (e.g., sintered) directly to the flat surface 332 of the paddle 361. For illustrative purposes, the gate strap 364, bond wire 365, and surface region 367 of Figure 4A-6 have been relabeled as gate strap 364-1, bond wire 365-1, and surface region 367-1 in Figure 4D-3.

[0205] Transistors T1-T4 may be controlled by a first control terminal signal received via connector lead 288g-1, and transistors T5-T8 may be independently controlled by a separate second terminal control signal received via connector lead 288g-2.

[0206] If T1-T8 take the form of MOSFETs, the structure shown in FIG. 4D-3 can be a version of switch module 376K of FIG. 3K. After 361 is attached, a case may be formed around the switch module shown in FIG. 4D-3, using, for example, transfer molding, to produce an example of packaged switch 247p shown in FIGS. 2A-1-2A-3. Prior to case formation, some or all of connector leads 288 may be bent to position the case exterior ends of connector leads 288 in a common plane, as shown in FIG. 2A-3.

[0207] The switch may include transistors connected in anti-parallel. Figure 4E-1 shows the structure of Figure 4B-2 without strap 359-2, connector lead 288g-2, transistor T3, transistor T4, and bond wires 365-2, 366-3, and 366-4. Figure 4E-2 shows the structure of Figure 4D-1 without transistor T5, transistor T6, and bond wires 366-6 and 366-5. Figure 4E-3 shows the structures shown in Figures 4E-1 and 4E-2 after they have been thermally and electrically attached to one another (e.g., sintered). 4E-1 and 4E-2 after the end face 1107 of the pedestal 1108 of FIG. 4E-1 has been directly electrically and thermally attached (e.g., sintered) to the flat surface 375 of the die clip 372, and after the end face 1107 of the pedestal 1108 of FIG. 4E-2 has been directly electrically and thermally attached (e.g., sintered) to the flat surface 362 of the die substrate 360. Transistors T1 and T2 may be controlled by a first control terminal signal received via connector lead 288g-1, and transistors T7 and T8 may be independently controlled by a separate second terminal control signal received via connector lead 288g-2.

[0208] Transistors T1, T2, T7, and T8 of FIGS. 4E-1 through 4E-3 may block large reverse voltages (e.g., 5, 10, 50, 100, 200, 400, 800, 1600 V, or more) when off without breakdown. Each of transistors T1, T2, T7, and T8 of FIGS. 4E-1 through 4E-3 may be an RB-IGBT, an NPT-IGBT, a GTO thyristor, a BJT, or the like. For example, each of transistors T1, T2, T7, and T8 of FIGS. 4E-1 through 4E-3 may be an RB-IGBT, a GTO thyristor, an NPT-IGBT, or a BJT in which the flat collector terminal pad surfaces of T1 and T2 are sintered to flat surface 362 and the flat collector terminal pad surfaces of T7 and T8 are sintered to flat surface 375. 4E-1-4E-3 may be a mix of transistors. For example, transistors T1 and T2 may each be an RB-IGBT with a flat collector terminal pad surface sintered to planar surface 362, and transistors T7 and T8 may each be an NPT-IGBT with a flat collector terminal pad surface sintered to planar surface 375.

[0209] If each of transistors T1, T2, T7, and T8 in FIGS. 4E-1 through 4E-3 is an RB-IGBT, the structure shown in FIG. 4E-3 can be a version of switch module 376I shown in FIG. 3I. Alternatively, transistors T1, T2, T7, and T8 can be NPT-IGBTs or BJTs. Using, for example, transfer molding, a case can be formed around the structure shown in FIG. 4E-3 to produce an example of packaged switch 247qI shown in FIG. 3I, which is an example of packaged switch 247q shown in FIGS. 2B-1 through 2B-3. Prior to case formation, some or all of connector leads 288 can be bent to position the case exterior ends of connector leads 288 in a common plane, as shown in FIG. 2B-3. In an alternative version, connector leads 288ds and / or 288dc are not included, thereby producing an alternative version of packaged switch 247q.

[0210] The switch module may include other devices such as sensors and drivers. The switch module may include a PCB or DBC on which devices such as drivers and sensors are mounted. FIG. 4F-1 shows the structure of FIG. 4A-2, but replaces the strap 364 with a PCB 340, which includes traces 342. In an alternative version, the PCB 340 may be replaced with a DCB, which may allow for more heat conduction from the mounted device (e.g., driver) to the underlying die substrate 360. A temperature sensor (e.g., a thermistor) 348 is mounted on the PCB 340 and electrically connected to traces 342-1 and 342-3. A thermistor is a semiconductor resistor whose resistance is linearly dependent on temperature. The temperature sensor 348 can affect the voltage between traces 342-1 and 342-3, which depends on the temperature between transistors T2 and T4. Trace 342-2 is electrically connected to a metal pad 346. Bond wires 366 may be wire bonded to pads 346. One end of PCB 340 may be attached (e.g., glued) to surface 362 of die substrate 360. The other end of PCB 340 extends from die substrate 360. The ends of traces 342 may be electrically connected to conductors of a connector (not shown), which may be attached to a driver PCB or control PCB (not shown) that includes a microcontroller, drivers, voltage regulators, and / or other components.

[0211] FIG. 4F-2 shows the structure of FIG. 4F-1 after the surface of the pedestal 1108 has been electrically and thermally directly attached (e.g., sintered) to the surface 395 of the second current terminal (e.g., source terminal, emitter terminal, anode terminal, etc.) pad of the transistors T1-T4. The flat first surface 1107 of FIG. 4F-2 may be substantially disposed in a common plane to accommodate attachment of the die clip to the flat surface. FIG. 4F-3 shows a top view and a side view of the structure of FIG. 4F-2 after the die clip 372 of FIG. 4A-4 has been added. Specifically, FIG. 4F-3 shows the structure after the flat surface 375 of the die clip 372 has been electrically and thermally directly attached (e.g., sintered) to the flat surface 1107 of the pedestal 1108. After the die clip 372 is attached to the pedestal 1108, a case may be formed around the switch module of FIG. 4F-3, for example, using transfer molding. The resulting packaged switch can replace one, more, or all of the packaged switches 247d used in one, more, or all of the converters described below, with alternative versions not including connector leads 288ds and / or 288dc creating alternative versions of the packaged switch.

[0212] The example bidirectional packaged switch shown in Figures 3G and 3L includes a BBJT electrically and thermally connected (e.g., sintered) between the die substrate and the die clip. The bidirectional packaged switch shown in Figure 3G includes one BBJT. Referring to Figures 2F and 2G, Figure 4G-1 shows top and side views of an example BBJT 250, which includes example collector / emitter (c / e) terminal pads 262 and 264 on its top side and example collector / emitter (c / e) terminal pads 272 and 278 on its bottom side. The c / e pads 262 and 264 may have substantially flat surfaces 280 and 282, respectively, and the c / e pads 272 and 278 may have substantially flat surfaces 284 and 286, respectively. Surfaces 280 and 282 may be disposed in a common plane, and surfaces 284 and 286 may be disposed in another common plane. Planar surface 280 may be electrically and thermally directly connected (e.g., welded) to a planar surface of the respective pedestal, and planar surface 282 may be connected (e.g., welded) to a planar surface of a first signal frame. Similarly, planar surface 284 may be electrically and thermally directly connected (e.g., welded) to a planar surface of the respective pedestal, and planar surface 286 may be connected (e.g., welded) to a planar surface of a second signal frame.

[0213] The signal frame may be connected to the flat surface of the base terminal pad. FIG. 4G-2 shows top and side views of BBJT 250 with signal frames 377-1 and 377-2 connected to base terminal pad surfaces 282 and 286, respectively. Specifically, the flat surface of signal frame 377-1 is connected to flat surface 282 of base terminal pad 264 on the top side of BBJT 250, and the flat surface of signal frame 377-2 is connected to flat surface 286 of base terminal pad 278 on the bottom side of BBJT 250. Signal frame 377 may be formed (e.g., by cutting, stamping, dicing, etc.) from a thin (e.g., 1.0 mm to 2.0 mm) metal sheet such as copper. The signal frame can transmit a base control signal to the base terminal pad.

[0214] The pedestal may be connected to the flat surfaces of the c / e terminal pads. FIG. 4G-3 shows a top view of the structure shown in FIG. 4G-2 after the pedestal 1112 has been electrically and thermally attached (e.g., sintered) directly to the surfaces 280 and 284 of the c / e terminal pads on either side of the BBJT 250. FIG. 4G-4 shows a side view of the structure of FIG. 4G-3. FIG. 4G-5 shows a cross-sectional view of the structure of FIG. 4G-3 along line 3-3. The pedestal 1112 in FIG. 4G-3 is similar to the pedestal 1104 or 1108 shown in the previous figures, but the pedestal 1112 in FIG. 4G-3 is substantially longer. The pedestal 1112 may have opposing flat first and second surfaces. Only the first flat surface 1113 is shown in FIG. 4G-3. The second planar surface is electrically and thermally attached (e.g., sintered) directly to the planar surface 280 or 284 of the respective c / e terminal pad 262 or 272. The flat second end faces of the pedestal 1112 may have a shape (e.g., generally rectangular) and size that is generally similar to, but slightly smaller than, the shape and size of the generally planar surface 280 or 284 of the respective second current terminal pad 262 or 272 to which they are electrically and thermally attached. The flat first surface 1113 of FIG. 4G-3 may be disposed substantially in a common plane to accommodate attachment of a bridge or die clip to the planar surface.

[0215] The die clip and die substrate may be electrically and thermally attached (e.g., sintered) directly to the pedestal 1112 of the structure shown in FIG. 4G-3. FIG. 4G-6 shows a top view and a side view of the structure shown in FIG. 4G-3 after the die substrate 360 ​​of FIG. 4A-1 has been electrically and thermally attached (e.g., sintered) directly to the pedestal 1112 on the underside of the BBJT 250 as shown. More specifically, a first flat surface of the pedestal 1112 may be sintered to the surface 362 of the die substrate 360. FIG. 4G-6 also shows connector leads 288g-1 and 288g-2, which are electrically connected to signal frames 377-1 and 377-2, respectively, by bond wires 365-1 and 365-2, respectively. FIG. 4G-7 shows a top view and a side view of the structure shown in FIG. 4G-6 after the die clip 372 of FIG. 4A-4 has been electrically and thermally attached (e.g., sintered) directly to the pedestal 1112 on the top side of the BBJT 250 as shown. More specifically, a first flat surface of the pedestal 1112 may be sintered to the surface 375 of the die clip 372. In this version, the die substrate 360 ​​and the die clip 372 may be formed from a thin copper sheet.

[0216] The structure shown in FIG. 4G-7 is an example of the switch module 376G shown in FIG. 3G. Using, for example, transfer molding, a case may be formed around the structure shown in FIG. 4G-7 to produce an example of the packaged switch 247qG shown in FIG. 3G, which is an example of the packaged switch 247q of FIGS. 2B-1-2B-3. Prior to case formation, some or all of the connector leads 288 may be bent to position the case exterior ends of the connector leads 288 in a common plane, as shown in FIG. 2B-3. In an alternative version, the connector leads 288ds and / or 288dc are not connected to the die substrate 360 ​​and die clip 372, respectively.

[0217] The bidirectional packaged switch shown in FIG. 3L includes four BBJTs electrically and thermally connected (e.g., sintered) between die substrate 360 ​​and die clip 372. FIG. 4G-8 shows a top view of the four BBJTs 250. Signal frames 377e-1 and 377e-2 may be connected to the base terminal pad surfaces on the upper and lower sides of BBJTs 250-1 through 250-4, respectively. Specifically, the flat surface of signal frame 377e-1 is connected to the flat surface of the base terminal pads on the upper side of BBJTs 250-1 through 250-4, and the flat surface of signal frame 377e-2 is connected to the flat surface of the base terminal pads on the lower side of BBJTs 250-1 through 250-4. Signal frame 377e may be formed (e.g., by cutting, stamping, dicing, etc.) from a thin (e.g., 1.0 mm to 2.0 mm) metal sheet such as copper. The signal frame can carry a base control signal to the base terminal pad.

[0218] The pedestal may be connected to the flat surfaces of the c / e terminal pads on both sides of the BBJTs 250-1 to 250-4. In FIG. 4G-8, the flat second end surface of the pedestal 1112 may be directly electrically and thermally attached (e.g., sintered) to the surfaces of the respective c / e terminal pads on both sides of the BBJTs 250-1 to 250-4. The die clip and die substrate may be directly electrically and thermally attached (e.g., sintered) to the pedestal 1112 of the structure shown in FIG. 4G-8. FIGS. 4G-9 and 4G-10 show top and side views of the structure shown in FIG. 4G-8 after the die substrate 360 ​​of FIG. 4A-1 has been directly electrically and thermally attached (e.g., sintered) to the pedestal 1112 on the underside of the BBJTs 250-1 to 250-4. More specifically, first flat end surfaces 1113 of the pedestals 1112 on the undersides of the BBJTs 250-1 through 250-4 may be sintered to the surface 362 of the die substrate 360. FIG. 4G-9 also shows connector leads 288g-1 and 288g-2, which are electrically connected to signal frames 377e-1 and 377e-2, respectively, by bond wires 365-1 and 365-2, respectively. FIGS. 4G-11 and 4G-12 show side and top views of the structure shown in FIG. 4G-10 after the die clip 372 of FIG. 4A-4 has been electrically and thermally attached (e.g., sintered) directly to the pedestals 1112 on the top sides of the BBJTs 250-1 through 250-4. More specifically, first flat end surfaces 1113 of the pedestals 1112 on the upper surfaces of the BBJTs 250-1 to 250-4 may be sintered to the surface 375 of the die clip 372. In this version, the die substrate 360 ​​and the die clip 372 may be formed from thin copper sheets.

[0219] The structure shown in FIGS. 4G-11 and 4G-12 is an example of switch module 376L shown in FIG. 3L. Using, for example, transfer molding, a case may be formed around the structure shown in FIG. 4G-11 to produce an example of packaged switch 247ql shown in FIG. 3L, which is an example of packaged switch 247q shown in FIGS. 2B-1-2B-3. Prior to case formation, some or all of connector leads 288 may be bent to position the case exterior ends of connector leads 288 in a common plane, as shown in FIG. 2B-3. An alternative version of packaged switch 247q is produced by not including connector leads 288ds and / or 288dc.

[0220] 4H shows a top and side view of the example diode module 378N of FIG. 3N, which includes a pair of diodes D1 and D2 sandwiched between die clip 372 and die substrate 360. D1 and D2 can be the same type of diode, or D1 and D2 can be a mix of different types of diodes.

[0221] 4H shows diodes D1 and D2 after the flat surfaces of their first current terminal (e.g., cathode terminal, not shown) pads have been electrically and thermally attached (e.g., sintered) directly to surface 362. A low-resistance path can exist between die substrate terminal 230 and each first current terminal pad. In FIG. 4H, each die-substrate bond (e.g., sintered bond, not shown) connecting the first current terminal pad surface to surface 362 can conduct 10, 20, 50, 100, 200, 300, 750 watts or more of heat while simultaneously carrying 50, 100, 200, 400 amps or more of current. Each die-substrate bond can have a length and width approximately equal to the length and width of the respective first current terminal pad surface.

[0222] Each diode D1 and D2 may include a second current terminal (e.g., anode terminal, not shown) pad. Each second current terminal pad may have a flat surface. FIG. 4H shows a pedestal 1117, which may be generally similar to pedestal 1108 described above. Each pedestal 1117 may have opposing first and second flat end faces. The second flat end faces of pedestal 1117 may be electrically and thermally directly attached (e.g., sintered) to the respective flat surfaces of the second current terminal pads of diodes D1 and D2. The flat second end faces of pedestal 1117 may have a shape and size that is generally identical to, but slightly smaller than, the shape and size of the flat surfaces of the respective second current terminal pads to which they are electrically and thermally attached. Each second joint (e.g., a sintered joint) connecting the second current terminal pad surface to the second flat end face of the pedestal 1117, and each pedestal 1117, may conduct 10, 20, 50, 100, 200, 300, 600 watts or more of heat while simultaneously carrying 10, 20, 50, 100, 200, 400 amps or more of current. Each of these second joints may have a length and width approximately equal to the length and width of the respective second flat end face of the pedestal 1117.

[0223] 4H shows the flat surface 375 of the die clip 372 electrically and thermally attached (e.g., sintered) directly to the first flat end face of the pedestal 1117. Each die clip joint (e.g., sintered joint) connecting the first flat end face of the pedestal 1117 to the surface 375 may conduct 10, 20, 50, 100, 300 watts or more of heat while simultaneously carrying 10, 20, 50, 100, 200 amps or more of current. Each die clip joint may have a length and width approximately equal to the length and width of the respective first flat end face of the pedestal 1117. A low resistance path may exist between the die clip terminal 344 and each second current terminal pad of the diodes D1 and D2.

[0224] For example, a case may be formed around the example diode module 378 of FIG. 4H using transfer molding to produce the example packaged diode 245 shown in FIGS. 2E-1-2E-3. Prior to case formation, connector leads 288 may be positioned with their case exterior ends in a common plane, as shown in FIG. 2E-3. In an alternative version, a "connector leadless" version of packaged diode 245 is produced in which connector leads 288ds and 288dc are not connected to die substrate 360 ​​and die clip 372.

[0225] Power Converter Example Inverter 460iT The power converter (hereinafter also referred to as converter) of the present disclosure includes an inverter and a rectifier and has high power density. For example, the inverter or rectifier of the present disclosure can supply peak power of 200 kW or more in a very small volume.

[0226] 5A-1 and 5A-2 show the relevant components of an exemplary inverter 460iT from the front and side, respectively. Some components shown in FIG. 5A-2 (e.g., driver PCB 461i, control PCB 462i, and DC link capacitor 403T) are not shown or are not fully shown in FIG. 5A-1 but are described below.

[0227] Converters and other power systems of the present disclosure may use the packaged switches 247 described above. While the example inverter 460iT is shown with packaged switch 247d, it is understood that in alternative versions, switch 247d may be replaced with packaged switch 247p or packaged switch 247q. All packaged switches 247d of inverter 460iT may be identical. Packaged switches 247d of inverter 460iT may be packaged switches 247dA, 247dB, or 247dD of FIGS. 3A, 3B, and 3D, respectively.

[0228] A converter or other power system may use one or more bus bars to distribute current to the switch 304 or diode D. The inverter 460iT includes a V+ bus bar 417T, a V- bus bar 412T, and a phase bus bar 418T. The bus bars, such as the V+ bus bar 417T, the V- bus bar 412T, and the phase bus bar 418T, may also function as heat sinks to cool the switch 304 or diode D, as described below. The case surface of the packaged switch 247, such as the packaged half-bridge 247d in FIG. 5A-1, may be thermally connected to the flat surfaces of the bus bars, such as the V+ bus bar 417T, the V- bus bar 412T, and the phase bus bar 418T.

[0229] A converter may have one or more phases. Inverter 460iT has three phases, a through c. Each phase in FIG. 5A-1 includes two packaged switches 247dH and 247dL electrically and thermally connected to a phase bus bar 418T, both of which are sandwiched between a V+ bus bar 417T and a V- bus bar 412T. Packaged switches 247dH and 247dL are also electrically and thermally connected to the V+ bus bar 417T and the V- bus bar 412T, respectively.

[0230] Volume of converters and other power systems may be conserved by stacking packaged switches and busbars. FIG. 5A-1 shows a packaged switch 247dH, a V+ busbar 417T, a phase busbar 418T, and a V− busbar 412T arranged in a line with one another. The packaged switch 247dH in FIG. 5A-1 may have a die substrate terminal 230 electrically and thermally connected (e.g., sintered, press-fit, etc.) to the or each flat surface of the V+ busbar 417T and a die clip terminal 344 electrically and thermally connected (e.g., sintered, press-fit, etc.) to the flat surface of each phase busbar 418Ta-418Tc, which may be electrically connected to the windings Wa-Wc, respectively. The packaged switch 247dL in FIG. 5A-1 may have die substrate terminals 230 electrically and thermally connected (e.g., sintered, press-fit, etc.) to the flat surfaces of the respective phase bus bars 418Ta-418Tc, and die clip terminals 344 electrically and thermally connected (e.g., sintered, press-fit, etc.) to the flat surface or each flat surface of the V-bus bar 412T.

[0231] Busbars, such as the V+ busbar 417T, V- busbar 412T, and phase busbar 418T in FIGS. 5A-1 and 5A-2, may have rectangular cross-sections. An example phase busbar 418T may have height, width, and length of approximately 12 mm, 29 mm, and 35 mm, respectively. An example V+ busbar 417T and V- busbar 412T may have height, width, and length of approximately 8 mm, 29 mm, and 100 mm, respectively. The busbars may have different dimensions to accommodate different converter designs.

[0232] Different materials expand at different rates when heated. For example, materials such as solder or silver sinter paste can be used to attach the die substrate terminals or die clip terminals to the busbar, but the attachment materials may crack when heated or cooled due to mismatched coefficients of thermal expansion (CTE). Mechanical structures (e.g., clamps) can press-fit the die substrate terminals 230 and die clip terminals 344 onto the respective flat surfaces of the busbar. The press-fit can reduce or eliminate problems associated with CTE mismatch. Ideally, the surfaces of the components being crimped together should be smooth to optimize electrical and thermal conduction between them. The addition of grease or a similar material can improve electrical and thermal conduction between the press-fit components.

[0233] Although not shown, the die substrate terminals 230 or die clip terminals 344 may be electrically and thermally connected to the flat surface of their respective busbar pedestals. The busbar pedestals are electrically and thermally connected to and extend from a heat sink, a busbar, or a busbar that also functions as a heat sink. The surface of the busbar pedestal may be slightly smaller than the surface of the terminal 230 or 344 to which it is connected. The terminal 230 or 344 may be flush with or slightly below the case surface of the packaged switch 247 or packaged diode 245 to which it is housed. Heat and / or current may be transferred between the terminal 230 or 344 and the connected busbar pedestal. While not required, applying a thin layer of thermally and / or electrically conductive grease or other material between the terminal 230 or 344 and the surface of the connected busbar pedestal may improve thermal and / or electrical conductivity during crimping.

[0234] Generally, heat sinks and busbars that also function as heat sinks may include one or more channels through which a cooling fluid can flow. The channels may house and support metallic conduits, which may have their own channels through which a cooling fluid can flow.

[0235] The channels in the busbar or heat sink may be rectangular, oval, square, etc. in cross section, and the conduits housed in the channels should have a similar cross-sectional shape. The channels in the busbar or heat sink are assumed to be circular (i.e., round) in cross section, and the conduits they hold are also assumed to be circular in cross section, although it is understood that the present disclosure is not limited in this respect. Thus, the conduits are assumed to be round tubes, although it is understood that tubes of other shapes (e.g., oval) are also contemplated. Round tubes (hereinafter, "tubes") may have an outer diameter approximately equal to the diameter of the channel in which they are housed. The tubes may be fluidly connected to a pump or other device.

[0236] Each busbar or heat sink in the converter may have one or more rows of channels for accommodating tubes. The V+ busbar 417T and V- busbar 412T each have a single row of three channels 40 that can accommodate tubes, and the phase busbar 418T has two rows of three channels 40 that can accommodate tubes. In an alternative version, the phase busbar 418T may have only a single row of channels. All channels in the converter may be the same size (e.g., diameter). In an alternative version, the channel dimensions may vary within a busbar or heat sink or between busbars in the converter.

[0237] Each busbar or heat sink within a converter may have the same number of rows of channels. For example, each busbar within a converter may have only one row of channels. The number of rows may vary between busbars or heat sinks within a converter. For example, the phase busbars within a converter may have two rows of channels, and each of the DC busbars (e.g., the V+ busbar and the V- busbar) may have one row of channels.

[0238] Each row within a converter may have the same number of channels. The number of channels within a row may vary within a converter or between busbars or heat sinks within a converter. For example, the V- busbar within a converter may have one row of two channels and the V+ busbar within a converter may have one row of three channels, or vice versa. The V- busbar within a converter may have one row of one channel and the V+ busbar within a converter may have one row of two channels, and a phase busbar located between the V+ and V- busbars may have one row of three channels. A busbar (e.g., a phase busbar) may have two rows of channels, with the first row having two channels and the second row having three channels.

[0239] To improve heat transfer, the channels may be located proximate to the surface of the busbar that is connected (e.g., sintered) to the die clip terminal or die substrate terminal. The channels extend parallel to the long axis of the heat sink or busbar. In alternative versions, the channels may extend perpendicular to the long axis of the heat sink or busbar. In the following disclosure, the channels will be referred to as extending parallel to the long axis of the heat sink or busbar that also functions as a heat sink, although it will be understood that the disclosure is not limited in this regard.

[0240] Tube Example The busbar channel can accommodate a tube. When accommodated, the outer cylindrical surface of the tube can be thermally connected to the cylindrical surface of the busbar channel. In some versions, a thermally conductive material (e.g., thermally conductive grease) can be used to improve thermal conduction between the tube and the cylindrical surface of the busbar channel.

[0241] The busbar channel can contain tubes made of one or more materials. The tubes can efficiently transfer heat to a cooling fluid flowing therethrough. The tubes can electrically insulate the busbar from a non-dielectric cooling fluid flowing therethrough. The tubes (e.g., aluminum nitride tubes) can electrically insulate the phase busbars in the converter. The tubes themselves can be formed of a dielectric material (e.g., aluminum nitride) and function as a heat transfer medium. If the tubes are constructed of a highly thermally conductive dielectric material, they can be used as a scaffold for subsequent metal layers, providing better electrical and / or thermal connection to the surface of the busbar channel in which they are housed. This enables processes for connecting the tubes to the walls of the busbar channel in which they are housed (e.g., soldering, sintering, brazing, welding, etc.). These connection processes can improve thermal and / or electrical conductivity between the tubes and the busbar. In the case of tubes made of two or more materials, one layer (e.g., primarily metal) can serve as a scaffold for subsequent dielectric layers. A third metal layer may be formed on the subsequent dielectric layer to enable the connection process.

[0242] FIGS. 5A-3 through 5A-17 illustrate exemplary tubes 420a through 420w that may be housed in busbar channels. FIG. 5A-3 illustrates cross-sectional views of exemplary tubes 420a through 420c, which may be formed (e.g., by extrusion, hot pressing, casting, isostatic pressing, growing, etc.) from a thermally conductive dielectric material such as aluminum nitride. A thin (e.g., 0.05-1.0 mm) metal layer may be formed over substantially the entire outer cylindrical surface of the tube. Tubes 420a through 420c are uncoated. In other words, no metal layer is formed on the outer surfaces of tubes 420a through 420c. FIG. 5A-4 illustrates cross-sectional views of tubes 420d through 420f after a thin metal layer 407 has been formed over substantially the entire outer surface of tubes 420a through 420c, respectively. Metal layer 407 may be formed by any of a variety of methods, such as chemical vapor deposition, physical vapor deposition, or spraying, roll coating, pad printing, etc. After the metal layer 407 is formed, the tube may be heated.

[0243] The metal layer 407 may be formed only on selected portions of the outer surface of the dielectric tube. For example, a thin metal layer may be formed only on portions of the dielectric tube that connect to the surfaces of each phase busbar channel. FIG. 5A-10 is a side view of a dielectric tube 420a-1 with a thin metal layer 407 formed on selected portions of the outer surface of the dielectric tube 420a. The tube 420a-1 may be housed in the aligned cylindrical channels of three phase busbars. The cylindrical surfaces of the three aligned channels may be thermally and electrically connected to the respective surfaces of the metal layer 407 formed on the tube 420a-1. The three phase busbars housed in the common tube 420a-1 are electrically insulated from one another. FIG. 5A-12 is a side view of a tube 420a-3 with a thin metal layer 407 formed only on the ends of the dielectric tube 420a.

[0244] 5A-6 show cross-sectional views of exemplary tubes 420j-420l, which may be formed (e.g., by extrusion, casting, hot pressing, powder molding, 3D printing, etc.) from a metal such as copper or aluminum. A thin (e.g., 0.05-1.0 mm) layer of a dielectric material (e.g., aluminum oxide, aluminum nitride, silicon nitride, chemical vapor deposition diamond coating, etc.) may be formed over substantially the entire inner and / or outer cylindrical surfaces of the tubes. FIG. 5A-7 shows cross-sectional views of exemplary tubes 420m-420o, each having a thin dielectric layer 422 formed over substantially the entire outer cylindrical surfaces of metal tubes 420j-420l.

[0245] In some versions, the thin dielectric layer 422 may be formed only on selected portions of the outer cylindrical surface of the metal tube. For example, the thin dielectric layer may be formed only on portions of the metal tube that connect to the cylindrical surfaces of each phase busbar channel. FIG. 5A-13 is a side view of a metal tube 420j-1 with a thin dielectric layer 422 formed on selected portions of its outer surface. The tube 420j-1 may be housed in the aligned cylindrical channels of three phase busbars. The cylindrical surfaces of the three aligned channels may be connected to respective surfaces of the dielectric layer 422. The three phase busbars housed in a common tube 420j-1 are electrically isolated from each other.

[0246] Before the tubes are received in the bus channels, a thin connecting layer such as solder, sintered material, brazing material, or the like may be deposited on substantially the entire outer surface. FIG. 5A-5 shows cross-sectional views of exemplary tubes 420g-420i that may be formed by depositing a thin connecting layer 421 such as solder, sintered material, brazing material, or the like on substantially the entire outer surface. Also, a thin connecting layer 441 may be formed on substantially the entire outer surface of tubes 420m-420o, but before the thin connecting layer is formed, a thin metal layer may be formed on substantially the entire dielectric layer 422. FIG. 5A-8 shows cross-sectional views of exemplary tubes 420p-420r after a thin metal layer 442 has been formed on substantially the entire surface of the dielectric layer 422 of tubes 420m-420o, respectively. FIG. 5A-9 shows cross-sectional views of exemplary tubes 420s-420u after a thin connecting layer 441 has been formed on substantially the entire surface of the metal layer 442 of tubes 420p-420r, respectively.

[0247] The connecting layer 441 may be formed only on selected portions of the tube. For example, a thin connecting layer may be formed only on the portions of the tube that connect to the cylindrical surfaces of the respective phase busbar channels. FIG. 5A-11 is a side view of a dielectric tube 420a-2 with a thin connecting layer 441 formed on each metal layer 407 of the tube 420a-1. The tube 420a-2 may be housed in the aligned cylindrical channels of the three phase busbars. The cylindrical surfaces of the three aligned channels may be thermally and electrically connected to the respective surfaces of the connecting layer 441 formed on the tube 420a-2. The three phase busbars housed in a common tube 420a-2 are electrically insulated from one another.

[0248] The thin connecting layer 441 may also be formed on the surface of the dielectric layer 422 of the tube 420j-1, but a thin metal layer may be formed on the surface of the dielectric layer 422 before the thin connecting layer is formed. FIG. 5A-14 is a side view of the tube 420j-2 in which the thin metal layer 442 is formed on each dielectric layer 422 of the dielectric tube 420j-1. FIG. 5A-15 is a side view of the tube 420j-3 in which the thin connecting layer 441 is formed on each metal layer 442 of the dielectric tube 420j-2. The tube 420j-2 may be housed in the aligned cylindrical channels of the three phase bus bars. The cylindrical surfaces of the three aligned channels may be thermally and electrically connected to the respective surfaces of the connecting layer 441 formed on the tube 420j-2. The three phase bus bars housed in the common tube 420j-2 are electrically insulated from each other.

[0249] The tube may be constructed by assembling separately formed components. FIGS. 5A-16 and 5A-17 show cross-sectional views of insert 443, which may be formed (e.g., extruded) from a metal or dielectric material. Insert 443 may have a length approximately equal to that of tube 420a or 420j, also shown in FIGS. 5A-16 and 5A-17. Insert 443 may be inserted into tube 420a or 420j. Insert 443 may have a rounded end. Upon insertion, the surface of the rounded end may connect to the inner cylindrical surface of tube 420a or 420j to form tubes 420v and 420w, respectively.

[0250] The dielectric layer 422 formed on the outer cylindrical surface of the tube may be the only dielectric in the thermal path between the switch 304 and the cooling fluid within the tube. In an alternative version, a thin dielectric layer may be formed on the inner cylindrical surface of the tube. In this version, that layer may be the only dielectric in the thermal path between the switch 304 and the fluid within the tube. In yet another version, thin dielectric layers may be formed on both the inner and outer cylindrical walls of the tube. These two dielectric layers may be the only dielectric in the thermal path between the switch 304 and the fluid within the tube.

[0251] The dielectric tube (e.g., 420a, 420b, or 420c) or dielectric layer 422 on the metal tube can electrically insulate the cooling fluid within the tube from the busbar in which the tube is housed. The dielectric tube or dielectric layer 422 should have a high dielectric strength (e.g., 1 to 10 kV). The dielectric layer 422 can be thin (e.g., 3.0, 5.0, 10.0, 50.0, 100.0, 200.0, 250.0 μm, or thicker). The dielectric layer 422 is assumed to be approximately 200.0 μm, but it is understood that other versions may be thinner or thicker. The thickness of the dielectric tube wall or dielectric layer 422 affects heat transfer to the cooling fluid. The table below includes calculated heat transfer W for different dielectric layer 422 materials and thicknesses. W is proportional to k·A·(T1-T2) / d, where k is the thermal conductivity, A is the area, ΔT=70 is the temperature difference across the dielectric layer, and d is the thickness in μm. For the calculated heat transfer W, assume a voltage of 4 kV is applied to the dielectric. [Table 1]

[0252] The dielectric layer 422 can be formed by spraying (e.g., plasma spraying or flame spraying) a dielectric material onto the outer cylindrical surface of the tube. The dielectric layer 422 can be formed by rolling the tube in a dielectric material (e.g., TIM). The dielectric layer 422 can be formed on the outer cylindrical surface of the tube by CVD, PVD, coating (pad printing, brushing, dipping, electrodeposition (in the case of porcelain enamel or electrostatic painting), etc., and heating). The dielectric layer 422 can be formed by wrapping a thin (e.g., 3.0, 5.0, 10.0, 50.0, 100.0, 200.0, 250.0 μm or more) dielectric film onto the outer surface of the tube.

[0253] In another version, the dielectric layer 422 can be grown on the outer and / or inner cylindrical surfaces of the tube. For example, the dielectric layer 422 can be grown on the inner and / or outer cylindrical surfaces of the aluminum tubes 420j-420l using plasma electrolytic oxidation or Type II or III hard anodizing. The tubes can have multiple dielectric layers. For example, a thin (e.g., 3.0, 5.0, 10.0, 50.0, 100.0 μm or thicker) layer of dielectric material (e.g., aluminum nitride) can be formed on the outer cylindrical surface of the metal tube after anodization. Other processes for forming the dielectric layer or layers are also contemplated.

[0254] Anodizing is an electrolytic passivation process for creating or thickening a native oxide layer on the surface of a metal part. Anodizing produces oxides roughly half on the surface of the metal part and half in the metal itself. The resulting oxide layer is electrically insulating. The oxide layer can be grown by passing a direct current through an electrolyte, typically sulfuric acid or chromic acid, with the metal part (e.g., a tube) suspended and partially exposed. The metal part serves as the anode (positive electrode of the electrolytic cell). The current in the electrolyte generates hydrogen at the cathode (negative electrode) and oxygen at the surface of the metal part, promoting oxide formation. The required voltage can range from 1 to 300 V DC. Thicker oxide films formed with sulfuric acid and organic acids typically require higher voltages. The anodizing current varies depending on the total area of ​​the metal part being anodized and is typically 30 to 300 A / m. 2 The oxide layer thickness ranges from 0.01 to 0.01 mm. Controlling conditions such as electrolyte concentration, acidity, solution temperature, and current allows for the formation of a uniform oxide layer. Harder and thicker oxide layers tend to be produced with more concentrated solutions, lower temperatures, higher voltages, and higher currents.

[0255] The anodization process can be used to grow a dielectric layer of oxide on the outer and / or inner cylindrical surfaces of an aluminum tube. The tube serves as the anode for the process. An electric current is passed through an electrolyte bath solution in which the tube is partially or completely suspended, generating hydrogen at the cathode (negative electrode) and oxygen on the outer surface and / or surface of the tube, promoting oxide formation. The anodization process can be used to grow a dielectric layer, such as dielectric layer 422, only on the outer surface of aluminum tubes, such as tubes 420j-420l used in rectifiers or inverters.

[0256] Plasma electrolytic oxidation (PEO) is another electrochemical surface treatment process for growing insulating layers on metal tubes. It is similar to anodization, but typically uses a higher potential, generating electrical discharges and the resulting plasma, which alters the structure of the oxide layer. This process can be used to grow thick (50, 100, 200, 250, 300 μm, or even more), primarily crystalline oxide coatings on metal tubes, such as aluminum, magnesium, and titanium. The coating is a chemical conversion of the metal to an oxide, growing both inward and outward from the original metal surface. Plasma electrolytic oxidation of aluminum requires the application of at least 200 V, which locally exceeds the breakdown potential of the growing oxide, generating electrical discharges. These electrical discharges trigger local plasma reactions, which transform the growing oxide under conditions of high temperature and pressure. The process can include melting, melt flow, resolidification, sintering, and densification of the growing oxide. One of the most important effects is the partial conversion of the oxide from amorphous alumina to a harder crystalline form such as corundum (α-Al2O3). Plasma electrolytic oxidation involves immersing a tube in an electrolytic bath, usually consisting of a dilute alkaline solution such as KOH. The tube is electrically connected and becomes one electrode of an electrochemical cell; the other electrode is typically made of an inert material such as stainless steel, and often consists of the wall of the bath itself. A potential of over 200 V can be applied between these two electrodes. Higher voltages can be used to form thicker oxide layers.

[0257] Anodizing or plasma electrolytic oxidation may offer several advantages over other methods of forming dielectric layers such as dielectric layer 422 (e.g., spray-applying a dielectric to the outer cylindrical surface of a tube, which may require smoothing to ensure a better thermally conductive interface with the busbar channel surface in which the tube is housed). For example, anodizing may provide a more mechanically robust dielectric layer. The outer surface of an anodized dielectric layer may be smoother compared to other methods, which may improve heat transfer between a heat sink or busbar on one side of the dielectric and the tube on the other side.

[0258] The tube channels may have different cross-sectional shapes, as shown in Figures 5A-3 through 5A-9. Each tube 420 includes one or more channels through which a cooling fluid can flow. Tubes 420a, 420b, 420d, 420e, 420g, 420h, 420j, 420k, 420m, 420n, 420p, 420q, 420s, and 420t include a single channel, while tubes 420c, 420f, 420i, 420l, 420o, 420r, 420u, 420v, and 420w include multiple channels.

[0259] Tubes 420a, 420d, 420g, 420j, 420m, 420p, and 420s may have smooth cylindrical inner walls. In an alternative version, tubes 420a, 420d, 420g, 420j, 420m, 420p, and 420s may have rifled inner cylindrical walls. Rifling is a process of machining spiral grooves into the inner surface of a tube to create or increase turbulence or molecular contact of the fluid.

[0260] The channels of tubes 420b, 420e, 420h, 420k, 420n, 420q, and 420t are "flower" shaped, with a ring of smaller cylindrical subchannels, each of substantially the same cross section, in fluid communication with a centrally located cylindrical subchannel having a larger cross section than the cylindrical subchannels in the ring. The spoke subchannels allow fluid communication between each cylindrical subchannel in the ring and the centrally located cylindrical subchannel. Each spoke subchannel may have any of a variety of cross-sectional shapes. In the illustrated version, each spoke subchannel has a substantially rectangular cross section, although square or circular cross sections are also contemplated. Flower-shaped tubes may increase heat transfer to the coolant flowing within the tube compared to tubes having a flat, smooth (e.g., non-rifled) inner cylindrical surface, such as that shown in tube 420a.

[0261] Tubes, whether metallic or dielectric, can be manufactured using three-dimensional printing techniques or extrusion processes. Extrusion is a process used to create objects of a fixed cross-sectional profile by forcing material through a die of the desired cross-sectional shape. This can be done with either hot or cold material. Commonly extruded materials include metals, polymers, ceramics, etc.

[0262] The dielectric layer 422 may electrically insulate the cooling fluid within the metal tube. The dielectric layer 422 may transfer heat to the cooling fluid flowing within the tube, but may have a higher thermal resistance compared to a metal such as copper. In an alternative version, there is no dielectric (e.g., layer 422) between the cooling fluid and the switch 304. However, in this alternative version, the cooling fluid should be a dielectric.

[0263] The diameters of the tubes within a busbar or heat sink need not be equal. The number, position, and / or diameter of the tubes within a busbar may depend on one or more variables. For example, the number, position, and / or diameter of the tubes may depend on the desired thermal capacity of the busbar or heat sink in which the tubes are housed. Alternatively, the number, position, and / or diameter of the tubes within a busbar may depend on the desired thermal resistance between the switch 304 and the fluid within the tubes. Alternatively, the number, position, and / or diameter of the tubes within a busbar may depend on optimizing the thermal capacity within the busbar.

[0264] In general, the converter's DC busbars (i.e., V+ and V- busbars) can accommodate any version of tubes 420a-420u, 420v, 420w, and 420a-3 within their channels 40. If the converter's DC busbar channels 40 accommodate pure metal tubes 420j-420l, the cooling fluid flowing through the tubes should be a dielectric (e.g., air, oil, deionized water, etc.) to extract heat. The phase busbars within the converter must be electrically isolated from each other. The phase busbars within the converter may be restricted to accommodate only tubes 420a-420c, 420m-420o, 420a-1, 420a-2, 420a-3, 420j-1, 420j-3, or 420w within aligned channels 40 to maintain electrical isolation. 5A-18 and 5A-19 show the inverter 460iT of FIGS. 5A-1 and 5A-2, respectively, in which a dielectric tube 420a is housed in each bus bar channel 40. The phase bus bars 418Ta to 418Tc are thermally connected to each other and electrically insulated from each other by the commonly housed dielectric tube 420a.

[0265] All tubes 420 in FIGS. 5A-18 and 5A-19 are dielectric tubes 420a. A power converter may use a mixture of tube types. For example, phase busbars within a converter, such as phase busbars 418Ta-418Tc, may share tube 420a-2, and DC busbars within the converter, such as V+ busbar 417T and V- busbar 412T, may share tubes 420h and 420m, respectively. Alternatively, phase busbars within a converter, such as phase busbars 418Ta-418Tc, may share tube 420n, and DC busbars within the converter, such as V+ busbar 417T and V- busbar 412T, may share tubes 420s and 420u, respectively.

[0266] Converters and other power systems may include one or more capacitors (hereinafter referred to as "DC link capacitors") electrically connected between the DC busbars (i.e., the V+ and V- busbars). The DC link capacitors may take the form of film capacitors (e.g., polypropylene film capacitors). The DC link capacitors may take the form of ceramic capacitors (e.g., Class 1 or Class 2 multilayer ceramic capacitors). Other types of DC link capacitors, such as electrolytic capacitors, may also be used. Converters may include a mix of DC link capacitor types. For example, a converter may include one or more thin film DC link capacitors and one or more ceramic DC link capacitors, all electrically connected in parallel between the V+ and V- busbars.

[0267] DC link capacitors can become hot. They may be thermally connected to the V+ and / or V- busbars. One or more DC link capacitors of converters and other power systems may be cooled by thermal connection to the DC busbars to which they are electrically attached.

[0268] The DC link capacitor may be housed in a rectangular parallelepiped-shaped package formed of a dielectric material such as plastic. For purposes of illustration, each DC link capacitor of the present disclosure is housed in a rectangular parallelepiped-shaped package having substantially flat dielectric side walls. The DC link capacitor in the package may be referred to as a packaged DC link capacitor.

[0269] A "bulk" packaged DC link capacitor (bulk capacitor) may have first and second metal capacitor leads extending from the sidewall. The first and second metal capacitor leads may be electrically and thermally connected to the first and second electrodes of the film capacitor, respectively. The flat surfaces of the first and second metal capacitor leads at the other ends may be electrically and thermally connected to the flat surfaces of the V+ and V- busbars, respectively. The surfaces of the bulk capacitor's flat dielectric sidewall may be thermally connected to the flat surfaces of the V+ and / or V- busbars, which also function as heat sinks. The opposing surfaces of the bulk capacitor's flat dielectric sidewall may be thermally connected to the flat surfaces of the V+ and V- busbars, respectively, which also function as heat sinks. The thermal connections of the sidewalls and / or capacitor leads enable heat extraction from the bulk capacitor.

[0270] The packaged ceramic DC link capacitor may have first and second metal terminals at opposite ends of the package. The first and second metal terminals may be electrically and thermally connected to the first and second electrodes, respectively, of the multilayer ceramic capacitor. The first and second metal terminals may be electrically connected to V+ and V- busbars, respectively, which also function as heat sinks. Each of the first and second metal terminals may have a flat end face and a flat sidewall surface. The flat end faces of the first and second metal terminals may face opposite directions. The flat surfaces of the first and second metal terminals may be electrically and thermally connected to the flat surfaces of the V+ and V- busbars, respectively. Alternatively, the first and second metal terminals may be electrically connected to first and second traces, respectively, of the PCB, and the first and second traces may be electrically connected to the V+ and V- busbars, respectively.

[0271] Inverter 460iT includes a bulk capacitor 403. An example bulk capacitor 403 has four dielectric sidewalls extending between a dielectric top and a dielectric bottom. Bulk capacitor 403 has first and second metal capacitor leads 405a and 405b, respectively, extending from the front dielectric sidewalls of the capacitor. Capacitor leads, including capacitor lead 405, may be rectangular in cross section. An example capacitor lead 405 has a height hbc, a length lbc, and a width wbc of approximately 6 mm, 20 mm, and 20 mm, respectively. Capacitor leads, including capacitor lead 405, may have opposing substantially flat rectangular top and bottom surfaces. An example area of ​​the top and bottom surfaces is approximately 400 mm. 2A majority (e.g., 10, 20, 50, 75, 90%, or more) of the flat surface area of ​​the capacitor leads may be electrically and thermally connected (e.g., by welding, soldering, press-fit with fasteners such as screws, etc.) to the flat surface of the V+ or V- busbar. For example, a majority of the flat bottom area of ​​capacitor lead 405a may be electrically and thermally connected to the flat surface of V+ busbar 417T, and a majority of the flat top area of ​​capacitor lead 405b may be electrically and thermally connected to the flat surface of V- busbar 412T. V+ busbar 417 and V- busbar 412 can extract a significant amount of heat (e.g., 1, 2, 5, 10, 20, 40, 80, 100, 200, 300 watts, or more) from the bulk DC link capacitor 403 via the flat surfaces of capacitor leads 405Ta and / or 405Tb, respectively.

[0272] FIG. 5A-19 illustrates the spacing between the front sidewall and the busbars 417T, 418T, and 412T. In an alternative version, the flat surface of the dielectric front sidewall of the exemplary bulk capacitor 403 may be thermally connected to the flat sidewall surfaces of the busbars 417T, 418T, and / or 412T. FIG. 5A-20 illustrates the inverter 460iT of FIG. 5A-19 implemented with a string of exemplary packaged ceramic DC link capacitors 433. For simplicity, only one packaged ceramic DC link capacitor 433-1 of the string is shown.

[0273] Each packaged ceramic DC link capacitor 433 has first and second metal terminals 437-1 and 437-2, respectively, which may be electrically connected to the V+ and V- bus bars, respectively. Figure 5A-20 shows an example in which packaged ceramic DC link capacitors 433 are mounted on a PCB 435 and electrically connected in parallel.

[0274] The dielectric sidewall extends between first and second metal terminals 437-1 and 437-2. The first and second metal terminals 437-1 and 437-2 may be electrically connected to first and second metal traces 511-1 and 511-2, respectively, on the side of PCB 435 opposite capacitor 433. Metal vias may electrically connect 511-1 and 511-2 to their respective terminals 437-1 and 437-2. The ends of first and second traces 511-1 and 511-2 may be widened to increase the surface area that can be electrically and thermally connected to the respective sidewall surfaces of V+ and V- busbars 417T and 412T, respectively.

[0275] A string of packaged ceramic DC link capacitors can be accommodated between the V+ and V- busbars. FIG. 5A-21 illustrates an example of an implementation of a string of exemplary packaged ceramic DC link capacitors 433l in the inverter 460iT of FIG. 5A-19. For simplicity, only one packaged ceramic DC link capacitor 433l-1 of the string is shown. FIG. 5A-21 also illustrates that the front dielectric wall surface of DC link capacitor 403T-2 is thermally connected to the sidewall surfaces of busbars 417T and 412T, although it will be understood that the front dielectric wall need not be thermally connected to the busbars.

[0276] Each packaged ceramic DC link capacitor 433l in FIG. 5A-21 may be longer than the packaged ceramic DC link capacitor 433 in FIG. 5A-20. The packaged ceramic DC link capacitors 433l in a row are electrically connected between the V+ and V- bus bars. In an alternative example, two or more rows of packaged ceramic DC link capacitors 433l may be electrically connected between the V+ and V- bus bars. Similar to the packaged capacitor 433 shown in FIG. 5A-20, the packaged capacitor 433l in FIG. 5A-21 has first and second metal terminals 437-1 and 437-2, respectively, which may be electrically and thermally connected to the first and second electrodes of the ceramic capacitors in the package. The metal terminals 437-1 and 437-2 have opposing flat end faces. The flat end face of the first terminal connector 437-1 may be electrically and thermally directly connected to the flat surface of the bus bar 417T, and the flat end face of the second terminal 437-2 may be electrically and thermally directly connected to the flat surface of the V- bus bar 412T. The V+ bus bar 417T and the V- bus bar 412T can extract a large amount of heat (e.g., 1, 2, 5, 10, 20, 40, 80 watts or more) from the capacitor 4331 via the flat end faces of the metal terminals 437-1 and / or 437-2, respectively.

[0277] The length and / or width of the busbars 417T and 412T may need to be extended to accommodate the packaged ceramic DC link capacitor 433l disposed between them.

[0278] The first and second metal terminals 437-1 and 437-2 of the packaged ceramic DC link capacitor may be electrically and thermally attached (e.g., welded) directly to the flat sidewall surfaces of the busbars 417T and 412T, respectively. FIG. 5A-22 illustrates an example of an implementation of a string of exemplary packaged ceramic DC link capacitors 433e in the inverter 460iT of FIG. 5A-19. For simplicity of illustration, only one packaged ceramic DC link capacitor 433e-1 of the string is shown.

[0279] Each packaged ceramic DC link capacitor 433e in FIG. 5A-22 may be longer than the packaged ceramic DC link capacitor 433 in FIG. 5A-19. The packaged ceramic DC link capacitors 433e in the string are electrically connected between the V+ and V- busbars. Similar to the packaged capacitor 433 shown in FIG. 5A-20, the packaged capacitor 433e in FIG. 5A-22 may have first and second metal terminals 437-1 and 437-2, respectively, which may be electrically and thermally connected to the first and second electrodes of the multilayer ceramic capacitors in the package. The metal terminals 437-1 and 437-2 have flat sidewalls and may be electrically and thermally directly connected (e.g., welded) to the flat sidewalls of the busbar 417T and the V- busbar 412T, respectively. V+ busbar 417T and V- busbar 412T can extract large amounts of heat (eg, 1, 2, 5, 10, 20, 40, 80 watts or more) from capacitor 433e through the flat sidewall surfaces of metal terminals 437-1 and / or 437-2, respectively.

[0280] Each switch 304 of a converter, such as inverter 460iT, may be electrically connected in parallel to one or more snubber circuits. Each snubber circuit may include a snubber resistor electrically connected in series with a snubber capacitor (e.g., a multilayer ceramic capacitor), which may be housed in a rectangular parallelepiped-shaped package with substantially flat dielectric sidewalls. Similar to the packaged ceramic DC link capacitor described above, each packaged snubber capacitor may have first and second metal terminals at opposite ends of the package. The packaged snubber circuit may be located adjacent to the packaged switch 247 to which it is electrically connected. The packaged snubber capacitor circuit may also be electrically connected between a phase busbar, such as phase busbar 418T, and a DC busbar, such as V+ busbar 417T or V− busbar 412T.

[0281] FIG. 5A-23 illustrates an example of a snubber circuit for phase c in inverter 460iT of FIG. 5A-22. The snubber circuit includes snubber capacitors 433sH and 433sL electrically connected in series with snubber resistors RH and RL, respectively. Although not shown, phases a and b may also include similar snubber circuits. Snubber capacitor 433s is similar to ceramic capacitor 433 of FIG. 5A-20 but may be shorter. Snubber capacitor 433s may have first and second metal terminals 437H-1 and 437L-2, respectively, electrically and thermally connected to first and second electrodes, respectively, of a multilayer ceramic capacitor within the package.

[0282] The opposing flat sidewall surfaces of terminal 437H-1 may be electrically and thermally directly connected (e.g., welded) to the flat sidewall surfaces of the V+ busbar 417T and the first terminal 437-1 of the ceramic capacitor 433e, respectively. The opposing flat sidewall surfaces of terminal 437L-2 may be electrically and thermally directly connected (e.g., welded) to the flat sidewall surfaces of the V- busbar 412T and the first terminal 437-2 of the ceramic capacitor 433e, respectively. The first electrodes of snubber resistors RHc and RLc may be electrically connected (e.g., welded) to terminals 437H-2 and 437L-1, respectively. The second electrodes of snubber resistors RHc and RLc may be electrically connected to each other and to the flat surface of the phase busbar 418T. FIG. 5A-24 shows the inverter 460iT of FIG. 5A-23 excluding resistor R. In this version, the flat sidewall surfaces of terminals 437H-2 and 437L-1 may be electrically and thermally directly connected (e.g., welded) to the flat sidewall surfaces of phase busbar 418Tc. The flat end surfaces of terminals 437H-2 and 437L-1 may also be electrically and thermally directly connected (e.g., welded) together. Snubber circuits for phases a and b are similarly connected to their respective phase busbar leads. V+ busbar 417T and V- busbar 412T can extract large amounts of heat (e.g., 1, 2, 5, 10, 20, 40, 80, 100 watts or more) from capacitors 433seH and 433seL through the flat sidewall surfaces of metal terminals 437H-1 and 437L-2, respectively. Phase bus bar 418T of FIG. 5A-24 can extract a large amount of heat (eg, 1, 2, 5, 10, 20, 40, 80 watts or more) from capacitors 433seH and 433seL through the flat sidewall surfaces of metal terminals 437H-2 and / or 437L-1, respectively.

[0283] Returning to FIG. 5A-18, current symbols are shown representing the current flow within inverter system 460iT at a given moment. More specifically, FIG. 5A-18 illustrates the current flow with phase a high-side switch 304dH operating and phases b and c low-side switches 304dL operating to transmit current to the V- terminal via V-busbar 412T. All other switches in the diagram are inactive. Each current symbol in the inverters herein is drawn with approximately the same length. Each current symbol in the inverters herein is drawn with different widths. Wider current symbols represent larger current values.

[0284] The die substrate terminals 230 and the die clip terminals 344 may be press-fit, soldered, sintered, welded, or otherwise connected directly to the corresponding flat surfaces of the bus bars to establish thermal and electrical connections. Each of the die substrate terminals 230 of the packaged switch 247dH of FIG. 5A-18 may be press-fit, soldered, sintered, welded, or otherwise connected directly to the flat surface or respective flat surfaces of the V+ bus bar 417T. The die clip terminals 344 of the packaged switch 247dH of FIG. 5A-18 may be press-fit, soldered, sintered, welded, or otherwise connected directly to the flat surfaces of the respective bus bars 418T. The die substrate terminals 230 of the packaged switch 247dL of FIG. 5A-18 may be press-fit, soldered, sintered, welded, or otherwise connected directly to the flat surfaces of the respective bus bars 418T. Each of the die clip terminals 344 of the packaged switch 247dL of FIG. 5A-18 may be press-fit, soldered, sintered, welded, or otherwise connected to a flat surface of the V-bus bar 412T or directly to a respective flat surface.

[0285] A converter such as inverter 460iT of FIGS. 5A-18 and 5A-19 may include a control PCB such as control PCB 462i of FIG. 5A-19. A converter such as inverter 460iT may include a driver PCB such as driver PCB 461i of FIG. 5A-19. A driver PCB such as driver PCB 461i may be electrically connected to switch 304 via a respective set of connector leads 288. Only connector leads 288gH and 288gL of phase c are shown in FIG. 5A-19.

[0286] The power PCB and the control PCB may communicate data with each other. The power PCB and the control PCB may have opposing sides. Components (e.g., drivers (e.g., base drivers, gate drivers, etc.), current sensors, voltage sensors, PMICs, MCUs, etc.) may be mounted on one or both sides of the power PCB and the control PCB, such as PCB 461i or 462i. Terminals of the components may be electrically connected to traces on the power PCB and the control PCB. Metal vias may connect the traces on the opposing sides of the power PCB and the control PCB, such as PCB 461i or 462i. The traces of the driver PCB may be electrically connected to respective connector leads 288.

[0287] The driver PCB may include a driver in data communication with each packaged switch 247 via a respective connector lead 288g or a respective set of connector leads 288g1 and 288g2. The drivers on the driver PCB may provide control signals to a respective transistor control terminal or a respective group of transistor control terminals. The driver PCB may include a PMIC that provides a supply voltage to each driver.

[0288] The driver PCB may include a voltage sensor in data communication with each packaged switch 247 via a respective set of connector leads 288dc and 288ds. The voltage sensor is capable of detecting a voltage across the current terminals of the switch 304 in the packaged switch 247 via the connector leads 288dc and 288ds.

[0289] The driver PCB may include openings through which the respective phase bus bar leads can extend. FIG. 5A-19 shows an example of a phase bus bar lead 465c. The phase bus bar lead extends between a first end and a second end. The first end may be electrically connected to the phase bus bar.

[0290] The driver PCB may include current sensors connected to wiring on the driver PCB and configured to measure current through each phase busbar lead. Each current sensor may take the form of a current transformer (CT) sensor, and the sensor may have an opening through which the respective phase busbar lead extends. If the current sensor has an opening to accommodate the busbar lead, the current sensor may be aligned with the respective opening in the driver PCB through which the respective phase busbar lead extends. Current sensors without openings may be positioned on the driver PCB near (e.g., within 5 mm, 3 mm, 1 mm, or less) the respective phase busbar lead.

[0291] The driver PCB 461i in FIG. 5A-19 includes a driver 306 in data communication with each packaged switch 247d of phase c via a respective connector lead 288g. The driver 306 may be located on the PCB 461i near the respective connector lead 288g to reduce stray inductance, capacitance, and resistance therebetween. For example, the wiring connection between the terminals of the driver 306 and the respective connector lead 288g may be 5 mm or less. A PMIC provides supply voltage to each driver 306 and may be located as close as possible to the opposite side of the driver PCB 461i as shown. The driver PCB 461i in FIG. 5A-19 includes a voltage sensor V_Sense in data communication with each packaged switch 247d. An example phase bus bar lead 465c extends laterally between a first end and a second end. A first end of the phase busbar lead 465c is electrically connected to the phase busbar 418Tc, and a second end is electrically connected to the winding Wc. The phase busbar lead 465c extends through an opening in the PCB 460i. A current sensor I_Sense measures the current through the phase busbar connector 465c. The I_Sense may include an opening through which the phase busbar connector 465c extends. FIG. 5A-19 shows the driver 306, voltage sensor V_Sense, PMIC, current sensor I_Sense, and phase busbar lead 465 for phase c. Similar groups of driver 306, voltage sensor V_Sense, PMIC, current sensor I_Sense, and phase busbar lead 465 are mounted on or extend through the PCB 461i for phases a and b.

[0292] The drivers, voltage sensors, current sensors, etc. implemented on the driver PCB may communicate data with a data processing unit, such as an MCU, implemented on the control PCB. The data processing unit may be located on the control PCB at a position furthest from the phase bus bar leads to reduce the adverse effects of electromagnetic interference (EMI). The data communication may be via a data connection comprising pin and socket connectors, also known as "headers," implemented on the driver PCB and control PCB, respectively. The data connection may comprise a flexible data bus, such as a flexible circuit or flexible PCB. The ends of the flexible circuit or flexible PCB may be electrically connected to the pin and socket headers.

[0293] FIG. 5A-19 shows an MCU mounted on the control PCB 462i. The MCU may communicate data with each driver 306, V_Sense, and I_Sense mounted on the driver PCB 461iT via a data connection 484, which may include a pin and socket connector (not shown) electrically connected to traces on the driver PCB 461iT and the control PCB 462iT, respectively. The pins of the pin connector may be directly received in the respective sockets of the socket connector. The driver PCB and the control PCB may be parallel to each other. The driver PCB 461iT and the control PCB 462i in FIG. 5A-19 are parallel to each other. Alternatively, the control PCB 462i may be positioned above and parallel to the flat surface of the V+ bus bar 417T. Other configurations are also contemplated.

[0294] All of the tubes 420, such as tube 420a in FIGS. 5A-18, housed in all of the converter's bus bars may be approximately the same length. Each tube 420 has a first end and a second end. The converter may have first and second fluid manifolds. The first ends of all of the tubes 420 in the converter may be in fluid communication with the first manifold, and the second ends of all of the tubes in the converter may be in fluid communication with the second manifold. The manifolds may have input and output ports in fluid communication with the internal chamber. The first manifold has an input port, which may be in fluid communication with the pump. The first manifold may have one or more output ports in fluid communication with and receive the first ends of each of the tubes 420. The second manifold may have one or more input ports in fluid communication with and receive the second ends of each of the tubes 420. The second manifold may have an output port that is in fluid communication with a heat exchange system, such as a radiator. The port comprises an opening in the sidewall of the manifold through which fluid can flow into or out of the manifold's internal chamber. A seal may be added between the manifold's input or output port and the tubing it receives. A seal is a device that helps join items (e.g., tubing and ports) by preventing leakage. The first and second manifolds may be substantially similar in size, shape, configuration, etc. The manifold may be formed (e.g., molded) from a dielectric material.

[0295] FIG. 5A-25 illustrates an example of the inverter 460iT of FIG. 5A-18 with first and second manifolds 466-1 and 466-2, respectively, in fluid communication with first and second ends of the tubes 420a. The first ends of the tubes 420a extend through respective output ports of the manifold 466-1, and the second ends of the tubes 420a extend through respective input ports of the manifold 466-2. The manifold 466 is shown in cross section to better illustrate the fluid flow. In one version, the input and output ports 467-1 and 467-2 of the manifolds 466-1 and 466-2, respectively, may be located at the ends of the manifolds 466-1 and 466-2, respectively, and may be closer to the V- busbar 412T than the V+ busbar 417T, as shown. Alternative locations or arrangements of input and output ports 467-1 and 467-2 of manifolds 466-1 and 466-2, respectively, are also contemplated.

[0296] Inverter 460ijc The packaged switch 247 can be used in power converters with bus bars that do not have tubes 420. Figures 5A-26 and 5A-27 show the relevant components of an example inverter 460ijc from the front and side, respectively, with bus bars that do not have cooling tubes 420. Some components shown in Figure 5A-27 (i.e., driver PCB 461i, control PCB 462i, and DC link capacitor 403jc) are not shown in Figure 5A-26 but are described below.

[0297] Inverter 460ijc employs packaged switch 247d, although it will be appreciated that in alternative versions packaged switch 247d may be replaced with packaged switch 247p or packaged switch 247q.

[0298] All of the packaged switches 247d of the inverters 460ijc may be identical, and the packaged switches 247d of the inverters 460ijc may be packaged switches 247dA, 247dB, 247dC, or 247dD of Figures 3A, 3B, 3C, and 3D, respectively.

[0299] The inverter 460ijc includes a V+ busbar 417ijc, a V- busbar 412ijc, and phase busbars 418ijc. As shown in FIGS. 5A-26 and 5A-27, the busbars are solid metal and do not have channels. The V+ busbar 417ijc and the V- busbar 412ijc have the same shape (e.g., rectangular) and size. As shown in FIG. 5A-27, the phase busbars 418ijc, including the busbar 418ijcc, are C-shaped.

[0300] The inverter 460ijc includes metal heat sinks 528-530, which may be electrically isolated from one another. Each heat sink includes an array of channels 40 through which a cooling fluid flows. Heat sink 528 is thermally coupled to and electrically isolated from the V+ bus bar 417ijc by a substantially planar layer 526-1 of a dielectric material (e.g., diamond-based dielectric, beryllium oxide, etc.). Heat sink 529 is thermally coupled to and electrically isolated from the phase bus bar 418ijc by substantially planar layers 526-2 and 526-3 of a dielectric material (e.g., diamond-based dielectric, beryllium oxide, etc.). Heat sink 530 is thermally coupled to and electrically isolated from the V- bus bar 412ijc by a substantially planar layer 526-4 of a dielectric material (e.g., diamond-based dielectric, beryllium oxide, etc.). Layer 526 may be formed from any of the dielectric materials listed in the table above. Other dielectric materials are also contemplated.

[0301] Inverter 460ijc has three phases, a to c. Each phase a to c in FIG. 5A-26 includes two packaged switches 247dH and 247dL electrically and thermally connected to a phase bus bar 418ijc, which are together sandwiched between a V+ bus bar 417ijc and a V- bus bar 412ijc. Packaged switches 247dH and 247dL are also electrically and thermally connected to the V+ bus bar 417ijc and the V- bus bar 412ijc, respectively.

[0302] FIG. 5A-26 illustrates the linear arrangement of packaged switch 247d, V+ busbar 417ijc, phase busbar 418ijc, V- busbar 412ijc, and dielectric layers 526-1 through 526-4 relative to one another. Packaged switch 247dH in FIG. 5A-26 may have die substrate terminal 230 electrically and thermally connected (e.g., sintered, press-fit, etc.) to the or each flat surface of V+ busbar 417ijc and die clip terminal 344 electrically and thermally connected (e.g., sintered, press-fit, etc.) to the flat surface of each phase busbar 418ijca through 418ijcc. These phase busbars may have terminals electrically connected to windings Wa through Wc, respectively. The packaged switch 247dL of FIG. 5A-26 may have die substrate terminals 230 electrically and thermally connected (e.g., sintered, press-fit, etc.) to the flat surfaces of each phase busbar 418ijca-418ijcc, and die clip terminals 344 electrically and thermally connected (e.g., sintered, press-fit, etc.) to the flat surface or each flat surface of the V-busbar 412ijc.

[0303] An example of the V+ busbar 417ijc and V- busbar 412ijc may be about 4 mm high, about 29 mm wide, and about 100 mm long. Heat sinks 528-530 are about 8 mm high, about 29 mm wide, and about 130 mm long.

[0304] The inverter 460ijc may include a driver PCB 461iT and a control PCB 462iT. The driver PCB 461iT of FIG. 5A-27 includes a driver 306 in data communication with each packaged switch 247d of phase c via a respective connector lead 288g. A current sensor I_Sense measures the current through the phase bus bar connector 465c. FIG. 5A-27 shows an MCU implemented on the control PCB 462iT. The MCU may be in data communication with each driver 306, V_Sense, and I_Sense implemented on the driver PCB 461iT via a data connection 484.

[0305] All of the heat sinks 528-530 may be approximately the same length. All of the heat sinks 528-530 have a first end and a second end. The first ends of the heat sinks 528-530 may be in fluid communication with a first manifold, and the second ends of the heat sinks 528-530 may be in fluid communication with a second manifold.

[0306] rectifier 460rT The packaged switch 247 may also be used in a rectifier. FIGS. 5B-1 and 5B-2 show relevant components of an exemplary rectifier 460rT from the front and side, respectively. The rectifier 460rT may be connected to inductive elements, such as inductive elements La through Lc, of the LCL filter 162 of FIG. 1C, which in turn is connected to a three-phase AC power source 164, also shown in FIG. 1C. For simplicity, the LCL filter 162 is not shown in the rectifier diagrams of this disclosure. The AC power sources φa through φc are shown connected directly to the phase bus bars of the rectifier, including phase bars 418Ta through 418Tc, respectively, in FIG. 5B-1.

[0307] The rectifier 460rT and the inverter 460iT are generally equivalent, but differences exist. The microcontroller implemented on the control PCB 462rT of the rectifier system 460rT may be different from the microcontroller implemented on the control PCB 462iT of the inverter system 460i, and the CPU-executable instructions stored in the memory of the microcontroller implemented on the control PCB 462rT of the rectifier system 460rT may be different from the CPU-executable instructions stored in the memory of the microcontroller implemented on the control PCB 462iT of the inverter system 462i. The control PCB 462rT may also include a phase-locked loop (PLL) or other components for synchronizing control of the switch 304 to the frequency (e.g., 60 Hertz) of the three-phase AC input voltage provided by the AC power sources φa-φc.

[0308] Passive Rectifier Rectifier 460rT is an example of an "active" rectifier because it uses a packaged switch 247d. Passive rectifiers are also contemplated. Passive rectifiers do not use switches. Instead, passive rectifiers use diodes. Compact rectifier 460rT shown in FIGS. 5B-1 and 5B-2 can be converted to a passive rectifier by replacing packaged switch 247d with packaged diode 245M or 245N shown in FIGS. 3M and 3N, respectively.

[0309] FIG. 5H shows an exemplary passive rectifier 460pr in which the packaged switch 247d of FIG. 5B-1 is replaced with a packaged diode 245M. The packaged diode 245M may not have connector leads. The V+ busbar 417T, V- busbar 412T, and phase busbar 418T of FIG. 5B-1 are renamed 417pr, 412pr, and 418pr, respectively, in FIG. 5H. The passive rectifier 460pr may not have a control PCB and a driver PCB.

[0310] The die substrate terminal 230 of the packaged diode 245MH is electrically and thermally attached (e.g., sintered, press-fit, etc.) directly to the or each flat surface of the V+ bus bar 417pr. The die clip terminal 344 of the packaged diode 245MH is electrically and thermally attached (e.g., sintered, press-fit, etc.) to the flat surface of the corresponding phase bus bar 418pr.

[0311] The die substrate terminals 230 of the packaged diodes 245ML are directly electrically and thermally connected (e.g., sintered, press-fit, etc.) to the flat surfaces of the corresponding phase bus bars 418pr. The die clip terminals 344 of the packaged diodes 245ML are directly electrically and thermally connected (e.g., sintered, press-fit, etc.) to the or each flat surface of the V-bus bar 404pr.

[0312] Inverter 460id 5C shows the relevant components of an exemplary inverter 460id from a front view, with some components (i.e., the driver PCB, control PCB, manifold, and DC link capacitors) not shown or not fully shown in FIG.

[0313] Inverter 460id has three phases, a to c. Each phase includes four packaged switches 247 and a phase bus bar 418d, which are sandwiched between a V+ bus bar 417d and a V- bus bar 412d. The diagram shows the linear arrangement of packaged switches 247, V+ bus bar 417d, phase bus bar 418d, and V- bus bar 412d relative to one another. Phase bus bars 418da to 418dc are electrically connected to stator windings Wa to Wc, respectively.

[0314] All packaged switches 247 of inverter 460id may be a version of packaged switches 247d, 247p, or 247q. In FIG. 5C, each phase of inverter 460id includes a mix of packaged switch versions. As shown, each phase includes a pair of packaged switches 247d and a pair of packaged switches 247q. Packaged switches 247d may be packaged switches 247dA, 247dB, 247dC, 247dD, or 247dO of FIGS. 3A, 3B, 3C, 3D, or 3O, respectively, and packaged switches 247q may be packaged switches 247qE, 247qF, 247qG, 247qI, 247qJ, 247ql, or 247qP of FIGS. 3E, 3F, 3G, 3I, 3J, 3L, and 3P, respectively. For example, each packaged switch 247d may be packaged switch 247dO shown in FIG. 3O or packaged switch 247dB shown in FIG. 3B, and each packaged switch 247q may be packaged switch 247qP shown in FIG. 3P or packaged switch 247qF shown in FIG. 3F. In another version, each packaged switch 247q of FIG. 5C is interchangeable with packaged switch 247dB, and each packaged switch 247d is packaged switch 247dA or 247dO. The packaged switch 247 of inverter 460id may take the form of a packaged switch without connector leads 288ds and / or 288dc. All switches 304 of inverter 460id are independently controllable by an MCU or other data processing device.

[0315] Each phase packaged switch 247dH and 247qH may have a die substrate terminal 230 electrically and thermally directly connected (e.g., by sintering, press-fitting, etc.) to the flat surface or each flat surface of the V+ bus bar 417d and a die clip terminal 344 electrically and thermally directly connected (e.g., by sintering, press-fitting, etc.) to the flat surface or each flat surface of the corresponding phase bus bar 418d. The phase bus bar 418d has terminals electrically connected to the windings Wa-Wc, respectively. Each phase packaged switch 247dL and 247qL may have a die substrate terminal 230 electrically and thermally directly connected (e.g., by sintering, press-fitting, etc.) to the flat surface or each flat surface of the corresponding phase bus bar 418d and a die clip terminal 344 electrically and thermally directly connected (e.g., by sintering, press-fitting, etc.) to the flat surface or each flat surface of the V- bus bar 412d.

[0316] 5C may have rectangular cross sections. An exemplary phase bus bar 418d may be approximately 12 mm high, approximately 30 mm wide, and approximately 70 mm long. An exemplary V+ bus bar 417d and V- bus bar 412d may be approximately 8 mm high, approximately 30 mm wide, and approximately 230 mm long.

[0317] FIG. 5C illustrates an inverter 460i-d with dielectric tubes 420a housed in respective channels (not shown) of the bus bars. All of the tubes 420a in FIG. 5C may be of approximately equal length. Each tube 420a has a first end and a second end and may be in fluid communication with first and second fluid manifolds (not shown), respectively, such as those shown in FIG. 5A-25. The phase bus bars 418da-418dc are thermally connected to and electrically insulated from one another by the commonly housed dielectric tubes 420a.

[0318] Inverter 460id includes a packaged DC link capacitor as shown in Fig. 5A-2 and has capacitor leads 405. Inverter 460id may also include a packaged multilayer ceramic DC link capacitor having first and second metal terminals directly electrically and thermally connected to bus bars 417d and 412d, respectively.

[0319] Figure 5C includes current symbols representing the current flowing through inverter system 460i at a given instant. More specifically, Figure 5C illustrates the current flow when switches 304 of packaged switches 247dH and 247qH of phase a are actuated and switches 304 of packaged switches 247dL and 247qL of phases b and c are actuated to transmit current to the V- terminal through V-busbar 412d. All other switches in the figure are in an inactive state.

[0320] Inverter 460id may include a control PCB and a driver PCB as shown in Figure 5A-2. The driver PCB may include a driver electrically connected to and controlling each switch 304 of packaged switch 247d via a respective connector lead 288g, and a driver electrically connected to and controlling each switch 304 of packaged switch 247q via a respective set of connector leads 288g1 and 288g2.

[0321] Inverter 460iq 5D-1, 5D-2, and 5D-3 show the relevant components of an exemplary inverter 460iq from the front, back, and side views, respectively. Some components (i.e., driver PCB 461iq1, driver PCB 461iq2, and DC link capacitor 403q) are not shown in all figures or are not fully illustrated, but are described below.

[0322] 5D-1 and 5D-2 show front and rear views of an exemplary inverter 460iq. Figures 5D-1 and 5D-2 show the leads 405q of the DC link capacitor 403q. The inverter 460iq has three phases, a through c, each of which includes eight packaged switches 247.

[0323] Inverter 460iq has a mix of packaged switches 247d and 247q. As shown in FIG. 5D-1, each phase includes packaged switches 247d1-247d4 and packaged switches 247q1-247q4. Alternatively, all packaged switches in inverter 460iq may be replaced with versions of packaged switches 247p, 247q, or 247d. The transistors of switch 304 in packaged switches 247 of inverter 460iq are independently controllable by the MCU on control PCB 462iq, regardless of whether the transistor is packaged switch 247d, 247p, or 247q. Packaged switches 247d2, 247d4, and 247q1-247q4 in each phase may take the form of packaged switches without connector leads 288dc and / or 288ds.

[0324] All of the packaged switches 247d1-247d4 may be identical, and all of the packaged switches 247q1-247q4 may be identical. The packaged switch 247d of the inverter 460iq may be packaged switch 247dA, 247dB, 247dC, 247dD, or 247dO of Figures 3A, 3B, 3C, 3D, and 3O, respectively, and the packaged switch 247q may be packaged switch 247qE, 247qF, 247qG, 247qI, 247qJ, 247ql, or 247qP of Figures 3E, 3F, 3G, 3I, 3J, 3L, and 3P, respectively. For example, each of the packaging switches 247d1 to 247d4 may be the packaging switch 247dO shown in FIG. 3O or the packaging switch 247dB shown in FIG. 3B, and each of the packaging switches 247q1 to 247q4 may be the packaging switch 247qP shown in FIG. 3P or the packaging switch 247qF shown in FIG. 3F.

[0325] Inverter 460iq includes a V+ busbar 417q, a V- busbar 412q, and a phase busbar 418q. Busbars such as V+ busbar 417q, V- busbar 412q, and phase busbar 418q may also function as heat sinks to cool switch 304 or diode D.

[0326] Each phase a-c includes packaged switches 247d1-247d4 and packaged switches 247q1-247q4 electrically and thermally connected to phase bus bar 418q, which are together sandwiched between V+ bus bar 417q and V- bus bar 412q. Packaged switches 247d1, 247d2, 247q1, and 247q2 are electrically and thermally connected to V+ bus bar 417q, and packaged switches 247d3, 247d4, 247q3, and 247q4 are electrically and thermally connected to V- bus bar 412q.

[0327] 5D-1 and 5D-2 show the linear arrangement of packaged switch 247, V+ bus bar 417q, phase bus bar 418q, and V- bus bar 412q relative to one another. Packaged switches 247d1 and 247d2 of each phase may have die substrate terminals 230 electrically and thermally directly connected (e.g., sintered, press-fit, etc.) to the or each flat surface of V+ bus bar 417q and die clip terminals 344 electrically and thermally directly connected (e.g., sintered, press-fit, etc.) to the or each flat surface of corresponding phase bus bar 418q, each of which has a terminal that can be electrically connected to windings Wa-Wc. The packaged switches 247q1 and 247q2 of each phase may have a die substrate terminal 230 electrically and thermally directly connected (e.g., sintered, press-fit, etc.) to the or each flat surface of the V+ bus bar 417q and a die clip terminal 344 electrically and thermally directly connected (e.g., sintered, press-fit, etc.) to the or each flat surface of the corresponding phase bus bar 418q. The packaged switches 247d3 and 247d4 of each phase may have a die substrate terminal 230 electrically and thermally directly connected (e.g., sintered, press-fit, etc.) to the or each flat surface of the corresponding phase bus bar 418q and a die clip terminal 344 electrically and thermally directly connected (e.g., sintered, press-fit, etc.) to the or each flat surface of the V- bus bar 412q. The packaged switches 247q3 and 247q4 of each phase may have die substrate terminals 230 that are electrically and thermally directly connected (e.g., sintered, press-fit, etc.) to the or each flat surface of the corresponding phase bus bar 418q, and die clip terminals 344 that are electrically and thermally directly connected (e.g., sintered, press-fit, etc.) to the or each flat surface of the V-bus bar 412q.

[0328] Busbars, such as V+ busbar 417q, V- busbar 412q, and phase busbar 418q in Figures 5D-1-5D-3, may have a rectangular cross-section. An exemplary phase busbar 418q may be approximately 8 mm high, approximately 60 mm wide, and approximately 70 mm long. An exemplary V+ busbar 417q and V- busbar 412q may be approximately 8 mm high, approximately 60 mm wide, and approximately 230 mm long. The busbars may have different dimensions to accommodate different converter designs.

[0329] 5D-1-5D-3 show inverter 460iq with dielectric tube 420a housed in each channel (not shown). In alternative versions, tubes other than 420a, such as tube 420b, may be housed in the channels. Phase bus bars 418qa-418qc are thermally connected to and electrically insulated from one another by commonly inserted dielectric tube 420a.

[0330] The inverter 460iq may include a packaged DC link capacitor 403q. First and second metal capacitor leads 405qa and 405qb may extend from a portion of the dielectric wall of the packaged capacitor. An exemplary capacitor lead 405q may have a height hbc, length lbc, and width wbc of approximately 6 mm, 30 mm, and 50 mm, respectively. The capacitor leads, including capacitor lead 405, may have substantially flat, rectangular, opposing upper and lower surfaces. A majority (e.g., 10, 20, 50, 75, 90%, or more) of the flat lower area of ​​each capacitor lead 405qa may be directly electrically and thermally connected (e.g., by welding, soldering, press-fit with screws or other fasteners, etc.) to the flat surface of the V+ busbar 417q. Additionally, a majority (e.g., 10, 20, 50, 75, 90% or more) of the flat top area of ​​each capacitor lead 405qb may be directly electrically and thermally connected (e.g., by welding, soldering, press-fit with screws or other fasteners, etc.) to the flat surface of the V-busbar 412q.

[0331] Inverter 460iq may include one or more packaged ceramic DC link capacitors (e.g., multilayer ceramic capacitors) having first and second metal terminals electrically and thermally connected, directly or indirectly, to the flat surfaces of V+ busbar 417q and V- busbar 412q, respectively.

[0332] FIG. 5D-1 includes current symbols representing the current flowing through inverter system 460iq at a given moment in time. More specifically, FIG. 5D-1 illustrates the current flow with switches 304 in packaged switches 247d1 and 247d2 of phase a operating and switches 304 in packages 247d3 and 247d4 of phases b and c operating to transmit current to the V- terminal via V-busbar 412q. All other switches, including switch 304 in packaged switch 247q, are in an inactive state, and it is understood that the combination of packaged switches 247d and 247q operates to convert power.

[0333] The inverter 460iq may include driver PCBs 461iq1 and 461iq2 having drivers 306 electrically connected to and controlling the respective switches 304 via respective connector leads 288 or respective sets of connector leads 288g1 and 288g2. Only connector leads 288gc, 288g1, and 288g2 of phase c are shown in FIG. 5D-3. The inverter 460iq may include a control PCB 462iq having an MCU, which is in data communication with the drivers 306, current sensor I_Sense, voltage sensor, and other components implemented on the driver PCBs 461iq1 and 461iq2. Data connections 484-1 and 484-2 may facilitate the data communication.

[0334] The driver PCB 461iq1 of FIG. 5D-3 includes a driver 306 in data communication with each packaged switch 247q of phase c via a respective set of connector leads 288g1 and 288g2. The driver PCB 461iq1 also includes a driver in data communication with each packaged switch 247q of phase a and b. The driver PCB 461iq2 of FIG. 5D-3 includes a driver 306 in data communication with each packaged switch 247d of phase c via a respective connector lead 288gc. The driver PCB 462iq2 also includes a driver in data communication with each packaged switch 247d of phase a and b.

[0335] The driver PCB 461iq2 includes a voltage sensor V_Sense that communicates with each packaged switch 247d via a respective pair of connector leads 288ds and 288dc (not shown). An exemplary phase bus bar lead 465c extends laterally between a first end and a second end. The first end of the phase bus bar lead 465c is electrically connected to the phase bus bar 418qc, and the second end is electrically connected to the winding Wc. The phase bus bar lead 465c extends through an opening in the PCB 461iq2. The current sensor I_Sense measures the current flowing through the phase bus bar connector 465c. The I_Sense may include an opening through which the phase bus bar connector 465c extends. FIG. 5D-3 illustrates the voltage sensor V_Sense, PMIC, current sensor I_Sense, and phase bus bar lead 465 for phase c. A similar voltage sensor V_Sense, PMIC, current sensor I_Sense, and group of phase busbar leads 465 are mounted on or extend through PCB461iq2 for phases a and b.

[0336] All of the tubes 420a housed in all of the bus bars, such as bus bar 412q, may be substantially the same length. Each tube 420a has a first end and a second end. The first ends of all of the tubes 420a may be in fluid communication with a first manifold, and the second ends of all of the tubes 420a may be in fluid communication with a second manifold.

[0337] Vienna Rectifier 400VR1 FIGS. 5E-1 through 5E-3 show front and side views of relevant components of an exemplary rectifier 400vr1. The rectifier 400vr1 is an example of a three-phase "Wien" rectifier. The rectifier system 400vr1 is not capable of bidirectional operation. The driver PCB 421 is shown in FIGS. 5E-2 and 5E-3, but not in FIG. 5E-1. Although not shown, the rectifier 400vr1 may include a manifold and a control PCB with an MCU.

[0338] Referring to FIG. 5E-1, rectifier 400vr1 has three phases, a through c. Each phase may include a bidirectional packaged switch 247. Phases a through c include packaged switches 247qa through 247qc, respectively. Packaged switches 247qa through 247qc may be packaged switches 247qG, 247qI, 247qJ, or 247ql, respectively, of FIGS. 3G, 3I, 3J, and 3L. In an alternative version, each phase may include packaged switch 247pK shown in FIG. 3K. All of the switches 304 of rectifier 400vr1 are independently controllable by an MCU or other data processing device.

[0339] The rectifier 400vr1 may include a rectangular V+ busbar 431, a V- busbar 430, a phase busbar 520, and a common busbar 404vr, each of which may also function as a heat sink to cool the switch 304 or the diode D.

[0340] Each of the phase bus bars 520 may be approximately 10 mm high, approximately 37 mm wide, and approximately 30 mm long. The cases of the packaged switches 247qa-247qc may be thermally connected to the phase bus bars 520a-520c, respectively. The packaged switches 247qa-247qc may have die substrate terminals 230 that are electrically and thermally connected directly to the surfaces of the phase bus bars 520a-520c, respectively. The phase bus bars 520a-520c are electrically connected to the AC power sources φa-φc, respectively. All figures show a common bus bar 404vr, which may be approximately 10 mm high, approximately 30 mm wide, and approximately 100 mm long. The case of the packaged switch 247q may be thermally connected to the bus bar 404vr and the surfaces of the respective phase bus bars 520.

[0341] FIGS. 5E-2 and 5E-3 are left and right side views of the rectifier 400vr1 of FIG. 5E-1. As shown in these figures, the V- busbar 430 and the V+ busbar 431 have a rectangular cross-sectional shape. The busbars 430 and 431 may be approximately 10 mm high, 17 mm wide, and 100 mm long. In another version, the busbars 430 and 431 may have different dimensions. The V- busbar 430 and the V+ busbar 431 have terminals for supplying DC power to devices such as a DC / DC converter. Like the busbar 404vr and the phase busbars 520, the busbars 430 and 431 have channels that hold tubes 420a through which cooling fluid flows.

[0342] 5E-2 and 5E-3 show the linear arrangement of packaged switch 247q, phase bar 520, V- bus bar 430, V+ bus bar 431, and bus bar 404vr relative to each other in phases a and c.

[0343] Each phase of rectifier 400vr1 may include a pair of packaged diodes 245-1 and 245-2, each including diodes D1 and D2. For illustrative purposes, packaged diodes 245-1 and 245-2 take the form of packaged diode 245M shown in FIG. 3M. The die substrate terminal 230 of packaged diode 245-2 of each phase and the die clip terminal 344 of packaged diode 245-1 are directly electrically and thermally attached (e.g., sintered, press-fit, etc.) to the flat surface or respective flat surfaces of V+ busbar 431 and V− busbar 430, respectively. The die substrate terminal 230 of packaged diode 245-1 of each phase and the die clip terminal 344 of packaged diode 245-2 are directly electrically and thermally attached (e.g., sintered, press-fit, etc.) to the flat surface or respective flat surfaces of corresponding phase busbar 520.

[0344] Die substrate terminals 230 of packaged switches 247qa-247qc are electrically and thermally directly connected (e.g., sintered, press-fit, etc.) to the flat surfaces of phase bus bars 520a-520c, respectively. Die clip terminals 344 of packaged switches 247qa-247qc are electrically and thermally directly connected (e.g., sintered, press-fit, etc.) to the flat surface or respective flat surfaces of common bus bar 404vr.

[0345] Capacitors C- and C+ may be polarized capacitors as shown and are electrically connected to bus bar 404vr. Capacitors C- and C+ may also be thermally connected to bus bar 404vr. The first terminal or lead surfaces of capacitors C- and C+ may be sintered, soldered, press-fit, welded, or otherwise connected to the flat surface or respective flat surfaces of bus bar 404vr. Capacitors C- and C+ are electrically connected to bus bars 430 and 431, respectively. The second terminal or lead surfaces of capacitors C- and C+ may be sintered, soldered, press-fit, welded, or otherwise connected to the flat surfaces of V- bus bar 430 and V+ bus bar 431, respectively. Bus bars 430 and 431 are shown symbolically in FIG. 5E-1.

[0346] 5E-1-5E-3 show rectifier 400vr1 in which a dielectric tube 420a is housed in each busbar channel (not shown). In alternative versions, tubes other than 420a, such as tube 420b, may be housed in the channels. The phase busbars 520 are thermally connected to and electrically insulated from one another by the commonly housed dielectric tube 420a.

[0347] The rectifier 400vr1 may include a driver PCB 421 having a driver 306 electrically connected to and controlling each switch 304 via a respective set of connector leads 288g1 and 288g2. Only the connector leads 288g1 and 288g2 for phases c and a are shown in FIGS. 5E-2 and 5E-3, respectively. The rectifier 400vr1 may include a control PCB having an MCU in data communication with the driver 306, current sensor I_Sense, voltage sensor V_Sense, and other components mounted on the driver PCB 421. A connector (e.g., a flexible PCB, not shown) may facilitate data communication.

[0348] The driver PCB 421 includes a voltage sensor V_Sense in data communication with each packaged switch 247q via a respective pair of connector leads 288ds and 288dc (not shown). Exemplary phase bus bar leads 465a and 465c extend laterally between first and second ends. The first ends of the phase bus bar leads 465a and 465c are electrically connected to the phase bus bars 520a and 520c, respectively, and the second ends are electrically connected to the AC power sources φa and φc, respectively. The phase bus bar leads 465a and 465c extend through respective openings in the PCB 421. The current sensors I_Sense-a and I_Sense-c measure the current flowing through the phase bus bar connectors 465a and 465c, respectively. I_Sense-a and I_Sense-c may include respective openings through which the phase bus bar connectors 465a and 465c, respectively, extend. 5E-2 and 5E-3 show the voltage sensor V_Sense, PMIC, driver 306, current sensor I_Sense, and phase bus bar leads 465 for phases a and c, respectively. For phase b, the voltage sensor V_Sense, PMIC, driver 306, current sensor I_Sense, and phase bus bar leads 465 are mounted on or extend through PCB 421.

[0349] The control PCB of rectifier 400vr1 may include a phase-locked loop (PLL) and other components to synchronize the control of switch 304 to the frequency (e.g., 60 Hertz) of the three-phase AC input voltage provided by AC power sources φa-φc. Additional components may be added for power factor correction.

[0350] All of the tubes 420, such as the tube 420a in FIG. 5E-1, housed in all of the bus bars may be substantially the same length. Each tube 420a has a first end and a second end. The first ends of all of the tubes 420a may be in fluid communication with a first manifold, and the second ends of all of the tubes 420a may be in fluid communication with a second manifold.

[0351] Vienna Rectifier 400VR2 FIGS. 5F-1 through 5F-3 show front and side views of relevant components of an exemplary rectifier 400vr2. The rectifier 400vr2 is another example of a three-phase Wien rectifier. The rectifier system 400vr2 is not capable of bidirectional operation. A driver PCB 521 is shown in FIGS. 5F-2 and 5F-3, but not in FIG. 5F-1. Although not shown, the rectifier 400vr2 may include a manifold and a control PCB with an MCU.

[0352] Referring to FIG. 5F-1, the rectifier 400vr2 has three phases, a to c. Each phase may include a pair of packaged switches 247dH and 247dL. Each packaged switch 247d may be packaged switch 247dA, 247dB, or 247dD of FIGS. 3A, 3B, and 3D, respectively. All switches 304 of the rectifier 400vr2 are independently controllable by an MCU or other data processing device.

[0353] The rectifier 400vr2 may include a rectangular V+ busbar 431, a V- busbar 430, phase busbars 520, and a common busbar 404vr, each of which may also function as a heat sink to cool the switch 304 or the diode D. Additionally, the rectifier 400vr2 may include a metal heat sink 522.

[0354] Each of the phase bus bars 520 may be approximately 10 mm high, approximately 37 mm wide, and approximately 30 mm long. Each of the metal heat sinks 520 may be rectangular and approximately 10 mm high, approximately 30 mm wide, and approximately 30 mm long. The cases of the packaged switches 247dHa-247dHc may be thermally connected to the phase bus bars 520a-520c, respectively. The packaged switches 247dHa-247dHc may have die substrate terminals 230, which are electrically and thermally connected to the surfaces of the phase bus bars 520a-520c, respectively. The phase bus bars 520a-520c are electrically connected to the AC power sources φa-φc, respectively. The packaged switches 247dHa-247dHc have die clip terminals 344, which are electrically and thermally connected to the surfaces of the metal heat sinks 522a-522c, respectively.

[0355] All figures show the common bus bar 404vr, which may be approximately 10 mm high, approximately 30 mm wide, and approximately 100 mm long. The cases of the packaged switches 247dLa-247dLc may be thermally connected to the bus bar 404vr and the surface of the respective heat sinks 522a-522c. The packaged switches 247dLa-247dLc may have die substrate terminals 230 that are electrically and thermally connected to the surface of the common bus bar 404vr or to the respective surface of the heat sinks 522a-522c. The packaged switches 247dLa-247dLc may have die clip terminals 344 that are electrically and thermally connected to the surface of the heat sinks 522a-522c, respectively.

[0356] 5F-2 and 5F-3 are left and right side views of the rectifier 400vr2 of FIG. 5F-1. As shown in these figures, the V- busbar 430 and the V+ busbar 431 have a rectangular cross-sectional shape. The busbars 430 and 431 may be approximately 10 mm high, 17 mm wide, and 100 mm long. In another version, the busbars 430 and 431 may have different dimensions. The V- busbar 430 and the V+ busbar 431 have terminals for supplying DC power to devices such as a DC / DC converter. Like the busbar 404vr, the metal heat sink 522, and the phase busbars 520, the busbars 430 and 431 have channels for holding tubes 420a through which a cooling fluid flows.

[0357] 5F-2 and 5F-3 show the linear arrangement of packaged switch 247d, phase bar 520, V- bus bar 430, heat sink 522, V+ bus bar 431, and bus bar 404vr in phases a and c relative to one another.

[0358] Each phase of rectifier 400vr2 may include a pair of packaged diodes 245-1 and 245-2, each including diodes D1 and D2. For illustrative purposes, packaged dies 245-1 and 245-2 take the form of packaged diode 245M shown in FIG. 3M. The die substrate terminal 230 of packaged diode 245-2 of each phase and the die clip terminal 344 of packaged diode 245-1 are electrically and thermally attached (e.g., sintered, press-fit, etc.) directly to the flat surface or respective flat surfaces of V+ busbar 431 and V− busbar 430, respectively. The die substrate terminal 230 of packaged diode 245-1 of each phase and the die clip terminal 344 of packaged diode 245-2 are electrically and thermally attached (e.g., sintered, press-fit, etc.) to the flat surface or respective flat surfaces of corresponding phase busbar 520.

[0359] The die substrate terminals 230 of the packaged switches 247dHa-247dHc are electrically and thermally directly connected (for example, by sintering, press-fitting, etc.) to the flat surfaces of the phase bus bars 520a-520c, respectively. The die clip terminals 344 of the packaged switches 247dHa-247dHc are electrically and thermally directly connected (for example, by sintering, press-fitting, etc.) to the flat surfaces of the metal heat sinks 522a-522c, respectively. The die clip terminals 344 of the packaged switches 247dLa-247dLc are electrically and thermally directly connected (for example, by sintering, press-fitting, etc.) to the flat surfaces of the metal heat sinks 522a-522c, respectively. The die substrate terminals 230 of the packaged switches 247dLa-247dLc are electrically and thermally directly connected (for example, by sintering, press-fitting, etc.) to the flat surfaces of the common bus bar 404vr.

[0360] Capacitors C- and C+ may be polarized capacitors as shown and are electrically connected to bus bar 404vr. Capacitors C- and C+ may also be thermally connected to bus bar 404vr. First terminal or lead surfaces of capacitors C- and C+ may be sintered, soldered, press-fit, welded, or otherwise connected to flat surfaces of bus bar 404vr. Capacitors C- and C+ are electrically connected to bus bars 430 and 431, respectively. Capacitors C- and C+ may also be thermally connected to bus bars 430 and 431, respectively. Second terminal or lead surfaces of capacitors C- and C+ may be sintered, soldered, press-fit, welded, or otherwise connected to surfaces of V- bus bar 430 and V+ bus bar 431, respectively. Bus bars 430 and 431 are shown symbolically in FIG. 5F-1.

[0361] 5F-1-5F-3 show a rectifier 400vr2 in which a dielectric tube 420a is housed in each bus bar and heat channel (not shown). The heat sinks 522 are thermally connected but electrically isolated by the commonly housed tube 420a. In alternative versions of the rectifier 400vr2, tubes other than 420a, such as tube 420b, may be housed in the channels. The phase bus bars 520 are thermally connected to each other and electrically isolated from each other by the commonly housed dielectric tube 420a.

[0362] The rectifier 400vr2 may include a driver PCB 521 having a driver 306 electrically connected to and controlling each switch 304 via a respective connector lead 288. Only connector leads 288gH and 288gL for phases c and a are shown in FIGS. 5F-2 and 5F-3. The rectifier 400vr2 may include a control PCB having an MCU in data communication with the driver 306, current sensor I_Sense, voltage sensor V_Sense, and other components mounted on the driver PCB 521. A connector (e.g., a flexible PCB, not shown) may facilitate data communication.

[0363] The driver PCB 521 includes a voltage sensor V_Sense in data communication with each packaged switch 247d via a respective pair of connector leads 288ds and 288dc (not shown). Exemplary phase bus bar leads 465a and 465c extend laterally between first and second ends. The first ends of the phase bus bar leads 465a and 465c are electrically connected to the phase bus bars 520a and 520c, respectively, and the second ends are electrically connected to the AC power sources φa and φc, respectively. The phase bus bar leads 465a and 465c extend through respective openings in the PCB 521. The current sensors I_Sense-a and I_Sense-c measure the current flowing through the phase bus bar connectors 465a and 465c, respectively. I_Sense-a and I_Sense-c may include respective openings through which the phase bus bar connectors 465a and 465c, respectively, extend. 5F-2 and 5F-3 show the voltage sensor V_Sense, PMIC, current sensor I_Sense, driver 306, and phase bus bar leads 465 for phases a and c, respectively. For phase b, the voltage sensor V_Sense, current sensor I_Sense, PMIC, driver 306, and phase bus bar leads 465 are mounted on or extend through PCB 521.

[0364] The control PCB for rectifier 400vr2 may include a PLL and other components for synchronizing the control of switch 304 to the frequency of the three-phase AC input voltage provided by AC power sources φa-φc. Additional components may be added for power factor correction.

[0365] All of the tubes 420, such as the tubes 420a in FIG. 5F-1, housed in all of the bus bars and heat sinks may be substantially the same length. Each tube 420a has a first end and a second end. The first ends of all of the tubes 420a may be in fluid communication with a first manifold, and the second ends of all of the tubes 420a may be in fluid communication with a second manifold.

[0366] Inverter 460fb 5G-1 and 5G-2 show the relevant components of an exemplary full-bridge inverter 460fb from the front and side, respectively. Some components shown in FIG. 5G-2 (i.e., driver PCB 461fb and control PCB 462fb) are not shown or are not fully shown in FIG. 5G-1, but are described below.

[0367] Inverter 460fb includes packaged switch 247d, although it will be understood that in alternative versions...

Claims

1. 1. An apparatus (e.g., the 460iT of FIG. 5A-25) comprising: a first bus bar (e.g., 412T in FIGS. 5A-25) having a first channel through which a fluid can flow to cool the first bus bar; A first device (e.g., 247dL of phase a in FIG. 5A-25, 247d of FIG. 2D-1, 247dA of FIG. 3A, 247dB of FIG. 3B), The first case (e.g., 248d in FIG. 2D-1, 248dA in FIG. 3A, and 248dB in FIG. 3B) a first metal structure (e.g., 360 of 247dL of phase a in FIGS. 5A-25, 360 of FIGS. 3A or 3B, 360 of FIGS. 4A-5) having a first surface and a second surface (e.g., 362 and 230 of FIGS. 4A-5), wherein the first surface and the second surface of the first metal structure are electrically connected, substantially flat, and opposite each other; a first metal element (e.g., 372 of 247dL of phase a of FIGS. 5A-25, 372 of FIGS. 3A or 3B, 360 of FIGS. 4A-5) having a first surface and a second surface (e.g., 344 and 375 of FIGS. 4A-5), wherein the first and second surfaces of the first metal element are electrically connected, substantially flat, and opposed to each other; a first metal pedestal (e.g., 1104 in FIGS. 4A-5) having a first surface and a second surface, the first surface and the second surface of the first metal pedestal being electrically connected, substantially flat, and facing each other, and the first surface of the first metal pedestal being sintered to the second surface of the first metal element; a first transistor (e.g., the MOSFET of FIG. 3A , the IGBT of FIG. 3B , or T3 of FIGS. 4A-5 ) having a first terminal and a second terminal, wherein the first transistor transmits a current of 1 ampere or more between the first terminal and the second terminal when in operation, the first terminal and the second terminal having a first surface and a second surface, respectively, the first surface and the second surface of the first terminal and the second terminal being substantially planar and facing each other; a first opening (e.g., 247d in FIG. 2D-1) through the first case; a first device having Equipped with the second surface of the first metal structure is electrically and thermally connected to the first bus bar; the first and second surfaces of the first and second terminals are sintered to the first and second surfaces of the first metal structure and the first metal base, respectively.

2. The device of claim 1 , further comprising a first tube (eg, 420 a in FIGS. 5A-25) housed within the first channel.

3. The device of claim 2 , wherein the first case has a second opening (eg, 247 d in FIG. 2D-2 ).

4. 4. The apparatus of claim 3, further comprising a second bus bar (e.g., 418Ta in FIGS. 5A-25) thermally and electrically connected to the first surface of the first metal element, the second bus bar having a second channel through which fluid can flow through the second bus bar.

5. a third bus bar (e.g., 417T in FIG. 5A-25), the third bus bar having a third channel through which fluid can flow through the third bus bar; A second device (e.g., 247 dH in phase a of FIG. 5A-25) The second case, a second metal structure (e.g., 360° of 247 dH of phase a in FIGS. 5A-25) having a first surface and a second surface, wherein the first surface and the second surface of the second metal structure are electrically connected, substantially flat, and opposite each other; a second metal element (e.g., 372 of 247dH of phase a in FIG. 5A-25) having a first surface and a second surface, wherein the first surface and the second surface of the second metal element are electrically connected, substantially flat, and facing each other; a second metal pedestal having a first surface and a second surface, the first surface and the second surface of the second metal pedestal being electrically connected, substantially flat, and facing each other, and the first surface of the second metal pedestal being sintered to the second surface of the second metal element; a second transistor having a third terminal and a fourth terminal, wherein the second transistor transmits a current of at least 1 ampere between the third terminal and the fourth terminal when in operation, the third terminal and the fourth terminal having a third surface and a fourth surface, respectively, the third surface and the fourth surface being substantially flat and facing each other; a first opening penetrating the second case; a second opening penetrating the second case; and and a second device having Further provided with the third and fourth surfaces are sintered to the first and second surfaces of the second metal structure and the second metal base, respectively; the second surface of the second metal structure is electrically and thermally connected to the second bus bar; The apparatus of claim 4 , wherein the first surface of the second metallic element is thermally and electrically connected to the third bus bar.

6. a capacitor (e.g., 403T-2 in FIG. 5A-24) having a first electrode and a second electrode; 6. The apparatus of claim 5, wherein the first electrode and second electrode are thermally and electrically connected to respective flat surfaces of the first busbar and third busbar.

7. a fourth bus bar (e.g., 418Tb in FIGS. 5A-25), the fourth bus bar having a fourth channel through which fluid can flow through the fourth bus bar; A third device (e.g., 247dL in phase b of FIG. 5A-25), The third case, a third metal structure (e.g., 372 of 247dL of phase b in FIG. 5A-25) having a first surface and a second surface, wherein the first surface and the second surface of the third metal structure are electrically connected, substantially flat, and opposed to each other; a third metal element having a first surface and a second surface, the first surface and the second surface of the third metal element being electrically connected, substantially planar, and facing each other; a third metal pedestal having a first surface and a second surface, the first surface and the second surface of the third metal pedestal being electrically connected, substantially flat, and facing each other, and the first surface of the third metal pedestal being sintered to the second surface of the third metal element; a third transistor having a fifth terminal and a sixth terminal, wherein a current of 1 ampere or more is transmitted between the fifth terminal and the sixth terminal when the third transistor is in operation, the fifth terminal and the sixth terminal having a fifth surface and a sixth surface, respectively, the fifth surface and the sixth surface being substantially flat and facing each other; a first opening extending through the third case; a second opening extending through the third case; and and a third device having Further provided with the fifth and sixth surfaces are sintered to the first and second surfaces of the third metal structure and the third metal pedestal, respectively; the second surface of the third metal structure is electrically and thermally connected to the first bus bar; the first surface of the third metal element is electrically and thermally connected to the fourth bus bar; The apparatus of claim 5 , wherein the fourth bus bar is thermally connected to and electrically isolated from the second bus bar.

8. A fourth device (e.g., 247 dH in phase b of FIG. 5A-25), The fourth case, a fourth metal structure (e.g., 360 of 247dH of phase b in FIG. 5A-25) having a first surface and a second surface, wherein the first surface and the second surface of the fourth metal structure are electrically connected, substantially flat, and opposite each other; a fourth metal element (e.g., 372 at 247dH in phase b of FIG. 5A-25) having a first surface and a second surface, wherein the first surface and the second surface of the fourth metal element are electrically connected, substantially flat, and facing each other; a fourth metal pedestal having a first surface and a second surface, the first surface and the second surface of the fourth metal pedestal being electrically connected, substantially flat, and facing each other, and the first surface of the fourth metal pedestal being sintered to the second surface of the fourth metal element; a fourth transistor having a seventh terminal and an eighth terminal, wherein a current of 1 ampere or more is transmitted between the seventh terminal and the eighth terminal when the fourth transistor is in operation, the seventh terminal and the eighth terminal having a seventh surface and an eighth surface, respectively, the seventh surface and the eighth surface being substantially flat and facing each other; a first opening that penetrates the fourth case; a second opening extending through the fourth case; and a fourth device having: the seventh and eighth surfaces are sintered to the first and second surfaces of the fourth metal structure and the fourth metal pedestal, respectively; the second surface of the fourth metal structure is electrically and thermally connected to the fourth bus bar; The apparatus of claim 7 , wherein the first surface of the fourth metallic element is electrically and thermally connected to the third bus bar.

9. a fifth bus bar (e.g., 418Tc in FIGS. 5A-25), the fifth bus bar having a fifth channel through which fluid can flow through the fifth bus bar; A fifth device (e.g., 247dL in phase c of FIG. 5A-25), The fifth case, a fifth metal structure (e.g., 360 of 247dL of phase c in FIG. 5A-25) having a first surface and a second surface, wherein the first surface and the second surface of the fifth metal structure are electrically connected, substantially flat, and opposite each other; a fifth metal element (e.g., 372 of 247dL of phase c in FIG. 5A-25) having a first surface and a second surface, wherein the first surface and the second surface of the fifth metal element are electrically connected, substantially flat, and opposed to each other; a fifth metal pedestal having a first surface and a second surface, the first surface and the second surface of the fifth metal pedestal being electrically connected, substantially flat, and facing each other, and the first surface of the fifth metal pedestal being sintered to the second surface of the fifth metal element; a fifth transistor having a ninth terminal and a tenth terminal, wherein the fifth transistor transmits a current of 1 ampere or more between the ninth terminal and the tenth terminal when the fifth transistor is in operation, the ninth terminal and the tenth terminal having a ninth surface and a tenth surface, respectively, the ninth surface and the tenth surface being substantially flat and facing each other; a first opening that penetrates the fifth case; a second opening extending through the fifth case; a fifth device having Further provided with the ninth and tenth surfaces are sintered to the first and second surfaces of the fifth metal structure and the fifth metal pedestal, respectively; the second surface of the fifth metal structure is electrically and thermally connected to the first bus bar; the first surface of the fifth metal element is electrically and thermally connected to the fifth bus bar; The apparatus of claim 8 , wherein the fifth bus bar is thermally connected to and electrically isolated from the second and fourth bus bars.

10. A sixth device (e.g., 247 dH in phase c of FIG. 5A-25), The sixth case, a sixth metal structure (e.g., 360 of 247dH of phase c in FIG. 5A-25) having a first surface and a second surface, wherein the first surface and the second surface of the sixth metal structure are electrically connected, substantially flat, and opposite each other; a sixth metal element (e.g., 372 at 247dH of phase c in FIG. 5A-25) having a first surface and a second surface, wherein the first surface and the second surface of the sixth metal element are electrically connected, substantially flat, and face each other; a sixth metal pedestal having a first surface and a second surface, the first surface and the second surface of the sixth metal pedestal being electrically connected, substantially flat, and facing each other, and the first surface of the sixth metal pedestal being sintered to the second surface of the sixth metal element; a sixth transistor having an eleventh terminal and a twelfth terminal, wherein a current of 1 ampere or more is transmitted between the eleventh terminal and the twelfth terminal when the sixth transistor is in operation, the eleventh terminal and the twelfth terminal having an eleventh surface and a twelfth surface, respectively, the eleventh surface and the twelfth surface being substantially flat and facing each other; a first opening that penetrates the sixth case; a second opening extending through the sixth case; and a sixth device having: the eleventh and twelfth surfaces are sintered to the first and second surfaces of the sixth metal structure and the sixth metal pedestal, respectively; the second surface of the sixth metal structure is electrically and thermally connected to the fifth bus bar; 10. The apparatus of claim 9, wherein the first surface of the sixth metallic element is electrically and thermally connected to the third bus bar.

11. 10. The apparatus of claim 1, further comprising a dielectric element (e.g., 420a) that electrically insulates the first bus bar from fluid flowing through the first channel of the first bus bar.

12. 10. The apparatus of claim 9, further comprising a second tube (e.g., 420a common to bus bars 418Ta, 418Tb, and 418Tc in FIGS. 5A-25) housed within the second channel, fourth channel, and fifth channel of the second bus bar, fourth bus bar, and fifth bus bar, respectively.

13. 1. A method comprising: Sintering the first surface of the first terminal of the first transistor to the first surface of the first metal structure (e.g., paragraph [0294]); Sintering the second surface of the second terminal of the first transistor to the second surface of the first metal base (e.g., paragraph [0298]); Sintering the second surface of the first metal base to the second surface of the first metal element (e.g., paragraph [0304]); Including, the first metal structure (e.g., 360 of 247dL of phase a in FIGS. 5A-25, 360 of FIGS. 3A or 3B, 360 of FIGS. 4A-5) has a second surface, and the first and second surfaces of the first metal structure are electrically connected, substantially flat, and face each other; the first metal element (e.g., 372 of 247dL of phase a in FIGS. 5A-25, 372 of FIGS. 3A or 3B, 360 of FIGS. 4A-5) has a second surface, and the first and second surfaces of the first metal element are electrically connected, substantially flat, and face each other; the first and second surfaces of the first metal base are electrically connected, substantially flat, and opposed to each other; the first transistor is operable to transmit a current of at least 1 ampere between the first terminal and the second terminal, the first surface and the second surface of the first terminal and the second terminal being substantially flat and facing each other; thermally and electrically connecting the second surface of the first metal structure to a surface of a first bus bar having a first channel through which a fluid can flow to cool the first bus bar; A method comprising:

14. The method of claim 13 , further comprising thermally and electrically attaching the first surface of the first metallic element to a surface of a second bus bar.

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