Determining Latency at the Physical Layer

Abstract

One or more examples generally relate to a method that includes recording a value representing the duration that a frame traveling towards a cable or MAC travels between a predetermined reference plane of a PHY-MAC interface and a predetermined reference plane of a PHY-able interface, and asserting an indication that the recorded value is available to be read from the PHY.

Description

[Technical Field]

[0001] (Priority Claim) This application claims the benefit of the filing date of Chinese Patent Application No. CN202310121644.5, filed on February 2, 2023, the disclosure of which is incorporated herein by reference in its entirety.

[0002] (Technical field) One or more examples generally relate to determining latency at a physical layer, including physical layers with variable or unknown latency. One or more examples generally relate to determining latency at a 10SPE physical layer. One or more examples generally relate to reporting determined latency at a physical layer to an upper layer device, such as a media access controller, and optionally utilizing such reported latency to synchronize a clock of the media access controller. [Background technology]

[0003] Interconnects are widely used to facilitate communication between devices, subsystems, and systems of a network. Generally speaking, electrical signals are transmitted over a physical medium (such as, without limitation, a bus, coaxial cable, or twisted pair—commonly referred to simply as a "line" or a "bus") by devices coupled to that physical medium.

[0004] According to the Open Systems Interconnection model (OSI model), Ethernet-based computer networking technology uses baseband transmission (i.e., electrical signals are discrete electrical pulses) to transport data packets and ultimately frames communicated between network devices. According to the OSI model, specialized circuitry called a physical layer (PHY) device or controller is used to interface between the analog domain of the line and the digital domain of the data link layer (also referred to herein simply as the "link layer"), which operates according to packet signaling. While the data link layer may include one or more sublayers, in Ethernet-based computer networking, the data link layer typically includes at least a media access control (MAC) layer, which provides control abstraction of the physical layer. As a non-limiting example, when transmitting data to another device on the network, the MAC controller may prepare frames for the physical media, add error correction elements, and implement collision avoidance. Additionally, when receiving data from another device, the MAC controller may ensure the integrity of the received data and prepare frames for higher layers.

[0005] There are various network topologies that implement the physical layer and link layer (and may include, without limitation, other layers). The Peripheral Component Interconnect (PCI) standard and the Parallel Advanced Technology Attachment (Parallel ATA), both of which have been in use since the early 1990s, can implement a multi-drop bus topology. The trend since the early 2000s has been to use a point-to-point bus topology; for example, the PCI Express standard (PCIe) and the Serial ATA (SATA) standard implement a point-to-point topology.

[0006] A typical point-to-point bus topology may implement a line between each device (e.g., without limitation, a dedicated point-to-point) or a line between a device and a switch (e.g., without limitation, a switched point-to-point). In contrast, in a multi-drop bus topology, the physical transmission medium is a shared bus, and each network device is coupled to the shared bus via circuitry selected based on, for example, the type of physical media (e.g., without limitation, coaxial or twisted pair).

[0007] Point-to-point bus topologies, such as dedicated point-to-point bus topologies or switched point-to-point topologies, require more wires and more expensive materials than multi-drop topologies, due in part to the larger number of links between devices. In certain applications, such as automobiles, physical constraints may exist that make it difficult to directly connect devices, and thus topologies that do not require direct connections or the same number of direct connections within a network or sub-network (e.g., without limitation, multi-drop topologies) may be less susceptible to or hindered by such constraints.

[0008] Without limitation, devices in the baseband network of a multi-drop network share the same physical transmission medium and typically use the entire bandwidth of that medium for transmission (i.e., the digital signals used in baseband transmission occupy the entire bandwidth of the medium). As a result, only one device in the baseband network can transmit at a given moment. Therefore, medium access control methods may be used to handle contention for such a shared transmission medium. [Brief explanation of the drawings]

[0009] To easily identify the discussion of any particular element or function, the most significant digit(s) of a reference number refers to the figure number in which that element is first introduced. [Figure 1] 1 illustrates an apparatus for determining latency in a 10SPE PHY, according to one or more examples. [Figure 2] 1 illustrates an apparatus for determining latency in a 10SPE PHY, according to one or more examples. [Figure 3A] 1 illustrates an apparatus for detecting the presence of a frame in a predetermined reference plane of a PHY-MAC interface and in a predetermined reference plane of a PHY-cable interface, according to one or more examples. [Figure 3B] 1 illustrates aspects of the subject matter according to one embodiment. [Figure 4] FIG. 10 is a timing diagram illustrating the transfer of frames, according to one or more examples. [Figure 5] 1 is a flow diagram illustrating a process for determining latency in a 10SPE PHY, according to one or more examples. [Figure 6] 1 is a flow diagram illustrating a process for determining latency in a 10SPE PHY, according to one or more examples. [Figure 7] 1 is a flow diagram illustrating a process for determining latency for a 10SPE PHY, according to one or more examples. [Figure 8A] 1 is a flow diagram illustrating a process for determining the presence of a frame in a given reference plane of a 10SPE PHY, according to one or more examples. [Figure 8B] 1 is a flow diagram illustrating a process for determining the presence of a frame in a given reference plane of a 10SPE PHY, according to one or more examples. [Figure 9] FIG. 10 is a flow diagram illustrating a clock synchronization process, according to one or more examples. [Figure 10] FIG. 10 is a flow diagram illustrating a process for canceling PHY latency from a timestamp, according to one or more examples. [Figure 11]FIG. 1 is a block diagram of circuitry that, in some embodiments, can be used to implement various functions, operations, acts, processes, and / or methods disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and which show, by way of illustration, specific examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable those skilled in the art to practice the disclosure. However, other examples may be utilized, and changes in structure, materials, and processes may be made without departing from the scope of the disclosure.

[0011] The illustrative diagrams presented herein are not meant to be actual illustrations of any particular method, system, device, or structure, but are merely idealized representations used to explain embodiments of the present disclosure. The drawings presented herein are not necessarily drawn to scale. Similar structures or components in various drawings may retain the same or similar numbering for the convenience of the reader. However, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0012] The following description may include examples to aid in enabling those skilled in the art to practice the disclosed embodiments. The use of the terms "exemplary," "example," and "for example" means that the associated description is illustrative, and the scope of the disclosure is intended to encompass examples and legal equivalents. The use of such terms is not intended to limit the examples or the scope of the disclosure to the specified components, steps, features, functions, etc.

[0013] It will be readily understood that the components of the embodiments, as generally described herein and illustrated in the figures, could be arranged and designed in a wide variety of different configurations. Thus, the following description of various embodiments is not intended to limit the scope of the disclosure, but is merely representative of various embodiments. While various aspects of the embodiments may be presented in figures, the figures are not necessarily drawn to scale unless specifically indicated.

[0014] Furthermore, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, circuitry, and functions may be shown in block diagram form so as not to obscure the present disclosure in unnecessary detail. Conversely, the specific implementations shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Additionally, the block definitions and partitioning of logic among various blocks are illustrative of specific implementations. It will be readily apparent to one skilled in the art that the present disclosure can be implemented with numerous other partitioning solutions. For the most part, details regarding timing considerations and the like have been omitted; such details are not necessary to obtain a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0015] Those skilled in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. Some figures may illustrate a signal as a single signal for clarity of presentation and explanation. Those skilled in the art will understand that a signal may represent a bus of signals, which may have various bit widths, and that the present disclosure may be implemented with any number of data signals, including a single data signal.

[0016] The various illustrative logic blocks, modules, circuitry, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, although the processor may alternatively be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer that includes a processor is considered a special-purpose computer, and the general-purpose computer is configured to execute computing instructions (e.g., software code) associated with embodiments of the present disclosure.

[0017] The embodiments may be described in terms of a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. While a flowchart may describe operational acts as a sequential process, many of these acts may occur in another sequence, in parallel, or substantially simultaneously. Additionally, the order of acts may be rearranged. A process may correspond to, but is not limited to, a method, a thread, a function, a procedure, a subroutine, or a subprogram. Further, methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another.

[0018] Any reference to elements herein using designations such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitation is expressly stated. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, reference to a first element and a second element does not imply that only two elements may be used or that the first element must precede the second element in any manner. Additionally, unless otherwise specified, a set of elements may include one or more elements.

[0019] As used herein, any relative terms such as "over," "under," "on," "underlying," "upper," "lower," etc. are used for clarity and convenience in understanding the disclosure and the accompanying drawings, and are not intended to imply or depend on any particular preference, orientation, or order unless the context clearly indicates otherwise.

[0020] As used herein, the term "substantially" when referring to a given parameter, characteristic, or condition means and includes the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition is met with slight variations, such as, for example, within acceptable manufacturing tolerances. As an example, depending on the particular parameter, characteristic, or condition that is substantially met, the parameter, characteristic, or condition may be at least 90% met, at least 95% met, or even at least 99% met.

[0021] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, the elements may be in direct physical or electrical contact, or there may be intervening elements or layers. In contrast, when an element is described as being "directly coupled" to another element, there are no intervening elements or layers present. The terms "on" and "connected" may be used interchangeably with the term "coupled" herein and have the same meaning unless expressly stated otherwise or unless the context otherwise indicates otherwise to one of ordinary skill in the art.

[0022] As used herein, the terms "assert" and "deassert," and their derivatives, when used with respect to a connection (e.g., without limitation, a physical or logical wire, terminal, pad, contact, circuit, pin, combination thereof, or any subcombination thereof), refer to asserting or deasserting, respectively, a signal associated with the connection (e.g., without limitation, a signal specifically assigned to the connection or a signal to which the connection is specifically assigned).

[0023] Vehicles, such as automobiles, trucks, buses, ships, and / or aircraft, may include a vehicle communication network. The complexity of the vehicle communication network may vary depending on the number of electronic devices in the network. For example, an advanced vehicle communication network may include various control modules for engine control, transmission control, safety control (e.g., without limitation, anti-lock brakes), and emissions control, as non-limiting examples. To support these control modules, the automotive industry relies on a variety of communication protocols.

[0024] 10SPE (i.e., 10 Mbps Single Pair Ethernet, also known as "10BASE-T1S") is a network technology specified by the Institute of Electrical and Electronics Engineers (IEEE) in IEEE 802.3cg™. 10SPE can be used, for example, but not limited to, to provide collision-free, deterministic transmission over multi-drop networks or shared transmission media.

[0025] The 1588 Precision Time Protocol (PTP) is a network technology used to synchronize clocks in computer networks defined by IEEE 1588.

[0026] In 10SPE, 1588 PTP, conceptually, utilizes the Media Dependent Interface (MDI) as a reference for generating timestamps. A reference plane is a timing plane associated with the MDI, and 1588 PTP timestamps are intended to represent the time at which a given portion of a frame crosses the MDI. In 10SPE, 1588 PTP is typically implemented in a MAC, which observes the time at which a frame start delimiter (SFD) inserted into a frame by the transmitting MAC (which may be the same or a different MAC, depending on whether the frame with the SFD is a receive or transmit frame) crosses the Media Independent Interface (MII), and then adds or subtracts a value representing a known fixed latency (e.g., from the MII to the reference plane closer to the MDI, or from the reference plane closer to the MDI to the MII, as the case may be) to determine when the SFD crossed the MDI.

[0027] Some PHYs exhibit unknown or variable latency. As a non-limiting example, latency may be variable (e.g., without limitation, potentially varying from frame to frame) in PHYs that include variable delay and variable depth buffers to implement physical layer collision avoidance (PLCA).

[0028] The inventors of the present disclosure understand that it may be desirable for a PHY to determine latency or information related to determining latency (collectively "latency information"), including, without limitation, on a frame-by-frame basis. It may be desirable for such a PHY to report or otherwise make the latency information available to a MAC. As a non-limiting example, a MAC may utilize such information to determine the time it takes for a data frame to traverse a PHY-cable interface, although utilizing such information for other purposes is not beyond the scope of this disclosure.

[0029] As used herein, the term "frame" means an "Ethernet frame," including, without limitation, those defined in IEEE 802.3.

[0030] 1 is a diagram illustrating an apparatus 100 for determining (and optionally reporting) latency in a 10SPE PHY, according to one or more examples. In one or more examples, apparatus 100 may be a PHY or a portion of a PHY, such as, without limitation, a 10SPE PHY, and may also be referred to as "PHY 100." In one or more examples, apparatus 100 may determine (and optionally report) latency for frames traveling from a PHY-MAC interface to a PHY cable interface, frames traveling from a PHY cable interface to a PHY-MAC interface, or both.

[0031] In one or more examples, device 100 includes a PHY side of PHY-cable interface 106 (also referred to herein as “PHY-cable interface 106”), a PHY side of a PHY-MAC interface (also referred to herein as “PHY-MAC interface 110”), a data path 120, logic circuitry 104, and an internal clock 122.

[0032] In one or more examples, the predetermined reference plane 108 is that of the PHY-cable interface 106, and the predetermined reference plane 112 is that of the PHY-MAC interface 110. Non-limiting examples of the predetermined reference plane 108 of the PHY-cable interface 106 include a predetermined reference plane 108 defined at a location along the data path 120 or at the PHY-cable interface 106. Non-limiting examples of the predetermined reference plane 112 of the PHY-MAC interface 110 include a predetermined reference plane 112 defined at a location along the data path 120 or at the PHY-MAC interface 110.

[0033] In one or more examples, the predetermined reference planes 108, 112 may be set at any location along the PHY's data path 120, respectively, provided that a predetermined pattern known to correspond to a particular symbol or bit can be reliably detected and the location where the particular symbol or bit is observed is a known, fixed latency from the predetermined reference plane, such as a known, fixed latency from a connection between the PHY and a cable (e.g., without limitation, a connection between the PHY) or a known, fixed latency from a connection between the PHY and a MAC. Thus, or in multiple examples, the location where the particular symbol or bit is observed may be the same or a different location from the location where the predetermined reference plane is defined. In various examples, the location where the particular symbol or bit is observed may be referred to herein as the "observed reference plane," and a location corresponding to the observed reference plane plus or minus a known, fixed latency may be understood to be the "predetermined reference plane."

[0034] In one or more examples, the exhibited pattern may be compared to a predetermined pattern to detect symbols or bits. Detecting that a frame exhibits the predetermined pattern is used as an indication that the frame resides in an associated predetermined reference plane, such as predetermined reference plane 108 or predetermined reference plane 112, or a respective observed reference plane.

[0035] The logic circuit 104 detects frames traveling on the data path 120 and calculates a duration value 118 representing the duration the frame travels between a predetermined reference plane 108 defined at the PHY-cable interface 106 and a predetermined reference plane 112 defined at the PHY-MAC interface 110.

[0036] In one or more examples, the logic circuit 104 may utilize the internal clock 122 of the device 100 to determine the duration (e.g., without limitation, counting clock cycles) that a frame traveling on the data path 120 travels between the predetermined reference plane 108 and the predetermined reference plane 112.

[0037] In one or more examples, the internal clock 122 may be different from the clock of the PHY-MAC interface 110 (e.g., without limitation, a different clock signal or clock source), and the resolution of the internal clock 122 may be finer than the resolution of the clock of the PHY-MAC interface 110 (e.g., without limitation, the MII clock or the RMII clock). In such cases, a clock cycle count or timestamp generated based on the internal clock 122 may be closer to the actual time at which a frame crosses a given reference plane 112 than a clock cycle count or timestamp based on the internal clock of the PHY-MAC interface 110.

[0038] The duration value 118 calculated by the logic circuitry 104 may be stored in the device 100 or provided to a downstream user via the PHY-MAC interface 110. Once stored, the duration value 118 is accessible to be read via the PHY-MAC interface 110 by a downstream user, which may be, as a non-limiting example, a MAC. The device 100, and more specifically the logic circuitry 104, may provide notification 116 that the duration value 118 is ready to be read. The notification 116 may be provided via a signal path that includes the PHY-MAC interface 110, as shown in the non-limiting example illustrated in FIG. 1, or that does not include the PHY-MAC interface 110 (e.g., without limitation, via an interrupt connection that does not include the PHY-MAC interface 110).

[0039] 2 illustrates an apparatus 200 for determining latency of a 10SPE PHY, according to one or more examples. The apparatus 200 is a non-limiting example of the logic circuit 104 shown in FIG.

[0040] In one or more examples, apparatus 200 includes counting logic 202 for counting and storing a number of clock cycles (i.e., as counted number of clock cycles 204) at least in part in response to assertion of clock signal 206 and indication 208 and indication 210, respectively. Indication 208 may be an indication of the presence of a frame at a predetermined reference plane of the PHY-MAC interface (e.g., without limitation, at predetermined reference plane 112 defined at PHY-MAC interface 110). Indication 210 may be an indication of the presence of a frame at a predetermined reference plane of the PHY-cable interface (e.g., without limitation, at predetermined reference plane 108 defined at PHY-cable interface 106).

[0041] When determining the latency of a frame traveling from the PHY-MAC interface 110 to the PHY-cable interface 106, the counting logic 202 may start counting clock cycles of the clock signal 206 (e.g., without limitation, start incrementing the counted number of clock cycles 204) at least in part in response to the asserted indication 208, and may stop counting clock cycles of the clock signal 206 (e.g., without limitation, stop incrementing the counted number of clock cycles 204) at least in part in response to the asserted indication 210.

[0042] When determining the latency of a frame traveling from the PHY-cable interface 106 to the PHY-MAC interface 110, the counting logic 202 may start counting clock cycles of the clock signal 206 (e.g., without limitation, start incrementing the counted number of clock cycles 204) at least in part in response to the asserted indication 210, and may stop counting clock cycles of the clock signal 206 (e.g., without limitation, stop incrementing the counted number of clock cycles 204) at least in part in response to the asserted indication 208.

[0043] In one or more examples, the counting logic 202 may output a value of the counted number of clock cycles 204, which represents the latency. The value output by the counting logic 202 may be used to directly set the duration value 118 (i.e., the duration value 118 is set equal to the value output by the counting logic 202) or may be used to indirectly set the duration value 118 (i.e., the duration value 118 is set based at least in part on the value output by the counting logic 202, for example, without limitation, in combination with other values ​​or adjustments).

[0044] In an indirect example, the counted number 204 of clock cycles output by the counting logic 202 may be combined with a predetermined value 226 by optional adjustment logic 224. The predetermined value 226 may represent a difference (e.g., without limitation, in clock cycles or bits) between the portion of the frame exhibiting the predetermined pattern (the “detectable portion of the frame”) and the portion of the frame of interest. In some cases, the portion of the frame of interest may not be reasonably detectable by the device 200. As a non-limiting example, the SFD portion of the frame's preamble is typically not detectable by the device 200 because the bits of the SFD portion are scrambled. Other bits of the preamble, i.e., bits of a stream start delimiter (SSD), for example, are not scrambled. The SSD is located a known number of bits from the SFD. Thus, the predetermined value 226 may represent the distance between the SSD and the SFD in bits (i.e., the number of clock cycles between the SSD and the SFD, or the number of bits at the respective bit rates).

[0045] The optional adjustment logic 224 can add or subtract a predetermined value 226 to the counted number of clock cycles 204 depending on whether the detectable portion of the frame is located before or after the portion of the frame of interest. As a non-limiting example where SSD occurs before SFD, in a receive example where the value output by the device 200 is expected to represent the latency of a frame traveling from the PHY-cable interface 106 to the PHY-MAC interface 110, the optional adjustment logic 224 subtracts a predetermined value 226 from the counted number of clock cycles 204. In a transmit example where the value output by the device 200 is expected to represent the latency of a frame traveling from the PHY-MAC interface 110 to the PHY-cable interface 106, the optional adjustment logic 224 adds a predetermined value 226 to the counted number of clock cycles 204.

[0046] In one or more examples, the counting logic 202 may automatically (e.g., counted number of clock cycles 204 may be directly coupled to duration value 118 via optional adjusting logic 224 to adjust according to a predetermined value) or selectively set the value of duration value 118. In examples in which duration value 118 is selectively set, device 200 may include optional gating circuitry 218 coupled to the output of counting logic 202 or, if provided, to the output of optional adjusting logic 224 to selectively enable recording of counted number of clock cycles 204 as duration value 118. Gating circuitry 218 may include message type detection logic 214 coupled to gate 212 (e.g., without limitation, with asserted indication 216 coupled to an enable input of gate 212). Message type detection logic 214 and gate 212 may be coupled to propagate counted number of clock cycles 204 at least in part in response to detecting a frame 222 corresponding to a predetermined frame type.

[0047] As a non-limiting example, when different types of frames travel through data path 220, the latency of some frame types may be of interest (e.g., 1588 PTP frames such as, without limitation, sync frames, follow-up frames, delay request frames, or delay response frames), while the latency of other frame types may not be of interest. Message type detection logic 214 may be, or may include, as a non-limiting example, a pattern matcher for detecting the frame type of a frame based at least in part on the frame 222 exhibiting a predetermined pattern of bits or symbols (e.g., without limitation, bits or symbols in a field of frame 222 corresponding to that type), and in response, asserting an indication 216. An enable input of gate 212 may be coupled to receive asserted indication 216, such that, when gate 212 receives asserted indication 216, gate 212 propagates the signal for the counted number 204 of clock cycles. Gate 212 is disabled when indication 216 is deasserted, and when disabled, gate 212, and more generally gating circuit 218, does not propagate counted number 204 of clock cycles.

[0048] FIG. 3A is a diagram illustrating an apparatus 300a for detecting the presence of a frame at a predetermined reference plane 112 of a PHY-MAC interface 110 and at a predetermined reference plane 108 of a PHY-cable interface 106, according to one or more examples.

[0049] In one or more examples, the apparatus 300a includes a first pattern matcher 304 and a second pattern matcher 316, each coupled to observe a frame 310 in the data path 302. In one or more examples, the first pattern matcher 304 conforms to a media dependent interface (MDI) that operates as a PHY-cable interface, but may be coupled to a portion of the receive data path 302 before the physical coding sublayer (PCS), which is responsible in the PHY for encoding, decoding, scrambling, descrambling, alignment market insertion and removal, and block and symbol deskew, as a non-limiting example. The second pattern matcher 316 may be coupled to a portion of the data path 302 that includes a connection with or within the PHY-MAC interface 110.

[0050] The first pattern matcher 304 detects that the pattern exhibited by the bits 312 of the frame 310 (i.e., the exhibited pattern 308) corresponds to the predetermined pattern 306, and, at least in part, in response thereto, asserts an indication 314 indicating the detection of the predetermined pattern 306. The indication 314 is a non-limiting example of the indication 210, which is an indication of the presence of a frame in the predetermined reference plane 108 of the PHY-cable interface 106.

[0051] The second pattern matcher 316 detects that the pattern exhibited by the bits 312 of the frame 310 (i.e., the exhibited pattern 308) corresponds to the predetermined pattern 306, and, at least in part, responsively asserts an indication 318 indicating the detection of the predetermined pattern 306. The indication 318 is a non-limiting example of the indication 208, which is an indication of the presence of a frame in the predetermined reference plane 112 of the PHY-MAC interface 110.

[0052] In one or more examples, the predetermined pattern 306 is a pattern of an SSD of an Ethernet frame. The SSD is inserted into the preamble of the Ethernet frame by the transmitting PHY. In one or more examples, detection of the SSD may be used as an indication of the SFD or preamble of the Ethernet frame more generally. The number of bits between the SSD and SFD of the Ethernet frame is generally known or specified.

[0053] FIG. 3B is a diagram illustrating an apparatus 300b for detecting the presence of a frame at a predetermined reference plane 112 of a PHY-MAC interface 110 and at a predetermined reference plane 108 of a PHY-cable interface 106, according to one or more examples.

[0054] While apparatus 300a includes two pattern matchers (first pattern matcher 304 and second pattern matcher 316) and associated circuitry, apparatus 300b includes the first pattern matcher 304 and associated circuitry from apparatus 300a and a signal detector 320 coupled to a first connection 322 and a second connection 324 of a PHY-MAC interface, such as PHY-MAC interface 110. The coupled connections are generally connections for signals indicating the presence of a frame at PHY-MAC interface 110. In one or more examples, first connection 322 of PHY-MAC interface 110 may carry a signal indicating a transmit frame is present at PHY-MAC interface 110, and second connection 324 of PHY-MAC interface 110 may carry a signal indicating received data is present at PHY-MAC interface 110. As a non-limiting example, the first connection 322 may carry a "Transmit Enable" (TXEN) signal utilized by a Media Independent Interface (MII) that, when asserted, indicates the presence of frame data on the MII's transmit data connection and, when deasserted, indicates the absence of frame data on the MII's transmit data connection. As a non-limiting example, the second connection 324 may carry a "Receive Data Valid" (RXDV) signal utilized by the MII that, when asserted, indicates the presence of frame data on the MII's receive data connection and, when deasserted, indicates the absence of frame data on the MII's receive data connection. The signal detector 320 may assert the indication 318 in response to the assertion of a signal on the first connection 322 or the second connection 324, as the case may be.

[0055] 4 is a timing diagram illustrating the transfer 400 of a frame 408, according to one or more examples. FIG. 4 illustrates a specific, non-limiting example of the transfer of a frame 408 over time. At time T0, a crossing of a reference plane 402 by the frame 408 is detected, and at time T1, which occurs after time T0, a crossing of a reference plane 404 by the frame 408 is detected. A duration 406 represents the elapsed time between time T1 and time T0. As a non-limiting example, the duration 406 may be captured by the counting logic 202 and represented as a number or count of clock cycles of a clock signal 410 beginning at time T0 and ending at time T1, which is stored as the counted number of clock cycles 204.

[0056] FIG. 5 is a flow diagram illustrating a process 500 for determining and reporting latency in a 10SPE PHY, according to one or more examples.

[0057] In operation 502, process 500 records a value (e.g., without limitation, duration value 118) representing the duration (e.g., without limitation, duration value 406 of 118 of FIG. 4) that a frame (e.g., without limitation, frame 408 of FIG. 4) travels towards the cable as it travels between a predetermined reference plane of the PHY-MAC interface (e.g., without limitation, predetermined reference plane 112 of PHY-MAC interface 110 of FIG. 1 or reference plane 402 of FIG. 4) and a predetermined reference plane of the PHY-cable interface (e.g., without limitation, predetermined reference plane 108 of PHY-cable interface 106 of FIG. 1 or reference plane 404 of FIG. 4).

[0058] In operation 504, the process 500 asserts an indication (e.g., without limitation, notification 116) that a recorded value (e.g., without limitation, duration value 118) is available to be read.

[0059] 6 is a flow diagram illustrating a process 600 for determining the latency of a 10SPE PHY, in accordance with one or more examples. In one or more examples, some or all of the operations of process 600 may be performed by counting logic 202.

[0060] In operation 602, process 600 executes when the duration is the duration for a frame traveling towards the cable to travel from a predetermined reference plane of the PHY-MAC interface to a predetermined reference plane of the PHY-cable interface.

[0061] At operation 604, process 600 begins counting clock cycles (e.g., without limitation, in counting logic 202 of FIG. 2 ) at least in part in response to an asserted indication of the presence of a frame in a given reference plane of the PHY-MAC interface (e.g., without limitation, in response to indication 208 of FIG. 2 ).

[0062] At operation 606, process 600 stops counting clock cycles at least in part in response to an asserted indication of the presence of a frame in a given reference plane of the PHY-cable interface (e.g., without limitation, in response to indication 210 of FIG. 2).

[0063] At operation 608, process 600 optionally enables providing a value representing the counted number of clock cycles to the PHY in response to, at least in part, detecting (e.g., without limitation, via message type detection logic 214 of FIG. 2) that the frame type of the frame corresponds to a predetermined frame type.

[0064] In operation 610, the process 600 provides a value representing the counted number of clock cycles to the PHY.

[0065] 7 is a flow diagram illustrating a process 700 for determining the latency of a 10SPE PHY, in accordance with one or more examples. In one or more examples, some or all of the operations of process 700 may be performed by the counting logic 202.

[0066] In operation 702, process 700 executes when the duration is the duration for a frame to travel from a predetermined reference plane of the PHY-cable interface to a predetermined reference plane of the PHY-MAC interface.

[0067] At operation 704, process 700 begins counting clock cycles (e.g., without limitation, in counting logic 202 of FIG. 2 ) at least in part in response to an asserted indication of the presence of a frame in a given reference plane of the PHY-cable interface (e.g., without limitation, in response to indication 210 of FIG. 2 ).

[0068] At operation 706, process 700 stops counting clock cycles at least in part in response to an asserted indication of the presence of a frame in a given reference plane of the PHY-MAC interface (e.g., without limitation, in response to indication 208 of FIG. 2).

[0069] At operation 708, process 700 optionally enables providing a value representing the counted number of clock cycles to the PHY in response to, at least in part, detecting (e.g., without limitation, via message type detection logic 214 of FIG. 2) that the frame type of the frame corresponds to a predetermined frame type.

[0070] In operation 710, the process 700 provides a value representing the counted number of clock cycles to the PHY.

[0071] FIG. 8A is a flow diagram illustrating a process 800a for detecting the presence of a frame in a predetermined reference plane, according to one or more examples.

[0072] In operation 802, process 800a detects that a pattern (e.g., without limitation, presented pattern 308) presented by a bit of a frame (e.g., without limitation, bit 312 of frame 310) at a predetermined reference plane of the PHY-MAC interface corresponds to a predetermined pattern (e.g., without limitation, predetermined pattern 306).

[0073] In operation 804, the process 800a asserts a first indication of detection of a predetermined pattern (eg, without limitation, asserting indication 318).

[0074] In operation 806, optionally, the asserted first indication of the presence of a frame in a predetermined reference plane of the PHY-MAC interface comprises an asserted indication of the detection of a predetermined pattern.

[0075] At operation 808, process 800a further detects that a pattern (e.g., without limitation, presented pattern 308) presented by a bit of a frame (e.g., without limitation, bit 312 of frame 310) at a predetermined reference plane of the PHY-cable interface corresponds to a predetermined pattern (e.g., without limitation, predetermined pattern 306).

[0076] In operation 810, the process 800a asserts a second indication of detection of the predetermined pattern (eg, without limitation, asserting indication 314).

[0077] At operation 812, optionally, the asserted indication of the presence of a frame in a predetermined reference plane of the PHY-cable interface includes an asserted second indication of detection of a predetermined pattern.

[0078] At operation 814, optionally, the frame comprises an Ethernet frame and the predetermined pattern comprises a pattern for a start of stream delimiter, the predetermined pattern comprises a pattern for a start of stream delimiter.

[0079] FIG. 8B is a flow diagram illustrating a process 800b for detecting the presence of a frame in a predetermined reference plane, according to one or more examples.

[0080] In operation 816, process 800b detects that a pattern (e.g., without limitation, presented pattern 308) presented by a bit of a frame (e.g., without limitation, bit 312 of frame 310) corresponds to a predetermined pattern (e.g., without limitation, predetermined pattern 306).

[0081] In operation 818, process 800b asserts a first indication of detection of the predetermined pattern (eg, without limitation, asserting indication 314).

[0082] At operation 820, optionally, the asserted first indication of the presence of a frame in a predetermined reference plane of the PHY-cable interface includes an asserted first indication of the detection of a predetermined pattern.

[0083] At operation 822, optionally, the frame comprises an Ethernet frame and the predetermined pattern comprises a pattern for a start of stream delimiter, the predetermined pattern comprises a pattern for a start of stream delimiter.

[0084] In operation 824, the process 800b detects assertion of the RX or TX signal on a connection of the PHY-MAC interface (eg, without limitation, the TXEN connection 322 or the RXDV connection 324 of FIG. 3B).

[0085] In operation 826, the process 800b asserts a second indication of detection of a signal indicating the presence of a frame on the RX or TX connection of the PHY-MAC interface.

[0086] At operation 828, optionally, an asserted second indication of the presence of a frame on a predetermined reference plane of the PHY-MAC interface is responsive to the asserted indication of detection of a signal indicating the presence of a frame on the RX or TX connection of the PHY-MAC interface.

[0087] The latency experienced by packets traveling through the PHY may vary. As a non-limiting example, a PHY implementing physical layer collision avoidance (PLCA) may include delay lines or other mechanisms that vary, sometimes unpredictably, the travel time for packets traveling through the PHY (towards the cable).

[0088] PTP (including gPTP, the automotive profile of PTP in 10SPE) utilizes four frames: a master-to-slave synchronization frame (SYNC), a master-to-slave follow-up frame (FOLLOW_UP), a slave-to-master delay request frame (DELAY_REQUEST), and a slave-to-master delay response frame (DELAY_RESPONSE) to synchronize a slave clock to a master clock coupled over a computer network. The SYNC and DELAY_RESPONSE frames contain a timestamp generated by the master that represents the time the master sent the frame. The slave generates timestamps that represent the time the SYNC and DELAY_RESPONSE frames were received at the slave, respectively. The slave uses these generated timestamps to calculate the offset between the slave clock and the master clock and, optionally, synchronize its clock to the master clock.

[0089] In typical configurations, hardware time stamping is triggered in the master and slave in response to the detection of a SYNC frame or a DELAY_RESPONSE frame in the respective MII. In these configurations, a fixed latency between each MDI and MII is assumed, and a value representing the fixed latency is subtracted in the case of receive and added in the case of transmit. However, the latency in the PHY may not be substantially fixed. For example, the latency in a PLCA PHY may exhibit variations of as much as 80% of the frame time. Furthermore, even if the latency is substantially fixed in the PHY, it may not be known, as a non-limiting example, because it is not reasonably convenient to determine the latency.

[0090] One or more examples generally relate to generating timestamps for PTP or generalized PTP (gPTP) clock synchronization using a duration value determined as disclosed above (e.g., without limitation, duration value 118) to represent PHY latency.

[0091] FIG. 9 is a flow diagram illustrating a clock synchronization process 900, according to one or more examples. In the non-limiting example illustrated by FIG. 9, a clock 908 of a slave device 906 is to be synchronized to a clock 904 of a master device 902. One or both of the master device 902 and the slave device 906 includes a “latency-aware” PHY that determines latency according to the examples described with reference to FIGS. 1-8 and a MAC that reads a duration value (e.g., duration value 118) from the respective latency-aware PHY and, more generally, synchronizes clocks using the duration value to calculate a timestamp used for PTP 1588 timestamps. In this particular example, the master device 902 includes a latency-aware PHY 922 (“PHY 922”) and a MAC 924, and the slave device 906 includes a latency-aware PHY 926 (“PHY 926”) and a MAC 928.

[0092] In operation 910 , the master device 902 sends a SYNC frame to the slave device 906 .

[0093] The MAC 924 of the master device 902 generates a timestamp T'0 representing the time when the SYNC frame is detected at the PHY-MAC interface (e.g., without limitation, RMII or MII) of the master device 902, and receives from the latency-aware PHY 922 a duration value T'0 representing the latency of the PHY 922 in the master device 902, as determined above. VAR0 The MAC 924 of the master device 902 reads a further timestamp T0 representing the time the SYNC frame was at the PHY-cable interface of the master device 902 (e.g., without limitation, at a reference plane defined in the MDI) using the formula T0=T'0+T VAR0 The MAC 924 of the master 902 sends the timestamp T'0 together with the SYNC frame.

[0094] The MAC 928 of the slave device 906 generates a timestamp T'1 representing the time when the SYNC frame is detected at the PHY-MAC interface (e.g., without limitation, RMII or MII) of the slave device 906, and receives from the latency-aware PHY 926 a duration value T'1 representing the latency of the latency-aware PHY 926 at the slave device 906, as determined above. VAR1 The MAC 928 of the slave device 906 reads a further timestamp T1, representing the time the SYNC frame was at the PHY-cable interface (e.g., without limitation, MDI) of the slave device 906, according to the formula T1=T'1-T VAR1 Calculate according to:

[0095] In operation 912, the master device 902 sends a FOLLOW_UP frame to the slave device 906. The FOLLOW_UP frame includes a timestamp T0 or a derivative thereof.

[0096] In operation 914, the slave device 906 sends a DELAY_REQUEST frame to the master device 902 in response to receiving the FOLLOW_UP frame.

[0097] The MAC 928 of the slave device 906 generates a timestamp T'2 representing the time when the DELAY_REQUEST frame was detected at the PHY-MAC interface (e.g., without limitation, the MII) of the slave device 906, and receives from the latency-aware PHY 926 a duration value T'2 representing the latency of the PHY 926 at the slave device 906, as determined above. VAR2 The timestamp T'2 is sent with the DELAY_REQUEST frame. The MAC 928 of the slave device 906 reads a further timestamp T2, representing the time when the DELAY_REQUEST frame was at the PHY-cable interface (e.g., without limitation, MDI) of the slave device 906, using the formula T2=T'2+T VAR2 Calculate according to:

[0098] The MAC 924 of the master device 902 generates a timestamp T'3 representing the time when the DELAY_REQUEST frame is detected at the PHY-MAC interface (e.g., without limitation, the MII) of the master device 902, and receives from the latency-aware PHY 922 a duration value T'3 representing the latency of the latency-aware PHY 922 in the master device 902, as determined above. VAR3 The MAC 924 of the master device 902 reads a further timestamp T3 representing the time the DELAY_REQUEST frame was in the PHY-cable interface (e.g., without limitation, MDI) of the master device 902, using the formula T3=T'3-T VAR3 Calculate according to:

[0099] In operation 916, the master device 902 sends a DELAY_RESPONSE frame to the slave device 906. The DELAY_RESPONSE frame includes a timestamp T3 or a derivative thereof.

[0100] In operation 918, the MAC 928 of the slave device 906 uses the timestamps T0, T1, T2, and T3 to calculate the offset between the clock 908 of the slave device 906 and the clock 904 of the master device 902.

[0101] In operation 920, the MAC 928 of the slave device 906 uses the calculated offset to synchronize the local clock 908 to the master clock 904.

[0102] 9, a single respective latency value was utilized to cancel the latency from the respective timestamp, but the disclosure is not so limited. By way of non-limiting example, it is specifically contemplated that multiple latency values ​​may be utilized to cancel the latency from the respective timestamp, including, without limitation, additional duration values ​​generated as disclosed herein, predetermined fixed delay values ​​representing a portion of the substantially fixed latency in the PHY, and combinations thereof.

[0103] FIG. 10 is a flow diagram illustrating a process 1000 for canceling PHY latency from a timestamp, according to one or more examples.

[0104] Process 1000 may be performed by a MAC implementing PTP in either a master context (e.g., without limitation, as part of master device 902) or a slave context (e.g., without limitation, as part of slave device 906), by way of non-limiting example.

[0105] At operation 1002, process 1000 reads a recorded duration value at the PHY in response, at least in part, to an asserted indication that the duration value is available to be read at the PHY. The duration value represents a latency of the PHY. In one or more examples, the duration value represents a duration for a frame to travel between a predetermined reference plane of the PHY-MAC interface and a predetermined reference plane of the PHY-cable interface.

[0106] In one or more examples, the duration value may represent the latency of the PHY when a frame is traveling from the MAC towards the cable (e.g., without limitation, transmitting a SYNC frame of operation 910 or a DELAY_REQUEST frame of operation 914), or the duration value may represent the latency of the PHY when a frame is traveling from the cable towards the MAC (e.g., without limitation, receiving a SYNC frame of operation 910 or a DELAY_REQUEST frame of operation 914).

[0107] At operation 1004, process 1000 changes the value of the timestamp from a first value to a second value at least in part in response to the duration value. The changed value of the timestamp represents the time the frame was at the PHY-cable interface. The value of the timestamp is intended to represent the time the frame was at the PHY-cable interface, while the first value represents the time the frame was at the PHY-MAC interface. Thus, using the duration value to change the value of the timestamp from the first value to the second value improves the degree to which the value of the timestamp represents the time the frame was at the PHY-cable interface.

[0108] Part or all of the synchronization process 900 may be performed for each timestamp for which latency cancellation is desired.

[0109] Those skilled in the art will appreciate that the functional elements (e.g., functions, operations, actions, processes, and / or methods) of the embodiments disclosed herein may be implemented in any suitable hardware, software, firmware, or combination thereof. Figure 11 illustrates a non-limiting example of an implementation of the functional elements disclosed herein. In some embodiments, some or all of the functional elements disclosed herein may be performed by hardware specially configured to perform the functional elements.

[0110] FIG. 11 is a block diagram of a circuit 1100 that, in some embodiments, may be used to implement various functions, operations, acts, processes, and / or methods disclosed herein. The circuit 1100 includes one or more processors 1102 (sometimes referred to herein as “processors 1102”) operably coupled to one or more data storage devices (sometimes referred to herein as “storage devices 1104”). The storage devices 1104 include machine-executable code 1106 stored thereon, and the processors 1102 include logic circuitry 1108. The machine-executable code 1106 includes information describing functional elements that may be implemented (e.g., executed) by the logic circuitry 1108. The logic circuitry 1108 is adapted to implement (e.g., execute) the functional elements described by the machine-executable code 1106. The circuitry 1100, when executing the functional elements described by the machine-executable code 1106, should be considered dedicated hardware configured to execute the functional elements disclosed herein. In some embodiments, processor 1102 may be configured to execute the functional elements described by machine-executable code 1106 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel processing streams.

[0111] When implemented by the logic 1108 of the processor 1102, the machine-executable code 1106 is configured to adapt the processor 1102 to perform the operations of the embodiments disclosed herein. As a non-limiting example, the machine-executable code 1106 may be configured to adapt the processor 1102 to perform some or all of the operations of one or more of the transfer 400, process 500, process 600, process 700, process 800a, synchronization process 900, or process 1000. Also, by way of non-limiting example, the machine-executable code 1106 may be configured to adapt the processor 1102 to perform some or all of the features, functions, or operations disclosed herein for one or more of the devices 100, 200, or 300a, and more specifically, for one or more of the memory 102, the logic circuitry 104, the PHY-cable interface 106, the PHY-MAC interface 110, the counting logic 202, the gating circuitry 218, the gate 212, the message type detection logic 214, the second pattern matcher 316, the first pattern matcher 304, the master device 902, or the slave device 906.

[0112] The processor 1102 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. While a general-purpose computer including a processor is considered a special-purpose computer, the general-purpose computer is also configured to execute functional elements corresponding to machine-executable code 1106 (e.g., software code, firmware code, hardware descriptions) related to embodiments of the present disclosure. Note that the general-purpose processor (sometimes referred to herein as a host processor or simply host) may be a microprocessor; however, the processor 1102 may alternatively include any conventional processor, controller, microcontroller, or state machine. The processor 1102 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0113] In some embodiments, the memory device 1104 includes a volatile data storage device (e.g., random access memory (RAM)), a non-volatile data storage device (e.g., flash memory, a hard disk drive, a solid state drive, an erasable programmable read-only memory (EPROM), etc.). In some embodiments, the processor 1102 and the memory device 1104 may be implemented in a single device (e.g., a semiconductor device product, a system-on-chip (SOC), etc.). In some embodiments, the processor 1102 and the memory device 1104 may be implemented in separate devices.

[0114] In some embodiments, machine-executable code 1106 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored by storage 1104, accessed directly by processor 1102, and executed by processor 1102 using at least logic circuitry 1108. Also, as a non-limiting example, the computer-readable instructions may be stored in storage 1104, transferred for execution to a memory device (not shown), and executed by processor 1102 using at least logic circuitry 1108. Thus, in some embodiments, logic circuitry 1108 includes electrically configurable logic circuitry 1108.

[0115] In some embodiments, machine-executable code 1106 may describe hardware (e.g., circuits) to be implemented in logic circuitry 1108 to perform the functional elements. This hardware may be described at any of a variety of levels of abstraction, from low-level transistor layouts to high-level description languages. At high levels of abstraction, a hardware description language (HDL) such as the IEEE standard hardware description language (HDL) may be used. As non-limiting examples, VERILOG®, SYSTEMVERILOG™, or very large scale integration (VLSI) hardware description language (VHDL) may be used.

[0116] The HDL description may be converted into a description at any of a number of other levels of abstraction, as desired. As a non-limiting example, the high-level description may be converted into a logic-level description, such as a register-transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, micro-operations performed by hardware logic circuits (e.g., without limitation, gates, flip-flops, registers) of logic circuit 1108 may be described in RTL and then converted by a synthesis tool into a GL description, which may be converted by a place-and-route tool into a layout-level description that corresponds to the physical layout of an integrated circuit of programmable logic devices, discrete gate or transistor logic, discrete hardware components, or a combination thereof. Thus, in some embodiments, machine-executable code 1106 may include HDL, RTL, a GL description, a mask-level description, other hardware descriptions, or any combination thereof.

[0117] In embodiments in which machine-executable code 1106 includes a hardware description (at any level of abstraction), a system (not shown, but including storage 1104) may be configured to implement the hardware description described by machine-executable code 1106. As a non-limiting example, processor 1102 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 1108 may be electronically controlled to implement circuitry corresponding to the hardware description in logic circuitry 1108. Also, as a non-limiting example, logic circuitry 1108 may include hardwired logic manufactured by a manufacturing system (not shown, but including storage 1104) according to the hardware description in machine-executable code 1106.

[0118] Regardless of whether the machine-executable code 1106 includes computer-readable instructions or a hardware description, the logic circuitry 1108, when implementing the functional elements of the machine-executable code 1106, is adapted to perform the functional elements described by the machine-executable code 1106. Note that the hardware description may not directly describe the functional elements, but rather the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description can perform.

[0119] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation configured to perform the actions of a module or component and / or software object or routine that may be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing device, etc.) of a computing system. In some embodiments, different components, modules, engines, and services described in this disclosure may be implemented as objects or processes (e.g., as separate threads) executing on a computing system. While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations, or a combination of software and specific hardware implementations, are also possible and contemplated.

[0120] As used in this disclosure, the term "combination," referring to a plurality of elements, can include a combination of all elements or any of various different subcombinations of elements. For example, the phrase "A, B, C, D, or combinations thereof" can refer to A, B, C, or D; each combination of A, B, C, and D; and any subcombination of A, B, C, or D, such as any one of A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0121] The terms used in this disclosure, and particularly in the appended claims (e.g., the body of the appended claims), are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "includes, but is not limited to," etc.). As used herein, the term "each" means "some or all," and the term "each and every" means "all."

[0122] Additionally, if a specific number of introduced claim recitations is intended, such intent will be expressly recited in the claim; absent such recitation, no such intent exists. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed as limiting any particular claim including such introduced claim recitations to embodiments including only one such recitation (e.g., "a" and / or "an" should be construed to mean "at least one" or "one or more"), even if the same claim includes the introductory phrase "one or more" or "at least one" and an indefinite article such as "a" or "an"). The same is true for the use of definite articles used to introduce claim recitations.

[0123] Additionally, even when a specific number of introduced claim recitations are explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the explicit recitation of "two recitations" without other modifiers means at least two recitations or more than two recitations). Furthermore, when conventions similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." are used, such constructions are generally intended to include A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together, etc.

[0124] Furthermore, any disjunction or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B."

[0125] One or more non-limiting examples of the present disclosure may include the following.

[0126] Example 1: A method comprising: recording a value representing a duration for a frame of a PHY data path to travel between a predetermined reference plane of a PHY-MAC interface and a predetermined reference plane of a PHY-cable interface; and asserting an indication that the recorded value is available to be read from the PHY.

[0127] Example 2: The method of example 1, wherein the duration that a frame travels between a predetermined reference plane of the PHY-MAC interface and a predetermined reference plane of the PHY-cable interface includes the duration that a frame travels from the predetermined reference plane of the PHY-MAC interface to the predetermined reference plane of the PHY-cable interface.

[0128] Example 3: A method as described in any of Examples 1 and 2, comprising: starting counting clock cycles at least in part in response to an asserted indication of the presence of a frame in a predetermined reference plane of the PHY-MAC interface; stopping counting clock cycles at least in part in response to an asserted indication of the presence of a frame in a predetermined reference plane of the PHY-cable interface; and setting a value to the counted number of clock cycles.

[0129] Example 4: A method as described in any of Examples 1 to 3, comprising: detecting that a pattern exhibited by bits of a frame at a predetermined reference plane of the PHY-MAC interface corresponds to the predetermined pattern; and asserting a first indication of detection of the predetermined pattern, wherein the asserted indication of the presence of a frame at the predetermined reference plane of the PHY-MAC interface is responsive to the first indication of detection of the predetermined pattern; detecting that a pattern exhibited by bits of the frame at a predetermined reference plane of the PHY-Cable interface corresponds to the predetermined pattern; and asserting a second indication of detection of the predetermined pattern, wherein the asserted indication of the presence of a frame at the predetermined reference plane of the PHY-Cable interface is responsive to the second indication of detection of the predetermined pattern.

[0130] Example 5: A method as described in any of Examples 1 to 4, comprising, at least in part, in response to detecting that the frame type of the frame corresponds to a predetermined frame type, enabling provision of a value representing the counted number of clock cycles to the PHY.

[0131] Example 6: A method according to any one of Examples 1 to 5, including: reading a value recorded at the PHY in response at least in part to an asserted indication that the value is available to be read at the PHY, the value representing a latency of the PHY; and changing the value of a timestamp from a first value to a second value in response at least in part to the read value, the changed value of the timestamp representing a time the frame was at the PHY-cable interface.

[0132] Example 7: The method of any one of Examples 1 to 6, wherein the duration that a frame travels between a predetermined reference plane of the PHY-MAC interface and a predetermined reference plane of the PHY-Cable interface includes the duration that a frame travels from the predetermined reference plane of the PHY-Cable interface to the predetermined reference plane of the PHY-MAC interface.

[0133] Example 8: A method as described in any of Examples 1 to 7, comprising: starting counting clock cycles at least in part in response to an asserted indication of the presence of a frame in a predetermined reference plane of the PHY-cable interface; stopping counting clock cycles at least in part in response to an asserted indication of the presence of a frame in a predetermined reference plane of the PHY-MAC interface; and setting a value to the counted number of clock cycles.

[0134] Example 9: A method according to any one of Examples 1 to 8, comprising: detecting that a pattern exhibited by bits of a frame at a predetermined reference plane of the PHY-cable interface corresponds to the predetermined pattern; and asserting a first indication of the detection of the predetermined pattern, wherein the asserted indication of the presence of a frame at the predetermined reference plane of the PHY-cable interface is responsive to the asserted first indication of the detection of the predetermined pattern; detecting that a pattern exhibited by bits of the frame at a predetermined reference plane of the PHY-MAC interface corresponds to the predetermined pattern; and asserting a second indication of the detection of the predetermined pattern, wherein the asserted indication of the presence of a frame at the predetermined reference plane of the PHY-MAC interface is responsive to the asserted second indication of the detection of the predetermined pattern.

[0135] Example 10: A method according to any one of Examples 1 to 9, including: reading a value recorded at the PHY in response at least in part to an asserted indication that the value is available to be read at the PHY, the value representing a latency of the PHY; and changing the value of a timestamp from a first value to a second value in response at least in part to the read value, the changed value of the timestamp representing a time the frame was at the PHY-cable interface.

[0136] Example 11: An apparatus comprising: a memory and logic circuitry provided in a PHY, the memory and logic circuitry coupled to record a value representing the duration a frame of the PHY's data path travels between a predetermined reference plane of the PHY-MAC interface and a predetermined reference plane of the PHY-cable interface, and to assert an indication that the recorded value is available to be read from the memory.

[0137] Example 12: The apparatus of Example 11, wherein the duration that a frame in the data path of the PHY travels between a predetermined reference plane of the PHY-MAC interface and a predetermined reference plane of the PHY-cable interface includes the duration that the frame travels from the predetermined reference plane of the PHY-MAC interface to the predetermined reference plane of the PHY-cable interface.

[0138] Example 13: An apparatus described in any of Examples 11 and 12, wherein the logic circuit comprises counter logic for starting counting clock cycles in response at least in part to an asserted indication of the presence of a frame in a predetermined reference plane of the PHY-MAC interface and for stopping counting clock cycles in response at least in part to an asserted indication of the presence of a frame in a predetermined reference plane of the PHY-cable interface, and the logic circuit sets a value according to the counted number of clock cycles.

[0139] Example 14: The apparatus of any of Examples 11-13, wherein the logic circuit comprises first and second pattern detector logic respectively coupled to observe frames in a transmission path of the PHY, the first pattern detector logic detecting that a pattern exhibited by bits of the frame at a predetermined reference plane of the PHY-MAC interface corresponds to the predetermined pattern and asserting a first indication of the detection of the predetermined pattern, the asserted indication of the presence of the frame at the predetermined reference plane of the PHY-MAC interface being responsive to the asserted first indication of the detection of the predetermined pattern, and the second pattern detector logic detecting that a pattern exhibited by bits of the frame at the predetermined reference plane of the PHY-cable interface corresponds to the predetermined pattern and asserting a second indication of the detection of the predetermined pattern, the asserted indication of the presence of the frame at the predetermined reference plane of the PHY-cable interface being responsive to the asserted second indication of the detection of the predetermined pattern.

[0140] Embodiment 15: The apparatus according to any one of embodiments 11 to 14, wherein the frame is an Ethernet frame, and the predetermined pattern includes a pattern for a stream start delimiter.

[0141] Example 16: An apparatus described in any of Examples 11 to 15, wherein the logic circuit comprises a gating circuit for selectively supplying a value representing the counted number of clock cycles to the PHY in response, at least in part, to detecting that the frame type of the frame corresponds to a predetermined frame type.

[0142] Example 17: An apparatus described in any of Examples 11 to 16, wherein the duration that a frame in the data path of the PHY travels between a predetermined reference plane of the PHY-MAC interface and a predetermined reference plane of the PHY-cable interface includes the duration that the frame travels from the predetermined reference plane of the PHY-cable interface to the predetermined reference plane of the PHY-MAC interface.

[0143] Example 18: An apparatus described in any of Examples 11 to 17, wherein the logic circuit comprises counter logic for starting counting clock cycles at least in part in response to an asserted indication of the presence of a frame in a predetermined reference plane of the PHY-cable interface and for stopping counting clock cycles at least in part in response to an asserted indication of the presence of a frame in a predetermined reference plane of the PHY-MAC interface, and the logic circuit sets a value according to the counted number of clock cycles.

[0144] Example 19: The apparatus of any of Examples 11 to 18, wherein the logic circuit comprises: first and second pattern detector logic respectively coupled to observe frames in a receive path of the PHY; a first pattern matcher configured to detect that a pattern exhibited by bits of the frame at a predetermined reference plane of the PHY-cable interface corresponds to the predetermined pattern and assert an indication of detection of the predetermined pattern, the asserted indication of the presence of the frame at the predetermined reference plane of the PHY-cable interface being responsive to the asserted indication of detection of the predetermined pattern by the first pattern matcher; and a second pattern matcher configured to detect that a pattern exhibited by bits of the frame at a predetermined reference plane of the PHY-MAC interface corresponds to the predetermined pattern and assert an indication of detection of the predetermined pattern, the asserted indication of the presence of the frame at the predetermined reference plane of the PHY-MAC interface being responsive to the asserted indication of detection of the predetermined pattern by the second pattern matcher.

[0145] Example 20: The apparatus according to any one of Examples 11 to 19, wherein the frame is an Ethernet frame, and the predetermined pattern includes a pattern for a stream start delimiter.

[0146] Example 21: A system comprising: a physical layer that records a value representing a duration a frame travels between a predetermined reference plane of a PHY-MAC interface and a predetermined reference plane of a PHY-cable interface and asserts an indication that the recorded value is available to be read from the physical layer; and a media access controller that, at least in part, responds to the asserted indication that the value is available to be read at the physical layer to read the recorded value of the duration and, at least in part, responds to the read value to change the value of a timestamp from a first value to a second value, wherein the changed value of the timestamp represents the time the frame was at the PHY-cable interface.

[0147] Example 22: The system of Example 21, wherein the media access controller is coupled to the physical layer via a PHY-MAC interface to read the value.

[0148] Example 23: The system of any of Examples 21 and 22, wherein the media access controller implements a precision time protocol and the frame is one of a SYNCHRONIZATION frame or a DELAY_REQUEST frame.

[0149] Example 24: The system of any of Examples 21 to 23, wherein the media access controller and the physical layer are provided in a device that includes a master clock of the Precision Time Protocol synchronization process.

[0150] Example 25: A system described in any of Examples 21 to 24, wherein the media access controller and the PHY-cable interface are provided in a device including a slave clock of a 1588 precision time protocol synchronization process.

[0151] Example 26: The system described in any of Examples 21 to 25, wherein the media access controller and the physical layer are provided in a device including a clock of the Precision Time Protocol synchronization process.

[0152] While the present disclosure has been described herein with reference to certain illustrated embodiments, those skilled in the art will recognize and understand that the present invention is not so limited. Rather, numerous additions, deletions, and modifications may be made to the illustrated and described embodiments without departing from the scope of the present invention as claimed below, along with their legal equivalents. In addition, features of one embodiment may be combined, as contemplated by the inventor, with features of other disclosed embodiments and still fall within the scope of the present disclosure.

Claims

1. 1. A method comprising: recording a value representing the duration a frame on the PHY data path travels between a predetermined reference plane of the PHY-MAC interface and a predetermined reference plane of the PHY-cable interface; asserting an indication that the recorded value is available to be read from the PHY; A method comprising:

2. the duration that the frame travels between the predetermined reference plane of the PHY-MAC interface and the predetermined reference plane of the PHY-Cable interface is:

2. The method of claim 1, comprising a duration for the frame to travel from the predetermined reference plane of the PHY-MAC interface to the predetermined reference plane of the PHY-cable interface.

3. commencing counting clock cycles at least in part in response to an asserted indication of the presence of the frame on the predetermined reference plane of the PHY-MAC interface; ceasing counting clock cycles at least in part in response to an asserted indication of the presence of the frame on the predetermined reference plane of the PHY-cable interface; setting said value to a counted number of clock cycles; The method of claim 2 , comprising:

4. detecting that a pattern exhibited by bits of the frame at the predetermined reference plane of the PHY-MAC interface corresponds to a predetermined pattern; asserting a first indication of detection of the predetermined pattern, the asserted indication of the presence of the frame on the predetermined reference plane of the PHY-MAC interface responsive to the first indication of detection of the predetermined pattern; detecting that the pattern exhibited by the bits of the frame at the predetermined reference plane of the PHY-cable interface corresponds to the predetermined pattern; asserting a second indication of detection of the predetermined pattern, the asserted indication of the presence of the frame at the predetermined reference plane of the PHY-cable interface being responsive to the second indication of detection of the predetermined pattern; The method of claim 3, comprising:

5. 3. The method of claim 2, comprising enabling provision of a value representing a counted number of clock cycles to the PHY at least in part in response to detecting that a frame type of the frame corresponds to a predetermined frame type.

6. reading the stored value at the PHY in response at least in part to the asserted indication that the value is available to be read at the PHY, the value representing a latency of the PHY; changing a value of a timestamp from a first value to a second value at least partially in response to the read value, the changed value of the timestamp representing a time when the frame was at the PHY-cable interface; The method of claim 2 , comprising:

7. the duration that the frame travels between the predetermined reference plane of the PHY-MAC interface and the predetermined reference plane of the PHY-Cable interface is:

2. The method of claim 1, including a duration for the frame to travel from the predetermined reference plane of the PHY-cable interface to the predetermined reference plane of the PHY-MAC interface.

8. commencing counting clock cycles at least in part in response to an asserted indication of the presence of the frame on the predetermined reference plane of the PHY-cable interface; stopping counting clock cycles at least in part in response to an asserted indication of the presence of the frame on the predetermined reference plane of the PHY-MAC interface; setting said value to a counted number of clock cycles; The method of claim 7, comprising:

9. detecting that a pattern exhibited by bits of a frame at the predetermined reference plane of the PHY-cable interface corresponds to a predetermined pattern; asserting a first indication of detection of the predetermined pattern, asserting the asserted indication of the presence of the frame in the predetermined reference plane of the PHY-cable interface in response to the asserted first indication of detection of the predetermined pattern; detecting that the pattern exhibited by bits of the frame at the predetermined reference plane of the PHY-MAC interface corresponds to the predetermined pattern; asserting a second indication of detection of the predetermined pattern; asserting the asserted indication of the presence of the frame on the predetermined reference plane of the PHY-MAC interface in response to the asserted second indication of detection of the predetermined pattern; The method of claim 8, comprising:

10. reading the stored value at the PHY in response at least in part to the asserted indication that the value is available to be read at the PHY, the value representing a latency of the PHY; changing a value of a timestamp from a first value to a second value at least partially in response to the read value, the changed value of the timestamp representing a time when the frame was at the PHY-cable interface; The method of claim 7, comprising:

11. 1. An apparatus comprising: A memory and a logic circuit provided in a PHY, the memory and the logic circuit comprising: recording a value representing the duration a frame in the PHY's data path travels between a predetermined reference plane of a PHY-MAC interface and a predetermined reference plane of a PHY-cable interface; asserting an indication that the stored value is available to be read from the memory; and a memory and logic circuit coupled to perform An apparatus comprising:

12. the duration that the frame in the data path of the PHY travels between the predetermined reference plane of the PHY-MAC interface and the predetermined reference plane of the PHY-cable interface, The apparatus of claim 11 , further comprising a duration for the frame to travel from the predetermined reference plane of the PHY-MAC interface to the predetermined reference plane of the PHY-Cable interface.

13. The logic circuit comprises: commencing counting clock cycles at least in part in response to an asserted indication of the presence of the frame on the predetermined reference plane of the PHY-MAC interface; ceasing counting clock cycles at least in part in response to an asserted indication of the presence of the frame on the predetermined reference plane of the PHY-cable interface; counter logic for performing 13. The apparatus of claim 12, wherein the logic circuitry sets the value according to a counted number of clock cycles.

14. the logic circuitry comprises first and second pattern detector logic respectively coupled to observe frames in a transmit path of the PHY; The first pattern detector logic comprises: detecting that a pattern exhibited by bits of the frame at the predetermined reference plane of the PHY-MAC interface corresponds to a predetermined pattern; asserting a first indication of detection of the predetermined pattern; the asserted indication of the presence of the frame on the predetermined reference plane of the PHY-MAC interface is responsive to the asserted first indication of detection of the predetermined pattern; and and The second pattern detector logic includes: detecting that the pattern exhibited by bits of the frame at the predetermined reference plane of the PHY-cable interface corresponds to the predetermined pattern; asserting a second indication of detection of the predetermined pattern; the asserted indication of the presence of the frame on the predetermined reference plane of the PHY-cable interface is responsive to the asserted second indication of detection of the predetermined pattern; and The apparatus of claim 13 ,

15. 15. The apparatus of claim 14, wherein the frames are Ethernet frames and the predetermined pattern includes a pattern for a start-of-stream delimiter.

16. 13. The apparatus of claim 12, wherein the logic circuitry comprises a gating circuit for selectively providing a value representing the counted number of clock cycles to the PHY at least in part in response to detecting that a frame type of the frame corresponds to a predetermined frame type.

17. the duration that the frame in the data path of the PHY travels between the predetermined reference plane of the PHY-MAC interface and the predetermined reference plane of the PHY-cable interface, 12. The apparatus of claim 11, further comprising a duration for the frame to travel from a predetermined reference plane of a PHY-cable interface to a predetermined reference plane of a PHY-MAC interface.

18. The logic circuit comprises: commencing counting clock cycles at least in part in response to an asserted indication of the presence of the frame on the predetermined reference plane of the PHY-cable interface; ceasing counting clock cycles at least in part in response to an asserted indication of the presence of the frame on the predetermined reference plane of the PHY-MAC interface; and counter logic for performing 18. The apparatus of claim 17, wherein the logic circuitry sets the value according to a counted number of clock cycles.

19. the logic circuitry includes first and second pattern detector logic respectively coupled to observe frames in a receive path of the PHY; a first pattern matcher, detecting that a pattern exhibited by bits of the frame at the predetermined reference plane of the PHY-cable interface corresponds to a predetermined pattern; and asserting an indication of detection of the predetermined pattern; the asserted indication of the presence of the frame in the predetermined reference plane of the PHY-cable interface is responsive to the asserted indication of detection of the predetermined pattern by the first pattern matcher. a first pattern matcher that performs a second pattern matcher, detecting that the pattern exhibited by bits of the frame at the predetermined reference plane of the PHY-MAC interface corresponds to the predetermined pattern; and asserting an indication of detection of the predetermined pattern; the asserted indication of the presence of the frame on the predetermined reference plane of the PHY-MAC interface is responsive to the asserted indication of detection of the predetermined pattern by the second pattern matcher. a second pattern matcher that 20. The apparatus of claim 18, comprising:

20. 20. The apparatus of claim 19, wherein the frames are Ethernet frames and the predetermined pattern includes a pattern for a start-of-stream delimiter.

21. 1. A system comprising: A physical layer, recording a value representing the duration for a frame to travel between a predetermined reference plane of the PHY-MAC interface and a predetermined reference plane of the PHY-cable interface; and Asserting an indication that the recorded value is available to be read from the physical layer. a physical layer that performs a media access controller, reading the recorded value for the duration at least in part in response to the asserted indication that the value is available to be read at the physical layer; and changing a value of a timestamp from a first value to a second value at least partially in response to the read value, the changed value of the timestamp representing a time that the frame was at the PHY-cable interface. The media access controller A system comprising:

22. 22. The system of claim 21, wherein the media access controller is coupled to the physical layer via the PHY-MAC interface to read the value.

23. 22. The system of claim 21, wherein the media access controller implements a precision time protocol and the frame is one of a SYNCHRONIZATION frame or a DELAY_REQUEST frame.

24. 22. The system of claim 21, wherein the media access controller and the physical layer are provided in a device that includes a master clock of a Precision Time Protocol synchronization process.

25. 22. The system of claim 21, wherein the media access controller and the PHY-cable interface are provided in a device that includes a slave clock of a 1588 precision time protocol synchronization process.

26. 22. The system of claim 21, wherein the media access controller and the physical layer are provided in a device that includes a clock for a precision time protocol synchronization process.

Images