Method, device and system for transmitting data in an Ethernet network

Abstract

A data transmission method, device, and system are provided. A PMA sublayer of an Ethernet device obtains an FEC-encoded data stream and performs a first data processing process on the data stream to obtain an interleaved data stream, where the first data processing process includes performing interleaving in a first interleaving manner, and the interleaving type of the first interleaving manner is specifically symbol interleaving or convolutional interleaving. According to the present application, the functionality of the PMA sublayer can be extended to meet requirements for reducing BER in high-rate Ethernet data transmission scenarios.

Description

[Technical Field]

[0001] This application claims priority to Chinese Patent Application No. 202310149106.7, filed February 14, 2023, entitled "ETHERNET PHYSICAL LAYER DATA PROCESSING METHOD," and Chinese Patent Application No. 202310247349.4, filed March 3, 2023, entitled "DATA SENDING METHOD, DEVICE, AND SYSTEM IN ETHERNET," both of which are incorporated herein by reference in their entireties.

[0002] The present application relates to the field of communications, and in particular to a method, device and system for transmitting data in an Ethernet. [Background technology]

[0003] In the Ethernet data transmission process, due to various factors such as environmental interference and system errors, the data received by the data receiver will be inconsistent with the data transmitted by the data transmitter. That is, bit errors are inevitable. Currently, the bit error rate (BER) can be reduced by using forward error correction (FEC), interleavers, and other means.

[0004] However, the existing manner of performing interleaving by the physical coding sublayer (PCS) cannot meet the requirements when there is an increase in data transmission rate. Summary of the Invention [Means for solving the problem]

[0005] To solve the problem that technical means for reducing the BER cannot meet the requirements for an increase in data transmission rate, a data transmission method, device and system are provided.

[0006] According to a first aspect, a data transmission method is provided. The method is performed by an Ethernet device. The Ethernet device may be an Ethernet transfer device such as an Ethernet chip, a switch, or a router, and an optical or electrical module pluggable in an Ethernet. When the Ethernet device is used as a data sender, a physical medium attachment (PMA) sublayer of the Ethernet device obtains an FEC-encoded data stream and performs a first data processing process on the data stream to obtain an interleaved data stream. The first data processing process includes performing interleaving in a first interleaving manner, where the interleaving type of the first interleaving manner is specifically symbol interleaving or convolutional interleaving. The data stream obtained by the PMA sublayer may be one data stream or multiple data streams, and the amount of data streams is related to the amount of data lanes between the PMA sublayer and the previous sublayer. Furthermore, the interleaving may be interleaving within one data stream or interleaving between multiple data streams. Additionally, the interleaved data stream may alternatively be one data stream or multiple data streams.

[0007] In this application, the PMA sublayer on the data transmitting side performs symbol interleaving or convolutional interleaving on the data stream, and the specific manner in which the PMA sublayer performs interleaving can be flexibly designed to ensure that the actual requirements for reducing the BER in the network are met. In addition, since the PMA sublayer is relatively easy to expand, the existing PCS does not need to be modified in the design of the PMA sublayer, and even when the PMA sublayer is in a pluggable module, the master chip of the existing Ethernet physical PHY layer does not need to be modified in the design of the PMA sublayer, so that the requirements for reducing the BER in high-rate data transmission scenarios are met while research and development costs are reduced as much as possible.

[0008] In a possible implementation, the PMA sublayer performs symbol interleaving at a 10-bit granularity, or the PMA sublayer performs 10-bit symbol interleaving, which matches the existing granularity at which the PCS performs interleaving, and the BER can be effectively reduced through symbol interleaving at that granularity.

[0009] In a possible implementation, the first data processing process performed on the data stream by the PMA sublayer further includes bit multiplexing or symbol-group multiplexing. The granularity of the bit multiplexing may be 1 bit, and the granularity of the symbol group multiplexing may be 20 bits or 40 bits. Through bit multiplexing or symbol group multiplexing, the amount of data stream output by the PMA sublayer can be adapted to the amount of data lanes between the PMA and the next sublayer in the data transmission direction. In some cases, the bit multiplexing or symbol group multiplexing process may be performed after the above-mentioned process of performing interleaving in a first interleaving manner, or the bit multiplexing or symbol group multiplexing process may be included in the above-mentioned process of performing interleaving in a first interleaving manner.

[0010] In a possible implementation, the first data processing process performed on the data stream by the PMA sublayer further includes bit demux or symbol-group demux, where the granularity of the bit demux is 1 bit, and the granularity of the symbol-group demux can be 20 bits or 40 bits.

[0011] In a possible implementation, the first data processing process performed on the data stream by the PMA sublayer further includes alignment marker (AM) locking and deskewing.

[0012] The data stream obtained by the PMA sublayer is from a previous sublayer in the data transmission direction, which may be, for example, a PCS, a data terminal equipment extender sublayer (DTE_XS), or another PMA sublayer. Through bit demultiplexing or symbol group demultiplexing, and alignment marker locking and deskewing, the data stream from the previous sublayer can be restored. In some cases, the bit demultiplexing or symbol group demultiplexing and alignment marker locking and deskewing processes may be performed before the above process of performing interleaving in a first interleaving manner. That is, the data stream from the previous sublayer is restored, and then subsequent interleaving is performed.

[0013] In a possible implementation, the data stream obtained by the PMA sublayer is a data stream obtained by performing a second data processing process, where the second data processing process includes performing interleaving in a second interleaving manner. That is, the data stream obtained by the PMA sublayer may be a data stream on which interleaving has been performed. The second data processing process may be performed by another sublayer preceding the PMA sublayer, for example, by a PCS or DTE_XS. In addition, the sublayer performing the second data processing process may or may not be directly adjacent to the PMA sublayer, i.e., the sublayer and the PMA sublayer are separated by another sublayer. That is, there is no conflict between the interleaving performed by the PMA sublayer and the interleaving performed by another preceding sublayer. Therefore, the data processing manner of an existing other sublayer does not need to be modified, and existing Ethernet devices are compatible.

[0014] In a possible implementation, the interleave depth of the first interleave style is different from that of the second interleave style. Specifically, an interleave change is performed through interleaving performed by the PMA sublayer. To a certain extent, it is possible that the interleave performed by the PMA sublayer covers the interleave performed by another previous sublayer. Through this interleave change, a new error correction design can be flexibly implemented in the PMA sublayer, thereby better meeting the requirement for reducing the BER for increasing Ethernet data transmission rates without modifying another previous sublayer or even modifying the master chip of the entire Ethernet PHY layer. In particular, the interleave depth of the interleave performed by the PMA sublayer can be different from that of the interleave performed by another previous sublayer. The interleave performed by the PMA sublayer can be flexibly designed based on actual network requirements to meet the requirement for reducing the BER for increasing Ethernet data transmission rates.

[0015] In a possible implementation, the interleaving depth of the second interleaving style is 2 FEC codewords. For example, when Reed-Solomon (RS) codewords are used, the interleaving depth of the second interleaving style is 2 RS codewords, i.e., 2×RS.

[0016] In a possible implementation, the first data processing process may include performing deinterleaving for the second interleaving style, or the first data processing process may not include performing deinterleaving for the second interleaving style. In some cases, deinterleaving for the second interleaving style may be performed before interleaving is performed in the first interleaving style. Specifically, the PMA sublayer first performs deinterleaving for the interleaving performed by another previous sublayer, and interleaving within the PMA sublayer is then performed. In addition, the PMA sublayer may not perform deinterleaving for the interleaving performed by another previous sublayer, and interleaving within the PMA sublayer is performed directly.

[0017] In a possible implementation, the interleaving depth of the first interleaving style is 4×RS. When the interleaving depth is increased to 4×RS, it can be guaranteed that the requirements for reducing the BER in various high-speed Ethernet data transmission scenarios are met, and the BER after the interleaved data passes through FEC can meet network requirements. For example, a depth of 4×RS can at least meet the requirements for reducing the BER in a scenario in which the rate of a single physical lane is 200 gigabits per second (Gbps).

[0018] In possible implementations, the Ethernet device may include at least one of the following: a PHY chip, a forwarding device, or a pluggable module.

[0019] In a possible implementation, the rate of a single physical lane of the data stream obtained by performing interleaving by the PMA sublayer is 200 Gbps. It is easy to understand that 200 Gbps is not the exact value of the lane rate at any instant, but rather a value that can freely fluctuate within a range common in the art.

[0020] In a possible implementation, the rate of the interface for receiving the data stream by the PMA sublayer is at least one of the following: 200 Gbps or 400 Gbps.

[0021] In possible implementations, the PMA sublayer obtains the data stream through one of the following interfaces: an attachment unit interface (AUI) or a common electrical interface (CEI). For example, the PMA sublayer may be circuit-separated from the previous sublayer and obtain the data stream from the previous sublayer through an interface, where the interface may be an AUI, a CEI, etc.

[0022] In a possible implementation, the PMA sublayer transmits the interleaved data stream to a physical medium dependent (PMD) sublayer, which in an Ethernet device at the transmitting side is the next sublayer after the PMD sublayer in the data transmission direction.

[0023] According to a second aspect, a data receiving method is provided. The method is performed by an Ethernet device. The Ethernet device may be an Ethernet transfer device, such as an Ethernet chip, a switch, or a router, and an Ethernet pluggable optical or electrical module. After the PMA sublayer of the Ethernet device at the data transmitting side performs interleaving, the PMA sublayer of the Ethernet device at the data receiving side needs to perform a deinterleaving process accordingly. The PMA sublayer of the Ethernet device at the data receiving side obtains a data stream and performs a third data processing process on the data stream to obtain a deinterleaved data stream. The third data processing process includes performing deinterleaving in a first deinterleaving manner, and the deinterleaving type of the first deinterleaving manner is specifically symbol deinterleaving or convolutional deinterleaving. The data stream obtained by the PMA sublayer may be one data stream or multiple data streams, and the amount of data streams is related to the amount of data lanes between the PMA sublayer and the previous sublayer. Furthermore, the deinterleaving may be within one data stream or between multiple data streams.

[0024] In this application, the PMA sublayer on the data transmitting side performs symbol interleaving or convolutional interleaving on the data stream. Correspondingly, the PMA sublayer on the data receiving side performs symbol deinterleaving or convolutional deinterleaving on the data stream. The specific manner in which the PMA sublayer performs deinterleaving can be flexibly designed to ensure that actual requirements for reducing the BER in the network are met. In addition, because the PMA sublayer is relatively easy to expand, existing PCSs do not need to be modified in the design of the PMA sublayer, and even when the PMA sublayer is in a pluggable module, existing master chips of Ethernet physical PHY layers do not need to be modified in the design of the PMA sublayer. Therefore, requirements for reducing the BER in high-rate data transmission scenarios are met while research and development costs are minimized.

[0025] In a possible implementation, the PMA sublayer performs symbol deinterleaving at 10-bit granularity, or the PMA sublayer performs 10-bit symbol deinterleaving.

[0026] In a possible implementation, the third data processing process performed on the data stream by the PMA sublayer further includes bit multiplexing or symbol group multiplexing. The granularity of the bit multiplexing may be 1 bit, and the granularity of the symbol group multiplexing may be 20 bits or 40 bits. Through bit multiplexing or symbol group multiplexing, the amount of the data stream output by the PMA sublayer can be adapted to the amount of data lanes between the PMA and the next sublayer in the data transmission direction. In some cases, the bit multiplexing or symbol group multiplexing process may be performed after the above-mentioned process of performing deinterleaving in the third interleaving manner, or the bit multiplexing or symbol group multiplexing process may be included in the above-mentioned process of performing deinterleaving in the third interleaving manner.

[0027] In a possible implementation, the third data processing process performed on the data stream by the PMA sublayer includes bit demux or symbol-group demux, where the granularity of bit demux is 1 bit, and the granularity of symbol-group demux can be 20 bits or 40 bits.

[0028] In a possible implementation, a third data processing process performed on the data stream by the PMA sublayer includes alignment marker (AM) locking and deskewing.

[0029] The data stream acquired by the PMA sublayer is from a previous sublayer in the data transmission direction, which may be, for example, a PMD sublayer. Through bit demultiplexing or symbol group demultiplexing, and alignment marker locking and deskewing, the data stream from the previous sublayer can be restored. In some cases, the processing in the first deinterleaving manner can be further implemented in the above processing of bit demultiplexing or symbol group demultiplexing, and alignment marker locking and deskewing. That is, through the processing of bit demultiplexing or symbol group demultiplexing, and alignment marker locking and deskewing, the data stream from the previous sublayer is restored and deinterleaving is implemented.

[0030] In a possible implementation, after performing deinterleaving in the third data processing process on the data stream, the PMA sublayer may further reinterleave the deinterleaved data stream in a second interleaving manner to obtain a reinterleaved data stream. This is to cooperate with the process of performing deinterleaving by the existing PCS or DTE_XS in the Ethernet device on the receiving side, so that the existing PCS or DTE_XS does not need to be improved to accommodate the existing PHY chip as much as possible.

[0031] In a possible implementation, the deinterleaving depth of the first deinterleaving manner is 4×RS.

[0032] In possible implementations, the Ethernet device may include at least one of the following: a PHY chip, a forwarding device, or a pluggable module.

[0033] According to a third aspect, a data receiving method is provided. The method is performed by an Ethernet device. The Ethernet device may be an Ethernet transfer device such as an Ethernet chip, a switch, or a router, or an Ethernet pluggable optical or electrical module. After the PMA sublayer of the Ethernet device at the data transmitting side performs an interleaving change, the PMA sublayer of the Ethernet device at the data receiving side needs to perform a corresponding interleaving change to change the interleaving pattern of the data stream to an interleaving pattern compatible with the deinterleaving process performed by another sublayer, thereby avoiding modifications to the PHY chip. For example, when an Ethernet PHY chip performs 2xRS deinterleaving on a data stream, the PMA sublayer can change the interleaving pattern for the acquired data stream to 2xRS interleaving, so that the correct data stream can be acquired by the PHY chip performing 2xRS deinterleaving on the data stream. In particular, the PMA sublayer of the Ethernet device at the data receiving side acquires a data stream and performs a third data processing process on the data stream to acquire an interleaved data stream, where the third data processing process includes performing interleaving on the data stream, and the interleaving type of the interleaving is symbol interleaving or convolutional interleaving. The data stream acquired by the PMA sublayer can be one data stream or multiple data streams, and the amount of data streams is related to the amount of data lanes between the PMA sublayer and the previous sublayer. Furthermore, the interleaving can be interleaving within one data stream or interleaving between multiple data streams.

[0034] In a possible implementation, symbol interleaving is performed at a granularity of 10 bits.

[0035] In a possible implementation, the interleaved data stream is deinterleaved by the physical coding sublayer PCS or the data terminal equipment extender sublayer DTE_XS.

[0036] In a possible implementation, the interleaving depth of the interleave is 2×RS. When the Ethernet PHY chip performs 2×RS deinterleaving on the data stream, the PMA sublayer may change the interleaving scheme for the obtained data stream to 2×RS interleaving, so that the correct data stream can be obtained by the PHY chip performing 2×RS deinterleaving on the data stream.

[0037] In a possible implementation, the third data processing process includes performing deinterleaving in a first deinterleaving manner, the deinterleaving type of which is, in particular, symbol deinterleaving or convolutional deinterleaving, to obtain a deinterleaved data stream.

[0038] In a possible implementation, the third data processing process includes bit demultiplexing or symbol group demultiplexing, where the granularity of the bit demultiplexing is 1 bit, and the granularity of the symbol group demultiplexing can be 20 bits or 40 bits.

[0039] In a possible implementation, the third data processing process includes alignment marker AM lock and deskew.

[0040] The data stream acquired by the PMA sublayer is from a previous sublayer in the data transmission direction, which may be, for example, a PMD sublayer. Through bit demultiplexing or symbol group demultiplexing, and alignment marker locking and deskewing, the data stream from the previous sublayer can be restored. In some cases, the processing in the first deinterleaving manner can be further implemented in the above processing of bit demultiplexing or symbol group demultiplexing, and alignment marker locking and deskewing. That is, through the processing of bit demultiplexing or symbol group demultiplexing, and alignment marker locking and deskewing, the data stream from the previous sublayer is restored and deinterleaving is implemented.

[0041] In a possible implementation, the third data processing process includes bit multiplexing or symbol group multiplexing. The granularity of the bit multiplexing is 1 bit, and the granularity of the symbol group multiplexing can be 20 bits or 40 bits. Through bit multiplexing or symbol group multiplexing, the amount of data streams output by the PMA sublayer can be adapted to the amount of data lanes between the PMA and the next sublayer in the data transmission direction. In some cases, the bit multiplexing or symbol group multiplexing process can be performed after the above-mentioned process of performing deinterleaving in the third interleaving manner, or the bit multiplexing or symbol group multiplexing process can be included in the above-mentioned process of performing deinterleaving in the third interleaving manner.

[0042] In a possible implementation, the Ethernet device includes at least one of the following: a physical layer PHY chip, a transport device, or a pluggable module.

[0043] According to a fourth aspect, there is provided an Ethernet device including at least one module. The at least one module is configured to perform the method provided in the first aspect or any one of the manners of the first aspect, or the at least one module is configured to perform the method provided in the second aspect or any one of the manners of the second aspect, or the at least one module is configured to perform the method provided in the third aspect or any one of the manners of the third aspect. The at least one module may be implemented based on software, hardware, or a combination of software and hardware, and the modules may be randomly combined or divided based on a specific implementation form.

[0044] According to a fifth aspect, there is provided an Ethernet device including a memory and a processor, wherein the memory is configured to store a computer program and the processor is configured to execute the computer program stored in the memory, or at least one module is configured to execute the method provided in the third aspect or any one of the manners of the third aspect, to enable the Ethernet device to perform the method provided in the first aspect or any one of the manners of the first aspect, or the method provided in the second aspect or any one of the manners of the second aspect.

[0045] According to a sixth aspect, there is provided an Ethernet device including a main control board and an interface board, wherein the main control board or the interface board is configured to implement the method provided in the first aspect or any one of the manners of the first aspect, or the main control board or the interface board is configured to implement the method provided in the second aspect or any one of the manners of the second aspect, or at least one module is configured to execute the method provided in the third aspect or any one of the manners of the third aspect.

[0046] According to a seventh aspect, there is provided a communication system, comprising an Ethernet device configured to perform the method provided in the first aspect or any one of the manners of the first aspect, or to perform the method provided in the second aspect or any one of the manners of the second aspect, or to perform the method provided in the third aspect or any one of the manners of the third aspect.

[0047] According to an eighth aspect, there is provided a computer-readable storage medium storing a computer program which, when executed, performs the method provided in the first aspect or any one of the manners of the first aspect, the method provided in the second aspect or any one of the manners of the second aspect, or the method provided in the third aspect or any one of the manners of the third aspect.

[0048] According to a ninth aspect, there is provided a computer program product, the computer program product comprising a program or code, which, when executed, performs the method provided in the first aspect or any one of the manners of the first aspect, the method provided in the second aspect or any one of the manners of the second aspect, or the method provided in the third aspect or any one of the manners of the third aspect.

[0049] According to a tenth aspect, a chip is provided, which, when executed, performs the method provided in the first aspect or any one of the manners of the first aspect, performs the method provided in the second aspect or any one of the manners of the second aspect, or performs the method provided in the third aspect or any one of the manners of the third aspect. The chip may be a control chip or a transfer chip, and the chip includes programmable logic circuitry and / or program instructions.

[0050] For the technical effects of the second to tenth aspects, please refer to the technical effects of the first aspect, and the details will not be described again in this specification.

[0051] In order to explain the technical solutions of the present application more clearly, the following briefly describes the accompanying drawings used in the embodiments. The accompanying drawings below are only the accompanying drawings of some embodiments of the present application, and it is obvious that those skilled in the art can still derive other technical solutions and accompanying drawings from these accompanying drawings of the present application without creative efforts. [Brief explanation of the drawings]

[0052] [Figure 1(a)] FIG. 1 is an illustration of a random error according to one embodiment of the present invention. [Figure 1(b)] FIG. 1 is an illustration of a random error according to one embodiment of the present invention. [Figure 2]FIG. 1 is a diagram of an interleaver processing process according to one embodiment of the present invention. [Figure 3] 2 is a schematic flowchart of a data transmission method according to an embodiment of the present invention; [Figure 4(a)] FIG. 2 is a diagram of an implementation of the physical layer of an Ethernet device, according to one embodiment of the present invention. [Figure 4(b)] FIG. 2 is a diagram of an implementation of the physical layer of an Ethernet device, according to one embodiment of the present invention. [Figure 4(c)] FIG. 2 is a diagram of an implementation of the physical layer of an Ethernet device, according to one embodiment of the present invention. [Figure 5] FIG. 2 is a diagram of a data processing process for interleaving according to one embodiment of the present invention. [Figure 6] FIG. 2 is a diagram of a data processing process for interleaving according to one embodiment of the present invention. [Figure 7(a)] FIG. 2 is a diagram of a data processing process for multiplexing according to one embodiment of the present invention. [Figure 7(b)] FIG. 2 is a diagram of a data processing process for multiplexing according to one embodiment of the present invention. [Figure 7(c)] FIG. 2 is a diagram of a data processing process for multiplexing according to one embodiment of the present invention. [Figure 8(a)] 2 is a schematic flowchart of a data receiving method according to an embodiment of the present invention; [Figure 8(b)] 2 is a schematic flowchart of a data receiving method according to an embodiment of the present invention; [Figure 9(a)] 1 is a schematic flowchart of a method for transmitting and receiving data by a PMA sublayer, in accordance with an embodiment of the present invention. [Figure 9(b)] 1 is a schematic flowchart of a method for transmitting and receiving data by a PMA sublayer, in accordance with an embodiment of the present invention. [Figure 9(c)] 1 is a schematic flowchart of a method for transmitting and receiving data by a PMA sublayer, in accordance with an embodiment of the present invention. [Figure 9(d)]1 is a schematic flowchart of a method for transmitting and receiving data by a PMA sublayer, in accordance with an embodiment of the present invention. [Figure 10] FIG. 2 is a diagram of the structure of an Ethernet device according to one embodiment of the present invention. [Figure 11] FIG. 2 is a diagram of the structure of an Ethernet device according to one embodiment of the present invention. [Figure 12] FIG. 2 is a diagram of the structure of an Ethernet device according to one embodiment of the present invention. [Figure 13] 1 is a diagram of a communication system according to one embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0053] In the communication transmission process, due to various reasons such as environmental interference and system errors, the data received by the data receiver may be inconsistent with the data transmitted by the data transmitter, where such inconsistency is also referred to as a bit error. It can be seen that bit errors are unavoidable in the communication transmission process. Bit errors can cause many problems. For example, bit errors present in key control signals exchanged between various devices in a network can cause system crashes, data loss, or other serious problems. In addition, the presence of bit errors significantly affects network communication delays, further affecting consumer experience in video viewing, online games, phone calls, and other activities. Therefore, the bit error rate (BER) is always an important performance indicator of a communication system. A smaller BER value at the data receiver indicates higher network transmission reliability.

[0054] To ensure high reliability of a communication system, certain requirements are usually placed on the BER of the communication system in the industry. For example, the Institute of Electrical and Electronics Engineers (IEEE) standard 802.3bs requires that the BER of data received by a data receiver for entering the media access control (MAC) sublayer must be 1×10 -13 However, after transmission over the network link is completed, when the data in the network enters the data receiver, the BER of the data is typically 2.4×10 -4 In this case, the data receiver can correct bit errors in the data stream through FEC to restore the data stream to the data that was to be transmitted. Since most bit errors can be removed through FEC, the BER of the processed data is significantly reduced.

[0055] The FEC effect is related to bit error distribution. When two data streams have different bit error distributions, even if the previous BER of the two data streams is the same, the subsequent BER of the two data streams will be different. The previous BER is the BER before FEC, and the subsequent BER is the BER after FEC. There are mainly two types of bit error distributions: random error and non-random error. For visual illustration, Figures 1(a) and 1(b) show examples of random error and non-random error, where b represents a bit in which the data is correct and x represents a bit in which a bit error occurs. Random error is embodied as bit errors being randomly distributed, as shown in Figure 1(a). Non-random error is embodied as multiple bit errors occurring in a short data sequence in a concentrated manner, as shown in Figure 1(b). Therefore, non-random errors are sometimes called burst errors. Burst errors are common in practical communication networks, such as consecutive bit errors caused by decision feedback equalization (DFE) and consecutive bit errors caused by fast fading due to the multipath effect of wireless information. As shown above, the current BER of the data in Figures 1(a) and 1(b) is the same, but different bit error distributions cause the data to have different BERs after FEC. Under most communication transmission conditions, based on the same previous FEC, the BER after burst errors is higher than that of random errors.

[0056] In the case of burst errors, an interleaver is usually introduced to further reduce the subsequent FEC. The use of an interleaver is shown in Figure 2. In Figure 2, Tx represents data to be input to an FEC encoder in a data transmitter. The data is encoded by the FEC encoder in the data transmitter and then input to an interleaver for interleaving. The data output by the interleaver is transmitted to a data receiver through a communication channel. The data is input to a deinterleaver in the data receiver for deinterleaving, and the deinterleaved data then enters an FEC decoder for decoding. Rx represents data output by the FEC decoder in the data receiver, and through FEC and interleaving, the BER of Rx is significantly reduced. The interleaver can be disposed in a PCS of an Ethernet device, for example, a PCS in an Ethernet PHY chip. That is, the PCS interleaves the data.

[0057] As explained above, with the development of Internet technology, the Ethernet data transmission rate continues to increase, and therefore the BER at the data receiver further increases. In this case, the interleaving performed by the PCS usually cannot meet the requirements for reducing the BER. In this case, if the PCS circuit is redesigned, it means that the Ethernet PHY chip must also be redesigned, which causes high costs.

[0058] The present application provides a data transmission method. The method is performed by an Ethernet device at a data transmitting side. In this method, the function of a PMA sublayer of the Ethernet device is extended, and the PMA sublayer interleaves data. Specifically, the PMA sublayer obtains an FEC-encoded data stream and performs a data processing process 1 on the data stream to obtain an interleaved data stream. The data processing process 1 includes performing interleaving in a first interleaving manner, where the interleaving type of the first interleaving manner is specifically symbol interleaving or convolutional interleaving. According to this method, the PMA sublayer performs symbol interleaving or convolutional interleaving on the data stream. The specific manner in which the PMA sublayer performs interleaving can be flexibly designed to ensure that actual requirements for reducing the BER in a network are met. In addition, since the expansion of the PMA sublayer is relatively easy, the existing PCS does not need to be modified in the design of the PMA sublayer, and even when the PMA sublayer is in a pluggable module, the master chip of the existing Ethernet physical PHY layer does not need to be modified in the design of the PMA sublayer, so that the requirement for reducing the BER in high-rate data transmission scenarios is met while research and development costs are reduced as much as possible.

[0059] 3 is a schematic flowchart of a data transmission method 300 according to an embodiment of the present application. For example, the method may include the following steps:

[0060] Step 301: A physical medium connection PMA sublayer of an Ethernet device obtains a data stream, where the data stream is a forward error correction (FEC) encoded data stream.

[0061] The Ethernet device may be an Ethernet transfer device such as an Ethernet chip, a switch or a router, or a pluggable optical or electrical module in the Ethernet. In this case, the Ethernet device is an Ethernet device at the data transmitting side. It is easy to understand that at some moments, the Ethernet device may alternatively act as an Ethernet device at the data receiving side to perform the method at the data receiving side.

[0062] In this embodiment of the present application, the Ethernet physical layer may be further divided into multiple sublayers based on major functions. These sublayers include, but are not limited to, a PCS, a PMA sublayer, a physical medium dependent (PMD) sublayer, etc. Specific implementations of these sublayers may be electronic circuits. The PCS is responsible for performing encoding, scrambling, and other processing on data, and FEC encoding is also performed in the PCS. In this embodiment of the present application, there may be three implementations of the Ethernet physical layer. As shown in FIG. 4(a), in the first mode, the Ethernet physical layer includes a PCS, a PMA sublayer, and a PMD sublayer, and these three sublayers are all included in the PHY chip. This mode is applicable to copper cable transmission, backplane transmission, and co-packaged optics (CPO) transmission scenarios. As shown in Figure 4(b), in the second style, the Ethernet physical layer includes a PCS, a PMA sublayer, and a PMD sublayer, where the PCS and one PMA sublayer are included in the PHY chip, and the other PMA sublayer and PMD sublayer are included in a pluggable optical module or a pluggable electrical module. The pluggable optical module or the pluggable electrical module is independent from the PHY chip in a circuit implementation and is connected to the PHY chip through an interface. The interface type shown in Figure 4(b) is AUI. It will be understood that the interface type may further include another type, for example, CEI. This style is generally applicable to optical fiber transmission or electrical transmission scenarios, and is also applicable to scenarios using concatenated codes.As shown in Figure 4(c), in a third manner, the Ethernet physical layer includes a PCS, a PMA sublayer, a PMD sublayer, a DTE_XS, and a physical layer device extender sublayer (PHY_XS), where the DTE_XS and the first PMA sublayer are included in the PHY chip, and the second PMA sublayer, PHY_XS, PCS, the third PMA sublayer, and the PMD sublayer are included in a pluggable optical module or a pluggable electrical module. The pluggable optical module or the pluggable electrical module is also independent from the PHY chip in a circuit implementation and is connected to the PHY chip through an interface. The interface type shown in Figure 4(c) is AUI. It will be understood that the interface type may further include another type, for example, CEI.

[0063] In this embodiment of the present application, the PMA sublayer that performs interleaving in the first interleaving manner may be the PMA sublayer in FIG. 4(a), the PMA sublayer in the pluggable optical module or pluggable electrical module in FIG. 4(b), the PMA sublayer in the PHY chip in FIG. 4(c), or the second PMA sublayer in the pluggable optical module or pluggable electrical module in FIG. 4(c), i.e., the PMA sublayer adjacent to the PCS and PMD.

[0064] When the PMA sublayer that performs interleaving in the first interleaving manner is a PMA sublayer in a pluggable optical module or a pluggable electrical module, only the PMA sublayer in the pluggable module needs to be designed to implement the method in this embodiment of the present application, and the PHY chip does not need to be modified, so that existing PHY chips can be compatible. In addition, the same PHY chip can be matched with multiple types of different pluggable optical modules or pluggable electrical modules to implement multiple different interleaving manner extensions. When the Ethernet data transmission rate further increases in the future, the error correction performance can be upgraded by directly replacing the pluggable module.

[0065] When the PMA sublayer that performs interleaving in the first interleaving manner is a PMA sublayer in a PHY chip, to implement the method in this embodiment of the present application, only the PMA sublayer in the chip needs to be redesigned, and the existing PCS can still be reused. As described above, the function of the PCS is complex, but the function of the PMA sublayer is simple, and the PMA sublayer is easier to expand. Therefore, according to the method in this embodiment of the present application, modifications to the PHY chip can be reduced as much as possible.

[0066] In any manner, the PMA sublayer that performs interleaving in a first interleaving manner receives a data stream, which may mean that the PMA sublayer receives the data stream from a previous sublayer in the transmission direction of the data stream. Referring to the above three physical layer implementations, the previous sublayer may be PCS, PMA, or DTE_XS. When the PMA sublayer is separated from the previous sublayer in a circuit implementation, the PMA sublayer receives the data stream from the previous sublayer through an interface, where the interface may be AUI, CEI, etc.

[0067] In any manner, the rate of the interface for acquiring the data stream by the PMA sublayer is at least one of the following, but this is not limited herein: 200 Gbps, 400 Gbps, or another rate value.

[0068] In any manner, the data stream obtained by the PMA sublayer may be one data stream or multiple data streams.

[0069] In any manner, after obtaining the data stream, the PMA sublayer may first divide the single data stream. For example, when the rate of the interface for receiving the data stream by the PMA sublayer is 400 Gbps, the PMA sublayer may first divide the data stream into two groups of data streams and then perform interleaving separately. This facilitates subsequent breakout processing in the pluggable module.

[0070] Step 302: The PMA sublayer performs a data processing process 1 on the data stream to obtain an interleaved data stream, where the first data processing process 1 includes performing interleaving in a first interleaving manner.

[0071] As described above, the data stream obtained by the PMA sublayer may be one data stream or multiple data streams, and correspondingly, the interleaving performed in the first interleaving manner may be interleaving within a data stream or interleaving between data streams.

[0072] In this embodiment of the present application, the interleaving style may have multiple attributes. The interleaving type is an attribute of the interleaving style, and the interleaving type of the first interleaving style is symbol interleaving or convolutional interleaving. Symbol interleaving is sometimes called block interleaving. Symbol interleaving and convolutional interleaving basically achieve the same error correction performance. However, when achieving the same error correction performance, the two styles may differ in delay and power consumption.

[0073] Interleave depth is also an attribute of the interleaving style. It indicates the amount of FEC codewords involved in the interleaving. The amount of FEC codewords involved in the interleaving affects the error correction performance.

[0074] FIG. 5 is an example diagram of a data processing style for symbol interleaving.

[0075] As shown in FIG. 5, multiple FEC-encoded codewords are obtained from the data stream to be interleaved as codewords participating in the interleaving, e.g., codeword A, codeword B, codeword C, and codeword D in the figure. When the codewords participating in the interleaving are from the same data stream, interleaving is performed within the data stream. When the codewords participating in the interleaving are from different data streams, interleaving is performed between the data streams. Each codeword includes p FEC-encoded symbols, and each symbol includes q bits, i.e., each codeword includes p×q bits. For example, the length of each symbol may be 10 bits, i.e., symbol interleaving is performed at a 10-bit granularity. As shown in the figure, four codewords are selected from the data stream to be interleaved to participate in the interleaving, i.e., the interleaving depth is 4 codewords. When the codewords are RS codewords, the interleaving depth may be referred to as 4×RS. The four codewords are alternately distributed across n data streams on n lanes at the granularity of the output symbols, so that adjacent symbols in each data stream come from different codewords, i.e., symbols from the four codewords alternate, forming an interleaved data sequence, i.e., interleaved lane 1 to interleaved lane n shown in the figure.

[0076] FIG. 6 is an example of a diagram of a data processing style of convolutional interleaving. Convolutional interleaving involves several design parameters, including the number of delay lines, delay block length, and delay block number. As shown in FIG. 6, several FEC-encoded code words are obtained from the data stream to be interleaved to participate in the interleaving, including cwA, cwB, cwC, and cwD. The interleaving depth is four code words, that is, four code words, i.e., cwA, cwB, cwC, and cwD, are selected from the data stream to be interleaved. The number of delay lines is four, that is, four data lines, line0, 1, 2, and 3, from top to bottom. In FIG. 6, D represents a delay block, and each delay block is formed by a shift register (LFSR) and can temporarily store specific data, and the number of delay blocks in each delay line is different. Each of the input and output sides of the interleaver has a switchable connection switch for connecting a specific delay line. The data of the FEC codeword enters the convolutional interleaver column by column at the granularity of the delay block length, e.g., a, b, c, and d in FIG. 6. When the length of the FEC codeword is the same as the delay block length, the granularity at which the data enters the convolutional interleaver is the length of the FEC codeword. When the length of the FEC codeword is different from the delay block length and the data of the FEC codeword enters the convolutional interleaver, the data needs to be adjusted to enter the convolutional interleaver at the granularity of the delay block length. Every time the input side inputs data with the delay block length, the output side also outputs data with the delay block length. The switchable connection switches on both sides then switch to the next delay line, and the round-robin is performed in the order {line 0, line 1, line 2, line 3, line 0, line 1, line 2, line 3, line 0, line 1, ...}.In addition, the x on the output side in Figure 6 represents the data that precedes the four code words and is stored in the delay block. In addition, although convolutional interleaving of one data stream is used as an example in Figure 6, the process of convolutional interleaving between multiple data streams is similar to that shown in Figure 6, with the difference being that the code words involved in the interleaving are from multiple data streams. Details will not be described herein.

[0077] In this embodiment of the present application, the first interleaving manner performed by the PMA sublayer can be implemented through the above-mentioned symbol interleaving or convolutional interleaving. In some cases, in the process in which the PMA sublayer performs interleaving, the availability of an alignment marker (AM) needs to be ensured so that data synchronization can still be performed at the data receiving side based on the AM.

[0078] In any manner, the data stream obtained by the PMA sublayer from the previous sublayer may be a data stream on which interleaving has been performed, i.e., another sublayer before the PMA sublayer may have performed interleaving on the data stream. In particular, the data stream obtained by the PMA sublayer is a data stream obtained by performing data processing process 2, which includes performing interleaving in a second interleaving manner. Data processing process 2 may be performed by another sublayer before the PMA sublayer. As described above, the sublayer performing data processing process 2 and the PMA sublayer may be directly adjacent to each other or may not be directly adjacent to each other, i.e., the sublayers are separated by another sublayer. In some cases, the PCS or DTE_XS may perform a second interleaving manner. The second interleaving manner may alternatively be implemented through the above-mentioned symbol interleaving or convolutional interleaving. That is, there is no conflict between the interleaving performed by the PMA sublayer and the interleaving performed by another sublayer before the PMA sublayer. In particular, when the PMA sublayer is in a pluggable optical module or a pluggable electrical module, the PCS or DTE_XS in the PHY chip do not need to be modified, so existing PHY chips can be compatible, and only the PMA sublayer in the pluggable module needs to be designed to meet the requirements for reducing the BER in the network. When the PMA sublayer is in the PHY chip, the existing PCS or DTE_XS can also be reused, and only the PMA sublayer in the chip needs to be redesigned to meet the requirements for reducing the BER in the network, making it relatively easy to extend.

[0079] In any manner, the first interleaving manner may be different from the second interleaving manner. Specifically, an interleaving change is performed through the interleaving performed by the PMA sublayer. To some extent, it is possible that the interleaving performed by the PMA sublayer covers the interleaving performed by another previous sublayer. Through this interleaving change, a new error correction design can be flexibly implemented in the PMA sublayer, thereby better meeting the requirement to reduce the BER resulting from increasing Ethernet data transmission rates without modifying another previous sublayer or even modifying the master chip of the entire Ethernet PHY layer.

[0080] In any manner, the interleaving change specifically involves the interleaving depth of the first interleaving manner being different from that of the second interleaving manner. An example is used in which the PCS performs 2×RS interleaving. The PMA sublayer then performs interleaving to a depth of 4×RS. That is, the PMA sublayer implements deeper interleaving, and error correction requirements in a scenario in which the speed of a single physical lane reaches 200 Gbps can be met.

[0081] In any manner, the interleaving type of the first interleaving manner can be the same as or different from that of the second interleaving manner. For example, both the PMA sublayer and the PCS sublayer perform symbol interleaving at 10-bit granularity. In another example, the PCS sublayer performs symbol interleaving and the PMA sublayer performs convolutional interleaving.

[0082] In any manner, before performing interleaving in a first interleaving manner, the PMA sublayer may perform deinterleaving for a second interleaving manner, or may not perform deinterleaving for the second interleaving manner. That is, the PMA sublayer may first perform deinterleaving for the interleaving performed by another sublayer before the PMA sublayer, and interleaving within the PMA sublayer is then performed. Alternatively, the PMA sublayer may not perform deinterleaving for the interleaving performed by another sublayer before the PMA sublayer, and interleaving within the PMA sublayer is performed directly. An example in which the PCS performs 2×RS interleaving is used. The PMA sublayer waits for the first obtained data of two codewords, and then begins to perform interleaving on the waiting data of two codewords and the data of the later arriving two codewords. The total number of codewords involved in the interleaving is 4, that is, the interleaving depth is 4×RS.

[0083] In any manner, the data processing process 1 performed on the data stream by the PMA sublayer further includes bit multiplexing or symbol group multiplexing. As described above, after data processing, the PMA sublayer outputs data to the next sublayer, for example, the PMD sublayer. Therefore, it is necessary to ensure that the output data adapts to the number of lanes connected to the next sublayer in the PMA sublayer. In particular, through bit multiplexing or symbol group multiplexing, the data to be output can be processed to adapt to the number of lanes connected to the next sublayer. The bit multiplexing or symbol group multiplexing can be included in the data processing process corresponding to the first interleaving manner. Specifically, in the process of performing interleaving by the PMA sublayer, the bit multiplexing or symbol group multiplexing is also performed on the data, taking into account the number of lanes connected to the next sublayer. Alternatively, the bit multiplexing or symbol group multiplexing can be performed after the data processing process corresponding to the first interleaving manner. That is, the PMA sublayer first performs an interleaving process and then performs bit multiplexing or symbol group multiplexing on the data so that the data stream adapts to the amount of lanes connected to the next sublayer.

[0084] 7(a) to 7(c) are diagrams of an example of a data processing manner for symbol group multiplexing. For example, there are two initial data streams involved in the multiplexing, namely, data stream 1 and data stream 2. The number of initial data streams involved in the multiplexing may be any value. This is not limited herein. In symbol group multiplexing, each data stream is divided at the granularity of a symbol, and the length of the symbol may be, for example, 20 bits or 40 bits, and at least two symbols of each data stream may form a symbol group. Then, data from the two data streams are multiplexed alternately at the granularity of the symbol group into lanes in a round-robin manner, where a lane is, for example, a multiplexed lane in FIG. 7(a). The multiplexed lanes correspond to the lanes of the interface between the sublayers. When the interface between two sublayers includes four lanes and multiplexing is performed in the manner shown in FIG. 7(a), it is easy to understand that eight data streams are multiplexed into four multiplexed lanes. In this embodiment of the present application, in the symbol group multiplexing performed by the PMA sublayer, the amount of input data streams and the amount of multiplexed lanes can be determined based on the actual situation. This is not limited herein. In addition, in symbol group multiplexing, when data from two data streams are multiplexed alternately into one lane in a round-robin manner at the granularity of a symbol group, an exchange between the positions of data in one of the data streams can be further included. For example, the positions of the two symbols can be exchanged as shown in FIG. 7(b), or the position of data in one of the data streams can be delayed by one symbol as shown in FIG. 7(c), forming a mismatch or another operation, where x is the previous or subsequent symbol that appears due to the delay. In bit multiplexing, the data streams involved in the multiplexing are divided at the granularity of one bit. Other operations are similar to those in symbol group multiplexing. Details will not be described again in this specification.

[0085] In any manner, before the PMA sublayer performs convolutional interleaving, a step of performing bit multiplexing or symbol group multiplexing on the data stream to adjust the amount of data stream in convolutional interleaving may alternatively be added. For specific operations, please refer to Figures 7(a) to 7(c). The details will not be described again in this specification.

[0086] In any manner, the data processing process 1 performed on the data stream by the PMA sublayer may further include other processes, such as one or more of bit demux or symbol-group demux, and AM lock and deskew. As described above, the data stream obtained by the PMA sublayer is from a previous sublayer, which may be, for example, PCS, DTE_XS, or another PMA sublayer. The PMA sublayer and the previous sublayer may or may not be separated on the circuit. When separated on the circuit, the PMA sublayer and the previous sublayer may be connected through an interface. Interface types include, but are not limited to, AUI, CEI, etc. Before the data stream is transmitted from the previous sublayer to the PMA sublayer, bit multiplexing or symbol group multiplexing may be performed on the data stream to accommodate the amount of lanes between the sublayers. In addition, when the data stream is transmitted through the interface, the data of the data stream may be out of lock or skew. Therefore, the PMA sublayer needs to recover the received data stream. For example, in the implementation of the Ethernet physical layer shown in FIG. 4(b), the PMA sublayer in the pluggable module receives the data stream through the AUI, the PMA sublayer in the PHY chip performs bit multiplexing or symbol group multiplexing on the data stream, and the PMA sublayer in the pluggable module needs to first perform corresponding bit demultiplexing or symbol group demultiplexing, and perform AM lock and deskew on the data that is out of lock or skew range and is transmitted through the AUI interface to recover the data stream transmitted to the lane by the previous sublayer. For example, when the previous sublayer is a PCS layer, the PCS lane data stream is recovered.In some cases, bit demultiplexing or symbol group demultiplexing, as well as alignment marker locking and deskewing, may be performed before the above process of performing interleaving in a first interleaving manner. That is, the PMA sublayer first recovers the data stream from the previous sublayer and then performs subsequent interleaving. In some cases, the granularity of bit demultiplexing may be 1 bit, and the granularity of symbol group demultiplexing may be 20 bits or 40 bits. In some cases, in the above deskewing process, data may be aligned to AM or to symbol boundaries. For example, data may be aligned to symbol boundaries at 10-bit granularity, data may be aligned to symbol boundaries at 20-bit granularity, or data may be aligned to symbol boundaries at 40-bit granularity.

[0087] Optionally, the PMA sublayer may further perform FEC encoding again to improve data error correction performance.

[0088] In any manner, the rate of a single physical lane of the data stream obtained by performing interleaving by the PMA sublayer is 200 Gbps. It is easy to understand that 200 Gbps is not the exact value of the lane rate at any instant, but rather a value that can freely fluctuate within a range common in the art.

[0089] The above describes a method performed by an Ethernet device at a data transmitting side. An Ethernet device at a data receiving side needs to execute the method in cooperation with the Ethernet device at the data transmitting side. FIG. 8(a) shows a data receiving method. After the PMA sublayer of the Ethernet device at the data transmitting side performs interleaving, the PMA sublayer of the Ethernet device at the data receiving side needs to perform a deinterleaving process accordingly. This method is performed by an Ethernet device. The Ethernet device may be an Ethernet forwarding device such as an Ethernet chip, a switch, or a router, and an Ethernet pluggable optical or electrical module. The PMA sublayer of the Ethernet device at the data receiving side obtains a data stream and performs a data processing process 31 on the data stream to obtain a deinterleaved data stream, where the data processing process 31 includes performing deinterleaving in a first deinterleaving manner, and the deinterleaving type of the first deinterleaving manner is specifically symbol deinterleaving or convolutional deinterleaving. In this method, the expansion of the PMA sublayer is relatively simple, so that the existing PCS does not need to be modified in the design of the PMA sublayer, and even when the PMA sublayer is in a pluggable module, the master chip of the existing Ethernet physical PHY layer does not need to be modified in the design of the PMA sublayer, so that the requirement for reducing the BER in high-rate data transmission scenarios is met while research and development costs are reduced as much as possible.

[0090] 8(a) is a schematic flowchart of a data transmission method according to an embodiment of the present application. For example, the method may include the following steps:

[0091] Step 8011: A PMA sublayer of an Ethernet device obtains a data stream, where the data stream is a forward error correction (FEC) encoded data stream.

[0092] The Ethernet device may be an Ethernet transfer device such as an Ethernet chip, a switch or a router, or a pluggable optical or electrical module in the Ethernet. In this case, the Ethernet device is an Ethernet device at the data receiving side. It is easy to understand that at some moments, the Ethernet device may alternatively act as an Ethernet device at the data transmitting side to perform the method at the data transmitting side.

[0093] For the implementation of the Ethernet physical layer in the Ethernet device at the data receiving side, please also refer to the implementation shown in Figures 4(a), 4(b), and 4(c), and the details will not be described again in this specification.

[0094] In this embodiment of the present application, the PMA sublayer that performs deinterleaving in the first deinterleaving manner may be the PMA sublayer in FIG. 4(a), the PMA sublayer in the pluggable optical module or pluggable electrical module in FIG. 4(b), the PMA sublayer in the PHY chip in FIG. 4(c), or the second PMA sublayer in the pluggable optical module or pluggable electrical module in FIG. 4(c), i.e., the PMA sublayer adjacent to the PCS and PMD.

[0095] In any manner, the PMA sublayer obtains a data stream, which may mean that the PMA sublayer obtains the data stream from a previous sublayer in the transmission direction of the data stream. Referring to the above three physical layer implementations, the previous sublayer may be a PMD. When the PMA sublayer is separated from the previous sublayer in a circuit implementation, the PMA sublayer obtains the data stream from the previous sublayer through an interface, where the interface may be an AUI, a CEI, etc.

[0096] In any manner, the data stream obtained by the PMA sublayer may be one data stream or multiple data streams.

[0097] Step 8012: The PMA sublayer performs a data processing process 31 on the data stream to obtain a deinterleaved data stream, where the data processing process 31 includes performing deinterleaving in a first deinterleaving manner.

[0098] As described above, the data stream obtained by the PMA sublayer may be one data stream or multiple data streams, and correspondingly, the interleaving performed in the first deinterleaving manner may be deinterleaving within a data stream or deinterleaving between data streams.

[0099] In this embodiment of the present application, the deinterleaving type of the first deinterleaving manner is symbol deinterleaving or convolutional deinterleaving. The data processing processes of symbol deinterleaving and convolutional deinterleaving are deinterleaving processes corresponding to the data processing processes shown in Figures 5 and 6, respectively. Their details will not be described in this specification.

[0100] In any manner corresponding to the first interleaving manner, deinterleaving is performed in the first deinterleaving manner at 10-bit granularity, or the PMA sublayer performs 10-bit symbol deinterleaving.

[0101] In an optional manner, the data processing process 31 performed by the PMA sublayer on the receiving side also includes bit multiplexing or symbol group multiplexing, so that the amount of the output data stream can be adapted to the amount of data lanes between the PMA sublayer and the next sublayer in the data transmission direction. The specific implementation form is similar to the bit multiplexing or symbol group multiplexing performed by the PMA sublayer on the transmitting side. Details will not be described again in this specification. The granularity of the bit multiplexing is 1 bit, and the granularity of the symbol group multiplexing can be 20 bits or 40 bits. In some cases, the bit multiplexing or symbol group multiplexing process can be performed after the above-mentioned process of performing deinterleaving in the third interleaving manner, or the bit multiplexing or symbol group multiplexing process can be included in the above-mentioned process of performing deinterleaving in the third interleaving manner.

[0102] In an optional manner, the data processing process 31 performed on the data stream by the PMA sublayer further includes bit demultiplexing or symbol group demultiplexing, where the granularity of bit demultiplexing is 1 bit, and the granularity of symbol group demultiplexing can be 20 bits or 40 bits.

[0103] In an optional manner, the data processing processes 31 performed on the data stream by the PMA sublayer further include AM lock and deskew.

[0104] The data stream from the previous sublayer can be restored through bit demultiplexing or symbol group demultiplexing, and alignment marker locking and deskewing. For example, the previous sublayer is a PMD. In some cases, the bit demultiplexing or symbol group demultiplexing and alignment marker locking and deskewing processes are performed before the deinterleaving process in the first deinterleaving mode. That is, the data stream from the previous sublayer is restored and deinterleaving is performed through the bit demultiplexing or symbol group demultiplexing and alignment marker locking and deskewing processes.

[0105] In any manner, after performing deinterleaving on the data stream in the data processing process 31, the PMA sublayer may further reinterleave the deinterleaved data stream in a second interleaving manner to obtain a reinterleaved data stream. This is to cooperate with the process of performing deinterleaving by the existing PCS or DTE_XS in the Ethernet device on the receiving side, so that the existing PCS or DTE_XS does not need to be improved to fit the existing PHY chip as much as possible.

[0106] In any mode, the deinterleaving depth of the first deinterleaving mode is 4×RS.

[0107] In an optional manner, the PMA sublayer may further perform FEC decoding to improve data error correction performance.

[0108] In addition, further implementation details of the Ethernet device on the receiving side may cooperate with further implementation details of the above Ethernet device on the transmitting side, the details of which will not be described herein.

[0109] 8(b) shows another data receiving method. This method is performed by an Ethernet device. The Ethernet device may be an Ethernet chip, an Ethernet transfer device such as a switch or router, or a pluggable optical or electrical module in Ethernet. After the PMA sublayer of the Ethernet device at the data transmitting side performs interleaving, the interleaving pattern of the data stream is changed. The PMA sublayer of the Ethernet device at the data receiving side needs to perform a corresponding interleaving modification to change the interleaving pattern of the data stream to an interleaving pattern that is compatible with the deinterleaving process performed by another sublayer, thereby avoiding modifications to the PHY chip. For example, when an Ethernet PHY chip performs 2×RS deinterleaving on a data stream, the PMA sublayer may change the interleaving pattern for the acquired data stream to 2×RS interleaving, so that the correct data stream can be acquired by the PHY chip performing 2×RS deinterleaving on the data stream. The PMA sublayer of the Ethernet device at the data receiving side receives a data stream and performs a data processing process 32 on the data stream to obtain an interleaved data stream, where the data processing process 32 includes performing interleaving on the data stream, and the interleaving type of the interleaving is symbol interleaving or convolutional interleaving. In this manner, the PMA sublayer of the Ethernet device at the data receiving side performs interleaving to change the interleaving manner of the data stream to an interleaving manner that is compatible with the deinterleaving process performed by another sublayer. That is, the interleaving change is implemented, and modifications to the PHY chip can be avoided, while error correction performance is improved and the requirement for reducing the BER is reduced in the network.

[0110] 8(b) is a schematic flowchart of a data transmission method according to an embodiment of the present application. For example, the method may include the following steps:

[0111] Step 8021: A PMA sublayer of an Ethernet device obtains a data stream, where the data stream is a forward error correction (FEC) encoded data stream.

[0112] The Ethernet device may be an Ethernet transfer device such as an Ethernet chip, a switch or a router, or a pluggable optical or electrical module in the Ethernet. In this case, the Ethernet device is an Ethernet device at the data receiving side. It is easy to understand that at some moments, the Ethernet device may alternatively be used as an Ethernet device at the data transmitting side to perform the method at the data transmitting side.

[0113] For the implementation of the Ethernet physical layer in the Ethernet device at the data receiving side, please also refer to the implementation shown in Figures 4(a), 4(b), and 4(c), and the details will not be described again in this specification.

[0114] In this embodiment of the present application, the PMA sublayer that performs deinterleaving in the first deinterleaving manner may be the PMA sublayer in FIG. 4(a), the PMA sublayer in the pluggable optical module or pluggable electrical module in FIG. 4(b), the PMA sublayer in the PHY chip in FIG. 4(c), or the second PMA sublayer in the pluggable optical module or pluggable electrical module in FIG. 4(c), i.e., the PMA sublayer adjacent to the PCS and PMD.

[0115] In any manner, the PMA sublayer obtains a data stream, which may mean that the PMA sublayer obtains the data stream from a previous sublayer in the transmission direction of the data stream. Referring to the above three physical layer implementations, the previous sublayer may be a PMD. When the PMA sublayer is separated from the previous sublayer in a circuit implementation, the PMA sublayer obtains the data stream from the previous sublayer through an interface, where the interface may be an AUI, a CEI, etc.

[0116] In any manner, the data stream obtained by the PMA sublayer may be one data stream or multiple data streams.

[0117] Step 8012: The PMA sublayer performs a data processing process 32 on the data stream to obtain an interleaved data stream, where the data processing process 32 includes performing interleaving on the data stream.

[0118] As described above, the data stream obtained by the PMA sublayer may be one data stream or multiple data streams, and correspondingly, the interleaving may be interleaving within a data stream or interleaving between data streams.

[0119] In this embodiment of the present application, the interleaving type of the interleaving is symbol interleaving or convolutional interleaving. For the data processing process of symbol interleaving or convolutional interleaving, please refer to the data processing process shown in Figure 5 and Figure 6. The details thereof will not be described again in this specification.

[0120] In any manner, symbol interleaving is performed at a granularity of 10 bits.

[0121] In any manner, the PCS or DTE_XS performs deinterleaving on the interleaved data stream.

[0122] In any manner, the interleaving depth of the interleaving is 2xRS. When the PCS or DTE_XS in the Ethernet PHY chip performs 2xRS deinterleaving on the data stream, the PMA sublayer can change the interleaving manner for the obtained data stream to 2xRS interleaving, so that the correct data stream can be obtained by the PHY chip performing 2xRS deinterleaving on the data stream.

[0123] In an optional manner, the data processing process 32 includes performing deinterleaving in a first deinterleaving manner. The deinterleaving type of the first deinterleaving manner is, in particular, symbol deinterleaving or convolutional deinterleaving to obtain a deinterleaved data stream. The first deinterleaving manner may be 4×RS deinterleaving. For further details about the process of performing deinterleaving in the first deinterleaving manner, please refer to the related description in the data transmission method shown in FIG. 8(a). The details will not be described again in this specification.

[0124] In an optional manner, the data processing process 32 includes bit demultiplexing or symbol group demultiplexing, where the granularity of the bit demultiplexing is 1 bit, and the granularity of the symbol group demultiplexing can be 20 bits or 40 bits.

[0125] In an optional manner, the data processing process 32 includes alignment marker AM locking and deskewing.

[0126] The data stream acquired by the PMA sublayer is from a previous sublayer in the data transmission direction, which may be, for example, a PMD sublayer. Through bit demultiplexing or symbol group demultiplexing, and alignment marker locking and deskewing, the data stream from the previous sublayer can be restored. In some cases, the processing in the first deinterleaving manner can be further implemented in the above processing of bit demultiplexing or symbol group demultiplexing, and alignment marker locking and deskewing. That is, through the processing of bit demultiplexing or symbol group demultiplexing, and alignment marker locking and deskewing, the data stream from the previous sublayer is restored and deinterleaving is implemented.

[0127] In an optional manner, the data processing process 32 includes bit multiplexing or symbol group multiplexing. The granularity of the bit multiplexing may be 1 bit, and the granularity of the symbol group multiplexing may be 20 bits or 40 bits. Through bit multiplexing or symbol group multiplexing, the amount of data stream output by the PMA sublayer can be adapted to the amount of data lanes between the PMA and the next sublayer in the data transmission direction. In some cases, the bit multiplexing or symbol group multiplexing process may be performed after the above-mentioned process of performing deinterleaving in the third interleaving manner, or the bit multiplexing or symbol group multiplexing process may be included in the above-mentioned process of performing deinterleaving in the third interleaving manner.

[0128] In an optional manner, the PMA sublayer may further perform FEC decoding to improve data error correction performance.

[0129] In addition, further implementation details of the Ethernet device on the receiving side may cooperate with further implementation details of the above Ethernet device on the transmitting side, the details of which will not be described herein.

[0130] In addition, in the method shown in FIG. 8(a) or FIG. 8(b), in the Ethernet device on the receiving side, after the interleaving change in the PMA sublayer, the data stream can immediately be AUI lane data or PCS lane data.

[0131] In this embodiment of the present application, the main steps performed by the PMA sublayers at the receiving and transmitting sides can be explained by using the examples in Figures 9(a) to 9(d).

[0132] When this method is applicable to the physical layer implementation shown in Figure 4(b), the PMA sublayer is in a pluggable optical module or a pluggable electrical module and is connected to the previous sublayer through an interface. The main steps performed by the PMA sublayer on the data transmitting side are shown on the left side of Figure 9(a), and the main steps performed by the PMA sublayer on the data receiving side are shown on the right side of Figure 9(a), where the arrows in the figure indicate the data transmission direction.

[0133] On the data transmission side, the PMA recovers the PCS lane data by performing the first two steps, i.e., bit demultiplexing or symbol group demultiplexing, and AM locking and deskewing. In the subsequent interleaving step, i.e., distribution and interleaving, a new symbol interleaving or convolutional interleaving is performed on the PCS lane data. The interleaving step can be implemented in different ways: deinterleaving can be first performed on the interleaving performed by the PCS to recover the complete RS codeword; after all four codewords are received, symbol interleaving or convolutional interleaving is then performed, and the required number of lanes is obtained through distribution. Alternatively, deinterleaving may not be performed; i.e., the complete RS codeword is not recovered, and the PCS lane data is directly arranged in a specific order to obtain the required number of lanes for output. For the interleaving step, please refer to the related description of the method shown in Figures 5 and 6. Details will not be described again here. In addition, a symbol group multiplexing or bit multiplexing step is further included in Figure 9(a), which is used to combine data into the amount of data lanes required by the next sublayer. For other details in Figure 9(a), please refer to the related description in the data transmission method shown in Figure 3. Details will not be described again in this specification. In addition, each step in the data receiving side corresponds to each step in the data transmitting side, and you may refer to the related description in the data receiving method shown in Figure 8(a) or Figure 8(b). Details will not be described again in this specification.

[0134] When this method is applicable to the physical layer implementation shown in FIG. 4(b), the PMA sublayer is in a pluggable optical module or a pluggable electrical module and is connected to the previous sublayer through an interface. The main steps performed by the PMA sublayer on the data transmitting side may alternatively be shown on the left side of FIG. 9(b), and the main steps performed by the PMA sublayer on the data receiving side may alternatively be shown on the right side of FIG. 9(b), where the arrows in the diagram indicate the data transmission direction. Compared with FIG. 9(a), the main difference in the steps shown in FIG. 9(b) is that the symbol group multiplexing or bit multiplexing process is included in the interleaving step, and the number of lanes obtained through interleaving dispersion is equal to the number of lanes required by the next sublayer. The number of lanes can be the number of physical lanes or the number of PCS lanes. Therefore, a separate multiplexing step is not required. Each step on the data receiving side corresponds to each step on the data transmitting side. Details will not be described again in this specification.

[0135] When this method is applicable to the implementation of the physical layer shown in FIG. 4(b), the PMA sublayer is in a pluggable optical module or a pluggable electrical module and is connected to the previous sublayer through an interface. The main steps performed by the PMA sublayer on the data transmitting side may alternatively be shown on the left side of FIG. 9(c), and the main steps performed by the PMA sublayer on the data receiving side may alternatively be shown on the right side of FIG. 9(c), where the arrows in the diagram indicate the data transmission direction. Compared with FIG. 9(a), the main difference in the steps shown in FIG. 9(c) is that the PMA layer performs an FEC encoding step. Each step on the data receiving side corresponds to each step on the data transmitting side. Details will not be described again in this specification.

[0136] When this method is applicable to the implementation of the physical layer shown in FIG. 4(b), the PMA sublayer is in a pluggable optical module or a pluggable electrical module and is connected to the previous sublayer through an interface. The main steps performed by the PMA sublayer on the data transmitting side may alternatively be shown on the left side of FIG. 9(d), and the main steps performed by the PMA sublayer on the data receiving side may alternatively be shown on the right side of FIG. 9(d), where the arrows in the diagram indicate the data transmission direction. Compared with FIG. 9(b), the main difference in the steps shown in FIG. 9(d) is that the PMA layer performs an FEC encoding step. Each step on the data receiving side corresponds to each step on the data transmitting side. Details will not be described again in this specification.

[0137] When this method is applicable to the physical layer implementation shown in FIG. 4(a) or 4(c), the PMA sublayer is not connected to the previous sublayer through an interface, and the PMA sublayer can directly obtain lane data. Therefore, compared with FIG. 9(a) to FIG. 9(d), when this method is applicable to the physical layer implementation shown in FIG. 4(a) or 4(c), the main steps performed by the PMA sublayer on the data receiving side do not include the two steps of bit demultiplexing or symbol group demultiplexing and AM locking and deskewing. Similarly, the main steps performed by the PMA sublayer on the data transmitting side do not include the two steps of bit demultiplexing or symbol group demultiplexing and AM locking and deskewing. The other steps are similar to those in FIG. 9(a) to FIG. 9(d). Details will not be described again in this specification.

[0138] The above describes a data transmitting method and a data receiving method in an embodiment of the present application. Corresponding to the above method, an embodiment of the present application further provides an Ethernet device for transmitting data and receiving data.

[0139] 10 is a diagram of the structure of an Ethernet device according to one embodiment of the present application. The Ethernet device may be configured to transmit data or receive data. The Ethernet device may be an Ethernet device in the data transmission method shown in FIG. 3. Based on the structure shown in FIG. 9, the Ethernet device can perform all or part of the operations in the method shown in FIG. 3. It should be understood that the Ethernet device may include additional structures more than those shown, or some of the structures shown may be omitted. This is not limited in this embodiment of the present application. As shown in FIG. 10, the Ethernet device a PMA circuit configured to: obtain a data stream, the data stream being a forward error correction (FEC) encoded data stream; and perform a first data processing process on the data stream to obtain an interleaved data stream, the first data processing process including performing interleaving in a first interleaving manner, wherein an interleaving type of the first interleaving manner is symbol interleaving or convolutional interleaving. Includes:

[0140] In some possible implementations, symbol interleaving is performed at a granularity of 10 bits.

[0141] In some possible implementations, the first data processing process further includes bit multiplexing or symbol group multiplexing.

[0142] In some possible implementations, the first data processing process further includes bit demultiplexing or symbol group demultiplexing before performing interleaving in the first interleaving manner.

[0143] In some possible implementations, the first data processing process further includes alignment marker AM locking and deskewing before performing interleaving in the first interleaving manner.

[0144] In some possible implementations, the data stream is a data stream obtained by performing a second data processing process, the second data processing process including performing interleaving in a second interleaving manner.

[0145] In some possible implementations, the interleaving depth of the first interleaving style is different from that of the second interleaving style.

[0146] In some possible implementations, the interleaving depth of the second interleaving style is 2×RS.

[0147] In some possible implementations, the first data processing process further includes performing deinterleaving for the second interleaving manner.

[0148] In some possible implementations, the second data processing process is performed by the physical coding sublayer PCS or the data terminal equipment extender sublayer DTE_XS.

[0149] In some possible implementations, the interleaving depth of the first interleaving style is 4×RS.

[0150] In some possible implementations, the lane rate of the interleaved data stream is 200 gigabits per second (Gbps).

[0151] In some possible implementations, the rate of the interface for receiving the data stream by the PMA circuitry is at least one of the following: 200 Gbps or 400 Gbps.

[0152] In some possible implementations, the PMA circuitry obtains the data stream from the attachment unit interface AUI or the common electrical interface CEI.

[0153] In some possible implementations, the PMA circuitry transmits the interleaved data stream to a physical medium dependent PMD sublayer.

[0154] For a specific description of the operations performed by the Ethernet device, please refer to the specific description of the method embodiment shown in Figure 3. The details will not be described again herein.

[0155] The Ethernet device can be an Ethernet chip, an Ethernet transport device such as a switch or a router, and an Ethernet pluggable optical or electrical module.

[0156] When the Ethernet device is an Ethernet chip, the Ethernet chip may be implemented by using the structure shown in Figure 4(a). The PMA circuit in the Ethernet device corresponds to the PMA sublayer shown in Figure 4(a). In some cases, the Ethernet device further includes a PCS and a PMD sublayer.

[0157] When the Ethernet device is a pluggable optical or electrical module, the pluggable optical or electrical module may be implemented by using the structure shown in Figure 4(b) or Figure 4(c). The PMA circuit in the Ethernet device corresponds to the PMA sublayer shown in Figure 4(b) or a PMA sublayer adjacent to the PMD layer shown in Figure 4(c). In some cases, the Ethernet device further includes a PMD sublayer.

[0158] When the Ethernet device is an Ethernet forwarding device such as a switch or a router, the Ethernet device may include an Ethernet chip or a pluggable optical or electrical module, which may perform all or part of the operations in the method in FIG.

[0159] FIG. 10 is a diagram of the structure of an Ethernet device according to one embodiment of the present application. The Ethernet device may be configured to transmit data or receive data. The Ethernet device may be an Ethernet device in the data receiving method shown in FIG. 8(a). Based on the structure shown in FIG. 9, the Ethernet device can perform all or part of the operations in the method shown in FIG. 8(a). It should be understood that the Ethernet device may include additional structures more than those shown, or some of the structures shown may be omitted. This is not limited in this embodiment of the present application. As shown in FIG. 10, the Ethernet device a PMA circuit configured to: obtain a data stream, the data stream being a forward error correction (FEC) encoded data stream; and perform a third data processing process on the data stream to obtain a deinterleaved data stream, the third data processing process including performing deinterleaving in a first deinterleaving manner, wherein a deinterleaving type of the first deinterleaving manner is symbol deinterleaving or convolutional deinterleaving. Includes:

[0160] In some possible implementations, symbol deinterleaving is performed at a 10-bit granularity.

[0161] In some possible implementations, the third data processing process includes bit multiplexing or symbol group multiplexing.

[0162] In some possible implementations, the third data processing process includes bit demultiplexing or symbol group demultiplexing.

[0163] In some possible implementations, the third data processing process includes alignment marker AM lock and deskew.

[0164] In some possible implementations, after the PMA circuit performs the third data processing process on the data stream, the method further includes the PMA circuit performing interleaving on the deinterleaved data stream in a second interleaving manner to obtain a re-interleaved data stream.

[0165] In some possible implementations, the re-interleaved data stream is de-interleaved by the physical coding sublayer PCS or the data terminal equipment extender sublayer DTE_XS.

[0166] In some possible implementations, the interleaving depth of the first deinterleaving manner is 4×RS.

[0167] In some possible implementations, the PMA circuit obtaining the data stream includes the PMA circuit sending the interleaved data stream to a physical medium dependent PMD sublayer.

[0168] For a specific description of the operations performed by the Ethernet device, please refer to the specific description of the method embodiment shown in Figure 8(a), and the details will not be described again in this specification.

[0169] The Ethernet device can be an Ethernet chip, an Ethernet transport device such as a switch or a router, and an Ethernet pluggable optical or electrical module.

[0170] When the Ethernet device is an Ethernet chip, the Ethernet chip may be implemented by using the structure shown in Figure 4(a). The PMA circuit in the Ethernet device corresponds to the PMA sublayer shown in Figure 4(a). In some cases, the Ethernet device further includes a PCS and a PMD sublayer.

[0171] When the Ethernet device is a pluggable optical or electrical module, the pluggable optical or electrical module may be implemented by using the structure shown in Figure 4(b) or Figure 4(c). The PMA circuit in the Ethernet device corresponds to the PMA sublayer shown in Figure 4(b) or a PMA sublayer adjacent to the PMD layer shown in Figure 4(c). In some cases, the Ethernet device further includes a PMD sublayer.

[0172] When the Ethernet device is an Ethernet forwarding device such as a switch or a router, the Ethernet device may include an Ethernet chip or a pluggable optical or electrical module, which can perform all or part of the operations in the method shown in FIG.

[0173] FIG. 10 is a diagram of the structure of an Ethernet device according to one embodiment of the present application. The Ethernet device may be configured to transmit data or receive data. The Ethernet device may be an Ethernet device in the data receiving method shown in FIG. 8(b). Based on the structure shown in FIG. 9, the Ethernet device can perform all or part of the operations in the method shown in FIG. 8(b). It should be understood that the Ethernet device may include additional structures more than those shown, or some of the structures shown may be omitted. This is not limited in this embodiment of the present application. As shown in FIG. 10, the Ethernet device a PMA circuit configured to obtain a data stream, the data stream being a forward error correction (FEC) encoded data stream. The PMA sublayer performs a third data processing process on the data stream to obtain an interleaved data stream, the third data processing process including performing interleaving on the data stream, wherein an interleave type of the interleaving is symbol interleaving or convolutional interleaving.

[0174] In some possible implementations, symbol interleaving is performed at a granularity of 10 bits.

[0175] In some possible implementations, the interleaved data stream is deinterleaved by the physical coding sublayer PCS or the data terminal equipment extender sublayer DTE_XS.

[0176] In some possible implementations, the interleaving depth of the interleaving is 2×RS.

[0177] In some possible implementations, the third data processing process further includes bit demultiplexing or symbol group demultiplexing.

[0178] In some possible implementations, the third data processing process further includes alignment marker AM lock and deskew.

[0179] In some possible implementations, the third data processing process further includes bit multiplexing or symbol group multiplexing.

[0180] For a specific description of the operations performed by the Ethernet device, please refer to the specific description of the method embodiment shown in Figure 8(b), and the details will not be described again in this specification.

[0181] The Ethernet device can be an Ethernet chip, an Ethernet transport device such as a switch or a router, and an Ethernet pluggable optical or electrical module.

[0182] When the Ethernet device is an Ethernet chip, the Ethernet chip may be implemented by using the structure shown in Figure 4(a). The PMA circuit in the Ethernet device corresponds to the PMA sublayer shown in Figure 4(a). In some cases, the Ethernet device further includes a PCS and a PMD sublayer.

[0183] When the Ethernet device is a pluggable optical or electrical module, the pluggable optical or electrical module may be implemented by using the structure shown in Figure 4(b) or Figure 4(c). The PMA circuit in the Ethernet device corresponds to the PMA sublayer shown in Figure 4(b) or a PMA sublayer adjacent to the PMD layer shown in Figure 4(c). In some cases, the Ethernet device further includes a PMD sublayer.

[0184] When the Ethernet device is an Ethernet forwarding device such as a switch or a router, the Ethernet device may include an Ethernet chip or a pluggable optical or electrical module, which can perform all or part of the operations in the method shown in FIG.

[0185] Fig. 12 is a diagram of the structure of an Ethernet device 2100 according to another exemplary embodiment of the present application. The Ethernet device 2100 shown in Fig. 12 is configured to perform all or part of the operations in the data transmission method shown in Fig. 3 or the data reception method shown in Fig. 8(a) or Fig. 8(b). The network device 2100 is, for example, an Ethernet forwarding device such as a switch or a router, and the Ethernet device 2100 may be implemented by using a general bus architecture.

[0186] As shown in FIG. 12, the Ethernet device 2100 includes a main control board 2110 and an interface board 2130 .

[0187] The main control board 2110 is also called a main processing unit (MPU) or a route processor card. The main control board 2110 is configured to control and manage the components in the Ethernet device 2100, including the functions of route calculation, device management, device maintenance, and protocol processing. The main control board 2110 includes a central processing unit 2111 and a memory 2112.

[0188] The interface board 2130 is also referred to as a line interface unit (LPU), line card, or service board. The interface board 2130 is configured to provide various service interfaces and perform data packet forwarding. The service interfaces include, but are not limited to, an Ethernet interface, a Packet over SONET / SDH (POS) interface, etc. The Ethernet interface is, for example, a Flexible Ethernet service interface (Flexible Ethernet Clients, FlexE Clients). The interface board 2130 includes a central processing unit 2131, a network processor 2132, a forwarding entry memory 2134, and a physical interface card (PIC) 2133.

[0189] The central processing unit 2131 on the interface board 2130 is configured to control and manage the interface board 2130 and to communicate with the central processing unit 2111 on the main control board 2110 .

[0190] The network processor 2132 is configured to perform packet forwarding processing. The network processor 2132 may take the form of a forwarding chip. The forwarding chip may be a network processor (NP). In some embodiments, the forwarding chip may be implemented by using an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). In particular, the network processor 2132 is configured to forward a received packet based on a forwarding table stored in the forwarding entry memory 2134. If the destination address of the packet is the address of the Ethernet device 2100, the network processor sends the packet to a CPU (e.g., central processing unit 2131) for processing. If the destination address of the packet is not the address of the Ethernet device 2100, the network processor searches the forwarding table for a next hop and an outbound interface corresponding to the destination address based on the destination address, and forwards the packet to the outbound interface corresponding to the destination address. Processing of uplink packets may include processing of the inbound interface of the packet and forwarding table lookup, and processing of downlink packets may include forwarding table lookup, etc. In some embodiments, the central processing unit may alternatively perform the functions of the forwarding chip and implement software forwarding, for example, based on a general-purpose CPU. Thus, a forwarding chip is not required on the interface board.

[0191] The physical interface card 2133 is configured to implement a physical layer interconnection function, such that original traffic enters the interface board 2130 from the physical interface card and processed packets are sent out from the physical interface card 2133. The physical interface card 2133, also called a subcard, may be installed on the interface board 2130 and is responsible for converting optical / electrical signals into packets, performing validation checks on the packets, and then forwarding the packets to the network processor 2132 for processing. In some embodiments, the central processing unit 2131 may alternatively perform the functions of the network processor 2132 and, for example, implement software forwarding based on a general-purpose CPU. Therefore, the network processor 2132 is not required in the physical interface card 2133.

[0192] In some cases, the Ethernet device 2100 includes multiple interface boards. For example, the Ethernet device 2100 further includes an interface board 2140. The interface board 2140 includes a central processing unit 2141, a network processor 2142, a forwarding entry memory 2144, and a physical interface card 2143. The functions and implementation forms of the components on the interface board 2140 are the same as or similar to those on the interface board 2130. The details will not be described again herein.

[0193] In some cases, the Ethernet device 2100 further includes a switching board 2120. The switching board 2120 may also be referred to as a switch fabric unit (SFU). When the network device 2100 has multiple interface boards, the switching board 2120 is configured to perform data exchange between the interface boards. For example, the interface board 2130 and the interface board 2140 may communicate with each other by using the switching board 2120.

[0194] The main control board 2110 is coupled to the interface boards. For example, the main control board 2110, the interface boards 2130, the interface boards 2140, and the switching board 2120 are connected to a system backboard by using a system bus to implement interworking. In a possible implementation, an inter-process communication (IPC) protocol lane is established between the main control board 2110, the interface boards 2130, and the interface boards 2140, and the main control board 2110, the interface boards 2130, and the interface boards 2140 communicate with each other through the IPC lane.

[0195] Logically, the Ethernet device 2100 includes a control plane and a forwarding plane. The control plane includes a main control board 2110 and a central processing unit 2111. The forwarding plane includes components that perform forwarding, such as a forwarding entry memory 2134, physical interface cards 2133, and network processors 2132. The control plane performs functions such as router functions, generating forwarding tables, processing signaling and protocol packets, and configuring and maintaining the state of the network device. The control plane provides the generated forwarding tables to the forwarding plane. In the forwarding plane, the network processors 2132 look up tables for forwarding packets received by the physical interface cards 2133 based on the forwarding tables provided by the control plane. The forwarding tables provided by the control plane may be stored in the forwarding entry memory 2134. In some embodiments, the control plane and the forwarding plane may be completely separate and not on the same network device.

[0196] It should be noted that there may be one or more main control boards, and when there are multiple main control boards, a primary main control board and a secondary main control board may be included. There may be one or more interface boards. A network device with more powerful data processing capabilities provides a larger number of interface boards. There may also be one or more physical interface cards on the interface board. There may be no switching board, or there may be one or more switching boards. When there are multiple switching boards, load balancing and redundancy backup may be implemented together. In a centralized forwarding architecture, a network device may not require a switching board, and the interface board provides the function of processing service data for the entire system. In a distributed forwarding architecture, a network device may have at least one switching board, and data exchange between multiple interface boards is implemented by using the switching board to provide large-capacity data exchange and processing capabilities. Therefore, the data access and processing capabilities of a network device in a distributed architecture are greater than those of a network device in a centralized architecture. In some cases, the network device may alternatively be in the form of a single board. Specifically, there is no switching board, and the functions of the interface board and the main control board are integrated into that board. In this case, the central processing unit on the interface board and the central processing unit on the main control board may be combined into one central processing unit on that board to perform the functions obtained by combining the two central processing units. A network device in this form (e.g., a network device such as a low-end switch or router) has low data exchange and processing capabilities. The specific architecture to be used depends on the specific networking deployment scenario. This is not limited herein.

[0197] In a particular embodiment, the Ethernet device 2100 corresponds to the Ethernet device shown in FIG. 10 or FIG.

[0198] For example, Ethernet device 2100 may be the Ethernet device shown in Figure 10 or 11, which is an Ethernet forwarding device such as a switch or router. In this case, an Ethernet chip performing the method shown in Figure 3, 8(a), or 8(b) may be in main control board 2110, or in interface board 2130 or interface board 2140, and the Ethernet chip may be in physical interface card 2133 or 2143 in particular.

[0199] An embodiment of the present application further provides a communication system 3000. The packet processing system includes a first Ethernet device 3001 and a second Ethernet device 3002. In some cases, the first Ethernet device may be an Ethernet device on the transmitting side and executes the data transmission method shown in Figure 3. The second Ethernet device may be an Ethernet device on the receiving side and executes the data reception method shown in Figure 8(a) or 8(b).

[0200] An embodiment of the present application further provides a computer-readable storage medium, which stores at least one instruction, and the instruction is loaded and executed by a processor to enable a computer to perform any one of the above data transmission methods or the above data reception methods.

[0201] An embodiment of the present application further provides a computer program (product), which, when executed by a computer, can enable the processor or computer to perform the corresponding steps and / or procedures in the above-mentioned method embodiments.

[0202] An embodiment of the present application further provides a chip including a processor, the processor being configured to retrieve from the memory instructions stored in the memory and execute the instructions to enable a communication device in which the chip is installed to perform any one of the above data transmission methods or the above data reception methods.

[0203] An embodiment of the present application further provides another chip including an input interface, an output interface, a processor, and a memory. The input interface, the output interface, the processor, and the memory are connected through an internal connection path. The processor is configured to execute code in the memory. When the code is executed, the processor is configured to perform any one of the above data transmission methods or the above data reception methods.

[0204] All or part of the above embodiments may be implemented by software, hardware, firmware, or any combination thereof. When software is used to implement an embodiment, all or part of the embodiment may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the procedures or functions according to the present application are generated, in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or another programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from a computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center in a wired (e.g., coaxial cable, fiber optic, or digital subscriber line) or wireless (e.g., infrared, radio, or microwave) manner. The computer-readable storage medium may be any available medium accessible by a computer, or a data storage device, such as a server or data center, that integrates one or more available media. The available media may be magnetic media (eg, a floppy disk, hard disk drive, or magnetic tape), optical media (eg, a DVD), semiconductor media (eg, a solid-state disk), or the like.

[0205] Those skilled in the art will recognize that the method steps and modules described with reference to the embodiments disclosed herein can be implemented by using software, hardware, firmware, or any combination thereof. To clearly describe the compatibility between hardware and software, the steps and components of the embodiments have been generally described in terms of functions in the above description. Whether a function is performed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but the implementation form should not be considered as going beyond the scope of this application.

[0206] Those skilled in the art will understand that all or part of the steps of the embodiments can be implemented by hardware or hardware associated with program instructions. The program can be stored in a computer-readable storage medium. The storage medium can include a read-only memory, a magnetic disk, or an optical disk.

[0207] When software is used to implement an embodiment, all or part of the embodiment may be implemented in the form of a computer program product. The computer program product includes one or more computer program instructions. In one example, methods according to embodiments of the present application may be described in the context of machine-executable instructions. For example, machine-executable instructions are included in program modules residing in a device for execution on a target real or virtual processor. Typically, program modules include routines, programs, libraries, objects, classes, components, data structures, etc., that perform particular tasks or implement particular abstract data structures. In various embodiments, the functionality of a program module may be combined or divided among the described program modules. The machine-executable instructions for a program module may be executed locally or in a distributed device. In a distributed device, the program module may reside in both local and remote storage media.

[0208] Computer program code for implementing the methods in the embodiments of the present application can be written in one or more programming languages. The computer program code can be provided for a processor of a general-purpose computer, a special-purpose computer, or another programmable data processing apparatus, so that when the program code is executed by the computer or another programmable data processing apparatus, the functions / operations specified in the flowcharts and / or block diagrams are performed. The program code can be executed entirely on the computer, partially on the computer as a separate software package, partially on the computer and partially on a remote computer, or entirely on a remote computer or server.

[0209] In the context of the embodiments of the present application, computer program code or associated data may be carried in any suitable carrier so as to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, etc.

[0210] Examples of signals may include electrical signals, optical signals, radio signals, audio signals, or other forms of propagated signals such as carrier waves and infrared signals.

[0211] A machine-readable medium may be any tangible medium that contains or stores a program used in or associated with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More specific examples of machine-readable storage media include an electrical connection using one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0212] For the sake of convenience and simplicity, those skilled in the art will clearly understand that for the detailed working processes of the above systems, devices and modules, please refer to the corresponding processes in the above method embodiments, and the details will not be described again in this specification.

[0213] In some embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other ways. For example, the device embodiments described are merely examples. For example, the division into modules is merely a division into logical functions, and other division modes may exist in actual applications. For example, multiple modules or components may be combined or integrated into another system, or some functions may be ignored or not performed. In addition, the shown or described mutual couplings or direct couplings or communication connections may be indirect couplings or communication connections implemented through some interfaces, devices, or modules, or may be electrical, mechanical, or other forms of connection.

[0214] Modules described as separate components may or may not be physically separate, and components displayed as modules may or may not be physical modules, may be in one location, or may be distributed over multiple network modules. Some or all of the modules may be selected based on actual requirements for implementing the objectives of the solutions of the embodiments of the present application.

[0215] In addition, the functional modules in the embodiments of the present application may be integrated into one processing module, or each module may exist physically alone, or two or more modules may be integrated into one module. The integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0216] When the integrated module is implemented in the form of a software function module and sold or used as an independent product, the integrated module may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may essentially be implemented in the form of a software product, or the part that contributes to the prior art, or all or part of the technical solution. The computer software product may be stored in a storage medium and include some instructions for instructing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method described in the embodiments of the present application. The above storage medium includes any medium that can store program code, such as a USB flash drive, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0217] In this application, terms such as "first" and "second" are used to distinguish between identical or similar items that have essentially the same role and function. It should be understood that there is no logical or timing dependency between "first," "second," and "nth," and that neither the quantity nor the order of execution is limited. Terms such as "first" and "second" are used in the following description to represent various elements, but it should be further understood that these elements should not be limited by these terms. These terms are used merely to distinguish one element from another. For example, a first image may be referred to as a second image, and similarly, a second image may be referred to as a first image, without departing from the scope of various examples. Both the first image and the second image may be images, and in some cases, may be separate and distinct images.

[0218] It should be further understood that the sequence numbers of the processes do not refer to the execution order in the embodiments of the present application, and the execution order of the processes should be determined based on the functions and internal logic of the processes, and should not be construed as any limitation on the implementation process of the embodiments of the present application.

[0219] As used herein, the term "at least one" means one or more, and the term "plurality" as used herein means two or more. For example, a plurality of second packets means two or more second packets. The terms "system" and "network" are often used interchangeably herein.

[0220] It should be understood that the terminology used in the description of the various examples herein is intended to describe particular examples only and is not intended to be limiting. As used in the descriptions of the various examples and in the appended claims, the singular forms "a" and "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise.

[0221] It should be further understood that the term "and / or" as used herein denotes and includes any or all possible combinations of one or more of the associated listed items. The term "and / or" describes an associative relationship between associated objects and represents that three relationships may exist. For example, A and / or B may represent the following three cases: only A is present, both A and B are present, and only B is present. Additionally, the character " / " in this application generally denotes an "or" relationship between associated objects.

[0222] It will be further understood that the term "comprising" (also referred to as "includes," "including," "comprises," and / or "comprising") as used herein specifies the presence of stated features, integers, steps, operations, elements, and / or components, and does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or components thereof.

[0223] It should be further understood that the terms "when" and "assuming" may be interpreted to mean "when" or "upon," or "in response to determining," or "in response to detecting." Similarly, depending on the context, the phrase "when it is determined" or "when [the stated condition or event] is detected" may be interpreted to mean "when it is determined," "in response to determining," "when [the stated condition or event] is detected," or "in response to detecting [the stated condition or event]."

[0224] It should be understood that determining B based on A does not mean that B is determined based only on A, but that B may alternatively be determined based on A and / or other information.

[0225] It should be further understood that references throughout this specification to "one embodiment," "an embodiment," and "possible implementations" mean that a particular feature, structure, or characteristic associated with that embodiment or implementation is included in at least one embodiment of the present application. Thus, the appearances of "in one embodiment," or "in an embodiment," or "possible implementations" throughout this specification may not necessarily refer to the same embodiment. In addition, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0226] The above description is only an arbitrary embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement, or improvement made without departing from the principle of the present application should fall within the protection scope of the present application. [Explanation of symbols]

[0227] 2100 Ethernet devices, network devices 2110 Main Control Board 2111,2131,2141 Central Processing Unit 2112 memory 2120 Switching Board 2130,2140 interface board 2132,2142 Network Processor 2133,2143 Physical Interface Card 2134,2144 Transfer entry memory 3000 Communication Systems 3001 First Ethernet Device 3002 Second Ethernet Device

Claims

1. 1. A data transmission method, comprising: obtaining a data stream by a physical medium attachment (PMA) sublayer of an Ethernet device, the data stream being a forward error correction (FEC) encoded data stream; performing, by the PMA sublayer, a first data processing process on the data stream to obtain an interleaved data stream, the first data processing process including performing interleaving in a first interleaving manner; Including, The method, wherein the interleaving type of the first interleaving manner is symbol interleaving or convolutional interleaving.

2. The method of claim 1 , wherein the symbol interleaving is performed at a granularity of 10 bits.

3. 3. The method of claim 1, wherein the first data processing process further comprises bit multiplexing or symbol group multiplexing.

4. 4. The method according to claim 1, wherein the first data processing process further comprises bit demultiplexing or symbol group demultiplexing before performing interleaving in a first interleaving manner.

5. 5. The method of claim 1, wherein the first data processing process further comprises alignment marker (AM) locking and deskewing before performing interleaving in a first interleaving manner.

6. 6. The method of claim 1, wherein the data stream is a data stream obtained by performing a second data processing process, and the second data processing process includes performing interleaving in a second interleaving manner.

7. The method of claim 6 , wherein an interleave depth of the first interleave style is different from an interleave depth of the second interleave style.

8. 8. The method of claim 6 or 7, wherein the interleaving depth of the second interleaving style is 2xRS.

9. 9. The method of claim 6, wherein the first data processing process further comprises performing deinterleaving for the second interleaving style.

10. 10. The method according to claim 6, wherein the second data processing process is performed by a physical coding sublayer (PCS) or a data terminal equipment extender sublayer (DTE_XS).

11. 11. The method of claim 1, wherein the interleaving depth of the first interleaving style is 4xRS.

12. 12. The method of claim 1, wherein the Ethernet device comprises at least one of a physical layer (PHY) chip, a forwarding device, or a pluggable module.

13. 13. The method of claim 1, wherein the lane rate of the interleaved data stream is 200 gigabits per second (Gbps).

14. 14. The method of claim 1, wherein a rate of an interface for receiving the data stream by the PMA sublayer is at least one of 200 Gbps or 400 Gbps.

15. 15. The method of claim 1, wherein the data stream is obtained by the PMA sublayer from an Attachment Unit Interface (AUI) or a Common Electrical Interface (CEI).

16. transmitting the interleaved data stream by the PMA sublayer to a physical medium dependent (PMD) sublayer.

16. The method of any one of claims 1 to 15, further comprising:

17. 1. A data receiving method, comprising: obtaining a data stream by a physical medium attachment (PMA) sublayer of an Ethernet device, the data stream being a forward error correction (FEC) encoded data stream; performing, by the PMA sublayer, a third data processing process on the data stream to obtain an interleaved data stream, the third data processing process including performing interleaving on the data stream; Including, A method wherein the interleaving type of the interleaving is symbol interleaving or convolutional interleaving.

18. 18. The method of claim 17, wherein the symbol interleaving is performed at a granularity of 10 bits.

19. 19. The method of claim 17 or 18, wherein the interleaved data stream is deinterleaved by a physical coding sublayer (PCS) or a data terminal equipment extender sublayer (DTE_XS).

20. 20. The method of claim 17, wherein the interleaving depth of the interleaving is 2xRS.

21. 21. The method according to any one of claims 17 to 20, wherein the third data processing process further comprises bit demultiplexing or symbol group demultiplexing.

22. 22. The method of claim 17, wherein the third data processing process further comprises alignment marker (AM) locking and deskewing.

23. 23. The method of any one of claims 17 to 22, wherein the third data processing process further comprises bit multiplexing or symbol group multiplexing.

24. 24. The method of claim 17, wherein the Ethernet device comprises at least one of a physical layer (PHY) chip, a forwarding device, or a pluggable module.

25. 1. A data receiving method, comprising: obtaining a data stream by a physical medium attachment (PMA) sublayer of an Ethernet device, the data stream being a forward error correction (FEC) encoded data stream; performing, by the PMA sublayer, a third data processing process on the data stream to obtain a deinterleaved data stream, the third data processing process including performing deinterleaving in a first deinterleaving manner; Including, The method, wherein the deinterleaving type of the first deinterleaving manner is symbol deinterleaving or convolutional deinterleaving.

26. 26. The method of claim 25, wherein the symbol deinterleaving is performed at a granularity of 10 bits.

27. 27. The method of claim 25 or 26, wherein the third data processing process comprises bit multiplexing or symbol group multiplexing.

28. 28. The method of any one of claims 25 to 27, wherein the third data processing process comprises bit demultiplexing or symbol group demultiplexing.

29. 29. The method of any one of claims 25 to 28, wherein the third data processing process comprises alignment marker (AM) locking and deskewing.

30. after the step of performing, by the PMA sublayer, a third data processing process on the data stream; performing, by the PMA sublayer, interleaving on the deinterleaved data stream in a second interleaving manner to obtain a reinterleaved data stream.

29. The method of any one of claims 25 to 28, further comprising:

31. 31. The method of claim 30, wherein the re-interleaved data stream is de-interleaved by a physical coding sublayer (PCS) or a data terminal equipment extender sublayer (DTE_XS).

32. 32. The method of claim 25, wherein the interleaving depth of the first deinterleaving manner is 4xRS.

33. 33. The method of any one of claims 25 to 32, wherein the Ethernet device comprises at least one of a physical layer (PHY) chip, a forwarding device, or a pluggable module.

34. said step of obtaining a data stream by a PMA sublayer comprising: obtaining, by the PMA sublayer, an interleaved data stream from a physical medium dependent (PMD) sublayer; 34. The method of any one of claims 25 to 33, comprising:

35. An Ethernet device configured to perform the method of any one of claims 1 to 16, 17 to 24, or 25 to 34.

36. A chip configured to perform the method of any one of claims 1 to 16, 17 to 24, or 25 to 34.

37. 1. A communication system comprising: a first Ethernet device and a second Ethernet device; The first Ethernet device is configured to perform the method of any one of claims 1 to 16 and the second Ethernet device is configured to perform the method of any one of claims 17 to 24, or The first Ethernet device is configured to perform the method of any one of claims 1 to 16, and the second Ethernet device is configured to perform the method of any one of claims 25 to 34. Communication system.

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