Analog video transmission to the display panel and integration of the source driver into the display panel

Abstract

The transmitter has a distributor that receives the stream of digital video samples and distributes the analog video samples to vectors in a buffer according to their order. A digital-to-analog converter (DAC) for each vector receives the digital video samples from the corresponding vector and converts the digital video samples to analog video samples. A wiring harness transmits the series of analog video samples to source drivers of the display panel of the display unit. Each source driver has a collector that receives the analog video samples from each DAC and stores the analog video samples of the corresponding vector, and an amplifier that receives the stored analog video samples from the collector in parallel and amplifies the stored analog video samples to the columns of the display panel. Synchronization uses modified MFM and sample phase alignment. The source drivers are integrated on the substrate of the display panel using transistors.

Description

[Technical Field]

[0001] Cross-references to related documents This application claims priority to U.S. Provisional Patent Application No. 63 / 500,341 (Attorney Docket No. HYFYP0015P2), filed May 5, 2023, entitled "Analog Video Transmission to a Display Panel and Integration of a Source Driver into a Display Panel," and U.S. Provisional Patent Application No. 63 / 447,241 (Attorney Docket No. HYFYP0015P), filed February 21, 2023, entitled "Analog Video Transmission to a Display Panel," all of which are incorporated herein by reference.

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 611,274 (Attorney Docket No. HYFYP0017P2), filed December 18, 2023, entitled "Video Transmission Within Mobile Devices," and U.S. Provisional Patent Application No. 63 / 516,220 (Attorney Docket No. HYFYP0017P), filed July 28, 2023, all of which are incorporated herein by reference.

[0003] This application claims priority to U.S. Provisional Patent Application No. 63 / 625,473 (Attorney Docket No. HYFYP0018P), entitled "In-Vehicle Signal Transmission," filed January 26, 2024, all of which are incorporated herein by reference.

[0004] This application incorporates by reference U.S. Patent Application No. 17 / 900,570, filed August 31, 2022 (Attorney Docket No. HYFYP009), U.S. Patent Application No. 18 / 098,612, filed January 18, 2023 (Attorney Docket No. HYFYP013), now assigned as U.S. Patent No. 11,769,468, and U.S. Patent Application No. 18 / 117,288, filed March 3, 2023 (Attorney Docket No. HYFYP014), now assigned as U.S. Patent No. 11,842,671.

[0005] This application incorporates by reference U.S. Patent Application No. 18 / 442,447 (Attorney Docket No. HYFYP017), filed on even date herewith.

[0006] The present invention relates generally to video transmission, and more particularly to the transmission of analog video samples, for example, into or to a display unit. [Background technology]

[0007] Image sensors, display panels, and video processors are constantly competing to achieve larger formats, deeper color depth, higher frame rates, and higher resolutions. Local site video transmission faces performance scaling bottlenecks that limit throughput and reduce performance, while also increasing costs and power consumption. Removing these bottlenecks offers numerous benefits.

[0008] For example, as display resolution increases, the data rate at which video information is transferred from the video source to the display screen increases exponentially. From 3Gbps for Full HD ten years ago, to 160Gbps for new 8K screens. A typical display with 4K display resolution requires about 18Gbps of bandwidth at 60Hz, but 36Gbps at 120Hz (split across P physical channels). An 8K display requires 72Gbps at 60Hz and 144Gbps at 120Hz.

[0009] Traditionally, data has been transferred digitally at a bit rate of 16 Gbps per signal pair using a variant of low-voltage differential signaling (LVDS) data transfer, with pairs paralleled to achieve the required total bit rate. With a wiring delay of 5 ns / m, each bit on the digital connection has a wavelength of 12 mm, near the limit of this type of connection and requiring extensive data synchronization to obtain usable data. This digital information then needs to be converted on the fly to analog pixel information using either ultra-fast digital-to-analog (DA) conversion in the display's source driver, or massively parallel slower conversion.

[0010] Currently, DA converters use 8 bits, but it is possible that 10-bit or even 12-bit DA conversion will soon be required, in which case it will be extremely difficult to perform accurate conversion at a sufficient data rate.As a result, displays must perform DA conversion in a very short time, and the time available for conversion is also shortened, making stabilizing DA conversion a challenge.

[0011] Therefore, new devices and techniques are desired for eliminating the need for digital-to-analog conversion in the display's source driver, increasing bandwidth, utilizing analog video signals within the display unit, and transmitting the video signals elsewhere. Summary of the Invention

[0012] To achieve the above objectives and in accordance with the purpose of the present invention, a sampled analog video transmission (SAVT) technique, also known as "clocked analog video transmission" or CAVT, is disclosed that overcomes the above-mentioned shortcomings in the prior art.

[0013] It is recognized that the requirements for bit-perfect communication between computing devices (e.g., text, spreadsheets, etc.) are significantly different from the requirements for communicating video content for human viewing. Because a video signal is essentially a list of luminance values, it is understood that precisely maintaining fixed-bit-width (i.e., digital) luminance values ​​is inefficient for transmitting video, and analog voltages offer greater resolution because bit-accurate reproduction of these luminance values ​​is not necessary. The unnecessary requirement for bit-perfect video transmission imposes a costly burden known as "digital overhead." Therefore, the present invention proposes transmitting video signals as analog signals rather than digital signals.

[0014] While traditional digital transmission uses expensive mixed-signal processes with high-speed digital circuits, embodiments of the present invention use fully amortized analog processes to increase flexibility and reduce manufacturing costs. Furthermore, using analog signals for data transfer between (for example) a display controller and a source driver of a display panel reduces complexity compared to traditional transmission between a signal source (via an LVDS or Vx1 transmitter) and a source driver receiver with a digital-to-analog converter.

[0015] In one embodiment, a transmitter is disclosed that processes received digital video samples, converts them to analog, and transmits them to a display panel. Also disclosed is a display panel source driver that receives the analog samples and drives them to the display panel. Analog signals are used to transmit digital video data received from a video source (or storage device) to a video sink for display. The analog signals may originate from a transmitter in a computer (or other processor) and be sent to a source driver in a display unit for display on the display panel, in which case the analog signals would be generated external to the display unit. Alternatively, the analog signals may be generated in a transmitter in the display unit itself.

[0016] In an alternative embodiment, if the required analog speed and accuracy can be ensured, the source driver can be partially or entirely integrated into the glass substrate of the display panel. Conventional source drivers are attached to the edge of the display panel (but are not integrated into the display panel) due to the complexity of high-speed digital circuits and the large area required for DA conversion. The present invention does not require a DA converter in the source driver, nor does it require a decoder, and the low-frequency sampling transfer of the SAVT signal (e.g., the SAVT video signal arrives at the source driver at one-tenth the data rate of a 3 GHz digital video signal) allows the source driver to be integrated into the glass itself.

[0017] The present invention can be used with any active matrix display substrate. High-mobility (e.g., low-temperature polysilicon (LTPS) or oxide (IGZO) TFT) substrates are most suitable. Consequently, if the entire source driver is integrated, the display panel can be connected to the GPU with only signal cables of any length and power supply. The absence of additional electronics on the glass allows for further reduction in edge width and thinner modules.

[0018] The present invention is particularly applicable to displays used in computer systems, televisions, monitors, gaming displays, home theater displays, retail signage, outdoor signage, and the like. Embodiments of the present invention are also applicable to video transmission within vehicles, such as automobiles, trains, airplanes, and ships, not only from a transmitter to a display or monitor within the vehicle, but also within such a display or monitor. The present invention is also applicable to video transmission to or within mobile devices, such as phones. In certain embodiments, the present invention is useful within display units used to transmit and receive video signals. For example, a transmitter of the present invention can be used to implement the transmitter described in U.S. Patent No. 11,769,468 (HYFYP013), and a receiver of the present invention can be used to implement the receiver described in U.S. Application No. 17 / 900,570 (HYFYP009).

[0019] The invention, together with further advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0020] [Figure 1] A method for providing an electromagnetic (EM) analog signal to a display panel of a display unit using conversion within the display unit is shown. [Figure 2] 1 shows the architecture of a transmitter within a display unit. [Figure 3] 10 illustrates an embodiment of a distributor that uses different predetermined permutations. [Figure 4] 10 shows a block diagram of an alternative embodiment of each DAC following the image processor. [Figure 5] 1 shows the architecture of a source driver for a display panel. [Figure 6] 1 shows another architecture of a source driver of a display panel. [Figure 7] FIG. 1 is a block diagram showing an integrated transmitter and timing controller located immediately after the display unit SoC. [Figure 8] The integrated transmitter and timing controller are shown in more detail. [Figure 9] FIG. 1 is a block diagram showing an integrated transmitter and timing controller and SoC in a display unit. [Figure 10] 1 shows a video transmission system within a display unit. [Figure 11] A particular subpixel transmission order is shown, with subpixels grouped by color, to minimize transmission bandwidth. [Figure 12A] To minimize transmission bandwidth, subpixels are grouped by color, indicating a specific subpixel transmission order in which the control signals all arrive on one dedicated amplifier channel. [Figure 12B] The subpixels are grouped by color and a particular subpixel transmission order is shown with transition bands between them. [Figure 13] Shown is a SAVT receiver integrated with a source driver, where each divider amplifier drives an adjacent column and all control signals are processed by a single amplifier. [Figure 14] 10 shows a source driver input for a source driver for interleaving multiple input amplifiers, allowing speed requirements to be met. [Figure 15] 14 is a summary of the pixel transmission order, showing how pixel and control signals are sent from the transmitter to the source driver of FIG. 13 and which amplifier each is assigned to. [Figure 16] FIG. 16 is a block diagram of transmitter input vectors with a predetermined permutation that allows for the sequence of sub-pixel transmissions required in FIG. 15. [Figure 17A] 13 shows the source driver in more detail with the control channel shown in more detail and the three comparators used to extract phase matching information from the control signal. [Figure 17B] An alternative source driver 820'' to that of Figure 17A is shown in more detail, along with the control signals at the first amplifier. [Figure 17C] 17B shows a preferred alternative source driver to that of FIG. 17B. [Figure 17D] 17D shows a summary of the order of the sub-pixels collected by the input amplifier of FIG. 17C. [Figure 18] A technique for introducing a timing reference into a sequence of control signals is presented. [Figure 19A] The following shows the commands and parameters of the control sequence. [Figure 19B] 1 illustrates another technique for sending commands and parameters using MFM. [Figure 20A] A technique for performing phase adjustment is shown. [Figure 20B] 1 shows a sampling phase adjustment circuit. [Figure 20C] It shows special synchronization video patterns that make locking easier. [Figure 20D] This shows an example where the MFM flag is lost due to PLL phase wraparound. [Figure 20E] An example is shown in which the MFM flag is lost if the phase extends beyond the end of the control bits. [Figure 20F] 10 is a flowchart showing a flow of phase adjustment performed by MFM flag search. [Figure 21] 1 shows an analog data path for one channel of an example of a source driver. [Figure 22] FIG. 1 is a block diagram illustrating the transmission of analog video samples within a mobile phone. [Figure 23] 1 illustrates an implementation of the integration of source driver functionality in various embodiments. [Figure 24A] 1 shows the arrangement of gate drivers and source drivers on the glass of the display panel. [Figure 24B] 1 shows a source driver fully implemented on glass. [Figure 25] 10 illustrates another embodiment of an EM signal arrangement. [Figure 26] 1 shows an analog architecture for commanding and receiving feedback. [Figure 27]Illustrates latching the values ​​from the column amplifiers. [Figure 28] 1 shows a digital architecture for commanding and receiving feedback. [Figure 29] Illustrates latching the values ​​from the column amplifiers. [Figure 30] 1 illustrates a SAVT transmitter configured to transmit various video samples from various sources. [Figure 31] Shows a SAVT receiver in an SoC, processor, legacy display, or other location. DETAILED DESCRIPTION OF THE INVENTION

[0021] Because the wiring harness within the display unit adheres closely to its design values, it is understood that the noise immunity gained by using spreading codes (such as those described in U.S. Pat. No. 10,158,396 for encoding and decoding video samples for transmission within the display unit) may be offset by the circuit overhead of decoding at the source driver. In particular, the use of spreading codes provides some immunity to thermal noise in the transmitter's DAC and the source driver's sample-and-hold amplifiers. Nevertheless, it is understood that such thermal noise is stochastic and therefore should be imperceptible. Therefore, in some applications, spreading codes are not strictly necessary, eliminating the need for encoding and decoding at the source driver. Therefore, it has been proposed to transmit video data as an analog signal from the transmitter to any number of source drivers of a display panel.

[0022] It can also be seen that digitization of the video signal typically occurs at the system's signal source (often a GPU), and then, typically using a combination of high-performance cabling systems, the digital signal is transferred to the display panel's source driver, where it is converted back to analog and loaded into the display's pixels. Therefore, the sole purpose of digitization is to transfer data from the video source to the display pixels. It can therefore be seen to be more beneficial to avoid digitization entirely (if possible) and transfer analog data directly from the video source (or a suitable transmitter) to the display source driver. Because such analog signals are highly accurate (although subject to circuit imperfections) and continuous, their resolution is always higher than can be expressed in a digital representation of any length. This means that the sampling rate is kept at least 10 times lower than for digital transfer, providing headroom for expanding bandwidth.

[0023] Furthermore, it is easier to perform digital-to-analog conversion at a point requiring less power than at the end that drives the display panel. Therefore, instead of transmitting digital signals from the video source (or SoC or timing controller) to where an analog signal needs to be generated, the signal is converted to analog near the SoC or timing controller in the transmitter and then transmitted to the display panel at a much lower sample rate than is typically used for digitization. This means that instead of sending gigabit-per-second signals over multiple lines, analog signals can be transmitted at only a few hundred megasamples per second, reducing the channel bandwidth used. This rate is approximately one-tenth the digital rate required for the same number of physical communication paths. Furthermore, in traditional digital transmission, every bit occupies approximately 1.25 cm of bandwidth (the propagation speed of a cable is approximately 0.2 m / ns, so 16 Gbps is 1 / 16 ns / bit, or 0.2 / 16 meter per bit). By contrast, transmitting analog data frees up ten times the available time, allowing for additional bandwidth. Furthermore, each bit of digital data must be clearly defined. This definition is very sensitive to errors and noise and requires very accurate detection of the highest and lowest points.

[0024] The invention is particularly applicable to high resolution, high dynamic range display units used in computer systems, televisions, monitors, machine vision, automotive displays, aviation displays, virtual or augmented reality displays, mobile phones, signage, scoreboards, and the like.

[0025] <Sending analog signals to the display panel> 1 illustrates the use of conversion within the display unit 100 to provide an electromagnetic (EM) analog signal to a display panel 150. In this embodiment, the conversion of the digital video signal to an analog signal is performed within the display unit 100 itself, improving display connectivity.

[0026] The diagram shows a video signal 110 being transmitted to a display unit using an HDMI® interface (other interfaces such as LVDS, HDBaseT, MIPI, and IP video can also be used). It also shows a schematic of a system-on-chip (SoC) 120 and timing controller (TCON) 130, which provide digital video samples from the video signal to a transmitter 140. The SoC 120 performs functions such as display control, decompression, and specific digital signal processing, and outputs the video signal to the TCON. Typically, LVDS or V-by-One is used to transmit digital video data 122 from the SoC to the TCON. If LVDS pairs (for example) are used, the number of pairs varies by implementation and depends on the data rate per pair, panel resolution, frame rate, bandwidth, etc. Furthermore, various physical layers, such as a serial-deserializer (SerDes) layer, known in the art, can be used to transmit video data from the SoC 120 to the TCON 130. When the transmitter 140 is integrated with the TCON 130, this physical layer carries video data from the SoC 120 to the integrated TCON and transmitter, as shown in Figure 7. For example, up to 48 or more SerDes channels can be used to carry this video data.

[0027] Some or all of the digital or image processing may be performed within the SoC, in which case no image processing is performed after the line buffer and before the DAC of Figure 2. Preferably, the image processing includes some form of gamma and demurration correction, and may include image enhancement or correction (e.g., for motion compensation or adjustment between the bottom and top of the panel). Image processing is easier to perform in a parallel manner, but can also be performed in a serial manner (e.g., processors 250-259) or using sequential pixel to serial conversion.

[0028] Various implementations are possible, including a discrete implementation where the transmitter 140 is incorporated into a mixed-signal integrated circuit and the TCON and SoC are discrete components, a mixed implementation where the transmitter 140 is integrated with the TCON in a single IC and the SoC is discrete, and a fully integrated implementation where as much functionality as possible is integrated into a custom mixed-signal integrated circuit where the transmitter is integrated with the TCON and SoC.

[0029] In this example of FIG. 1, the display panel 150 is within the panel frame 151 of the display unit. As shown, the transmitter 140 and panel frame 151 are all within the display unit 100. The display panel 150 may be a display panel of any size, such as a monitor, a large screen television, a billboard, a scoreboard, or the like, or may be a display or displays within a VR headset, or a heads-up display (HUD) where the display is projected onto a windshield, visor screen, or the like. For purposes of this disclosure, "display panel" refers to the portion of the display unit (often called "glass") that implements the pixels that generate the light for viewing, and "display unit" refers to the entire (typically) rectangular housing that includes the display panel, panel assembly, frame, drivers, cables, and associated electronics for generating video images. Generally, a display panel having a size of approximately N 2 A mass-producible display panel containing pixels is controlled by approximately N voltages, each voltage being updated approximately N times per display interval (in reverse order of the frame rate).

[0030] Even if the signal input to a display unit is a digital video signal, there are significant advantages to using an analog signal for transmission within the display unit. Prior art display units must decompress the HDMI® signal to obtain full-bit-rate digital data and transmit it from the receiving point of the display unit to all source drivers within the display unit. These connections are quite long for a 65-inch or 80-inch display. The digital data must be transmitted from one location within the display unit where the input is located to another location (probably on the other side) where the final source driver is located. Therefore, converting the digital signal to an analog signal internally and sending that analog signal to the source driver has advantages, such as allowing the use of a lower frequency signal.

[0031] 1 is a transmitter 140 that generates analog EM signals 192 for the source drivers 186. Included are rigid PCBs 182 and individual flexible PCBs 184 that each hold a source driver 186 that generates source voltages for the display panel. As explained in more detail below, signal 180 optionally provides information about the display panel back to transmitter 140 to aid in the processing of video sampling. The generation of gate driver control signals 190 by the gate driver controller may be performed by a timing controller (or by other specific hardware) as known in the art, and may be based on synchronization signals from the source drivers.

[0032] Typically, the transmitter 140 and the receiver (in this case, the source driver 186) are connected by a transmission medium. In various embodiments, the transmission medium can be a cable (such as an HDMI®, flat cable, fiber optic cable, metallic cable, non-metallic carbon track flex cable, or metal wire) or can be wireless. The transmission medium has many EM paths, one path for each EM signal 192. The transmitter includes a distributor that distributes the received video samples to the EM paths. The number of paths can vary from one to multiple. In this example, the transmission medium is a combination of cable, wires on a PCB, IC interconnects, and other media used by those skilled in the art.

[0033] In operation, a stream of time-ordered digital video samples 110, containing color values ​​and pixel-related information, is received by display unit 100 from a video source and sent to transmitter 140 via the SoC and TCON. The number and content of input video samples received from the video source depends on the color space operating at the source (and the samples may be black and white). Regardless of the color space used, each video sample represents the amount of light sensed or measured in the specified color space.

[0034] The signal from the SoC (typically an LVDS digital signal, but other signals are possible) is pixel values ​​delivered in row-major order through successive video frames. Multiple pixel values ​​may arrive at a time (e.g., two, four, etc.), but groups of pixels are serial in the sense that they are transmitted sequentially from one end of the line to the other. A processing unit, such as a timing controller unpacker, can be used to unpack (or expand) these serial pixel values, for example, into parallel RGB values. It should also be understood that the expanded color information for each sample set is not limited to RGB and can be any color information (e.g., Y, C, Cr, Cb). If color information other than RGB subpixels is used, additional processing may be required before the source driver drives the columns (which are essentially subpixel luminance values). The number of output sample values ​​S for each pixel sample set depends on the color space applied by the video source: S = 3 for RGB and S = 2 for YCbCr4:2:2. In other situations, each sample set may have one or more sample values ​​S.

[0035] The unpacker can also unpack framing information from the digital signal in the form of framing flags that accompany the pixel values. Framing flags indicate the location of pixels within a particular video frame. They mark the start of a line, the end of a line, the active video section, the horizontal and vertical blanking sections, etc., as known in the art. Framing flags are used to instruct the gate drivers which line is currently being sent to the display panel and also control the timing of the gate driver operation. Framing flags can be included in the gate driver control signals 190, as known in the art. Typically, symbol and sampling synchronization occurs before extracting framing information such as Hsync and Vsync (and other line control information).

[0036] The TCON 130 provides a reference clock 170 to each source driver 186. That is, each source driver chip (e.g., a HyphyHY1002 chip) has a clock input provided by the TCON (whether an FPGA or an IC). Although clock 170 is shown as an input to only the first source driver for clarity, each source driver receives a reference clock. This reference clock may be at a relatively low frequency, for example, on the order of 10.5 MHz. See FIG. 17C for details about the reference clock.

[0037] <Transmitter> FIG. 2 shows the architecture of the transmitter 140 in the display unit. It shows a distributor 240 containing two line buffers 241 and 242, a distributor controller 230, a number P of image processors 250-259, digital-to-analog converters 260-269 following each image processor, and analog EM signals 270-279 output from each DAC. In this example, there are 24 source drivers, i.e., 24 EM paths, or P=24. There may be a single EM path or multiple EM paths. Depending on the implementation and design decisions, multiple outputs may improve performance, or more paths may be required.

[0038] The controller 630 stores a line of pixels for display in one of the line buffers and, when the line is complete, outputs the line (to a DAC or other line buffer, as described below). Typically, a line of pixels for the display panel arrives serially from the SoC, but because the gate drivers display a line of pixels simultaneously, the source driver must prepare an entire line of pixels simultaneously. Thus, each line buffer stores a line of pixels. Furthermore, because the gate drivers may enable only half the line of pixels on the display panel, a line is stored in the line buffer, and half is extracted and transmitted while a new line is stored.

[0039] Generally, when a stream of input digital video samples is received in row-major order within the transmitter 140, the input digital video samples are repeatedly (1) distributed to one of the EM paths according to a predetermined permutation (in this example, row-major order, i.e., identical permutation), (2) converted to analog, and (3) transmitted over the transmission medium as one EM signal per EM path. Each source driver 186 receives the input analog EM signal at its input terminal, and each analog sample is distributed via sampling circuitry to the storage cells of a particular column driver in the reverse order of the predetermined permutation used by the transmitter. Once all samples for that source driver are in their proper locations, they are driven to the display panel. As a result, the original stream of time-ordered video samples, including color and pixel-related information, is transmitted from the video source to the video sink. Due to the reverse permutation, the received samples are effectively stored as rows in the storage array (for display on the panel) in the same order as the rows of samples received at the distributor. The samples may arrive sequentially in R, G, B order, or RGB may arrive in parallel as three separate signals. A distributor 240 can be used to change the order of the samples as needed.

[0040] In one embodiment, four control signals are inserted into the distributor's sample stream sent to the source driver every 60 video samples. As shown, each input vector 280 of the line buffer contains 1024 values, including four control signals for every 60 video samples. The control signals can be inserted at various locations in the input vector. For example, "samples" 960-1023 of input vectors 280-288 may actually be control signals. Any number of control signals can be used in each input vector. Furthermore, any finite number of control signals can be used. The more control signals transmitted, the higher the required data transmission rate. Ideally, the number of control signals is limited to fit within the blanking period to allow for transmission speed and display line correspondence (reducing storage requirements and additional resynchronization). Furthermore, the control signals can be inserted into the sample stream at the distributor or elsewhere.

[0041] The distributor 240 is configured to receive color information (e.g., R, G, and B values) of pixels decomposed in a sample input set. The distributor 240 receives the decomposed color information and writes multiple input vectors 280-288 into a first line buffer 241 (one input vector per EM path) according to a predefined permutation. When the line buffer 241 is full, each input vector 280-288 is read out via a corresponding output port 281-289 to a corresponding DAC or, as appropriate, to a corresponding image processor 250-259. Once these input vectors are read out of the line buffer 241 (or when the line buffer 241 is full), the next line of RGB input samples is written into input vectors 290-298 of the second line buffer 242. Thus, once the second line buffer 242 is full (and the DAC or image processor has finished reading the input vector from the first line buffer 241), the DAC or image processor begins reading samples from the second line buffer 242 via output ports 291-299. Writing and reading from the first and second line buffers continues in this "ping-pong" fashion as long as input samples arrive at the transmitter. Output ports 281-289 and 291-299 may be bit-serial, but are more likely to be consecutive word-wide samples or parallel word-wide samples.

[0042] In a preferred embodiment for writing to and reading from line buffers, as samples arrive at transmitter 140, they are written to only one of the line buffers, for example, buffer 241. When that buffer is full, all samples are written in parallel from buffer 241 to line buffer 242. Samples are then output only from buffer 242 to the DAC (or image processor). This process occurs continuously: while buffer 242 is outputting samples, buffer 241 fills, and when buffer 242 is empty, all samples from buffer 241 are written to buffer 242, and so on. Samples can be written from buffer 241 to buffer 242 during the horizontal blanking interval.

[0043] The number of line buffers required is determined by the relative times it takes to load and unload the buffers. The RGB input comes in as a continuous stream of data. If it takes time T to load all the samples into a buffer and the same time T to unload, then two buffers are used (so one can be loaded while the other is unloaded). If the unloading time becomes shorter or longer, the buffer length can be adjusted (i.e., by adjusting the number of input vectors or by adjusting N for each input vector) so that only two line buffers are required. Nevertheless, more than two buffers can be used if desired, and any of the above embodiments can be used to write to and read from the buffers.

[0044] The distributor controller 230 controls the operation and timing of the line buffers. In particular, the controller is responsible for defining the permutation and number of samples N to use in constructing the four input vectors. In this example, N=1024. The controller 230 may also include a permutation controller that controls the distribution of RGB samples to positions within the input vectors.

[0045] The controller 230 may also include a permutation controller that controls the distribution of samples to positions within the input vector. The controller is also responsible for coordinating clock domain crossings from a first clock frequency to a second clock frequency. In a particular embodiment, the samples are permuted as follows: PIXEL The analog samples are clocked in at a frequency of Fsavt, and samples are serially clocked out from each input vector at a sampled analog video transmission (SAVT) frequency of Fsavt. It is also possible to clock in samples two at a time, three at a time, etc., rather than one at a time. The analog samples are transmitted along the electromagnetic path of the transmission medium to the SAVT receiver as analog EM signals 270-279.

[0046] In a particular embodiment, each line buffer 241 or 242 has three input ports for input RGB samples, and the samples are F PIXEL Each line buffer has 24 more output ports, e.g., 281 or 291 (if there are 24 EM signals, each going to one of the 24 source drivers), and samples are clocked out of each input vector at the sampled analog video transmission (SAVT) frequency, Fsavt. It is also possible to clock in two R, two G, and two B samples simultaneously, or even three at a time, rather than one at a time. In one embodiment, for 24 channels, Fsavt=663.552 MHz.

[0047] For illustrative purposes, one possible permutation is one in which each input vector contains N samples of color information and control signals. In this example, the unwrapped RGB samples of a sample set are assigned to input vectors from left to right. That is, the "R," "G," and "B" values ​​of the first sample set are assigned to input vector 280, in that order (i.e., RGBRGB, etc.). Once input vector 280 has been assigned N samples and control signals, the above process is repeated for each of the other input vectors, in order, until each input vector has been assigned N values. The number of N values ​​per input vector may vary significantly. As shown in this example, this predetermined permutation maintains a row-major order of the input samples. That is, the first input vector 280 contains samples 0 through 1023 of the first row, in that order, and subsequent input vectors continue that permutation (including control signals). Thus, distributor controller 230 performs the permutation by assigning input samples to specific addresses within the line buffer. It should also be understood that the distributor controller 230 can use any permutation scheme, and regardless of the permutation scheme used by the transmitter, the control logic of each source driver uses the inverse permutation to distribute the input samples to the column drivers. If only one electromagnetic path is used and the video samples are received at the SAVT transmitter, the distributor writes to one input vector in each line buffer.

[0048] Although image processors 250-259 are shown after the line buffers and before the DACs, it is preferable to have an image processor (or processors) before the line buffers because this reduces the number required: image processing can be performed as RGB samples arrive, and then the samples are distributed to the line buffers. Pixels arriving one at a time are displayed. If pixels arrive one at a time, one image processor is used; if pixels arrive two at a time, two image processors are used. Even if the image processors are located before the line buffers, certain processing, such as gain management, may be performed after the line buffers.

[0049] Typically, image processing involves a) applying gamma correction to each sample; b) level-shifting each gamma-corrected sample by mapping it to the range (0...255) to (-128...127) to remove DC components from the signal; and c) applying path-specific amplifier dispersion correction to each gamma-corrected, level-shifted sample, performing gain correction for each sample, performing offset adjustment for each sample, and performing demurrage correction for each sample. Other corrections and adjustments may also be performed depending on the target display panel. Individual image processors 250-259 may process each output stream of samples (e.g., 281 and 291), or a single monolithic image processor may process all outputs at once (e.g., 281 and 291, 285 and 295, etc.). To avoid performing image processing on the control signals in the line buffer, the timing of the control signals and their location in the buffer are known, allowing the control logic to determine that no image processing of the control signals should be performed. As mentioned above, image processing does not have to occur within the transmitter 140, but may occur elsewhere, such as within the SoC 120, within the TCON, or within the receiver. For example, gamma correction is traditionally performed in the receiver (source driver), but de-mura and more complex image processing cannot be achieved in the source driver.

[0050] The processed digital samples of each input vector are serially input to one of the DACs 260-269 (regardless of whether image processing occurs before or after the line buffer), which converts these modified digital samples at a frequency of Fsavt and transmits the modified analog samples as analog EM signals 270-279 along the electromagnetic path of the transmission medium to the display unit's source driver. Each DAC converts the received samples from the digital domain to a single analog level. This analog level can be transmitted as a differential pair of voltage signals with a magnitude proportional to the received digital value. The analog level is serially transmitted as an output from each DAC. The DAC output voltage can range from a maximum voltage to a minimum voltage, ranging from approximately 1 volt to 4 volts Vpp (peak-to-peak), with approximately 2 volts Vpp being effective. In one particular embodiment, it represents signals with a dynamic range of ±500 mV or 1 V (in practice, the dynamic range at the input is approximately 30% higher, i.e., approximately 1.3 V).

[0051] Although two line buffers are shown in distributor 240 (and are preferred), a single line buffer could be used, and while samples from a particular input vector are being read into its image processor (or its DAC), the distributor backfills that input vector with incoming samples so that there is no interruption in the serial delivery of samples from the line buffer to the DAC or image processor. Additionally, although less preferred, it is possible to place each DAC (or multiple DACs per EM path) after the distributor and before the image processor (if any) and perform image processing on the analog samples.

[0052] FIG. 3 shows an embodiment of the distributor 240' in which a different predetermined permutation is used. This predetermined permutation can be used to reduce wiring complexity within each source driver. The distributor 240' orders the samples and control signals in each input vector 380-388 in this order: 0, 64, 128, 960, 1, 65, 129, 961, and so on, up to 63, 127, 255, 1023. (This index corresponds to the index shown in FIG. 6, i.e., each amplifier handles 64 samples and control signals.) Thus, each input vector inputs 1,024 values ​​for its particular EM path at a time (assuming 64 control signals are applied to each of the 960 actual samples from the TCON), and the samples are distributed by the controller to each input vector as shown using the predetermined permutation. Although not shown, 64 control signals could also be added to the end of each input vector to distribute four control signals to each amplifier, as shown in the source driver of FIG. 6. The numbers 64 and 960 are implementation dependent; a different number of control signals and / or number of columns per vector may be used.

[0053] The samples of input vectors 380-388 are then output from line buffer 245 to image processors 250-259 via output ports 381-389. Similar to the distributor of FIG. 2, the distributor alternates between writing samples to line buffer 245 or line buffer 246 and reading samples from line buffer 245 or line buffer 246. Line buffer 246 outputs samples to the image processor via output ports 391-399. By shuffling the sample order within the transmitter in this manner, each interleaved input sampling amplifier of a source driver (e.g., as shown in FIG. 6) can alternately operate to drive adjacent columns. Output ports 381-389 and 391-399 may be bit-serial, but could also represent sequential word-wide samples or parallel word-wide samples.

[0054] In another embodiment (not shown), the predetermined permutation used by distributor 240 orders samples by color for each input vector, i.e., sends all 320 red subpixels, followed by all 320 green subpixels, followed by all 320 blue subpixels, followed by all 64 subband signals. Thus, using the first input vector as an example, sample locations 0-319 contain red subpixels, sample locations 320-639 contain green subpixels, sample locations 640-959 contain blue subpixels, and locations 960-1023 contain the 64 subband signals for a particular row. The samples are then sent to the image processor (all red, all green, all blue, all subbands). Other input vectors use the same permutation to group samples by color. Of course, the subpixel colors within an input vector can be in any order (not necessarily red, green, blue), and the 64 subband signals can be inserted anywhere within the grouping. The reason for this ordering is to take advantage of a natural image heuristic: individual color components tend not to exhibit high spatial frequencies, thereby reducing potential electromagnetic interference signals generated by the system when samples are grouped in this manner. In fact, as long as substantially all of the subpixels of a particular color are grouped together, substantial EMI is reduced. Furthermore, this ordering not only allows for the use of slower S / H amplifiers in the source drivers, but also reduces the bandwidth required for the communication channel from the transmitter to the receiver. The control logic in each source driver uses the reverse of this ordering to direct input samples to the correct column drivers.

[0055] 4 is a block diagram of an alternative embodiment of each DAC following the image processor. As shown, instead of a single DAC following (for example) image processor 250, there are four interleaved DACs 361-364 that process the modified samples output from the image processor. Any number of DACs is possible, but multiples of two DACs (e.g., 2, 4, 8, 16) are common. Latches 351-354 are used to sample and route specific samples output from the image processor to the corresponding DAC. Thus, for example, using four DACs, the first four samples (Sample 0, Sample 1, Sample 2, Sample 3) would be delivered to DACs 361-364 in that order, and the next four samples (Sample 4, Sample 5, Sample 6, Sample 7) would also be delivered to DACs 361-364 in that order. The multiplexer 340 is used to multiplex the analog samples output from each DAC so that they are arranged in the EM signal 270 in the same order as they were output from the image processor 250. The multiplexer 340 can be implemented as a selector, and the control of the selector can be either an alternating enable bit in a shift register or a counter + decoder. Although not shown, each of the other image processors also has a similar interleaved DAC. This embodiment allows the use of slower DACs. The image processor 250 can also follow a DAC, in which case it is an analog signal processor.

[0056] <Source driver architecture> FIG. 5 shows one embodiment of the architecture of a source driver 400 of a display panel. Typically, there are 24 such source drivers of a display panel, i.e., P equals 24 (for an 8K display, less for a 4K display). Note that the source drivers do not require an analog-to-digital converter (ADC) to convert samples to analog for display. Table 1 shows the parameters, values, and units of the source drivers used in an 8K144 display panel. Thus, each of the 24 source drivers drives 960 columns, providing one row of subpixels of the display (23,040 subpixels per line). [Table 1]

[0057] The input to source driver 400 at input terminal 410 is one of the EM signals from transmitter 140. In this example, terminal 410 receives 1,024 analog values ​​serially at a time, which are stored in either row A or row B of storage array 434 or 436 via S / H amplifiers 420-429. The analog video samples arrive in their natural order according to the predetermined permutation shown in the example of Figure 2, although this requires more complex wiring in the source driver as shown. Other permutations can also be used.

[0058] The source driver 400 consists of 16 interleaved hold input amplifiers 420-429 that sample the input 410 at Fsavt / 16. There are 16 blocks (430 being the first) of 60 video signals and 4 control signals. Each of the S / H amplifiers 420-429 sequentially samples a specific analog sample and stores it in one of 64 storage arrays 434 or 436, 60 of which are fed directly to the column driver 440. Because the input amplifiers 420-429 are interleaved, they can run 16 times slower than the input signal. Each is phase-shifted by one SAVT interval. As shown, S / H amplifier #0 420 drives columns 0, 16, 32, etc., and S / H amplifier #1 421 drives columns 1, 17, 33, etc. Thus, each S / H amplifier output spans all 960 columns (one amplifier output for every 16 columns).

[0059] In one embodiment, each of these storage elements in storage array A or B is a storage cell, such as a switched capacitor. Other terms for a storage cell are a "sampler capacitor" or an "analog latch." There are also 960 high voltage column drivers 440, each of which drives (via output pins) columns 450 that supply the voltages required by the display panel 480. As shown, there are 16 blocks of 60 video + 4 sync signals 460 (Hsync, Vsync, CTRL, etc.) per block.

[0060] Once stored (e.g., in row A), these 960 samples are driven to each output column 450 via the column driver 440 while the next set of 960 analog samples is simultaneously stored in the other row (e.g., row B). Thus, while one set of input 960 samples is being driven onto the column from either row A or B, the next set of 960 samples is being stored on the other row. In one particular implementation, each analog level arrives at the S / H amplifier 420 as a differential signal, swinging between approximately +0.5 or −0.5V, with a maximum swing of approximately 18V around the midpoint of each single-ended column driver and therefore requiring amplification. Note that in addition to amplification, at some point the differential signal (−full scale representing dark and +full scale representing light) is converted to single-ended, and a drive polarity is applied so that the dark subpixels are at, e.g., 9V, and the light subpixels are at full-scale positive (e.g., 18V) or minimum (e.g., 1V) voltage, depending on the polarity setting. An example source driver is shown in more detail in Figure 21.

[0061] Control logic 470 implements the reverse of the predetermined permutation used in transmitter 140, controlling the timing of the S / H amplifiers (when each samples a particular input analog sample) via control lines 471, the timing of the storage elements of rows A and B (when each row latches a particular analog sample) via control lines 472, and the timing of when each column driver 440 drives each column via control lines 473. For example, if the transmitter uses the predetermined permutation described above in which particular subpixel colors are grouped in an input vector and then transmit those groups in an EM signal, control logic 470 uses the reverse of this predetermined permutation to route the input samples to the correct column drivers. At a minimum, control logic 470 knows how distributor controller 230 arranged the input samples in the input vector and uses this prior knowledge to direct the input samples to the correct column drivers so that the samples are displayed as they appeared in the original source image.

[0062] Note that the number of S / H amplifiers 420–429 is a trade-off between quantity and quality. The more amplifiers used, the slower, smaller, and noisier they are, and the smaller the load each amplifier drives. However, the load on the input terminal 410 increases with the number of S / H amplifiers, affecting transfer quality. Therefore, the number of input amplifiers used is a design decision. To address RFI / EMI emissions concerns, it is possible to slightly vary the interval between each clock period. The inputs to the S / H amplifiers only swing ±250 mV around the common-mode voltage (positive and negative inputs, respectively), resulting in a ±500 mV signal (1 V dynamic range). This is a voltage swing similar to that of traditional digital signals such as CEDS and LVDS. In both cases, clock modulation can be used to reduce RFI / EMI emissions, but this modulation is undesirable because it cuts into the sampling window. Furthermore, to optimize the source driver performance (to counteract process variations in the implemented S / H amplifiers), a low-frequency feedback network can be added off-chip to characterize the gain and offset of each amplifier in the source driver, but this approach is not preferred due to area and performance constraints.

[0063] An alternative way to optimize the performance of the source driver output is to utilize existing compensation techniques in the display unit itself. Modern OLED (and microLED) manufacturing techniques characterize the response of each subpixel in the array and pre-compensate for individual offsets using a table of manufacturing data that is stored in the TCON and used when generating samples. Therefore, based on the physical characteristics of the entire display unit (including the transmitter, amplifier, source driver, each pixel, etc.), each subpixel may have a different characteristic response, i.e., be too bright or too dark. The table contains the individual offsets for each characteristic response.

[0064] Note that in source driver architecture 400 or 500, a given one of interleaved sampling amplifiers 420-429 or 520-529 stores pixel voltages in switched capacitors, which are then amplified for a given column. Therefore, each column is driven through the same amplifier in each row. As-fabricated amplifier linearity errors, such as gain error, overlap in a regular pattern with other errors measured for individual subpixels along a column by existing compensation techniques. Therefore, these existing OLED error compensation techniques will also compensate for all linearity errors in the amplifiers of the proposed source driver. This observation suggests that design requirements (e.g., with respect to gain accuracy) can be relaxed, potentially enabling a lower-cost implementation. In a particular preferred embodiment, there are three amplification stages, and the amplifier includes a common-mode feedback amplifier.

[0065] Figure 6 shows another embodiment of the architecture of a display panel source driver 500. Similar to Figure 5, there are shown input terminals 510, input S / H amplifiers 520-529, rows of storage elements in arrays 534 and 536, column driver 540, output 550, sub-band signals 560 (e.g., synchronization signals such as Hsync, Vsync, and CTRL), control logic 570, and display panel 580.

[0066] In this embodiment, each S / H amplifier 520-529 drives 64 adjacent locations (60 columns + 4 subband values), reducing wiring complexity within the source driver and shortening the physical distance that one of amplifiers 520-529 must drive. It also facilitates Demura correction. For example, the first block 530 of 60 video signals and 4 subband signals is driven by amplifier 520, block 531 is driven by amplifier 521, and block 539 is driven by amplifier 529. This configuration facilitates conventional high-MTF Mura correction solutions because gain errors from any input sampling amplifier will also appear in 60 adjacent columns, making them easier to detect in a Demura system.

[0067] To implement this embodiment, as shown in FIG. 3, distributor 240′ transmits the samples in this order (0, 64, 128, 960, 1, 65, 129, 961, and continuing through 63, 127, 255, 1023), with the last 64 values ​​being control signals. Thus, by permuting the sample order at the transmitter, each interleaved sampling amplifier can alternately drive adjacent columns. Control logic 570 implements the reverse of the predefined permutation used in distributor 240′ of FIG. 3, controlling the timing of the S / H amplifiers (when each samples a particular input analog sample) via control line 571, the timing of the storage elements of rows A and B (when each row latches a particular analog sample) via control line 572, and the timing of when each column driver 540 drives each column via control line 573. Note that in this embodiment, each sampling amplifier drives 60 column and 4 sub-band signals.

[0068] <Embodiment of Source Driver Architecture> 5 and 6 disclose source driver architectures. Other architectures are also possible, where the order in which subpixels are sent from the transmitter is manipulated, control signals are distributed among multiple amplifiers, certain amplifiers are sent exclusively through one channel, subpixels are grouped by color, etc., all for a variety of reasons depending on the particular implementation.

[0069] FIG. 11 illustrates a specific subpixel transmission order in which subpixels are grouped by color to minimize transmission bandwidth. Table 800 shows the RGB subpixel indexes of the subpixels collected by each input amplifier of the source driver. As shown, each amplifier 802 first receives a control signal, followed by a series of subpixels 804—in this example, first red, then green, and then blue. The subpixel transmission order from the transmitter is top to bottom, left to right, and is received by a particular amplifier as shown. Because color information tends to change more slowly than luminance information in a video image, grouping subpixels by color results in fewer transitions and reduces bandwidth.

[0070] While this is a desirable architecture for certain applications, extracting the control information can be difficult if the control signals are distributed to all S / H amplifiers (as in Figures 5 and 6), and this architecture (also in Figure 5) increases the load on each amplifier channel because each amplifier must also drive all 960 columns of the display.

[0071] FIG. 12A shows a specific subpixel transmission order in which subpixels are still grouped by color to minimize transmission bandwidth, and the control signals all arrive on one dedicated amplifier channel. Table 810 shows the RGB subpixel indexes of the subpixels collected by each input amplifier of the source driver. As shown, amplifiers 812 are numbered 0 through 15, and each amplifier 0 through 14 receives a sequence of subpixels 804—in this example, first red, then green, followed by blue. Amplifier 15 receives only a control track 816 of control signals. This configuration has the advantages of fewer transitions and reduced bandwidth, as discussed above, as well as simplified extraction of control information. Also, each amplifier serves only 320 columns, rather than the entire 960 columns.

[0072] While color grouping has some advantages and is the preferred architecture for certain applications, 960 subpixels / 15 amplifiers / 3 colors is not an integer number, so the video data must be padded. The additional padding overhead means that there are 66 samples per line per amplifier instead of 64. This means that the transmission frequency must be multiplied by 64 or 66, partially defeating the purpose of reducing transmission bandwidth by color grouping. Also, driving the entire 320 columns is not as desirable as driving only 64 columns.

[0073] FIG. 12B shows a specific embodiment in which subpixels are grouped by color with transition bands between the groups. This embodiment can be used in the implementation of the HYPHY integrated circuit chip "1002." Because color has a lower frequency content than luminance, when color changes, the change occurs more slowly because it can be abrupt. For example, going from pixel index 958 to 2 (green to blue) can take a long time if the transmitter channel bandwidth is not wide enough. Adding a blank transition band 817 slows down the change and helps minimize bandwidth.

[0074] To minimize the bandwidth requirements of the SAVT, the 1002 chip uses the illustrated permutation, transmitting all subpixels of each color in groups. This permutation inserts blank transition bands (i.e., bands of blanking transition signals) between color groups to reduce the bandwidth required between groups. SHA amplifier 0 is a control channel 818 that provides control signals 0 through 64, i.e., 65 samples per line are transmitted. As shown, red subpixel indexes run from 0 to 957, green from 1 to 958, and blue from 2 to 959. Sample 815 is the red blanking transition signal (tr0...tr4), sample 816 is the green blanking transition signal (tg0...tg4), and sample 817 is the blue blanking transition signal (tb0...tb4). These transition bands 815, 816, and 817 provide the blanking transitions between colors.

[0075] In light of the above, and recognizing that bandwidth limitations may not be important in certain applications, that the control information is substantially random, that padding may not be desirable, and that it is advantageous to group control signals into one channel, an alternative architecture is proposed.

[0076] FIG. 13 shows an alternative architecture for a source driver in which each distribution amplifier drives adjacent columns and all control signals are processed by a single amplifier. Provided the bandwidth is sufficient, FIG. 13 provides an architecture that minimizes wiring. An input terminal 822 is shown that demultiplexes and distributes pixel data and control signals from the transmitter to an S / H amplifier 824 (which inputs pixel data numbered 0 through 14) and an amplifier 826 that receives the control signals. The pixel data from amplifier 824 is forwarded to either storage array A 828 or storage array B 830 as described above, and the control signals are processed by component 836 and output at 838. The pixel data from either storage array is then input to column driver 832 and output to column 834 as described above. Control logic for controlling the timing of the input amplifiers, storage arrays, and column drivers is not shown; however, such control logic is described above with reference to FIGS. 5 and 6. Pixel data is received sequentially on a single channel (per chip) and stored sequentially (at 1 Fsavt cycle intervals) in the A / B collector, but it is also possible to store 15 subpixels from 15 SHA amplifiers in parallel in the array.

[0077] In this way, 15 interleaved S / H amplifiers receive incoming pixel data and each drive 64 adjacent columns, i.e., 64 video tracks, thereby minimizing the span of columns driven by each amplifier. This architecture provides 15 blocks of 64 video samples and one 64-bit subband channel (control signal) per display line (per source driver). For example, amplifier 0 drives columns 0-63, the second amplifier drives columns 64-127, etc., the 15th amplifier drives columns 896-959, and amplifier 826 drives the control signal. Having all the control signals on one channel means there are no differences in amplitude or delay from one signal to the next (as would be the case if they were on different channels). It is also possible for the control signal to arrive at channel 0 (i.e., amplifier 0) rather than amplifier 15. This is advantageous in that the control information arrives earlier than the pixel data. Another advantage of this architecture is that synchronization is simplified since the control signal extraction only needs to look at one de-interleaved amplifier output, rather than being distributed to all amplifiers.

[0078] In this diagram, there are 15 video amplifiers, each driving 64 subpixels, for a total of 960 subpixels per chip. There is one control channel, carrying 64 symbols per line (per source driver). By using MFM for timing synchronization (see below), the 64 symbols are transition encoded, leaving 24 or 25 control bits per line after accounting for flag and command bits.

[0079] As shown, the control channel receives a control signal at amplifier 826. This control signal is input to comparator 836, which has a reference voltage of 0V and operates at 1 / 16 of Fsavt (i.e., approximately 41.5 MHz). Assuming the control signal is in the range of -0.5V to +0.5V, the comparator detects whether the control signal is greater than 0V (representing a digital one) or whether the control signal is less than 0V (representing a digital zero). This digital data is output at 838, providing one control bit every 16 samples. The control signal provides synchronization and phase adjustment, as will be described below.

[0080] This particular embodiment is for an 8K144 display, with example parameter values ​​shown above in Table 1. Those skilled in the art will recognize that the architecture can be easily modified for other display sizes and speeds. By changing the order of the samples in the transmitter, each interleaved S / H amplifier can drive adjacent columns, operating in alternating fashion, as described below.

[0081] Figure 14 shows the source driver inputs of source driver 820 for interleaving multiple input amplifiers, allowing for speed requirements to be met. (A single amplifier could also be used, but at a reduced transmission speed.) Shown are input terminal 822, distribution input amplifiers 0-14 (824) and amplifier 826, and, in some cases, associated switches 842 that alternately connect one amplifier at a time to receive one of the incoming subpixels or control signals. Thus, the inputs are interleaved by 16, and the outputs of the switches are demultiplexed into 16 channels operating at 1 / 16 the data rate. The 960 subpixels in a line are grouped into 15 groups of 64 subpixels each, with one channel dedicated to detecting and processing the control signals.

[0082] Figure 15 is an overview of the pixel transmission order 300, showing how pixels 0-959 and control signals 0-63 are transmitted from the transmitter to the source driver of Figure 13 and assigned to which amplifiers. Shown is the natural order of subpixels delivered from the TCON to the source driver via conventional CEDS, e.g., subpixels arrive to be read from left to right, then top to bottom. Because the source driver interleaves the input data 16-way, the preferred way to transmit subpixels to the source driver is from top-left, top to bottom, then left to right, i.e., the transmitted subpixel (and control signal) indices are 0, 64, 128, etc. Shown are the indexes of the S / H amplifiers 302, an example subpixel index 304, and the control track 306 for the 16th amplifier.

[0083] In this permutation, 15 amplifiers (0-14) each drive 64 adjacent columns with subpixel values, and amplifier 15 processes all 64 control signals. This variation minimizes the source driver hardware and minimizes the wiring load on the input amplifiers. Furthermore, this variation allows for the slowest possible SAVT (analog video transmission) transmission rate (64 × 16 samples per line) because no padding is required in the data sequence. For optimal display of text and other abrupt intensity transitions, it is desirable for the sampling amplifiers to settle to a new value every 1 / Fsavt, or approximately 1.5 ns per sample. To implement this architecture, the transmitter sends the following sequence of subpixel indices: 0, 64, 128, 832, 896; 1, 65, 897; 63, 127, 191, 895, 959.

[0084] Figure 16 is a block diagram of a transmitter input vector 320 with a predetermined permutation that provides the sequence of subpixel transmissions required by Figure 15. As previously described, as the subpixels arrive at the distributor from the timing controller, they are distributed to the input vector 320 in the order shown. Once filled, the samples in the input vector are then serially output via output port 321 to an image processor as previously described, where they are converted and transmitted to a source driver having an architecture similar to that described in Figure 13. Not shown are the other input vectors for the line buffer. Each input vector has a similar permutation, and the other source drivers corresponding to each input vector have the same architecture as shown in Figure 13. Also shown are control samples at specific locations. As with any of the synchronization signals, sub-bands, control tracks, and digital data of Figures 5, 6, 11, 12A, 12B, 13, and 16, i.e., signals that are sent for control purposes rather than actual video samples that are displayed, these signals may be spread across many S / H amplifiers as shown, or may be sent on a dedicated channel or track, i.e., for example, track 15 in Figure 12A or track 0 in Figure 12B.

[0085] The above architecture of the source driver-driver 820 of Figure 13 together with the above transmission order provides the above advantages and also keeps the SAVT clock rate as slow as possible. Accurate sampling of each sub-pixel within the available time is provided by synchronization as described below.

[0086] <Transmitter integrated into timing controller> As mentioned above, in an alternative embodiment, the transmitter is integrated into the timing controller rather than the separate implementation shown in FIG.

[0087] FIG. 7 is a block diagram illustrating an integrated transmitter and timing controller 640 located immediately after the SoC 120 of a display unit 600. The digital video signal 110 is shown input via an HDMI connector (or via LVDS, HDBaseT, MIPI, IP video, etc.) to the system-on-chip 120, which performs functions such as display control, decompression, brightness, contrast, and overlay. The modified digital video signal 664 is then sent to the integrated transmitter and timing controller 640 using LVDS, V-by-one, etc. In this embodiment, the timing controller is integrated with the transmitter, and both are implemented in a circuit, preferably an integrated circuit, on a semiconductor chip. Note that the transmitter and timing controller chip 640 is located immediately after the SoC chip 120, thus facilitating the transmission of the digital signal (at that point). Preferably, the chip 640 is located approximately 10 cm or less from the SoC chip, approximately 5 cm or less in other embodiments, and approximately 2 cm or less in other embodiments. The physical characteristics of LVDS limit the maximum distance for chip-to-chip communication to a few inches.

[0088] The integrated transmitter and timing controller 640 receives the digital video signal 664, distributes it to the line buffer or buffers, performs image processing, converts the digital samples to analog samples, and transmits the EM signals to the source drivers as described above. Typically, the EM signals 192 are sent to the source drivers 186 using differential pairs of wires (or metal lines), e.g., one pair per source driver. The gate driver control signals 190 control the gate drivers 160 to synchronize with the source drivers and enable the correct lines of the display. A single reference clock 170 from the transmitter and timing controller 640 can be distributed universally to all source drivers, since each source driver chip performs its own synchronization, although practical constraints on drive strength may mean that multiple clocks are preferable. In either case, frequency lock between the source driver chips is maintained.

[0089] Figure 8 shows the integrated transmitter and timing controller 640 in more detail, using many of the same blocks as Figure 2. Signal 664 is typically an LVDS digital signal as described above. Unpacker 620 unpacks (or unpacks) these serial pixel values ​​into parallel RGB values ​​and outputs framing flags 627 to distributor controller 630 and gate driver controller 650. Distributor 642 is arranged to receive the unpacked color information (e.g., RGB) from unpacker 620 and fill line buffers 241 and 242 according to a predetermined permutation.

[0090] As described above, the controller 630 coordinates the storage and retrieval of pixel values ​​to and from the line buffers.

[0091] As mentioned above, framing flags 627 come from the unpacker 620 and are input to the distributor controller 630. The distributor controller 630 uses these flags to determine the pixel's position within the line and store / place the pixel in the correct input vector. After the framing flags are output from the controller 630 (typically with a delay), they are input to the gate driver controller 650. The gate driver controller 650 generates a number of gate driver control signals 671 to control the timing of the gate drivers. These signals 671 include at least one clock signal, at least one frame strobe signal, and at least one line strobe signal. When pixel values ​​are pushed to the source driver for a particular line, the line strobe signal is used for the particular line enabled by the panel gate driver controller. The line strobe signal thus drives the selected line at the appropriate time. Timing control of the gate driver controller can be performed as is well known to those skilled in the art. Also shown is two-way communication 637 between the controller 630 and the gate driver controller 650, which is used for timing management between the source drivers and the gate drivers.

[0092] The operation of the two line buffers, image processors 250-259, and DACs 260-269 may be performed as described above. Preferably, the image processing occurs after the unpacker 620 and before the line buffers, in which case the image processing blocks 250-259 are eliminated and replaced with a single image processing block between 620 and 241, 242. Also, as described above, the image processing need not occur within the transmitter 640, but may occur in the SoC 120 or elsewhere.

[0093] <Transmitter integrated with timing controller and system-on-chip> As mentioned above, in an alternative embodiment, the transmitter is integrated with the timing controller and SoC rather than the separate implementation shown in FIG.

[0094] 9 is a block diagram illustrating an integrated transmitter, timing controller, and SoC 684 in a display unit 680. In this embodiment, the conversion of the digital video signal 110 to an analog signal 192 occurs within the single chip 684 that integrates the transmitter, timing controller, and SoC.

[0095] Shown is the input of a digital video signal 110 via an HDMI connector (or via LVDS, HDBaseT, MIPI, IP video, etc.) to the display unit 680, which is then transmitted internally 111 to an integrated SoC. The SoC performs conventional functions such as display controller, decompression, brightness, contrast, overlay, etc. After the SoC performs its conventional functions, the modified digital video signal (not shown) is delivered internally to an integrated transmitter and timing controller using an appropriate protocol such as LVDS, V-by-one, etc. In this embodiment, the timing controller and transmitter are both integrated with the SoC, with all three implemented within a single integrated circuit, preferably on a semiconductor chip.

[0096] A transmitter in circuit 684 converts the modified digital video signal into an analog EM signal 192 and transmits it to a display panel 690. Preferably, the signal 192 is sent to the source driver 186 using a differential pair of wires (or metal lines), e.g., one pair per source driver. Gate driver control signals 190 control the gate driver 160 to synchronize with the source driver and enable the correct lines of the display. Typically, the distance between chip 684 and source driver 186 ranges from about 5 cm to about 1.5 m, depending on the panel size. A transmitter timing controller and a single reference clock 170 from SoC 684 can be distributed to all source drivers.

[0097] The integrated chip 684 can be implemented as described herein, i.e., as shown in FIGS. 1-4 and 7-8, with the understanding that the transmitter timing controller and SoC functions are all integrated on the same chip or circuit. This embodiment of FIG. 9 has the same advantages as those listed above with respect to FIG. 7. Furthermore, integrating the transmitter and timing controller with the SoC chip provides additional advantages such as fewer chips, reduced complexity, smaller area requirements, and lower power requirements. Furthermore, no DACs (Digital-to-Analog Converters) are required in either the display panel or the source driver for video signal conversion.

[0098] <Embodiment of a video transmission system> 10 shows a video transmission system 700 within a display unit. A timing controller 702 is shown outputting a set of color samples, as described above, such as digital sub-pixel values ​​representing luminance values ​​from an image or video to be displayed on a display panel 710. The samples are input to a transmitter 704, converted to analog, and sent via a low-voltage wiring harness 706 to a source driver array 708 for display on the display panel 710.

[0099] The transmitter distributor includes a line buffer 720, any number of input vectors (or banks) 722-726, and a distributor controller 728. RGB samples (or black and white, or other color space) are continuously received by the distributor and distributed to the input vectors according to a predetermined permutation controlled by the distributor controller 728. In this example, a row-major permutation is used, with the first portion of a row of the received video frame (or image) stored in input vector 722, and so on, from left to right, with the last portion of the row stored in input vector 726. Thus, when the line buffer 720 is full, it contains all of the pixel information from the first row of the video frame, which will be transmitted to and displayed on the display panel 710 in the first line of the video frame. Each input vector is serially read out to a corresponding DAC 732-736. Each sample is converted to an analog sample for transmission. As the samples arrive continuously from the timing controller 702, they are distributed, converted, transmitted, and ultimately displayed as video on the display panel 710. As shown and described in Figures 2, 3 and 8, there may be more than one line buffer.

[0100] Connecting the transmitter 704 to the source driver array 708 is a low-voltage wiring harness 706 consisting of differential wire pairs 742-746, each carrying a continuous stream of analog samples (electromagnetic or EM signals) from one of the DACs 732-736. Each differential wire pair terminates at an input terminal 760 of one of the source drivers 752-756. Other transmission media (e.g., wireless, optical) are possible in place of a wiring harness.

[0101] Each source driver in a source driver array, such as source driver 752, includes an input terminal 760, a collector 762, and a number of column drivers 764 (corresponding to the number of samples in each input vector, in this example, 1024). Samples are received serially at input terminal 760 and collected in collector 762. Collector 762 can be implemented as a one-dimensional storage array or an array with a length equal to the size of the input vector. Each collector can be implemented using an A / B sampler (storage array) as shown in FIG. 5 or FIG. 6. Once each collector is full, all collected samples are then output in parallel to all column drivers 764 of all source drivers, amplified to the appropriate high voltage required by the display panel, and output to columns 766 using a single-ended format. As samples arrive continuously through the wiring harness, each collector continues to collect and output samples to the display panel, affecting the display of video.

[0102] <Synchronization of analog video sample transmission> Synchronization can be used to provide horizontal synchronization (start of a display line), vertical synchronization (first display line of a frame), and sample phase alignment (when to sample received subpixel samples). In other words, a receiver, such as a source driver, receiving a stream of video pixels needs information from the transmitter indicating the start of the frame, the start of the line, and when to sample the data representing a particular subpixel. For example, each switch 842 needs to know when the input sample is valid and stable so that it can sample the correct value. The timing of the sampling is determined by a process called sample phase alignment. Sample phase alignment accounts for different delays from the TCON to the display's geographically distributed source drivers. As explained in more detail below, the phase of the locally generated clock 171 (derived from the reference clock 170) is optimized relative to the locally distributed samples.

[0103] Synchronization is useful (and can be difficult) for a variety of reasons. For one, a constant stream of video subpixels inherently carries no information indicating the start of a frame, the start of a line, or phasing data. Also, the delay along the cable from transmitter to receiver can be variable and is generally unknown. Furthermore, attenuation on the cable (which can differ between paths to various source driver chips) can also be an issue. Finally, the waveform of the incoming subpixel values ​​can be unknown or fluctuating due to ringing, overshoot, filtering, rate of change of the input values, or other types of signal distortion.

[0104] Recognizing that synchronization is important and can be difficult due to the factors described above, the techniques described herein provide commands for synchronization and phase adjustment of analog samples.

[0105] A timing reference (i.e., a special timing violation that does not occur during normal data transmission) called a "flag" herein is used to notify the receiver, i.e., the source driver, that it may reset its clock and that what follows is a known command or data for synchronization. For example, when a flag is received, a command to initiate phase adjustment is received and the optimal sampling phase for sampling the incoming subpixels is determined. First, the sampling transmission frequency (the rate at which samples arrive at the input terminal of the source driver) is known; in this example, Fsavt is approximately 664 MHz (673.92 MHz for the HY1002). Because transmitting this high-frequency clock is impractical, in one embodiment, a slower clock, Fsavt / 64=10.375 MHz (10.53 MHz for the HY1002), is transmitted to each source driver, and each source driver uses a phase-locked loop to multiply the frequency to the high-frequency clock. We also know that each input amplifier has 15 sub-pixel data streams arriving at Fsavt / 16, each of these input amplifiers supplies 64 samples, and the 16th amplifier has a control stream arriving (either analog or digital control signal), for a total of 64 control signals per line.

[0106] FIG. 17A illustrates the source driver of FIG. 13 , showing the control channel in more detail and illustrating three comparators used to extract phase adjustment information from the control signal. In this particular embodiment, the control channel handled by amplifier 826 includes three comparators 835-837. Comparator 836 outputs a logic "1" or a logic "0" depending on the value of the control signal, as described above. Comparator 835 has a high reference voltage used to detect the upper threshold, and comparator 837 has a low reference voltage used to detect the lower threshold; these references may be set by a DAC. Comparators 835-837 operate at Fsavt=650 MSPS.

[0107] The central comparator is reliable (because it is a zero-crossing detector), and generally, the data extracted from this central comparator corresponds to the data extracted from the high and low channels, assuming everything is working correctly (i.e., if the control signal is +0.4V, both the central comparator 836 and the high comparator 835 will detect a logic "1"). However, if the sampling occurs at the wrong time, it is very likely that the central comparator will provide the correct bit, but the high and low values ​​from the other two comparators will be missing. The concept here is that the high and low data require the input to be nearly settled in order to receive the correct value, whereas the zero-crossing detector will receive the correct value even if the input sample is still changing. It is also possible to use only the high or low comparator along with the central comparator. The use of this information will be discussed later in relation to phase adjustment.

[0108] FIG. 17B shows an alternative source driver 820″ to that of FIG. 17A, showing more detailed control signals for the first amplifier. Shown are timing generation 821 (described below), input terminal 822, DAC 838 for adjustable threshold, and sampler block 839. Comparators 835-837 are clocked comparators for extracting the control signal. Amplifier 832 is an amplification stage including preamplifiers, level conversion, and a high-voltage driver. Sixteen interleaved sampling amplifiers with offset cancellation (SHA amplifier and offset control), including amplifier 826, are shown. Preferably, this embodiment uses amplifier 0 (826) for the control signal (rather than amplifier 15 as in FIG. 17A), ensuring that the control information arrives well before the end of the display line time. This allows a small amount of time to decode the control channel and set the signals to be used within the next line time.

[0109] FIG. 17C shows a preferred source driver 820″ for the source driver of FIG. 17B. Timing generation 821, input terminal 822, and sampling block 839 are shown. Comparator 836 is a comparator for extracting the control signal. Amplifier 832 is an amplification stage including preamplifiers, level translation, and high voltage drivers. Sixteen interleaved sampling amplifiers with offset cancellation (SHA amplifiers and offset control) are shown, including amplifier 826. Preferably, this embodiment uses amplifier 0 (826) for the control signal (rather than amplifier 15 as in FIG. 17A) so that the control information arrives well before the end of the display line time. This allows a small amount of time to decode the control channel and set the signals to be used within the next line time.

[0110] In this embodiment, synchronization is realized requiring only a single comparator 836 (zero-crossing detector) on a single SHA channel, and no DAC is required to set the comparison threshold. The synchronization algorithm is performed in the digital domain (zero-crossing detector output) and can perform both clock-level synchronization (adjusting the SHA output so that the side channel is seen at one specific SHA channel output) and phase-level synchronization (selecting the optimal sampling phase within a clock cycle).

[0111] There is one analog input differential with matched termination and ESD protection at input terminal 822. This is driven through a 50R transmission line with a 50R source impedance on each side. This results in a 50% reduction in receive voltage compared to the transmit voltage. The PLL 821 multiplies the relatively slow reference clock 170 (e.g., Fsavt / 64) from the TCON up to the full-speed Fsavt clock 171 with 11 selectable phases per clock cycle (e.g., approximately 675 MHz for the HY1002). There is also high-speed timing generation, generating the sampling strobes, reset signals, and output transfer strobes for SHA amplifiers 0 through 15. As shown in Figure 14, the SHA amplifiers are used to build a 16-way deinterleave circuit 840, whose ON switches are rotated so that only one is actually ON at a time. (In the HY1002, two amplifiers are always on simultaneously, overlapping by one SAVT cycle.) Thus, 16 consecutive samples are sequentially deinterleaved among 16 amplifiers, allowing each amplifier more time to settle. As shown, 15 SHAs each drive 64 adjacent subpixel columns, and are comprised of a preamplifier, a level converter (differential to single-ended), and a high-voltage driver to drive the display columns. One SHA drives a control sample (note that each control sample is 16 samples apart). The control sample represents a digital value that uses a form of transition coding (e.g., MFM) to provide timing control information and makes the system robust. The bandgap voltage reference circuit 840 provides current and voltage references to the various input amplifiers.

[0112] FIG. 17D is a summary of the subpixel order collected by the input amplifiers of FIG. 17C. This summary shows how pixels 0-959 and control signals 0-63 are transmitted to the source driver of FIG. 17C and which amplifier each subpixel is assigned to. Because the source driver has 16-channel interleaving, the preferred method of transmitting subpixels to the source driver is from the top left, top to bottom, and left to right, i.e., the transmitted subpixel (and control signal) indices are ctrl0, 0, 64, 128, etc., and transmitted to the 16 amplifiers in order. Shown are the indexes of the S / H amplifiers 842, an example of a subpixel index 844, and the control signal 306 for the 0th amplifier 826.

[0113] This subpixel ordering minimizes source driver hardware and also minimizes wiring load on the input amplifiers. To optimally display text and other abrupt intensity transitions, it is desirable for the sampling amplifiers to settle to a new value every 1 / Fsavt, or approximately 1.5 ns per sample. As shown, SHA0 carries control timing, SHAs 1 through 15 carry video data, and each SHA drives 64 adjacent columns of the display. Because the SHAs are sampled sequentially, the transmission order is as follows: CTL[0], V[0], V

[64] , V

[0896] , CTL[1], V[1], V

[65] , V

[0897] , CTL

[63] , V

[63] , V

[0127] , V

[0959] . This sequence transmits 64 control bits per line, 960 video samples per line, for a total of 1,024 samples per line (per source driver).

[0114] FIG. 18 illustrates a technique for introducing a timing reference into a control signal sequence to provide synchronization and other commands to the source driver's control channel. Because the control signal appears as a continuous stream of bits, a timing reference is introduced into the control sequence to interpret the sequence. Modified Frequency Modulation (MFM) is typically used in wireless transmission to provide a timing reference. While known in the art, MFM has never been used to encode control sequences for video transmission. In the present invention, MFM can be used to introduce a timing reference and transmit commands and data. Furthermore, MFM has not previously been used to transmit these types of commands in the context of video transmission. For example, the use of horizontal and vertical synchronization commands with specific parameters allows the transmission of all parameters supported by CEDS. Furthermore, the phase adjustment commands are novel, as are certain phase adjustment techniques described below.

[0115] The timing reference indicates when what follows is a command and data in the control sequence. The timing reference is the MFM flag, which is an intentional timing violation. We assume that the wire length from Tx to Rx is more than one SAVT cycle and that the wire length is variable. Since we extract the digital data of the control channel, it is robust even if the analog samples are not perfect. Furthermore, the level value is irrelevant, only the transition is important, and the true value and the complement value have the same meaning.

[0116] The timing signal 852 is Fsavt / 16, which corresponds to the timing of the output from the input amplifiers, i.e., the rate at which each amplifier outputs data. The control bit cells 854 represent a 64-bit sequence received as a control signal at the output 838 of one of the source drivers. The MFM cells 856 represent MFM encoding bits, one MFM cell for every two control bits. The payload 858 is the command and data. The control sequence 860 is a sequence of control bits received on the control channel of one of the source drivers and output, for example, at the control 838 of source driver 820'''.

[0117] As shown, the control sequence includes an MFM flag 862, a sequence that does not normally occur in a stream of control bits. The flag 862 consists of a 4-3-4 control bit interval transition sequence, with the end of the fifth transition indicating the end of the flag (a timing violation). Then, before the actual payload begins, there is a trailing zero 864, an MFM-encoded zero that is ignored by the data receiver. The payload is typically transmitted LSB first, but may also be transmitted MSB first. The LSB 866 in the 0 position of the MFM bit cell 856 is shown to have a value of "0" in the control sequence. A total of 25 MFM-encoded cells are transmitted, with the payload 867 shown to the right of the control sequence. A second control sequence, different from sequence 860 but with the same MFM flag and trailing zero, is shown at 868. The second control sequence transmits a different payload, reflecting the different commands and data that may be transmitted over a single control channel. Another example of a control sequence is shown at 869. The payload sent may be a command, a parameter, or reserved for future use.

[0118] Synchronization is complicated because data is received from the deinterleaving amplifier across 16 channels. The source driver does not know which channel holds the control sequence until synchronization occurs. One proposed method is to use a flag sequence that appears on only one channel output. Identifying the MFM flag instructs the source driver chip to resynchronize and respond to commands and data such as horizontal and vertical synchronization commands and phase adjustment modes. At power-up (or after a power outage), the transmitter sends the MFM flag and control sequence to all channels. The correct control channel (the 16th channel in this example) recognizes the flag, resynchronizes the timing, and recognizes the commands and parameters. Once resynchronization is complete, only the control sequence needs to be sent on the control channel, and video data needs to be sent on the other 15 channels.

[0119] Another, more preferable method is to initially transmit the MFM flag on one channel rather than all 16 channels. The receiver looks for the flag on one channel (which may be the wrong channel before synchronization is complete). If the flag is not detected after one line time (~1.5us), the clock cycle is slipped (skipped) for one cycle, effectively rotating the amplifier usage. Therefore, synchronizing to the clock cycle can take up to 16 display lines.

[0120] Because the control stream is continuous, commands and parameters can be spread across multiple display lines if necessary. We also recognize that, even though conventional CEDS transmits approximately 28–32 control bits per display line, some of these bits do not need to be transmitted line-by-line (some, e.g., low-temperature mode, power control, etc., may be frame parameters), i.e., transmission infrequently is appropriate. Furthermore, the control channel disclosed herein is robust enough to not require a CRC because it extracts digital data and transmits analog video samples with 10-bit accuracy on the same channel. However, a CRC can be added if desired. Another advantage of using MFM in the context of video transmission is that it provides an accurate timing reference immediately upon flag generation, without the need to wait for correlation, as with other techniques such as Kronecker. Furthermore, this control channel is well-suited to convey commands such as frame synchronization, line synchronization, parameter data, and phase adjustment information. Commands are transmitted interspersed (one symbol at a time over one line period), and received control information is applied to the next display line. Typically, the control sequence never ends; one control packet is transmitted per line period. Information such as column driver polarity and driver strength is transmitted for each line.

[0121] FIG. 19A illustrates one embodiment for transmitting commands and parameters via MFM encoding. Shown is the bottom timing clock Fsavt / 16, as described above, and control bit field 879 used to encode the MFM data. Control sequence 870, which includes the initial MFM flag, is shown, followed by the 25 MFM cells described above. Control sequence 871 illustrates using three of the MFM cells to hold a three-cell command, leaving 21 cells for parameters. Depending on the implementation, more or fewer cells may be used for commands. Sequence 872 illustrates the location of the MFM flag relative to the MFM cells. Sequence 873 illustrates a three-cell horizontal sync command, followed by 21 cells for parameters. Sequence 874 illustrates a three-cell vertical sync command, followed by 21 cells for parameters. Sequence 875 illustrates a set phase adjust mode command, followed by parameters that may include comparator thresholds. Sequence 876 illustrates an exit phase adjust mode command. This command is not strictly necessary in that receipt of any other command will cause the termination of phase adjust mode. Sequence 877 indicates the possible values ​​of the command and space for its parameters, which are reserved for future use.

[0122] The synchronization stream 878 is the stream that is transmitted continuously on the control channel during phase adjust mode. For purposes of determining the threshold of the upper comparator 835 (if the phase adjust of FIG. 20 is used), this stream is contemplated to be modulated to include two levels: 1V every other pulse and 1.2V every other pulse, although these voltages may vary. Phase adjust is typically performed before turning on the display and during frame blanking (as thermal and other effects may change the optimal phase for a sample). Once the phase adjust is set, phase adjust mode is exited and the video displays normally.

[0123] FIG. 19B illustrates another embodiment for transmitting commands and parameters via MFM encoding. While FIG. 19A illustrates different command lines, each identified by a different three-cell command, FIG. 19B illustrates a single command line containing the parameters for the various commands. Shown are control bits 854 containing flags 862, trailing zeros 864, and MFM cells 856 holding command / parameters 858. As shown, two samples are used to represent each MFM cell, there is one MFM packet per line, and an MFM flag is prepended to each MFM packet with a (4,3,4,2) transition. This results in 25 MFM cells per line. Data reception terminates upon receipt of the flag. The 25 command / parameter cells are not valid until all 25 are received, and any prior reception of a new flag is ignored. Either normal message (1) or (2) can be used, depending on the final state of the previous message. During initial synchronization, fast flag messages can be used to send up to four flags per line to speed up synchronization and provide control signals earlier to channel 0. The point is that parameters and control information can be passed line by line along with the sampling of the analog video data.

[0124] When VSYNC 881 is asserted, it indicates that the current line being received is in the vertical blanking interval, so no data is displayed and the video controller state machine is reinitialized. The polarity control bit 882 determines the polarity with which pairs of columns are driven relative to the dark level. Each pair of columns is driven complementary (one column output is driven more positive than the dark level, and the adjacent column is driven more negative), and the polarity control of the column-pair determines the direction. Four polarity controls independently control four column pairs in a group of eight columns, and this pattern is repeated every eight columns for all subpixel columns in a line. The polarity control can be updated row by row. In practice, the polarity control bit will likely be changed at most once per line (to reduce power consumption).

[0125] The short control bits 883 include "short_gena," which, when asserted, shorts adjacent columns only if the corresponding polarity control bit is changed, unless short_all is also asserted. When deasserted, no shorting occurs. "short_all" allows shorting of all column pairs regardless of the polarity control change state, but is only effective if short_gena is also asserted. The drive time controller 884 specifies the number of Fsavt / 16 cycles from the start of the high-voltage driver drive period until the driver is tri-stated or charge-shared (depending on SHORTCTL). The high-voltage driver sampling phase 885 is a chopper clock that swaps both the input and output of the main amplifier to cancel offsets. The SHA calibration control signals 886 include two SHA calibration control signals: sha_video (sha_cal[0]) and sha_meas (sha_cal[1]), both of which are directly controllable from the side-channel control bits. These signals control the SHA's Calibration_Phase1 and Calibration_Phase_2 signals, respectively.

[0126] <Phase adjustment technology> As mentioned above, it is desirable to determine the optimal sampling phase of the input samples for a specific source driver due to delays and attenuation in the cable, the presence of ringing in the input samples, inter-symbol interference, etc. This phase adjustment can be performed at periodic intervals such as at power-on, frame synchronization, or frame blanking, and the phase adjustment mode can be switched by issuing the "Set Phase Adjustment Mode" command mentioned above. Below, we propose two phase adjustment techniques.

[0127] FIG. 20A illustrates one technique for implementing phase adjustment useful in the source driver of FIGS. 17A and 17B with three comparators. The synchronization stream 878 is shown in more detail at 890, depicted as a square wave for ease of illustration. Preferably, each sample or pulse in stream 890 is 16 SAVT samples long (the sampled output of a single channel of the deinterleaving amplifier). When compared to a threshold at the SAVT rate, 16 identical values ​​are seen. Preferably, the stream is modulated (e.g., using a triangular or trapezoidal wave) to generate two distinct levels 891 and 892 (and corresponding negative levels 897 and 898). For ease of illustration, levels of approximately 1.0V and 1.2V (and corresponding negative levels −1.0V and −1.2V) are shown, but in practice, it is assumed that the positive levels will vary around approximately 0.5V and the negative levels will vary around −0.5V. In this way, the sync stream will continuously cycle through two positive and two negative levels until the phase adjust mode is exited.

[0128] Upon entering phase adjustment mode, a synchronization stream 878 is sent along the source driver's control channel. For example, this synchronization stream arrives at the input amplifier 826, and is detected by the central comparator 836 as well as the upper threshold comparator 835 and the lower threshold comparator 837. This synchronization stream is preferably a valid MFM data stream (i.e., MFM zero and MFM one) with a regular 50% duty pattern of positive and negative values ​​of known amplitude. Because this is a valid MFM data stream, the "Exit Phase Adjustment Mode" command can be issued at any time. Comparators 835 and 837 must be sufficiently fast, but absolute precision is not required as long as the offset is less than the difference between the last two amplitude levels.

[0129] Essentially, the central comparator 836 provides zero-crossing detection, indicating whether the detected input is positive or negative. If the sample is positive and the sampling phase is correct, the upper threshold comparator 835 should also produce a positive value; if not, this indicates that the sampling occurred too early or too late, i.e., before or after the transition to a positive value. The lower threshold comparator 837 provides similar information if the sample is negative. If the upper or lower comparator does not match the central comparator, the sampling phase is adjusted. A detailed technique for adjusting the phase to properly sample positive inputs is described below, but one skilled in the art would be able to apply this technique to negative inputs.

[0130] For example, the upper comparator should report the same value detected by the zero-crossing detector. If we rotate the sampling phase (advance the PLL phase), we will eventually reach a point where the next transition begins to occur. That transition will cause the upper comparator to produce a result that does not match the zero-crossing detector. This tells us we have detected a transition, so by moving the sampling phase back one phase (or two phases to be safe), we can sample later in the symbol period after the sample has settled, but before the transition to the next sample. Note that if the transition is very fast, the zero-crossing detector may also flip when the symbol transition occurs, in which case we do not need to look at the upper comparator, and so the "transition" may be determined by the logical OR of these two events.

[0131] As mentioned above, the first step is to enter phase adjustment mode and transmit synchronization stream 890 along the control channel. Preferably, amplitudes 891 and 892 are set far enough apart to handle input ringing, etc., and to provide a window (approximately 0.2 V in this example) within which upper threshold 893 can be set so that pulse 891 does not trigger the upper comparator and pulse 892 does, when the sampling phase is approximately correct. In one example, if the expected amplitudes of the control signal are approximately 1.5 V and approximately −1.5 V, the amplitudes of pulses 891 and 892 are set below those expected amplitudes, as shown. The corresponding amplitudes of pulses 897 and 898 can be set similarly.

[0132] In selecting the initial voltages for these two pulse amplitudes, one objective is to set the modulation level so that the transition can be detected. In one embodiment, the two amplitudes of the synchronization stream are 50% and 75% (for the positive pulse). This makes it easy to set the DAC threshold between the two amplitudes (accounting for noise, etc.), while still indicating when the transition occurs (when the 75% amplitude pulse drops below the DAC upper threshold).

[0133] The selection of the initial sampling phase may be a random selection, a reset value (e.g., phase 0), or some other phase selection. Because the zero-crossing detector is used to determine the expected signal level, it is unlikely (~1 / 16 probability, but possible) that the sampling phase will be selected at a symbol transition where the zero-crossing detector output looks random. However, if this occurs and no flag is detected after 16 clock skips, the phase is advanced to a position where the zero-crossing detector will function. In our implementation, there are 11 phases. Shifting the phase by 2-3 steps is sufficient; other implementations may differ.

[0134] When the sync stream arrives, logic and circuitry within the source driver (not shown) can adjust the upper threshold by sliding it up or down to determine the optimal voltage. For example, if the upper threshold is too low, the upper comparator will trigger on both pulses 891 and 892; if the upper threshold is too high, it will not trigger on pulse 892; and if the upper threshold is correctly positioned, it will not trigger on pulse 891 but will trigger on pulse 892. The source driver does not know what the amplitudes of pulses 891 and 892 will be due to attenuation, etc., but as long as the amplitudes are far enough apart to accurately position the upper threshold, the source driver does not need to know the exact values. This adjustment process uses a sampling phase that is approximately correct but not optimal. If the upper threshold is correctly positioned, it will not be triggered by the ringing of pulse 891 but will be triggered by pulse 892. A DAC can also be used to adjust the upper threshold.

[0135] Once the upper threshold is set, logic and circuitry within the source driver begin rotating the sampling phase around 11 different phase positions to determine the optimal phase for the sample. As an example, the initial sampling phase could occur approximately in the center of pulse 892, which may not be the optimal point to sample at because the pulse may not be stable at this point, potentially resulting in an erroneous value. Typically, the optimal point to sample is just before the transition to the next pulse, when the signal is most settled—before the trailing edge of the pulse. When the sampling phase rotates to point 894, both the center and upper comparators trigger, signaling that a positive value has been received. When it rotates to point 895, both trigger again. However, when the sampling phase rotates to point 896, the upper comparator suddenly stops triggering, indicating that it has just passed the transition. No agreement occurs between the upper and center comparators. (Even though a perfect square wave is shown, the transition is a more gradual drop rather than a steep drop to -1.2V, so the center comparator registers a positive value.) Therefore, by moving the phase back one or two taps, to point 895 or 894, the optimum sampling phase can be found. A different number of phase positions can also be used; 11 was determined by the process (the number of inversions that fit within the 1.5ns clock period). Depending on the VCO structure, an odd number of phases may also be useful.

[0136] The use of two pulses 891, 892 to set the upper threshold ensures that the upper threshold is high enough to perform a search for the optimal sampling phase, as described below. Providing an upper threshold that is less than the amplitude of pulse 892 ensures that the outputs of the upper and middle comparators will not coincide when sampling occurs after the transition of pulse 892, facilitating the selection of the optimal sampling phase. While it is possible to use a single sampling phase once found, averaging multiple measurements is desirable to combat noise and overshoot.

[0137] The above describes a technique for determining the optimal sampling phase for positive pulses. The same approach can be applied to negative pulses and the results averaged. In one particular embodiment, the lower threshold comparator 837 is not required, and only comparators 835 and 836 are used to determine the optimal sampling phase using positive pulses as described above. In other embodiments, the upper threshold comparator is not used, and only the lower threshold comparator and the center comparator are used for negative pulses to determine the optimal sampling phase. In yet another embodiment, the upper threshold comparator is used only when all positive pulses in the synchronization stream have the same amplitude, with the upper threshold set below the amplitude of these positive pulses, and the sampling phase is rotated back and forth depending on when the upper threshold comparator no longer triggers. The upper threshold comparator can also be used exclusively when the synchronization stream contains alternating positive pulses of different amplitudes, as shown in FIG. 20A. Similarly, in yet another embodiment, the lower threshold comparator is used exclusively when the negative pulses in the synchronization stream all have the same amplitude, the lower threshold is set below the amplitude of these negative pulses, and the sampling phase is rotated forward and backward depending on when this lower comparator stops triggering. In this embodiment, the negative pulses may be as shown in Figure 20A.

[0138] Above, Figure 20A describes one technique for phase adjustment. While it is possible to use phase adjustment commands embedded in the video stream, it is preferable to perform phase adjustment via a state machine that monitors flag timing within the MFM sequence. This method does not use commands within the stream, but instead treats dynamically changing parameters as payload. Below, we describe a second preferred technique that combines phase adjustment with searching for MFM flags (or other flags) within the control sequence.

[0139] Figure 20B shows a sampling phase adjustment circuit useful in the source drivers of Figure 17C and Figures 20C-20F. The input controls are the clock cycle and phase adjustment control, and the sample_phase output (sampling clock) is sent to each SHA amplifier. Phase rotation (and clock skipping) affects all samples. These are performed before the PLL, as shown in Figure 20B. Skipping a clock cycle easily changes which SHA channel sees the control information. (The sample-and-hold amplifier / deinterleaver samples a different channel each cycle, so skipping a clock cycle subsequently rotates the information carried on each channel by one.) Phase adjustment is performed by rotating (selecting) one of the PLL's 11 phases (only one phase step is allowed at a time to avoid clock glitches). The VCO high-frequency clock is the clock whose phase is adjusted to generate the sampling clock output. The input reference clock 170 is constant. The inputs "skip," "adv," and "ret" come from a synchronous state machine in the chip's digital logic, as illustrated in Figure 20F.

[0140] Figure 20C shows a special synchronization video pattern to facilitate locking. Using this special video pattern, during synchronization, all video samples in a line (per source driver) are negative constant value 942 (zero-crossing detector 836 output is 0) except for the last video sample 944, which is sent as a positive constant value (zero-crossing detector output is 1). Shown is control data 940 for SHA channel 0 and SH amplifiers 1-15 (Video 0-Video 14). Therefore, with this knowledge, when SHA channel 0 (the control channel) samples the video stream to extract the control data, it knows which direction it needs to adjust the phase to sample the control bit at the optimal time. For example, moving the phase backward while sampling with data 940 will result in a "1"; moving the phase forward will result in a "0." Because all SHA channels share the same (relative) timing with respect to the sampling phase, this also means that the video samples are sampled optimally (near the end of the sample's settling time).

[0141] Figure 20D shows an example where the MFM flag is lost due to PLL phase wrapping. A clock skip is required in this situation. 11 sampling phase steps 950 are shown, with the optimal step being 952. Thus, rotating the PLL phase from step 10 to step 0 moves the sampling back to the previously transmitted sample 949. If the currently selected sampling phase is within the CTRL field, the flag is detected (Y). If it is outside the CTRL field, the flag is not detected (N: incorrect MFM on video channel), so we know that the sampling has gone back too far and can move the sampling phase forward by 3 steps.

[0142] Figure 20E shows an example of losing the MFM flag when the phase extends beyond the end of the control bit, where sampling at steps 9 and 10 moves to the next sample 942. Since no clock skip is required in this situation, once MFM flag detection is lost at step 9, the phase selection is moved back two steps to optimal step 7.

[0143] Figure 20F is a flow diagram of the synchronization state machine implemented in the digital logic of the source driver chip, illustrating how phase adjustment is performed in the MFM flag search. In this diagram, EOL means the end of the received display line (64 control samples received for a single source driver), V=1 means the zero-crossing detector output is 1, indicating that when the MFM flag disappears, we are looking at the last video sample of the previous line instead of the control bit, V=0 means the zero-crossing detector output is 0, indicating that when the MFM flag disappears, we are looking at the first video sample of the same line instead of the control bit, and "!" means negation, e.g., "!" flag" means that the flag has not been detected.

[0144] If the flag is not detected and the detector output is 1 in step 974, it means that the previous line sample 949 has been oversampled, and the process proceeds to step 972 shown in Figure 20D. Thus, step 973 advances the phase by three steps. If the flag is not detected in step 974 and the detector output is 0, it means that the next sample 942 has been oversampled, and the process proceeds to step 976 shown in Figure 20E. Therefore, in step 976, the phase is returned by two steps to be optimal, and synchronization occurs in step 977.

[0145] Once the optimal phase is determined, it is implemented within the source driver by sending the output of the sampling phase adjustment circuit to the SHA amplifier as the sampling clock. Preferably, all amplifiers in all source drivers operate in unison; that is, there is only one sampling phase alignment circuit and clock cycle alignment controlling all SHA amplifiers. Within each source driver, these input SHA amplifiers are time-interleaved to generate sample outputs that are skewed in time by 1 Fsavt cycle between adjacent channels. The SHA amplifiers then transfer these samples to the collector (A / B sampler) with a time lag. After the collector collects all samples for one line, the preamplifier transfers all samples simultaneously to the next stage (level converter). This wastes 16 Fsavt cycles of transfer time at the preamplifier output, but due to the sampling rate decimation, sufficient time is ensured.

[0146] Other synchronization techniques can be used. For example, horizontal and vertical synchronization can be achieved by transmitting a low-frequency clock. To adjust the phase of the sampling points, a known black / white reference can be transmitted in the subband and the receiver's PLL can be adjusted until the blackest black and whitest white are found.

[0147] In another synchronization technique, the reference clock is not just a reference clock, but also contains data (parameters, etc.), but at a lower clock frequency. The clock and its parameters are transmitted over a separate wire from the SAVT samples (which already exist). Because there is no need to mix side channel data with video data, the SAVT rate is reduced, and only 60*16 = 960 samples need to be transmitted per line, requiring less bandwidth for communication. Bandwidth can be further reduced by using sub-pixel color grouping. It is also possible to introduce color transition blanking into this technique. Because the side channel bits are not embedded in the video stream, there is no problem of side channel bits bleeding into the video bits.

[0148] <Source driver example> Figure 21 shows the analog data path of one channel of an example source driver. In this particular example, the source driver drives an LCD display, and the various components shown are specific to that type of display. However, the invention is applicable to other types of displays.

[0149] Shown is the input terminal 902 and one of the 16 input distribution amplifiers (in this case, SHA[0] 824, shown at 904). Not shown are the input terminal's switch 842 and the other 15 distribution amplifiers that drive the video samples. The input sampling is indicated by a switch sampling to a capacitor. The input sampling switch is symbolically controlled by signals b and t. While SHA[0] carries the side channel information, there are 15 other identical amplifiers (with skewed timing) that carry the video. Which SHA channel carries the side channel is arbitrary, but the advantage of using SHA[0] is that the control information arrives before the video sample, rather than after, allowing time for setup before the control information is needed. Each amplifier 904 has a nominal gain of 1, but this can vary.

[0150] Each SHA channel drives 64 columns 920 through a series of sampling blocks / collectors 908, preamplifiers 910, level converters 912, HV drivers 914, and column shorting switches 918, as indicated by the array notation [63:0] used in the component identifiers in the figure. The level converters 912 are sometimes called differential-to-single-ended converters. The preamplifiers 910 provide the necessary gain to the signal coming from the transmission medium.

[0151] 21 shows one of the 64 A / B sampling capacitor blocks 908 for a channel's amplifier 904 and its associated preamplifier 910. In one particular embodiment, timing skew introduced by the input distribution amplifier's deinterleaving process can be corrected by timing the source driver's preamplifier. For example, once all 64 samples have arrived at either the A or B sampling capacitor block, the preamplifier 910 waits 16 clock cycles after the first sample arrives (or until the last sample arrives) before beginning to drive all 64 samples to the level converter 912. Thus, all preamplifiers 960 in the source driver will be driving samples simultaneously.

[0152] One of the channel's 64 level converters 912 is shown, which converts the differential signal to a single-ended signal, adds an offset, changes the signal polarity, and amplifies it. When pol=0, the output out_p 913 = vmax + 0.5 * (Vinp - Vinn). When pol=1, the output out_p 913 = vmin - 0.5 * (Vinp - Vinn). A high-voltage driver 914, one of the 64 drivers for such a channel, multiplies the input signal to provide the voltage (positive or negative) expected by the display. A column shorting switch 918 provides shorting for the LCD display, as is known in the art. Finally, the expected voltage is output to the column at 920. The preamplifier 910, level converter 912, and HV driver 914 can be thought of as an amplification stage before each column, in this case a pipeline amplifier, or simply "amplifier."

[0153] The switch 842, source driver input amplifier 904, and A / B sampling block 908 of Figure 14 may also be referred to as the collector 915 because the collector receives the incoming serial analog samples and stores (or "collects") them in the sampling block, which can then be output in parallel to the column driver 916 for display as part of one line on the display panel.

[0154] Mobile phone specific embodiment 22 is a block diagram illustrating the transmission of analog video samples within a mobile phone. U.S. Application Serial No. 18 / 442,447 (Attorney Docket No. HYFYP017), entitled "Video Transmission Within a Mobile Device," and incorporated by reference above, discloses further details regarding various technologies. Prior art displays on existing OLED DIC devices, such as mobile phones, require improvement due to the high refresh rates of 4K smartphone displays, MIPI receivers, SRAM, digital image processing, and extensive use of analog signals, requiring approximately 1,000 digital-to-analog converters.

[0155] The split OLEDDDIC architecture as shown in Figure 22 has the following advantages: it allows optimal DDIC-TCON and DDIC-SD splitting, provides short-reach MIPI transmission from the SoC, optimizes the digital DDIC-TCON for SRAM and image processing, and provides a simplified DDIC that is all analog, requiring only a few digital-to-analog converters in the transmitter and integrated DDIC-TCON.

[0156] Shown is a mobile phone (or smartphone) 980, or similar handheld, mobile device used for communicating and displaying images or video. Device 980 includes a display panel 982, a conventional mobile SoC 984, an integrated DDIC-TCON (Display Driver IC Timing Controller) and transmitter module 988, and an integrated analog DDIC-SD (DDIC Source Driver) and receiver 992. Mobile SoC 984 and module 988 are internal components of the mobile phone but are shown external to the mobile phone for ease of illustration.

[0157] Mobile SoC 984 is a standard SoC used in mobile devices and provides digital video samples to module 988 via MIPI DSI 986 (Mobile Industry Processor Interface Display Serial Interface) in a manner similar to the Vx1 input signal described above. Included within module 988 is a transmitter as described above, such as the transmitters of Figures 1-4 and 7-10, with an integrated DDIC-TCON. After reading this disclosure and referring to the previous figures, one skilled in the art will understand how to implement the transmitter to output any number of analog EM signals 990. In this example, the transmitter outputs 12 pairs of analog EM signals at 380 Msps. Not shown are the gate driver control signals from module 988 to the gate drivers of display panel 982. Typically, in a mobile phone, the DDIC is located in the narrow bottom edge of the phone, and the SoC is located approximately in the center of the device. Therefore, the integrated DDIC-TCON / transmitter is located close to the SoC, within approximately 10 cm, or perhaps within approximately 1-2 cm. Due to the extreme frequencies involved in digital data transmission, it is advantageous to keep the conductor lengths as short as possible. For tablet computers, this distance is approximately 25-30 cm or less.

[0158] These analog signals 990 are received by an integrated analog DDIC-SD and receiver 992. The DDIC-SD receiver 992 receives any number of analog signal pairs and generates voltages to drive the display panel 982, and can be implemented, for example, as shown in Figures 5, 6, 10, 13, or 17. Advantageously, only a single source driver may be needed to drive the display panel 982, and the module 992 does not require a digital-to-analog converter.

[0159] The analog DDIC-SD receive 992 may be a single integrated circuit with 12 source drivers in it (each handling a single pair), or it may be 12 discrete integrated circuits, each a source driver and handling one of the 12 signal pairs. Of course, there may be fewer signal pairs, which means correspondingly fewer source drivers.

[0160] <Integration of analog video transmission source driver and display panel> As mentioned above, analog video transmission is used within the display unit to deliver video information to the display panel's source drivers. Furthermore, modern large-screen display architectures are comprised of large areas of active-matrix display pixels. In the early days, display drivers (source and gate drivers) were attached to the glass edge, but not directly on the glass itself, providing the source and gate driver circuits. The complexity of high-speed digital circuits and the large area required for digital-to-analog conversion (DA) have hindered the integration of drive electronics on the glass. For example, digital transmission to the source driver circuits operates at approximately 3 GHz, which is too high a frequency for integration on the glass. Furthermore, to drive a complete high-resolution LCD or OLED screen, many display drivers must be attached to the display edge. A typical driver has approximately 1,000 outputs, so a typical 4K display requires 4,000 x RGB = 12,000 connections, or 12 source drivers. Increasing the panel resolution to 8K increases this number to 24 source drivers. Data rates, synchronization difficulties, and bonding logistics make it difficult to continue in this direction.

[0161] A display panel (such as an LCD panel) is composed of a glass substrate and thin-film transistors (TFTs), i.e., field-effect transistors fabricated by thin-film deposition techniques, formed on the glass substrate. These TFTs are used to implement the pixels of the display. These TFTs (along with appropriate capacitors, resistors, and other appropriate analog components) are also used to create logic circuits to implement elements of the novel source drivers described herein, and these components are integrated with the glass. These elements are integrated at the extreme edge of the glass, just outside the display area of ​​the pixels and inside the glass's perimeter seal. Thus, the source drivers disclosed herein may be, and in the embodiments described below, integrated with the glass using these required transistors, capacitors, resistors, and other analog components. Thus, the source drivers (or elements thereof) previously located on the outside and edges of the display panel glass are now moved to the display panel glass itself. Furthermore, the gate driver functions of the gate drivers can also be moved onto the display panel glass.

[0162] The SAVT video signal can be transmitted along the edge of the display glass using relatively simple wiring and, unlike the existing Vx1 interface, is less susceptible to interference. Because of its low sample rate, the source driver's required analog electronics (which are less complex) can be designed on the edge of the TFT panel, directly on the display glass. Building the source driver circuitry on the glass edge allows the following elements of the source driver, along with their typical functions, to be integrated with the glass: input terminals and switches (receive analog samples via the SAVT signal and distribute them to the collectors), collectors (receive analog samples via input amplifiers and collect samples in a storage array or line buffer), level converters (convert to single-ended, provide voltage inversion and voltage offset), and amplifiers such as high-voltage drivers (provide the amplified voltage and the current required to charge the capacitance of the display source lines).

[0163] FIG. 23 illustrates the implementation of integrated source driver functionality in various embodiments. Depending on the quality of the transistors used in the glass, various elements of the source driver can be integrated into the glass. As is known in the art, TFTs can handle frequencies ranging from low to high (for example). Three main technologies are used to manufacture TFTs: amorphous silicon (a-Si); oxide (indium gallium zinc oxide (“IGZO”) or similar materials), which can routinely handle frequencies of about 50 kHz to 100 kHz, and up to about 200 kHz depending on the voltage used (oxide allows frequencies up to 1 MHz at 50 volts with certain components); and low-temperature polysilicon (LTPS), which can handle frequencies on the order of about 5 MHz, and up to above about 10 MHz depending on the voltage used. Additionally, crystalline silicon TFTs implemented using CMOS technology can handle even higher frequencies. Other types of TFTs can also be used.

[0164] If faster, higher-quality TFT transistors are used, the high-frequency portion of the source driver may be integrated with the glass. Furthermore, smaller device sizes improve the transistor's switching speed, allowing devices using such devices to be implemented on glass. For example, the channel length of the TFT influences its size. Oxide TFTs preferably have a channel length of less than approximately 0.2 μm, while LTPS TFTs have a channel length of less than approximately 0.5 μm. A 50% reduction in channel length results in a fourfold improvement in speed. Furthermore, implementation may depend on the display type. Display sizes with resolutions of 2K, 1K, and smaller may use devices that do not require the high frequencies of 4K and 8K displays. Amorphous silicon transistors are generally not used because they are prone to threshold shift and are unstable. Note that the source driver disclosed herein does not require a digital-to-analog converter to convert video samples or a decoder to decode the input video samples.

[0165] In the first embodiment 102, the level converter 620 and amplifier 621 are integrated with the glass because the level converter requires only a relatively low-frequency clock. The level converter switches once per line, requiring a switching frequency of approximately 50 kHz for a 2K display and 100 kHz for a 4K display. Therefore, the first embodiment of the integration can use TFTs that can operate at a clock frequency of at least approximately 50 kHz, assuming a 2K panel (e.g., 100 kHz for a 4K panel). Therefore, the first embodiment can use IGZO or LTPS TFTs.

[0166] In the second embodiment 104, which uses faster transistors, the level converter 620, amplifier 621, and collector 786 can also be integrated with the glass, thereby integrating the entire source driver. The collector 786 requires a higher frequency clock because each collector operates a pixel sequence, requiring a switching frequency of approximately 50 MHz for a 2K display and 100 MHz for a 4K display. Therefore, the integration of the second embodiment can use TFTs capable of operating at a clock frequency of at least approximately 50 MHz, assuming a 2K panel. Thus, the second embodiment can use LTPS TFTs for a 2K panel.

[0167] Figure 24A shows the arrangement of gate drivers and source drivers on a display panel glass. A display panel is typically implemented with two glass substrates: a top (or common) glass and a bottom (or active) glass, with the bottom glass being smaller than the top glass. The TFTs are implemented on the bottom glass; the following description refers to this bottom glass, and the drawings show only the bottom glass. A single display panel glass 150 (for clarity, the panel frame and surrounding display unit are not shown) is shown, with two rectangular regions 130 and 132 on either side of the display panel glass (in this example, an LCD panel) that is a few millimeters wide. In this embodiment, the gate drivers are also integrated using TFT devices on the glass as switching elements. Because gate drivers are typically implemented as simple shift registers, these shift registers can be located in regions 130 or 132.

[0168] Also shown is a rectangular area 140 located on the glass itself where elements of the source driver can be located. The source driver functionality can be partially or fully integrated with the glass by utilizing TFT switches on the glass in this area 140. In a first embodiment, the amplifier and level converter (formed in area 140) are integrated into the glass, while in a second embodiment, the amplifier, level converter and collector (also formed in area 140) are integrated into the glass.

[0169] The source drivers disclosed herein do not receive digital signals, do not include DA converters or related circuits for processing digital video samples, and do not include decoders. Because these drivers have low processing frequencies and small dimensions, they can be integrated onto the glass. For example, the pixel width of a typical 64-inch 4K television panel is 80 μm (40 μm for an 8K display), and the dimensions of the output amplifier are expected to fit within this space, making the driver wide enough to be integrated directly onto the glass. The specific TFTs can be selected depending on the pixel width of a particular implementation.

[0170] The interconnect printed circuit board 182 receives the EM signal 602 and passes it via the flexible PCB 184 to the source drivers located on the integrated circuits 186a and partially integrated with the glass of the TFTs 186b. Passing the EM signal in this manner is implemented for embodiment 1 because a portion (at least the collector) of each source driver is still located within the flexible PCB 184 on the IC 186a, while the level converters and amplifiers are located on the glass of the TFTs 186b. As shown, each integrated circuit 186a passes an analog signal 187 to corresponding circuitry on the glass 186b. The nature of these analog signals differs depending on whether embodiment 1 or embodiment 2 is being implemented. An implementation of embodiment 2 is shown below. Gate clocks 190 and 192 are sent to the gate drivers via the circuit board 182 and the flexible PCB 184. The PCB 184 is attached to the panel glass 150 as known in the art.

[0171] 24B shows a source driver 186 implemented completely on glass. This second embodiment fully integrates the source driver functionality on the glass. As shown, the flexible PCB 184 only contains the EM signal 602 and does not include source driver functions such as collectors, level converters, and amplifiers; all source driver functions are implemented in the TFTs (and other analog components) on the glass in 186. Although not shown, each other source driver can have its own PCB 184 and EM signal 602 (from a corresponding transmitter); in one particular embodiment, there are 24 such source drivers.

[0172] FIG. 25 shows another embodiment of the placement of the EM signal 602 when implementing embodiment 2. As previously mentioned, in embodiment 2, all of the source driver functionality is integrated on the glass, eliminating the need to route the EM signal 602 through a large circuit board 182 (the length of the display) and multiple flexible printed circuit boards 184, as shown in FIGS. 7A and 7B. Therefore, a much smaller printed circuit board 183 and a single flexible PCB 185 are attached to the display panel glass 150 in one location, and the EM signal 602 is passed to the glass via 183 and 185, transmitted along the glass, and sent to each of the source drivers 186 on the glass within region 140. Furthermore, because all of the functionality for each source driver is on the glass, no integrated circuits 186 are required on the flexible PCB. As shown, the EM signal 602 is routed in parallel to each source driver.

[0173] Returning now to the exemplary source driver of FIG. 21 , it should be noted that portions of the source driver may be implemented on the glass in many other embodiments. As one example, only the high-voltage driver 914 (and optionally the column short 918) may be implemented on the glass in region 186b, while the remaining elements shown are implemented on the integrated circuit 186a outside the edge of the glass. Alternatively, the driver 914 and level converter 912 may be implemented on the glass, with the remaining upstream elements implemented outside the edge of the glass. Alternatively, the driver 914, level converter 912, and preamplifier 910 may be implemented on the glass, with the remaining upstream elements implemented outside the edge of the glass. Alternatively, the driver 914, level converter 912, preamplifier 910, and A / B sampling block 908 may be implemented on the glass, with the remaining upstream elements implemented outside the edge of the glass. Alternatively, the driver 914, level converter 912, preamplifier 910, A / B sampling block 908, and input distribution amplifier 904 are mounted on the glass, with the remaining upstream elements mounted outside the edge of the glass. Alternatively, as shown in Figure 24B, all of the shown elements (including the input terminal 902 with its switch 842) are mounted on the glass, with no elements of the source driver mounted on the flexible PCB 184.

[0174] Alternatively, all column drivers 916 of the source driver are mounted on the glass, with the remaining upstream elements (i.e., collector 915) mounted outside the edge of the glass. Alternatively, all column drivers 916 and collector 915 of the source driver are all mounted on the glass, with no elements of the source driver mounted on the flexible PCB 184, as shown in Figure 24B.

[0175] In one specific embodiment, the SHA input amplifier operates at an input rate of approximately 664 MHz, the A / B sampling block operates at 1 / 16 of the input rate, and the preamplifier and downstream components operate at 1 / 1024 of the input rate (1 / 64 of 1 / 16 of the input rate). Of course, the input rate can vary, and the percentage of the input rate at which the downstream components operate will vary depending on the implementation, the number of columns, the interleaving technique used, etc. In another embodiment, only the HV driver is implemented on the glass because the output from the level converter 912 is single-ended (making implementation easier). Alternatively, the preamplifier, level converter, and HV driver are implemented on the glass because they require lower frequencies than the SHA amplifier and A / B block. Also, because the amplifier 904 operates at the highest frequency, it is possible to implement only the SHA amplifier 904 on the source driver chip and all other downstream components on the glass.

[0176] <Improved video image through feedback from display column amplifiers> Figure 1 shows an example of a display panel with (typically) 24 novel source drivers 186, and Figure 13 shows one embodiment of a SAVT receiver integrated with the source drivers. Figure 21 then shows in more detail how the 64 columns 920 of that source driver are driven, starting from a sampling input 902. Unfortunately, due to manufacturing variations in display panels and their source drivers, the 23,000 (for example) column amplifiers (and the associated analog circuitry leading to them) will produce different output levels when driven with identical inputs.

[0177] This paper discloses a technique for compensating for this variation by providing appropriate feedback to the display unit's timing controller (TCON). Thus, the present invention allows 24 (or any number of) demultiplexing / source driver chips to feed back the level of a single column amplifier to the TCON. By collecting performance information from all 23,000 column amplifiers, the TCON can prescale the intended value for a given column to equalize performance between columns. Advantageously, there is no requirement for high-speed performance, and the present invention can be used pre-sale for screen calibration purposes. In other words, this technique can be used during production testing when all columns are available, measuring drive characteristics without any additional area penalty on the chip (due to per-column area overhead for sampling). This prescaling of values ​​based on individual column feedback is in addition to the prescaling performed by the TCON to equalize performance of different rows in the display. Rows farther from the source driver may require additional current to achieve the same light output.

[0178] There are two main implementations: analog feedback and digital feedback. Both use an interface like JTAG, I2C or SPI to allow the TCON to issue a command to a specific column driver to send back the value coming out of the column amplifier. This command can also be issued using an MFM command as mentioned above. In the analog version, the value is sampled via an analog switch onto an analog bus shared by all source driver chips (a single analog connector back to the TCON). The TCON then performs analog-to-digital conversion (ADC) and digital processing of the result. Because the source driver outputs are high voltage, multiplexing requires the use of high-voltage transistors, although it is also possible to generate a lower-voltage representation of the column voltage before multiplexing (done by a resistor or capacitor divider). Either way, there is an area overhead for each column.

[0179] Figure 26 shows an analog architecture 1010 for sending commands and receiving feedback. The novel pre-scaling control unit 1020 of the TCON 130 sends commands to any particular column driver (such as driver 916) in the source driver 186 to sample the analog value of the output from that amplifier in the HV driver 914, using a protocol and communication lines such as JTAG, I2C, or SPI 1022 (or similar). Once sampled, the value is sent back to the ADC 1032 in the TCON via a single analog bus 1024. The converted digital value is sent to the controller 1020, which collects all values ​​from all column amplifiers alike, processes all values, determines how to pre-scale each value to make them equal, and outputs the results to a pre-scaling value storage device 1034 that stores each column's actual value, offset value, percentage, ratio, etc. The values ​​1034 are then used (along with other pre-scaling) during operation of the display to modify the samples sent from the TCON to the display, as known in the art.

[0180] Figure 27 illustrates the sampling of values ​​from a column amplifier. Shown is one HV driver 914 for a particular column (in this case, column 63 of SHA[0] from Figure 21), which feeds the output of its built-in amplifier 1040 to an analog switch 1042, the output of which is connected to the analog bus 1024 to feed the column output back to the TCON. The command arrives via a control signal 1041 (i.e., using JTAG, I2C, SPI, etc.) to sample the value. Switch 1042 is an example; other types of analog switches could be used (e.g., using FETs), and other similar sampling circuits could also be used.

[0181] In the digital version, each source driver chip has its own dedicated analog-to-digital converter, sampling the column amplifiers locally (thus avoiding the loading effects of long analog return paths) and returning digital values ​​to the TCON via the same JTAG, I2C or SPI path used to send commands.

[0182] Figure 28 shows a digital architecture 1050 for sending commands and receiving feedback. The novel pre-scaling control unit 1020 of the TCON 130 sends a command to a particular column driver (such as driver 916) in one of the source drivers 186 to sample the analog value of the output from that amplifier in the HV driver 914, using a protocol and communication lines such as JTAG, I2C, or SPI 1052 (or similar). Once sampled and converted, the digital value is also returned via line 1052 to the control unit 1020 in the TCON. The controller 1020 similarly collects all values ​​from all column amplifiers, processes all values, determines how to pre-scale each value to make them equal, and outputs the results to a pre-scaling value storage device 1034 that stores the actual value, offset, percentage, ratio, etc. for each column. The values ​​1034 are then used (along with other pre-scaling) during operation of the display to modify the samples sent from the TCON to the display, as known in the art.

[0183] Figure 29 illustrates sampling values ​​from a column amplifier. Shown is one HV driver 914 for a particular column (in this case, column 63 of SHA[0] from Figure 21), which feeds the output of its built-in amplifier 1040 into an analog switch 1042, which may be implemented and controlled as described above. An ADC 1060 is included for each source driver, converting the analog values ​​from each column amplifier into digital values ​​and sending them back to the TCON. One or more ADCs per HV driver may also be used (provided the column voltages are kept low enough to avoid damaging the ADC input circuitry). This allows for simple screen measurement. The display can self-calibrate after manufacturing (before sale during production test), on user command, recalibration, or at other times. The ability to recalibrate after sale is an advantage of having additional hardware on-chip, rather than performing calibration during production test.

[0184] Another embodiment models how a pixel's performance varies with neighboring pixels (e.g., in the same column) and uses that model to pre-scale the subpixel input before it is sent to the source driver chip to produce the desired brightness. Typically, it is difficult for each subpixel to report its light output; such measurements require elaborate test setups. Instead, the current through each subpixel at a particular pixel value is measured, and the measured current is used as a proxy for light emission to model the pixel's (or subpixel's) performance.

[0185] A variant uses actual screen measurements to model the performance of the display, particularly how adjacent sub-pixel values ​​affect luminance (due to slew rate issues, etc.), and then uses this model to pre-scale the sub-pixel inputs before sending them to the source driver chip to produce the desired luminance.

[0186] <Video signal transmission in other environments> The above describes embodiments for transmitting video signals to a display panel and within a display unit. The present invention also includes embodiments for transmitting video signals using SAVT in other environments, such as directly from a camera or other image sensor, from an SoC or other processor, and for receiving SAVT signals in a SAVT receiver (as described above) that is not necessarily integrated into a display panel, such as a SAVT receiver not integrated into an SoC, a computer processor, or a legacy display panel. U.S. Patent Applications 63 / 611,274 and 63 / 625,473 (HYFYP017P2 and HYFYP018P), incorporated by reference above, disclose examples of such other environments in mobile devices and vehicles, respectively.

[0187] FIG. 30 illustrates a SAVT transmitter 1240 configured to transmit various video samples from various sources. Shown is a distributor 1241 including two line buffers 1242 and 1243 with input vectors, a distributor controller 1230, optional digital-to-analog converters 1260-1269, and analog EM signals 1270-1279 output from each input vector, which may be implemented as shown and described in FIG. 2. While outputs 1281 and 1291 are shown as serial outputs, the outputs may also be described as in FIG. 2, and in one embodiment, all samples may be output in parallel from the first buffer to the second buffer. Similar to FIG. 2, each DAC (if present) converts its received sample from the digital domain to a single analog level (if no DAC is present, the analog level is output from the line buffer), which may be transmitted as a differential pair of voltage signals having a magnitude proportional to its received digital value, with the analog level being transmitted serially as output from each DAC. Although not shown, image processors 250-259 may optionally be present depending on the implementation, and may be present after the buffer, or preferably before it.

[0188] In this example, multiple EM paths are present, which may be a single EM path or multiple EM paths. Depending on implementation and design decisions, multiple outputs improve performance but require more paths. To minimize wiring from the transmitter 1240, only a single path carrying a single EM signal 1270 may be used. The SAVT transmitter 1240 may have different inputs, an image processor is not necessarily required (it may be implemented downstream in an SoC or other processor), and the DAC is optional but may be implemented substantially as described above for the transmitter of FIG. 2. Furthermore, the number of input vectors per line buffer and the number of samples per input vector, N, may vary widely depending on the implementation, the type of input signal, the desired bandwidth, whether the transmitter is implemented in a camera or an SoC or other processor, etc. Also, to minimize wiring from the transmitter 1240, only a single path carrying a single EM signal 270 may be used.

[0189] Depending on the embodiment described immediately below, analog RGB video samples 1239a may be input, analog or digital RGB samples 1239b may be input, digital G samples 1239c may be input, or analog BGBG...RGRG samples 1239d may be input. If the samples are digital, DACs 1260-1269 are used. In general, the transmitter can accept analog or digital video samples from any color space used, not necessarily RGB. Samples may arrive serially, for example, R→G→B, or RGB may arrive in parallel as three separate signals. A distributor 1241 can be used to reorder the samples as needed.

[0190] As mentioned above, the input can vary depending on the implementation. Input 1239d can occur as follows: The image sensor can output raw analog samples without using an ADC and without performing "demosaicing" using interpolation. Thus, the image sensor output is a continuous stream of time-ordered analog video samples, each representing a row of pixels per frame, in row-major order (for example), from left to right, as far as the image sensor is aware. Of course, a different order can be used. When Bayer filtering is used, the samples are output by rows of BGBG··· followed by rows of RGRG···, often referred to as RGGB format because each 2x2 pattern contains one of RGGB. These rows of analog video samples 1239d are input to the SAVT transmitter 1240 and transmitted as EM signals 1270-1279 to the SAVT receiver of FIG. 31, from which they are serially output 1360. Since the samples are still raw data from the image sensor (i.e. the Bayer filtered output from the sensor), a downstream ADC is used (if necessary) and the ISP performs "demosaicing" using CFA interpolation to interpolate the "missing" color values ​​at each location to create an RGB sample per pixel.

[0191] Input 1239c can occur as follows: Raw analog samples coming from the image sensor are converted to digital in an ADC, and then "demosaicing" is performed in the image signal processor (ISP) to obtain digital RGB samples per pixel. From each set of RGB samples per pixel, only the green channel (i.e., one G sample per element of the array) is selected and sent to become input 1239c. These rows of G digital video samples 1239c are input to the SAVT transmitter 1240 and transmitted as EM signals 1270-1279 to the SAVT receiver of FIG. 31, where they are serially output. Thus, image delay on any display is significantly reduced to provide immediate feedback to the viewer in applications where near-eye displays are used, such as virtual reality, augmented reality, etc.

[0192] Alternatively, because only the green channel is transmitted, interpolation only needs to be performed on the R and B components of the sensor to obtain the G samples. No interpolation is required on the G components, as the G samples are already present there and the R and B samples in those G components are not needed. This makes the interpolation process simpler and faster. Because the green channel corresponds to the luminance (or "luma") channel, there is no perceived loss of resolution. However, downstream display devices will display a monochrome image.

[0193] Input 1239a is generated as follows: Modify the readout from the image sensor to read out at least two rows simultaneously. For example, read out the first two rows at the bottom of the image sensor simultaneously and output a serial stream of values ​​such as BGRGBGRG··· or GBGRGBGR···. Thus, the readout order would be first the blue value from row 1, then the green and red values ​​from row 2, followed by the green value from row 1···, resulting in the serial output BGRGBGRG. Alternatively, an alternative readout order would be first the green value from row 2, then the blue and green from row 1, then the red from row 2, resulting in the serial output GBGRGBGR. Other readout orders that blend color values ​​from two adjacent rows can also be used, and the order of pixel values ​​may vary depending on whether a particular row begins with red, green, or blue values.

[0194] Two rows are read out at a time, and each of the four values ​​from those two rows (e.g., BG from the beginning of the first row and GR from the beginning of the second row, i.e., two Gs, Rs, and Bs) is available for serial output. This results in a serial pattern such as BGRG··· or GBGR···, as shown. After the first two rows are read out, the next two rows are read out, and so on. Other similar outputs are possible, with each group of four values ​​containing two green, red, and blue values. The image sensor can also be read out from a specific corner, top-to-bottom or bottom-to-top, row-by-row or column-by-column, or in other similar ways. Thus, the output from the video source is a series of values ​​such as BGRGBGRG··· or GBGRGBGR. Demosaicing is performed using this series in the analog domain of the SoC, without the use of digital-to-analog converters or digital processing.

[0195] This ordering of color values ​​facilitates interpolation in the analog domain. Other color spaces that read more than one row at a time and mix color values ​​from different rows in the serial output also facilitate color interpolation in the analog domain. A video source containing an image sensor outputs a pattern such as BGRGBGRG··· or GBGRGBGR, which is illustrated in FIG. 30 at 1239a and referred to as "RGGB···." These RGGB video samples are serially input to transmitter 1240, transmitted as EM signals 1270-1279 to the SAVT receiver in FIG. 31, and serially output from the SAVT receiver.

[0196] Input 1239b may originate as follows: digital RGB samples may be input as shown in FIG. 2, or analog RGB samples 1239b may be input as shown in FIG. 30. These analog RGB samples may originate within a processor that performs demosaicing in the analog domain on the raw image sensor output, within a processor that receives the digital RGB samples and converts them to analog RGB samples, or may originate in some other way. These analog RGB video samples are input to transmitter 1240 and transmitted as EM signals 1270-1279 to the SAVT receiver of FIG. 31, where they are serially output from the SAVT receiver.

[0197] Figure 31 shows a SAVT receiver 1300 that can reside in an SoC, processor, legacy display, or elsewhere. The receiver receives any number of EM signals 1270-1279 and inputs them into a collector 1320 that has two line buffers 1301 and 1302. Similar to the distributor of the SAVT transmitter in Figure 30, each line buffer has any number of output vectors 1304, 1306, 1308 (or 1314, 1316, 1318), each holding any number of video samples corresponding to an input vector (e.g., N=1024). In operation, each output vector 1304-1308 of the first line buffer 1301 is filled with samples from the corresponding EM signal 1270-1279, and while the buffer 1301 is outputting its samples (via outputs 1305, 1307, 1309) to the receiver output 1360, the second line buffer 1302 is filling from the corresponding EM signal 1270-1279. When the first line buffer empties, it begins to refill while the second line buffer is outputting to the receiver output 1360.

[0198] As with the SAVT transmitter of Figure 30, there are preferably two line buffers, but more may be used if desired, and the buffer lengths may be adjusted as described above. For the collector 1320, the output is serial, but the output from each buffer may be parallel (i.e., outputting all N samples from each output vector at once), which may take longer per sample to output than the input samples. Thus, if 100 samples are output at a time, the transfer to the output may be 100 times slower than the input samples (assuming the input samples were one at a time).

[0199] The collector controller 1330 sequences the loading of samples from the inputs 1270-1279 and also controls when to unload samples for further processing. Because the input stream is continuous, the collector controller loads samples into one line buffer while the samples in the other line buffer are transferred to the output for further processing.

[0200] A receiver embodiment suitable for use with the embodiment described in FIG. 30 is shown in which rows of the image sensor are serially output and sent via SAVT transmitter 1240 (using input 1239d, i.e., BG···RG··) to collector 1320, and then serially output from the collector in the same format as the input, i.e., BG···RG··. Once output, the samples are sent for further processing or display. As mentioned above, the output from the collector may be parallel if parallel input to a processor is desired. Whatever permutation is used by the corresponding SAVT transmitter to distribute the received samples to the line buffers, the reverse permutation is used in the SAVT receiver so that receiver output 1360 outputs the samples in the order received by the SAVT transmitter (i.e., the order received by 1239d).

[0201] Although SAVT receiver 1300 only shows BG.RG... outputs, it can also receive and output samples input using the other embodiments described in Figure 30. Thus, when input 1239a is input to the SAVT transmitter, output 1360 is RGGB... samples, when input 1239c is input to the SAVT transmitter, output 1360 is G... samples, and when input 1239b is input to the SAVT transmitter, output 1360 is RGB... samples.

[0202] Because the outputs 1360 are analog samples, an ADC 1362 or ADC may be used as needed to convert the samples to digital samples. Thus, each output vector can output its samples one at a time through an analog-to-digital converter (ADC) 1362 to provide a continuous stream of digital samples 1364.

[0203] <Additional Embodiments> The present invention includes the following additional embodiments. C1. An apparatus that integrates a DDIC-TCON (Display Driver Integrated Circuit - Timing Controller) into a transmitter, said apparatus comprising: a distributor configured to receive a stream of digital video samples originating from a system-on-chip of a mobile phone and distribute the digital video samples to a plurality of input vectors according to a predetermined permutation; a plurality of digital-to-analog converters configured to receive the digital video samples from the plurality of input vectors, convert the digital video samples into a series of analog video samples, and output the series of analog video samples to a display panel of the mobile phone via an electromagnetic path; a gate driver control signal output to a gate driver of the display panel; An apparatus comprising:

[0204] C2. The distributor is a first line buffer for storing the plurality of input vectors; a second line buffer for storing a plurality of second input vectors; and the distributor is further configured to distribute the lines of the digital video samples alternately between the input vectors of the first line buffer and the second input vectors of the second line buffer; The transmitter of claim C1, wherein the plurality of image processors alternately read from the first line buffer while the distributor writes to the second line buffer, and from the second line buffer while the distributor writes to the first line buffer.

[0205] C3. The transmitter of claim C1, wherein the digital video samples distributed among the input vectors constitute lines of an image.

[0206] C4. The transmitter of claim C1, wherein the digital video samples are distributed to the input vectors at a first frequency, and the digital video samples are serially output from each input vector at a second frequency different from the first frequency.

[0207] C8. The integrated transmitter timing controller of claim C1, wherein the device is located within about 2 cm of the system-on-chip.

[0208] C9. The apparatus of claim C1, wherein the apparatus is integrated within a single integrated circuit of the mobile phone.

[0209] C10. The transmitter of claim C9, wherein the device is integrated with the system-on-chip of the mobile phone.

[0210] C11. The apparatus of claim C1, further comprising a plurality of image processors, each image processor configured to serially read the digital video samples of the one input vector from one of the input vectors and perform at least gamma correction on the digital video samples of the one input vector.

[0211] D1. An input terminal configured to receive, via an electromagnetic path, an analog electromagnetic signal comprising a continuous series of analog video samples; a plurality of sampling amplifiers each configured to exclusively sample a portion of the analog video samples and write the portion of the analog video samples to a storage array location designated for the respective sampling amplifier; a plurality of column drivers each configured to read one of the analog video samples from one of the storage array locations, amplify one of the analog video samples, and drive the amplified one of the analog video samples to a column of the display panel of the mobile phone; The display unit includes a source driver. The mobile phone includes an analog DDIC-SD (Display Driver Integrated Circuit - Source Driver).

[0212] D2. Further comprising a second storage array having a location assigned to each sampling amplifier; the sampling amplifier is further configured to alternately write portions of each of the analog video samples to the storage array or the second storage array; The analog DDIC-SD of claim D1, wherein the column driver alternately reads from the storage array while the sampling amplifier writes to the second storage array, and from the second storage array while the sampling amplifier writes to the storage array.

[0213] D3. The analog DDIC-SD of claim D2 further comprising control logic circuitry that enables each of the sampling amplifiers to sample a portion of the analog video sample, that enables the sampling amplifiers to write to the storage array or the second storage array, and that enables the column drivers to read from the storage array or the second storage array.

[0214] D3. The analog DDIC-SD of claim D1, wherein some of the analog video samples are used for synchronization and are not driven to columns of the display panel.

[0215] D4. The analog DDIC-SD of claim D1, wherein the analog DDIC-SD does not have a digital-to-analog converter (DAC) used to convert video samples.

[0216] D5. The analog DDIC-SD of claim D2, wherein the column drivers are further configured to read in parallel from the storage array when the storage array is full or to read in parallel from the second storage array when the second storage array is full.

[0217] D6. The analog DDIC-SD of claim D1, wherein the series of analog video samples arrive in a predetermined permutation that directs each sampling amplifier to output a respective portion of the analog video sample to successive storage locations within the storage array.

[0218] D7. The analog DDIC-SD of claim D1, wherein the electromagnetic signal includes a control signal used for synchronization and is not driven to a column of the display panel, and the source driver further includes a dedicated sampling amplifier for sampling the control signal.

[0219] F1.Transmitter and a plurality of electromagnetic paths; a source driver array; Equipped with The transmitter a distributor configured to receive a stream of digital video samples from a system on chip of a mobile phone and distribute the digital video samples to a plurality of input vectors in a line buffer according to a predetermined permutation; one digital-to-analog converter (DAC) per input vector; and each of the plurality of digital-to-analog converters configured to serially receive the digital video samples from its corresponding input vector and convert the digital video samples into a series of analog video samples; each of the plurality of electromagnetic paths configured to transmit one of the series of analog video samples to a display panel of the mobile phone; the source driver array includes a source driver corresponding to each of the digital-to-analog converters; Each source driver is a collector configured to receive the series of analog video samples from each of the digital-to-analog converters and store the analog video samples of the corresponding input vector; a plurality of column drivers configured to receive the stored analog video samples in parallel from the collector and to amplify each stored analog video sample for a column of the display panel; A video transmission device comprising:

[0220] F2. The apparatus of claim F1, wherein the transmitter is integrated into a DDIC-TCON, and the apparatus has gate driver control signals output to gate drivers of the display panel.

[0221] F3. The apparatus of claim F2, wherein the transmitter is located within about 2 cm of the system-on-chip.

[0222] F4. The apparatus of claim F2, wherein the transmitter is integrated within a single integrated circuit of the mobile phone.

[0223] F5. The apparatus of claim F2, wherein the transmitter is also integrated with the system-on-chip of the mobile phone.

[0224] F6. The apparatus of claim F1, in which each source driver is an analog DDIC-SD (Display Driver Integrated Circuit-Source Driver) in a mobile phone.

[0225] F7. The apparatus of claim F6, wherein the analog DDIC-SD does not include a digital-to-analog converter (DAC) used to convert video samples.

[0226] I1. An input terminal for receiving analog sample values ​​representing a video stream; a collector configured to receive the analog sample values ​​from the input terminal, store the analog sample values ​​in a storage array, and output the analog sample values ​​in parallel, the input terminal and the collector being mounted outside an edge of a display panel of the display unit; a plurality of column drivers that receive the analog sample values ​​in parallel and output voltage values ​​to columns of the display panel, the plurality of column drivers being implemented on a glass substrate of the display panel using at least transistors; A source driver for a display unit comprising:

[0227] I2. The source driver of claim I1, wherein the analog sample values ​​are an ordered sequence of continuous amplitude analog levels.

[0228] I3. The source driver of claim I1, wherein the plurality of column drivers are disposed on the glass substrate of the display panel between a pixel display area and a periphery of the glass substrate.

[0229] I4. The source driver of claim I1, wherein the source driver does not include a digital-to-analog converter for converting video samples.

[0230] I5. The source driver of claim I1, wherein the transistor is operable at a clock frequency required by the column driver.

[0231] I6. The source driver of claim I5, wherein the transistor is a thin-film transistor (TFT), a low-temperature polysilicon (LTPS) transistor, or an indium gallium zinc oxide (IGZO) transistor.

[0232] I7. The source driver of claim I1, wherein the pixels of the display panel are implemented using the same type of transistors as used to implement the column drivers.

[0233] I8. The source driver of claim I1, wherein the display unit is a display of a mobile phone.

[0234] I9. The source driver of claim I1, wherein each of the column drivers comprises a high voltage driver.

[0235] I10. The source driver of claim I9, wherein each of the column drivers further includes a level converter, each level converter operative to shift at least the output voltage of the column driver.

[0236] I11. The source driver of claim I1, wherein the collector is a two-stage collector.

[0237] J1. An input terminal for receiving analog sample values ​​representing a video stream; and a collector configured to receive the analog sample values ​​from the input terminal, store the analog sample values ​​in a storage array, and output the analog sample values ​​in parallel; a plurality of column drivers that input the analog sample values ​​in parallel and output voltage values ​​to columns of the display panel, the collector and the plurality of column drivers being implemented using at least transistors on a glass substrate of the display panel.

[0238] J2. The source driver of claim J1, wherein the analog sample values ​​are an ordered sequence of continuous amplitude analog levels.

[0239] J3. The source driver of claim J1, wherein the collector and the plurality of column drivers are disposed on the glass substrate of the display panel between a pixel display area and a periphery of the glass substrate.

[0240] J4. The source driver of claim J1, wherein the source driver does not include a digital-to-analog converter for converting video samples.

[0241] J5. The source driver of claim J1, wherein the transistor is operable at a first clock frequency required by the column driver and a second clock frequency required by the collector.

[0242] J6. The source driver of claim J5, wherein the transistor is a thin film transistor (TFT), a low temperature polysilicon (LTPS) transistor, or an indium gallium zinc oxide (IGZO) transistor.

[0243] J7. The source driver of claim J1, wherein the pixels of the display panel are implemented using the same type of transistors used to implement the collector and the column driver.

[0244] J8. The source driver of claim J1, wherein the display unit is a display of a mobile phone.

[0245] J9. The source driver of claim J1 wherein each of the column drivers comprises a high voltage driver.

[0246] J10. The source driver of claim J9, wherein each of the column drivers further includes a level converter, each level converter operative to shift at least the output voltage of the column driver.

[0247] J11. The source driver of claim J1, wherein the input terminal is mounted outside an edge of a display panel of the display unit.

[0248] J12. The source driver of claim J1, wherein the input terminal is mounted on the glass substrate of the display panel.

[0249] J13. The source driver of claim J1, wherein the collector is a two-stage collector.

[0250] K1. A display panel having a glass substrate; a plurality of source drivers, each of which a collector configured to receive analog sample values ​​representing the video stream, store the analog sample values ​​in a storage array, and output the analog sample values ​​in parallel; a plurality of column drivers that receive the analog sample values ​​in parallel and output voltage values ​​to columns of the display panel;

[0251] K2. The collector of each source driver is mounted outside the edge of the display panel of the display unit; the column drivers are implemented with at least transistors on the glass substrate of the display panel; The display unit of claim K1, wherein the transistors are operable at a clock frequency required by the column driver.

[0252] K3. The collector of each of the source drivers and the column driver are implemented using at least a transistor on the glass substrate of the display panel; A display unit as described in claim K1, wherein the transistor is operable at a clock frequency required by the collector and the column driver.

[0253] K4. The display unit of claim K1, wherein the analog sample values ​​are an ordered sequence of continuous amplitude analog levels.

[0254] K5. The display unit of claim K2, wherein the plurality of column drivers of each source driver are disposed on the glass substrate of the display panel between a pixel display area and a periphery of the glass substrate.

[0255] K6. The display unit of claim K1, wherein each source driver does not include a digital-to-analog converter for converting video samples.

[0256] K7. The display unit of claim K2, wherein the transistor is a thin-film transistor (TFT), a low-temperature polysilicon (LTPS) transistor, or an indium gallium zinc oxide (IGZO) transistor.

[0257] K8. The display unit of claim K3, wherein the transistor is a thin-film transistor (TFT), a low-temperature polysilicon (LTPS) transistor, or an indium gallium zinc oxide (IGZO) transistor.

[0258] K9. The display unit of claim K1, wherein the display unit is a mobile phone display.

[0259] K10. The source driver of claim K1, wherein each collector of each source driver is a two-stage collector.

[0260] P1. An analog switch having an input connected to an output of an amplifier of a column driver of a display panel of a display unit, a control input configured to receive a control signal from a timing controller of said display unit, and an output connected to an analog line connected to said timing controller; The feedback device for the source driver of the display unit, wherein the analog switch is configured to latch a voltage value of the amplifier upon receiving the control signal and send the voltage value to the timing controller.

[0261] P2. The feedback device of claim P1, wherein the control signal instructs the analog switch to latch the voltage value when the column driver is driving a column of the display.

[0262] P3. Further comprising an analog-to-digital converter disposed between the output of the analog switch and the timing controller; The feedback device of claim P1, wherein the analog-to-digital converter is configured to convert the voltage value from the output to a digital voltage value that is sent to the timing controller.

[0263] P4. The feedback device of claim P1, wherein the voltage values ​​delivered to the timing controller are analog voltage values.

[0264] P5. A source driver of the display unit, comprising a feedback device according to claim P1 for each column of the display panel.

[0265] Q1. Sending a command from the timing controller to a column driver of the source driver to latch a voltage value output by an amplifier of the column driver into a display panel of the display unit; latching the voltage value at the output of the amplifier; receiving the voltage value at the timing controller and storing the voltage value; A method for providing feedback from a source driver to a timing controller of a display unit, comprising:

[0266] Q2. The received voltage value is an analog voltage value, converting the analog voltage value to a digital voltage value within the timing controller and storing the digital voltage value; The method of claim Q1, further comprising:

[0267] Q3. The voltage value is an analog voltage value at the output of the amplifier; converting the analog voltage values ​​into digital voltage values ​​within the source driver; receiving the digital voltage value at the timing controller; The method of claim Q1, further comprising:

[0268] Q4. Sending said commands to said column drivers via a digital control interface; receiving the digital voltage value at the timing controller via the digital control interface; The method of claim Q3, further comprising:

[0269] Q5. Sending said commands to said column drivers via a digital control interface; receiving the analog voltage value over an analog line; The method of claim Q2, further comprising:

[0270] Q6. Implementing the transmitting, latching, and receiving for multiple column drivers; pre-scaling output voltage values ​​of the timing controller destined for columns of the display panel using the stored voltage values; The method of claim Q1, further comprising:

[0271] R1. A distributor configured to receive a stream of video samples originating from an image sensor, distribute an initial selection of the digital video samples as a plurality of first input vectors to a first line buffer according to a predetermined permutation, and distribute a subsequent selection of the video samples as a plurality of second input vectors to a second line buffer according to the predetermined permutation, and further configured to distribute the selection of video samples alternately between the first line buffer and the second line buffer; a plurality of output ports, each configured to alternately read from one of the first input vectors of the first line buffer while the distributor writes to the second line buffer, and to alternately read from one of the second input vectors of the second line buffer while the distributor writes to the first line buffer, and to output as an electromagnetic signal a series of analog levels corresponding to the video samples of the one of the first input vectors or the second input vectors; A transmitter comprising:

[0272] R2. The transmitter of claim R1, wherein the video samples are analog RGB video samples.

[0273] R3. The video samples are digital RGB video samples; 10. The transmitter of claim R1, further comprising a plurality of digital-to-analog converters (DACs), each configured to receive the digital RGB video samples from one of the first input vector or the second input vector, convert the digital RGB video samples to analog video samples, and output the analog video samples to one of the output ports.

[0274] R4. The transmitter of claim R1, wherein the video samples are raw analog BGRG video samples.

[0275] R5. The transmitter of claim R1, wherein the video samples are raw analog RGGB video samples output in modified form from the image sensor.

[0276] R6. The video samples are digital G video samples; The transmitter of claim R1, further comprising a plurality of digital-to-analog converters (DACs), each configured to receive the G digital video samples from one of the first input vector or the second input vector, convert the digital video samples to analog video samples, and output the analog video samples to one of the output ports.

[0277] S1. A plurality of input terminals, each receiving an electromagnetic signal via an electromagnetic path, each said electromagnetic signal including a series of analog levels representing analog video samples; a collector configured to collect the analog video samples of each of the electromagnetic signals into one of a plurality of first output vectors in a first line buffer and into one of a plurality of second output vectors in a second line buffer, the collector further configured to alternately collect a selection of the analog video samples between the first line buffer and the second line buffer, the collector further configured to output analog video samples from the first output vector of the first line buffer according to a predetermined permutation while the second line buffer is filled, and output analog video samples from the second output vector of the second line buffer according to the predetermined permutation while the first line buffer is filled, whereby the receiver continuously outputs the stream of analog video samples; A receiver comprising:

[0278] S2. The source driver of claim S1, further comprising a collector controller configured to collect the input analog levels from the electromagnetic signal into the first line buffer and the second line buffer, and output the analog levels from the first line buffer and the second line buffer according to the predetermined permutation.

[0279] S3. The receiver of claim S1, wherein the first line buffer outputs analog video samples from the first output vector when the first line buffer is full.

[0280] S4. The receiver of claim S1, wherein the receiver does not include a digital-to-analog converter used to convert video samples.

[0281] S5. The receiver of claim S1, wherein the receiver includes at least one analog-to-digital converter that converts the stream of analog video samples into digital video samples.

[0282] G1. Sending a control sequence from a transmitter in the display unit to a source driver of the display unit, the control sequence being an MFM (Modified Frequency Modulation) encoded sequence; introducing an MFM flag into the control sequence to indicate to the source driver that at least one command follows the MFM flag; The method for sending commands to a source driver of a display unit includes sending at least one video synchronization command in the control sequence to the source driver after the MFM flag.

[0283] G2.: The method of claim G1, further comprising using said video synchronization command to perform vertical or horizontal synchronization of an image displayed on a display panel of said display unit.

[0284] G3. The method of claim G1 further comprising inserting, at the transmitter, the control sequence into a stream of analog video samples destined for the source driver such that the control sequence is received at a single input amplifier of the source driver.

[0285] G4. The method of claim G1 further comprising introducing the MFM flag into the control sequence upon power-on of the display unit.

[0286] G5. Sending the control sequence including the introduced MFM flag to all input channels of the source driver until a resynchronization occurs; After resynchronization, transmitting the control sequence to only a single input channel of the source driver; The method of claim G1 further comprising:

[0287] G6. The method of claim G1, further comprising simultaneously sending the control sequence along with the introduced MFM flag to all source drivers of the display unit.

[0288] H1. Receive a control sequence, which is a modified frequency modulation (MFM) encoded sequence, from a transmitter in the display unit at a source driver of the display unit; receiving and recognizing an MFM flag in the control sequence that indicates to the source driver that at least one command will follow the MFM flag; A method of receiving commands at a source driver of a display unit, wherein the next MFM cell in the control sequence after the MFM flag is interpreted by the source driver as a video synchronization command.

[0289] H2. The method of claim H1, further comprising using the video synchronization command to perform vertical or horizontal synchronization of an image displayed on a display panel of the display unit.

[0290] H3. The method of claim H1, in which the control sequence is received at a single input amplifier of the source driver.

[0291] H4. The method of claim H1 further comprising receiving the MFM flag in the control sequence upon power-up of the display unit.

[0292] H5. The source driver receives the control sequence including the introduced MFM flag on all input channels of the source driver until a resynchronization occurs; The method of claim H1, wherein after resynchronization, the control sequence is received on only a single input channel of the source driver.

[0293] H6. The method of claim H1, further comprising simultaneously receiving the control sequence along with the introduced MFM flag at all source drivers of the display unit.

[0294] L1. receiving a command to enter a phase adjustment mode in a source driver of a display unit; receiving a synchronous stream of at least positive pulses having a first amplitude; setting an upper threshold of an upper comparator receiving the synchronization stream such that the upper comparator triggers upon receipt of the positive pulse; rotating the sampling phase of the positive pulse toward the trailing edge of the positive pulse until the upper comparator does not trigger at a particular sampling phase; when it is determined that the upper comparator does not trigger, rotating the sampling phase back by at least one tap from the particular sampling phase, and setting the rotated back sampling phase as a source driver sampling phase for sampling input analog video samples at the source driver; 2. A method for performing phase adjustment to determine a sampling phase of a source driver, comprising:

[0295] L2. The synchronization stream includes positive pulses alternating with second positive pulses having a second amplitude less than the first amplitude; The method of claim L1, further comprising: setting the upper threshold of the upper comparator by adjusting the upper threshold so that the upper comparator triggers on the positive pulse but not on the second positive pulse.

[0296] L3. The method of claim L1, comprising sampling, by the source driver, at least one input analog video sample using a sampling phase of the source driver, and displaying the input analog video sample on a display panel of the display unit.

[0297] L4. The source driver includes a central comparator that indicates whether a pulse of the synchronization stream is positive or negative; The method of claim L1, further comprising rotating the sampling phase backward from the particular sampling phase only if the result of the central comparator does not match the result of the upper comparator.

[0298] L5. The method of claim L1, wherein the commands are MFM (Modified Frequency Modulation) encoded commands and the synchronization stream is an MFM encoded stream.

[0299] L6. The method of claim L1, wherein the command and the synchronization stream are all received on a single channel of the source driver.

[0300] L7. The synchronization stream includes negative pulses alternating with the positive pulses, the negative pulses including negative amplitudes; setting a lower threshold for a lower comparator receiving the synchronization stream such that the lower comparator triggers upon receiving the negative pulse; rotating the second sampling phase of the negative pulse toward the trailing edge of the negative pulse until the lower comparator does not trigger at a particular second sampling phase; when it is determined that the lower comparator does not trigger, rotating the second sampling phase back by at least one tap from the specific second sampling phase, and setting the rotated back second sampling phase as a second sampling phase of a source driver; determining an average of the unrotated sampling phase and the second unrotated sampling phase as a sampling phase of the source driver for sampling input analog video samples at the source driver; The method of claim L1, further comprising:

[0301] M1. An input reference clock; Phase adjustment control; a phase selector configured to advance the sampling phase of the reference clock when the phase adjustment control indicates that sampling occurred before a control sequence of video samples received at the source driver, and configured to delay the sampling phase of the reference clock when the phase adjustment control indicates that sampling occurred after a control sequence of video samples received at the source driver; an output sampling clock having the sampling phase output by the phase selector and sent to an amplifier of the source driver receiving the video samples; A sampling phase adjustment circuit for a source driver of a display unit comprising:

[0302] M2. The sample phase adjust circuit of claim M1, further comprising an input clock cycle skip control configured to cause the sample phase adjust circuit to skip the reference clock cycle.

[0303] N1. Receiving a stream of samples at a source driver of a display unit; interleaving the samples across multiple channels; searching for an MFM flag in one of said channels; if it is determined that the MFM flag is not found in the one channel, searching a next one of the channels and determining that the MFM flag is present in the next channel; A method for sending commands to a source driver of a display unit, including:

[0304] N2. The method of claim N1, further comprising: implementing a clock cycle skip to search the next channel for the MFM flag.

[0305] N3. The method of claim N1, further comprising: transmitting the deinterleaved samples to a plurality of sample-and-hold amplifiers, each sample-and-hold amplifier implementing one of the channels.

[0306] N4. The method of claim N1, further comprising, after determining that the MFM flag is present in the next channel, specifying a command for a display panel of the display unit after the MFM flag in the next channel.

[0307] N5. The method of claim N1 further comprising, after determining that the MFM flag is present in the next channel, performing sample phase alignment using samples received on the next channel.

[0308] O1. Receiving a plurality of video samples and control samples at a source driver of the display unit, the video sample arriving immediately before the control sample having a different analog level than the video sample arriving immediately after the control sample; changing a sampling phase of one of the control samples by a phase step to sample one of the control samples; skipping a clock cycle to sample at the control sample if it is determined that sampling occurred at a sample prior to the control sample; if it is determined that sampling occurred at a sample after the control sample, returning the sampling phase by at least one phase step; 10. A method for performing phase alignment in a display unit for sampling a video signal comprising:

[0309] O2. The method of claim O1, further comprising advancing the sampling phase by at least one phase step after skipping the clock cycle to sample at the control sample.

[0310] O3. The method of claim O1, further comprising using a single comparator to determine that the sampling occurred at a previous sample or that the sampling occurred at a sample after the control sample.

[0311] O4. The method of claim O1, further comprising, after skipping the clock cycle or retarding the sampling phase, sending the sampling phase to each of a plurality of amplifiers that sample the video samples and the control samples.

Claims

1. a distributor configured to receive a stream of digital video samples from a system-on-chip of a display unit and distribute the digital video samples to a plurality of input vectors according to a predetermined permutation; a plurality of digital-to-analog converters (DACs); Equipped with each of the plurality of digital-to-analog converters configured to receive the digital video samples from one of the plurality of input vectors, convert the digital video samples of the one input vector into a series of analog video samples, and output the series of analog video samples to a display panel of the display unit via an electromagnetic path; Transmitter.

2. The distributor comprises: a first line buffer for storing the plurality of input vectors; a second line buffer for storing a plurality of second input vectors; and the distributor is further configured to distribute the lines of the digital video samples alternately between the input vectors of the first line buffer and the second input vectors of the second line buffer; 2. The transmitter of claim 1, wherein the plurality of digital-to-analog converters alternately read from the first line buffer while the distributor writes to the second line buffer, and read from the second line buffer while the distributor writes to the first line buffer.

3. 2. The transmitter of claim 1, wherein the digital video samples distributed among the input vectors constitute lines of an image.

4. the digital video samples are distributed to the input vectors at a first frequency; 2. The transmitter of claim 1, wherein the digital video samples are output serially from each of the input vectors at a second frequency different from the first frequency.

5. 2. The transmitter of claim 1, wherein the predetermined permutation enables each sampling amplifier of a source driver that receives one of the series of analog video samples to output the one of the series of analog video samples to consecutive storage locations.

6. The transmitter is integrated with a timing controller of the display unit, and the integrated transmitter and timing controller:

10. The transmitter of claim 1, further comprising a gate driver control signal output to a gate driver of the display panel.

7. 7. The integrated transmitter and timing controller of claim 6, wherein the integrated transmitter and timing controller is located within about 10 cm of the system-on-chip, within about 5 cm of the system-on-chip, or within about 2 cm of the system-on-chip.

8. The integrated transmitter and timing controller of claim 6 , wherein the integrated transmitter and timing controller is integrated with the system-on-chip of the display unit.

9. 6. The transmitter of claim 5, wherein the predetermined permutation allows one of the sampling amplifiers to exclusively sample only a control signal.

10. 10. The transmitter of claim 1, further comprising an image processor configured to receive the digital video samples, perform at least gamma correction on the digital video samples, and output corrected digital video samples.

11. an input terminal for receiving, via an electromagnetic path, an analog electromagnetic signal comprising a continuous series of analog video samples; a plurality of sampling amplifiers configured to exclusively sample a portion of the analog video samples and write the portion of the analog video samples to a storage array location designated for each sampling amplifier; a plurality of column drivers configured to read one of the analog video samples from one of the storage array locations, amplify the one analog video sample, and drive the amplified one analog video sample onto a column of the display panel; A source driver for a display unit comprising:

12. a second storage array having a location assigned to each sampling amplifier; the sampling amplifier is further configured to alternately write portions of each of the analog video samples to the storage array or the second storage array; 12. The source driver of claim 11, wherein the column driver alternates between reading from the storage array while the sampling amplifier writes to the second storage array and reading from the second storage array while the sampling amplifier writes to the storage array.

13. 13. The source driver of claim 12, further comprising: control logic circuitry configured to enable each of the sampling amplifiers to sample a portion of the analog video sample, to enable the sampling amplifiers to write to the storage array or the second storage array, and to enable the column driver to read from the storage array or the second storage array.

14. the electromagnetic signals include control signals that are not driven to columns of the display panel and are used for synchronization; The source driver of claim 11 , further comprising a dedicated sampling amplifier for sampling the control signal.

15. 12. The source driver of claim 11, wherein the source driver does not include a digital-to-analog converter (DAC) used to convert video samples.

16. 13. The source driver of claim 12, wherein the column drivers are further configured to read in parallel from the storage array when the storage array is full or to read in parallel from the second storage array when the second storage array is full.

17. 12. The source driver of claim 11, wherein the series of analog video samples arrive in a predetermined permutation that enables each sampling amplifier to output a portion of each of the analog video samples to consecutive storage locations in the storage array.

18. 18. The source driver of claim 17, wherein the predetermined permutation allows one of the sampling amplifiers to exclusively sample only a control signal.

19. A transmitter; a plurality of electromagnetic paths; a source driver array; Equipped with The transmitter a distributor configured to receive a stream of digital video samples and distribute the digital video samples to a plurality of input vectors in a line buffer according to a predetermined permutation; a digital-to-analog converter (DAC) arranged for each input vector and configured to serially receive the digital video samples from a corresponding input vector and convert the digital video samples into a series of analog video samples; and each of the plurality of electromagnetic paths configured to transmit one of a series of analog video samples to a display panel of a display unit; the source driver array includes a source driver corresponding to each of the digital-to-analog converters; Each source driver is a collector configured to receive a series of analog video samples from each digital-to-analog converter and store said analog video samples of a corresponding input vector; a plurality of column drivers configured to receive the stored analog video samples in parallel from the collector and to amplify each stored analog video sample for a column of the display panel; A video transmission device comprising:

20. 20. The video transmission device of claim 19, wherein the predetermined permutation enables each collector to store each of the analog video samples in consecutive storage locations.

21. 20. The video transmission device of claim 19, wherein the predetermined permutation allows the collector sampling amplifier to exclusively sample only the control signal.

22. The distributor comprises: a first line buffer; a second line buffer; 2. The transmitter of claim 1, wherein the distributor is further configured to distribute the input vector of digital video samples to the first line buffer, transfer lines of the input vector to the second line buffer, and output each input vector of digital video samples from the second line buffer to one of the digital-to-analog converters while distributing digital video samples from the stream to the first line buffer.

Images