Pixel circuits, their driving methods, and display panels

Abstract

This invention discloses a pixel circuit, its driving method, and a display panel. The pixel circuit includes a driving module, a data writing module, a first initialization module, a storage module, a compensation control module, and a light-emitting module. The driving module includes a dual-gate transistor, and the dual-gate transistor and the light-emitting module are connected via a first power line and a second power line. The data writing module is connected between the first gate of the dual-gate transistor and a data line. The storage module is connected to the first gate, second gate, and second terminal of the dual-gate transistor, respectively. The compensation control module is connected between the first terminal and the second gate of the dual-gate transistor. The first initialization module is used to transmit a first initialization voltage on a first initialization signal line to the first gate of the dual-gate transistor and the first terminal of the light-emitting module. The technical solution provided by this invention can compensate for threshold voltage fluctuations over a large range, which is beneficial for improving display performance.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel circuit, its driving method, and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) display panels have become a research hotspot in the field due to their low power consumption, low production cost, and self-emissive characteristics.

[0003] The display panel includes pixel circuits, which contain driving transistors used to drive light-emitting devices to emit light. Because the driving current generated by the driving transistors is easily affected by factors such as the threshold voltage, and existing pixel circuits have poor threshold voltage compensation for the driving transistors, the display panel suffers from poor brightness uniformity, thus reducing the display effect. Summary of the Invention

[0004] This invention provides a pixel circuit, its driving method, and a display panel to improve the uniformity of display brightness, thereby enhancing the display effect.

[0005] According to one aspect of the present invention, a pixel circuit is provided, comprising: a driving module, a data writing module, a first initialization module, a storage module, a compensation control module, and a light-emitting module;

[0006] The driving module includes a dual-gate transistor, which is connected between a first power line and a first end of the light-emitting module, and the second end of the light-emitting module is connected to a second power line.

[0007] The data writing module is connected between the first gate of the dual-gate transistor and the data line, and is used to transmit the data voltage output by the data line to the first gate of the dual-gate transistor.

[0008] The storage module is connected to the first gate, the second gate, and the second electrode of the dual-gate transistor, respectively.

[0009] The compensation control module is connected between the first electrode and the second gate of the dual-gate transistor, and is used to control the voltage of the second gate of the dual-gate transistor to compensate for the threshold voltage of the dual-gate transistor, and to control the storage module to store the associated information of the threshold voltage of the dual-gate transistor.

[0010] The first initialization module is used to transmit the first initialization voltage on the first initialization signal line to the first gate of the dual-gate transistor and the first terminal of the light-emitting module. The first initialization module includes a first initialization unit and a second initialization unit. The first terminal of the first initialization unit is connected to the first initialization signal line, the second terminal of the first initialization unit is connected to the first gate, the first terminal of the second initialization unit is connected to the second terminal of the first initialization unit, and the second terminal of the second initialization unit is connected to the first terminal of the light-emitting module.

[0011] Optionally, the first initialization unit includes a first transistor, and the second initialization unit includes a second transistor;

[0012] The gates of the first transistor and the second transistor are both connected to the first scan line. The first terminal of the first transistor is connected to the first initialization signal line. The second terminal of the first transistor is connected to the first terminal of the second transistor. The second terminal of the second transistor is connected to the first end of the light-emitting module. The second end of the light-emitting module is connected to the second power line.

[0013] The second terminal of the first transistor is connected to the first gate of the dual-gate transistor;

[0014] Preferably, the first initialization voltage transmitted on the first initialization signal line is less than the turn-on voltage of the light-emitting module.

[0015] Optionally, the storage module includes a first storage unit and a second storage unit, wherein a first end of the first storage unit is connected to the first gate of the dual-gate transistor, a second end of the first storage unit is connected to the second electrode of the dual-gate transistor, a first end of the second storage unit is connected to the second gate of the dual-gate transistor, and a second end of the second storage unit is connected to the second electrode of the dual-gate transistor.

[0016] Preferably, the first memory cell includes a first capacitor, the second memory cell includes a second capacitor, the first terminal of the first capacitor is connected to the first gate of the dual-gate transistor, the second terminal of the first capacitor is connected to the second terminal of the dual-gate transistor, the first terminal of the second capacitor is connected to the second gate of the dual-gate transistor, and the second terminal of the second capacitor is connected to the second terminal of the dual-gate transistor.

[0017] Optionally, it also includes a light-emitting control module, which is connected between the first power line and the first electrode of the dual-gate transistor;

[0018] Preferably, the light emission control module includes a third transistor, the gate of which is connected to the light emission control signal line, the first terminal of which is connected to the first power supply line, and the second terminal of which is connected to the first terminal of the dual-gate transistor.

[0019] Optionally, the first gate of the dual-gate transistor is a top gate, the second gate is a bottom gate, the data writing module includes a fourth transistor, the compensation control module includes a fifth transistor, and the light-emitting module includes a light-emitting diode;

[0020] The gate of the fourth transistor is connected to the second scan line, the first terminal of the fourth transistor is connected to the data line, the second terminal of the fourth transistor is connected to the first gate, the gate of the fifth transistor is connected to the first scan line, the first terminal of the fifth transistor is connected to the first terminal of the dual-gate transistor, and the second terminal of the fifth transistor is connected to the second gate.

[0021] The first terminal of the light-emitting diode is connected to the second terminal of the dual-gate transistor, and the second terminal of the light-emitting diode is connected to the second power line.

[0022] Optionally, it also includes a second initialization module, which is connected to a second initialization signal line and is used to transmit a second initialization voltage on the second initialization signal line to the second pole of the dual-gate transistor during the data writing phase;

[0023] Preferably, the second initialization module includes a sixth transistor, the gate of the sixth transistor is connected to the third scan line, the first terminal of the sixth transistor is connected to the second initialization signal line, and the second terminal of the sixth transistor is connected to the second terminal of the dual-gate transistor;

[0024] Preferably, the conduction duration of the second initialization module is the same as that of the data writing module;

[0025] Preferably, the first initialization signal line is multiplexed as the second initialization signal line.

[0026] According to another aspect of the present invention, a method for driving a pixel circuit is provided for driving the pixel circuit provided in any embodiment of the present invention.

[0027] The driving method for the pixel circuit includes:

[0028] During the initialization phase, the first initialization module is controlled to transmit the first initialization voltage on the first initialization signal line to the first gate of the dual-gate transistor and the first terminal of the light-emitting module;

[0029] During the compensation phase, the compensation control module controls the voltage of the second gate of the dual-gate transistor to compensate for the threshold voltage of the dual-gate transistor, and controls the storage module to store the associated information of the threshold voltage of the dual-gate transistor.

[0030] During the data writing phase, the data writing module is controlled to transmit the data voltage output from the data line to the first gate of the dual-gate transistor.

[0031] During the light-emitting phase, the driving module is controlled to drive the light-emitting module to emit light.

[0032] Optionally, the pixel circuit further includes a second initialization module, which is connected between the second initialization signal line and the second terminal of the dual-gate transistor; during the data writing phase, the driving method of the pixel circuit further includes:

[0033] The second initialization module is controlled to transmit the second initialization voltage on the second initialization signal line to the second terminal of the dual-gate transistor.

[0034] The pixel circuit further includes a light-emitting control module, which is connected between the first power line and the first electrode of the dual-gate transistor;

[0035] During the initialization phase, the first initialization module, the light emission control module, and the compensation control module are turned on.

[0036] During the compensation phase, the first initialization module, the driving module, and the compensation control module are turned on.

[0037] During the data writing phase, the data writing module is turned on.

[0038] During the light-emitting phase, the light-emitting control module and the driving module are turned on.

[0039] According to another aspect of the present invention, a display panel is provided, including the pixel circuit provided in any embodiment of the present invention.

[0040] The technical solution provided in this invention initializes the first gate and second electrode of a dual-gate transistor (DMT) using a first initialization module, ensuring a voltage difference of 0V between them. A compensation control module controls the potential of the second gate, turning the DMT on. The voltage stored in the storage module discharges through the compensation control module and the first initialization module, adjusting the voltage of the second gate. This gradually shifts the threshold voltage of the DMT forward until it equals the voltage difference between the first gate and the second electrode, at which point the DMT is turned off. The storage module then stores the voltage between the second gate and the second electrode, fixing the threshold voltage and achieving threshold compensation. Since threshold compensation and data writing are performed separately through two independent paths, they do not interfere with each other. By controlling the conduction duration of the compensation control module and the first initialization module, the threshold compensation duration can be controlled, compensating for threshold voltage fluctuations over a wide range. This ensures complete threshold voltage compensation, improves the uniformity of display brightness, and ultimately enhances the display effect. Furthermore, since the data writing module is directly connected to the first gate of the dual-gate transistor, the data voltage can be written to the dual-gate transistor quickly, and the data writing time is not affected by the threshold compensation time, which can shorten the data writing time and is beneficial to achieving high refresh rate and high resolution.

[0041] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0044] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0045] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0046] Figure 4 A control timing waveform diagram of a pixel circuit provided in an embodiment of the present invention;

[0047] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0048] Figure 6 A flowchart illustrating a pixel circuit driving method provided in an embodiment of the present invention;

[0049] Figure 7 A flowchart of another pixel circuit driving method provided in an embodiment of the present invention;

[0050] Figure 8 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0051] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0053] As described in the background section, existing pixel circuits cannot meet the requirements for uniform display brightness. The inventors have discovered that this problem arises because existing pixel circuits typically perform threshold voltage compensation simultaneously with data writing. By controlling the data writing module to conduct, the threshold voltage of the driving module is compensated. This compensation time is limited by the conduction time of the data writing module, resulting in a fixed threshold compensation time. Consequently, the threshold voltage is not fully compensated after data writing is completed, limiting the threshold voltage compensation range. At higher refresh rates, the frame time is compressed further, significantly reducing the threshold compensation time. Furthermore, differences still exist between the driving circuits of different pixels, leading to variations in the driving current generated, which in turn affects the uniformity of display brightness.

[0054] To address the above problems, embodiments of the present invention provide a pixel circuit to improve the uniformity of display brightness. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, with reference to... Figure 1 The pixel circuit provided in this embodiment of the invention includes a driving module 110, a data writing module 120, a first initialization module 130, a storage module 140, a compensation control module 150, and a light-emitting module 160.

[0055] The driving module 110 includes a dual-gate transistor T0, which is connected between a first power line and a first terminal of the light-emitting module 160, and the second terminal of the light-emitting module 160 is connected to a second power line. The data writing module 120 is connected between the first gate G1 of the dual-gate transistor T0 and the data line Data, and is used to transmit the data voltage Vdata output by the data line Data to the first gate G1 of the dual-gate transistor T0. The storage module 140 is connected to the first gate G1, the second gate G2, and the second terminal S of the dual-gate transistor T0, respectively. The compensation control module 150 is connected between the first terminal D and the second gate G2 of the dual-gate transistor T0, and is used to control the voltage of the second gate G2 of the dual-gate transistor T0 to compensate for the threshold voltage of the dual-gate transistor T0, and to control the storage module 140 to store the associated information of the threshold voltage of the dual-gate transistor T0.

[0056] The first initialization module 130 is used to transmit the first initialization voltage Vref1 on the first initialization signal line Rest1 to the first gate G1 of the dual-gate transistor T0 and the first terminal of the light-emitting module 160. The first initialization module 130 includes a first initialization unit 1301 and a second initialization unit 1302. The first terminal of the first initialization unit 1301 is connected to the first initialization signal line Rest1, the second terminal of the first initialization unit 1301 is connected to the first gate G1, the first terminal of the second initialization unit 1302 is connected to the second terminal of the first initialization unit 1301, and the second terminal of the second initialization unit 1302 is connected to the first terminal of the light-emitting module 160.

[0057] Specifically, the driving module 110 and the light-emitting module 160 are connected between a first power line and a second power line. The first power line transmits the first power supply voltage VDD, and the second power line transmits the second power supply voltage VSS. The driving module includes a dual-gate transistor T0, which is typically a vertical dual-gate transistor used as a driving transistor in the pixel circuit to drive the light-emitting module 160 to emit light. The first gate G1 can be a top gate, and the second gate G2 can be a bottom gate. The threshold voltage of the dual-gate transistor T0 is adjusted by setting the voltage of the second gate G2 to achieve threshold voltage compensation. The threshold voltage of the dual-gate transistor T0 is affected by the voltage difference between the second gate G2 and the second electrode S. The larger the voltage difference between the second gate G2 and the second electrode S, the more negative the threshold voltage of the dual-gate transistor T0; the smaller the voltage difference between the second gate G2 and the second electrode S, the more positive the threshold voltage of the dual-gate transistor T0. When the voltage difference between the second gate G2 and the second electrode S remains constant, the threshold voltage of the driving transistor DT remains constant.

[0058] The dual-gate transistor T0 can be either an N-type transistor or a P-type transistor. In each embodiment of the present invention, the dual-gate transistor T0 is described as an N-type transistor.

[0059] In this embodiment, the operation of the pixel circuit includes at least an initialization phase, a compensation phase, and a data writing phase. During the initialization phase, the first initialization module 130 is turned on, and the first initialization voltage Vref1 on the first initialization signal line Rest1 is transmitted to the first gate G1 of the dual-gate transistor T0 through the first initialization unit 1301, and to the first terminal of the light-emitting module 160 through the first initialization unit 1301 and the second initialization unit 1302, thereby initializing the potentials of the first gate G1 of the dual-gate transistor T0 and the first terminal of the light-emitting module 160. During the initialization phase, the light-emitting module 160 can be controlled to not be turned on by configuring the first initialization voltage Vref1. Simultaneously, a fixed high potential voltage is written to the second gate G2 by the compensation control module 150, and the storage module 140 stores the voltage between the second gate G2 and the second terminal S.

[0060] Here, since the potentials of the first gate G1 and the second terminal S of the dual-gate transistor T0 are both the first initialization voltage Vref1, the voltage difference between the first gate G1 and the second terminal S is 0V. At this time, the threshold voltage of the dual-gate transistor T0 is determined by the voltage difference between the second gate G2 and the second terminal S. Since the second gate G2 is at a high potential, the voltage difference V between the second gate G2 and the second terminal S is... G2S Greater than the voltage difference V between the first gate G1 and the second gate S G1S Based on the characteristics of a vertical dual-gate transistor, it can be known that when V... G2S When the voltage is large, the threshold voltage of the dual-gate transistor T0 is negative, therefore the voltage difference V between the first gate G1 and the second gate S is large. G1S When the voltage exceeds the threshold voltage of the dual-gate transistor T0, the dual-gate transistor T0 is turned on.

[0061] During the compensation phase, the high potential stored in the storage module 140 is discharged through the compensation control module 150, the dual-gate transistor T0, and the first initialization module 130, causing the potential of the second gate G2 of the dual-gate transistor T0 to gradually decrease. As the potential of the second gate G2 decreases, the threshold voltage of the dual-gate transistor T0 is forward biased. When the potential of the second gate G2 decreases to the point that the threshold voltage of the dual-gate transistor T0 is 0V, the dual-gate transistor T0 is turned off, and the storage module 140 stores the voltage of the second gate G2. Thus, the threshold compensation of the dual-gate transistor T0 is completed. Here, the information associated with the threshold voltage of the dual-gate transistor stored by the storage module 140 is the voltage difference between the second gate G2 and the second electrode S when the threshold voltage of the dual-gate transistor T0 is 0V.

[0062] During the data writing phase, the control data writing module 120 transmits the data voltage Vdata on the data line Data to the first gate G1 of the dual-gate transistor T0.

[0063] In this embodiment, the compensation phase is controlled by the compensation control module 150. The conduction duration of the compensation phase is determined by the conduction duration of the compensation control module 150 and the first initialization module 130, so that the compensation phase and the data writing phase are not performed simultaneously. This ensures that the data writing phase and the compensation phase do not affect each other, and threshold compensation can be achieved within a large range, which can adapt to high refresh rate applications.

[0064] The technical solution provided in this invention initializes the first gate and second electrode of a dual-gate transistor (DMT) using a first initialization module, ensuring a voltage difference of 0V between them. A compensation control module controls the potential of the second gate, turning the DMT on. The voltage stored in the storage module discharges through the compensation control module and the first initialization module, adjusting the voltage of the second gate. This gradually shifts the threshold voltage of the DMT forward until it equals the voltage difference between the first gate and the second electrode, at which point the DMT is turned off. The storage module then stores the voltage between the second gate and the second electrode, fixing the threshold voltage and achieving threshold compensation. Since threshold compensation and data writing are performed separately through two independent paths, they do not interfere with each other. By controlling the conduction duration of the compensation control module and the first initialization module, the threshold compensation duration can be controlled, compensating for threshold voltage fluctuations over a wide range. This ensures complete threshold voltage compensation, improves the uniformity of display brightness, and ultimately enhances the display effect. Furthermore, since the data writing module is directly connected to the first gate of the dual-gate transistor, the data voltage can be written to the dual-gate transistor quickly, and the data writing time is not affected by the threshold compensation time, which can shorten the data writing time and is beneficial to achieving high refresh rate and high resolution.

[0065] Continue to refer to Figure 1 In this embodiment, the pixel circuit further includes a light-emitting control module 170, which is connected between the first power supply line and the first terminal D of the dual-gate transistor T0. During the initialization phase, by controlling the light-emitting control module 170 to be turned on, the first power supply voltage VDD can be written to the second gate G2 through the compensation control module 150. During the compensation phase, the light-emitting control module 170 is turned off, allowing the voltage of the second gate G2 to discharge through the compensation control module 150 and the first initialization module 130, preventing the first power supply voltage VDD from affecting the discharge process.

[0066] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 2Based on the above technical solutions, the first initialization unit 1301 includes a first transistor T1, and the second initialization unit 1302 includes a second transistor T2; the gate of the first transistor T1 and the gate of the second transistor T2 are both connected to the first scan line; the first terminal of the first transistor T1 is connected to the first initialization signal line Rest1; the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2; the second terminal of the second transistor T2 is connected to the first end of the light-emitting module 160; the second end of the light-emitting module 160 is connected to the second power supply line; the second terminal of the first transistor T1 is connected to the first gate G1 of the dual-gate transistor T0.

[0067] Specifically, the first transistor T1 and the second transistor T2 are connected in series, and the first scan signal line is used to transmit the first scan signal S1. During the initialization phase, the first transistor T1 and the second transistor T2 are turned on in response to the first scan signal S1. The first initialization voltage Vref1 is transmitted through the first transistor T1 to the first gate G1 of the dual-gate transistor T0, and then through the second transistor T2 to the first terminal of the light-emitting module 160. The purpose of setting the second transistor T2 here is to prevent the data voltage Vdata from being connected to the first terminal of the light-emitting module 160 during the data writing phase, thereby affecting the potential of the second terminal S of the dual-gate transistor T0.

[0068] In this embodiment, the first initialization voltage Vref1 transmitted on the first initialization signal line Rest1 is less than the turn-on voltage of the light-emitting module 160, so as to ensure that the light-emitting module 160 will not emit light during the initialization phase.

[0069] Continue to refer to Figure 2 The storage module 140 includes a first storage unit 1401 and a second storage unit 1402. The first end of the first storage unit 1401 is connected to the first gate G1 of the dual-gate transistor T0, and the second end of the first storage unit 1401 is connected to the second terminal S of the dual-gate transistor T0. The first end of the second storage unit 1402 is connected to the second gate G2 of the dual-gate transistor T0, and the second end of the second storage unit 1402 is connected to the second terminal S of the dual-gate transistor T0.

[0070] Specifically, the first storage unit 1401 is used to store the voltage between the first gate G1 and the second terminal S of the dual-gate transistor T0, and the second storage unit 1402 is used to store the voltage between the second gate G2 and the second terminal S of the dual-gate transistor T0. The first storage unit 1401 may include a first capacitor C1, and the second storage unit 1402 may include a second capacitor C2. The first terminal of the first capacitor C1 is connected to the first gate G1 of the dual-gate transistor T0, and the second terminal of the first capacitor C1 is connected to the second terminal S of the dual-gate transistor T0. The first terminal of the second capacitor C2 is connected to the second gate G2 of the dual-gate transistor T0, and the second terminal of the second capacitor C2 is connected to the second terminal S of the dual-gate transistor T0.

[0071] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 3 Based on the above technical solutions, the light-emitting control module 170 includes a third transistor T3, the gate of which is connected to the light-emitting control signal line, the first terminal of which is connected to the first power supply line, and the second terminal of which is connected to the first terminal D of the dual-gate transistor T0. The data writing module 120 includes a fourth transistor T4, the compensation control module 150 includes a fifth transistor T5, and the light-emitting module 160 includes a light-emitting diode D1. The gate of the fourth transistor T4 is connected to the second scan line, the first terminal of which is connected to the data line Data, and the second terminal of which is connected to the first gate G1. The gate of the fifth transistor T5 is connected to the first scan line, the first terminal of which is connected to the first terminal D of the dual-gate transistor T0, and the second terminal of which is connected to the second gate G2. The first terminal of the light-emitting diode D1 is connected to the second terminal S of the dual-gate transistor T0, and the second terminal of the light-emitting diode D1 is connected to the second power supply line.

[0072] In this embodiment, the dual-gate transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all N-type transistors. Figure 4 A control timing waveform diagram for a pixel circuit provided in this embodiment of the invention is applicable to... Figure 3 The pixel circuit shown. Combined with... Figure 3 and Figure 4 The working process of the pixel circuit provided in this embodiment of the invention includes at least: initialization stage t1, compensation stage t2, data writing stage t3, and light emission stage t4.

[0073] During the initialization phase t1, the light-emitting control signal EM transmitted on the light-emitting control signal line is at a high level, the first scan signal S1 transmitted on the first scan line is at a high level, and the second scan signal S2 transmitted on the second scan line is at a low level. Therefore, the first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 are turned on. The first initialization voltage Vref1 is transmitted through the first transistor T1 to the first gate of the dual-gate transistor T0, and through the second transistor T2 to the first terminal of the light-emitting diode (the second terminal S of the dual-gate transistor T0), respectively initializing the potentials of the first gate G1 and the first terminal of the light-emitting diode. The first initialization voltage Vref1 is stored in the first capacitor C1. At this time, the potentials of the first gate G1 and the second terminal S of the dual-gate transistor T0 are equal, i.e., Vref1 = Vref1. G1S =0. At the same time, the first power supply voltage VDD is transmitted to the second gate G2 of the dual-gate transistor T0 through the third transistor T3 and the fifth transistor T5, and stored in the second capacitor C2. The voltage of the second gate G2 is equal to the voltage of the first terminal D.

[0074] During the initialization phase t1, since the potential of the second terminal S of the dual-gate transistor T0 is the first initialization voltage Vref1, and the voltage of the second gate G2 is the first power supply voltage VDD, the voltage difference V between the second gate G2 and the second terminal S is... G2S Greater than the voltage difference V between the first gate G1 and the second gate S G1S The threshold voltage of the dual-gate transistor T0 is negative, therefore the voltage difference V between the first gate G1 and the second gate S is... G1S When the voltage is greater than the threshold voltage of the dual-gate transistor T0, the dual-gate transistor T0 is turned on. Since the voltage at the first terminal of the LED D1 is clamped by the first initialization voltage Vref1, and the first initialization voltage Vref1 is less than the turn-on voltage of the LED D1, the LED D1 does not emit light.

[0075] During compensation phase t2, the light-emitting control signal EM transmitted on the light-emitting control signal line is at a low level, the first scan signal S1 transmitted on the first scan line is at a high level, and the second scan signal S2 transmitted on the second scan line is at a low level. Therefore, the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on. The first power supply voltage VDD stored in the second capacitor C2 is discharged through the fifth transistor T5, the dual-gate transistor T0, the second transistor T2, and the first transistor T1, causing the potential of the second gate G2 of the dual-gate transistor T0 to gradually decrease. As the potential of the second gate G2 decreases, the threshold voltage of the dual-gate transistor T0 is forward biased. When the potential of the second gate G2 decreases to the point that the threshold voltage of the dual-gate transistor T0 is 0V, the dual-gate transistor T0 is turned off. The second capacitor C2 stores the voltage of the second gate G2, thus fixing the threshold voltage of the dual-gate transistor T0 at 0V.

[0076] During the data writing phase t3, the light-emitting control signal EM transmitted on the light-emitting control signal line is at a low level, the first scan signal S1 transmitted on the first scan line is at a low level, and the second scan signal S2 transmitted on the second scan line is at a high level. Therefore, the fourth transistor T4 is turned on. The data voltage Vdata on the data line Data is written to the first gate G1 of the dual-gate transistor T0 through the fourth transistor T4, and the voltage of the first gate G1 is Vdata. Under the coupling effect of the first capacitor C1 and the parasitic capacitance of the light-emitting diode, the potential of the second terminal S of the dual-gate transistor T0 is coupled up, and the voltage increase is (Vdata-Vref1)*[c1 / (c1+c0)], where c1 is the capacitance of the first capacitor C1 and c0 is the capacitance of the parasitic capacitance of the light-emitting diode D1. Due to the potential change of the second terminal S of the dual-gate transistor T0, under the coupling effect of the second capacitor C2, the potential of the second gate G2 is also raised, and the voltage change of the second gate G2 is (Vdata-Vref1)*[c1 / (c1+c0)]. Since the voltage changes at the second terminal S and the second gate G2 of the dual-gate transistor T0 are the same, the voltage difference V between the second terminal S and the second gate G2 of the dual-gate transistor T0 is... G2S It remains unchanged, that is, the threshold voltage of the dual-gate transistor T0 remains unchanged.

[0077] In this embodiment, since the compensation phase t2 and the data writing phase t3 are not performed simultaneously, and the threshold compensation and data writing are implemented through two separate paths, the data writing phase t3 and the compensation phase t2 do not affect each other. By controlling the conduction duration of the compensation control module 150 and the first initialization module 130, the duration of threshold compensation can be controlled, thereby compensating for threshold voltage fluctuations over a large range, ensuring that the threshold voltage is fully compensated, improving the uniformity of display brightness, and thus improving the display effect.

[0078] During the light-emitting stage t4, the light-emitting control signal EM transmitted on the light-emitting control signal line is at a high level, the first scan signal S1 transmitted on the first scan line is at a low level, and the second scan signal S2 transmitted on the second scan line is at a low level. Therefore, the third transistor T3 and the dual-gate transistor T0 are turned on. The dual-gate transistor T0 generates a driving current in response to the voltage between the first gate G1 and the second gate S, and provides this driving current to the light-emitting diode D1 to drive the light-emitting diode D1 to emit light. Here, the voltage at the second gate S of the dual-gate transistor T0 increases as the voltage across the light-emitting diode D1 increases. Under the coupling effect of the first capacitor C1 and the second capacitor C2, V G1S and V G2S All remain unchanged, therefore the threshold voltage of the dual-gate transistor T0 remains 0V. In this embodiment, the drive current I generated by the dual-gate transistor T0 can be expressed as:

[0079]

[0080] Where μ is the electron mobility of the dual-gate transistor T0, Cox is the channel capacitance per unit area of ​​the dual-gate transistor T0, W / L is the width-to-length ratio of the dual-gate transistor T0, and Vth is the threshold voltage of the dual-gate transistor T0.

[0081] As shown in the above formula, the driving current of LED D1 is related to the data voltage Vdata and the first initialization voltage Vref1. Since the threshold voltage Vth of the dual-gate transistor T0 is 0V, it will not affect the magnitude of the luminous current. Furthermore, the driving current is not affected by the second power supply voltage VSS, thus compensating for the IR drop of the second power supply voltage VSS and the aging of LED D1.

[0082] In this embodiment, the light-emitting diode D1 can be a light-emitting device such as an LED, OLED, or Micro-LED.

[0083] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 5 Optionally, based on the above technical solutions, the pixel circuit further includes a second initialization module 180, which is connected to the second initialization signal line Rest2 and is used to transmit the second initialization voltage Vref2 on the second initialization signal line Rest2 to the second pole S of the dual-gate transistor T0 during the data writing stage.

[0084] The second initialization module 180 includes a sixth transistor T6, the gate of the sixth transistor T6 is connected to the third scan line S3, the first terminal of the sixth transistor T6 is connected to the second initialization signal line Rest2, and the second terminal of the sixth transistor T6 is connected to the second terminal S of the dual-gate transistor T0.

[0085] In this embodiment, when writing the data voltage Vdata to the first gate G1 of the dual-gate transistor T0, the sixth transistor T6 (second initialization module 180) transmits the second initialization voltage Vref2 on the second initialization signal line Rest2 to the second terminal S of the dual-gate transistor T0 to clamp the potential of the second terminal S. Therefore, the third scan line can be the same as the signal transmitted on the second scan line, that is, the second scan line is multiplexed as the third scan line, making the conduction time of the fourth transistor T4 and the sixth transistor T6 the same. In addition, during the initialization phase, the potential of the second terminal S of the dual-gate transistor T0 is Vref1. In order to keep the potential of the second terminal S unchanged, in this embodiment, the second initialization voltage Vref2 is equal to the first initialization voltage Vref1, that is, the first initialization signal line Rest1 is multiplexed as the second initialization signal line Rest2, which can save the number of signal lines and is beneficial to achieving a high PPI of the display.

[0086] Specifically, Figure 5 The pixel circuit shown is also applicable to Figure 4 The driving timing shown illustrates the specific working processes of the initialization phase t1 and the compensation phase t2. Figure 3 The operation of the pixel circuit shown is the same, and will not be described again here.

[0087] During the data writing phase t3, the light-emitting control signal EM transmitted on the light-emitting control signal line is at a low level, the first scan signal S1 transmitted on the first scan line is at a low level, and the second scan signal S2 transmitted on the second scan line is at a high level. Therefore, the fourth transistor T4 and the sixth transistor T6 are turned on. The data voltage Vdata on the data line Data is written to the first gate G1 of the dual-gate transistor T0 through the fourth transistor T4, and the voltage of the first gate G1 is Vdata. The second initialization voltage Vref2 is transmitted to the second terminal S of the dual-gate transistor T0 through the sixth transistor T6. Here, the second initialization voltage Vref2 is equal to the first initialization voltage Vref1, so the voltage of the second terminal S of the dual-gate transistor T0 is Vref1. G2S The threshold voltage of the dual-gate transistor T0 remains unchanged.

[0088] During the light-emitting stage t4, the light-emitting control signal EM transmitted on the light-emitting control signal line is at a high level, the first scan signal S1 transmitted on the first scan line is at a low level, and the second scan signal S2 transmitted on the second scan line is at a low level. Therefore, the third transistor T3 and the dual-gate transistor T0 are turned on. The dual-gate transistor T0 generates a driving current in response to the voltage between the first gate G1 and the second gate S, and provides this driving current to the light-emitting diode D1 to drive the light-emitting diode D1 to emit light. Here, the voltage at the second gate S of the dual-gate transistor T0 increases as the voltage across the light-emitting diode D1 increases. Under the coupling effect of the first capacitor C1 and the second capacitor C2, V G1S and V G2S All remain unchanged, therefore the threshold voltage of the dual-gate transistor T0 remains 0V. In this embodiment, the drive current I generated by the dual-gate transistor T0 can be expressed as:

[0089]

[0090] As can be seen from the above formula, the driving current is still independent of the threshold voltage Vth of the dual-gate transistor T0 and the second power supply voltage VSS. It can compensate for the display abnormalities caused by the unevenness of the threshold voltage Vth of the dual-gate transistor, the IR drop of the second power supply voltage VSS, and the aging of the light-emitting diode D1.

[0091] Optionally, embodiments of the present invention also provide a driving method for a pixel circuit, applicable to the pixel circuits provided in any of the above embodiments. (In conjunction with...) Figure 1 The pixel circuit provided in this embodiment of the invention includes a driving module 110, a data writing module 120, a first initialization module 130, a storage module 140, a compensation control module 150, and a light-emitting module 160. The driving module 110 includes a dual-gate transistor T0, which is connected between a first power line and a first terminal of the light-emitting module 160, and the second terminal of the light-emitting module 160 is connected to a second power line. The data writing module 120 is connected between the first gate G1 of the dual-gate transistor T0 and a data line Data. The storage module 140 is connected to the first gate G1, the second gate G2, and the second terminal S of the dual-gate transistor T0, respectively. The compensation control module 150 is connected between the first terminal D and the second gate G2 of the dual-gate transistor T0.

[0092] The first initialization module 130 includes a first initialization unit 1301 and a second initialization unit 1302. The first terminal of the first initialization unit 1301 is connected to the first initialization signal line Rest1, the second terminal of the first initialization unit 1301 is connected to the first gate G1, the first terminal of the second initialization unit 1302 is connected to the second terminal of the first initialization unit 1301, and the second terminal of the second initialization unit 1302 is connected to the first terminal of the light-emitting module 160.

[0093] Figure 6 A flowchart of a pixel circuit driving method provided in an embodiment of the present invention is shown below. Figure 6 The driving method includes:

[0094] S110. During the initialization phase, the first initialization module is controlled to transmit the first initialization voltage on the first initialization signal line to the first gate of the dual-gate transistor and the first terminal of the light-emitting module.

[0095] S120. During the compensation phase, the compensation control module controls the voltage of the second gate of the dual-gate transistor to compensate for the threshold voltage of the dual-gate transistor, and controls the storage module to store the associated information of the threshold voltage of the dual-gate transistor.

[0096] S130. During the data writing stage, the control data writing module transmits the data voltage output from the data line to the first gate of the dual-gate transistor.

[0097] S140. During the light-emitting stage, the control drive module drives the light-emitting module to emit light.

[0098] The technical solution provided in this invention initializes the first gate and second electrode of a dual-gate transistor (DMT) using a first initialization module, ensuring a voltage difference of 0V between them. A compensation control module controls the potential of the second gate, turning the DMT on. The voltage stored in the storage module discharges through the compensation control module and the first initialization module, adjusting the voltage of the second gate. This gradually shifts the threshold voltage of the DMT forward until it equals the voltage difference between the first gate and the second electrode, at which point the DMT is turned off. The storage module then stores the voltage between the second gate and the second electrode, fixing the threshold voltage and achieving threshold compensation. Since threshold compensation and data writing are performed separately through two independent paths, they do not interfere with each other. By controlling the conduction duration of the compensation control module and the first initialization module, the threshold compensation duration can be controlled, compensating for threshold voltage fluctuations over a wide range. This ensures complete threshold voltage compensation, improves the uniformity of display brightness, and ultimately enhances the display effect. Furthermore, since the data writing module is directly connected to the first gate of the dual-gate transistor, the data voltage can be written to the dual-gate transistor quickly, and the data writing time is not affected by the threshold compensation time, which can shorten the data writing time and is beneficial to achieving high refresh rate and high resolution.

[0099] Combination Figure 5 The pixel circuit also includes a second initialization module 180, which is connected to the second initialization signal line Rest2. Figure 7A flowchart of another pixel circuit driving method provided in an embodiment of the present invention is shown below. Figure 7 The driving method for this pixel circuit includes:

[0100] S110. During the initialization phase, the first initialization module is controlled to transmit the first initialization voltage on the first initialization signal line to the first gate of the dual-gate transistor and the first terminal of the light-emitting module.

[0101] S120. During the compensation phase, the compensation control module controls the voltage of the second gate of the dual-gate transistor to compensate for the threshold voltage of the dual-gate transistor, and controls the storage module to store the associated information of the threshold voltage of the dual-gate transistor.

[0102] S130. During the data writing phase, the control data writing module transmits the data voltage output from the data line to the first gate of the dual-gate transistor, and the control second initialization module transmits the second initialization voltage on the second initialization signal line to the second terminal of the dual-gate transistor.

[0103] S140. During the light-emitting stage, the control drive module drives the light-emitting module to emit light.

[0104] The specific working principle of the above driving method can be found in the above embodiments. Figure 5 The pixel circuit shown has the same beneficial effects and will not be repeated here.

[0105] Optionally, embodiments of the present invention also provide a display panel, which includes the pixel circuit provided in any embodiment of the present invention. Figure 8 This is a schematic diagram of a display panel provided in an embodiment of the present invention. The display panel can be... Figure 8 The mobile phone panel shown can also be applied to tablets, smartwatches, wearable devices, as well as in-vehicle displays, camera displays, television and computer screens, and all other display-related electronic products. Since this display panel includes the pixel circuitry provided in any embodiment of the present invention, the display panel provided in the embodiments of the present invention also possesses the beneficial effects described in any embodiment of the present invention.

[0106] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0107] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pixel circuit, characterized in that, The application relates to a display module and a display device. The application relates to a display module and a display device. The application relates to a display module and a display device. The application relates to a display module and a display device. The application relates to a display module and a display device. The application relates to a display module and a display device. The application relates to a display module and a display device. The application relates to a display module and a display device. The application relates to a display module and a display device. The application relates to a display module and a display device. The application relates to a display module and a display device. The application relates to a display module and a display device. The application relates to a display module and a display device. The application relates to a display module and a display device. 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3. The pixel circuit of claim 2, wherein, The first storage unit comprises a first capacitor, the second storage unit comprises a second capacitor, a first electrode of the first capacitor is connected with the first gate of the double-gate transistor, a second electrode of the first capacitor is connected with the second electrode of the double-gate transistor, a first electrode of the second capacitor is connected with the second gate of the double-gate transistor, and a second electrode of the second capacitor is connected with the second electrode of the double-gate transistor.

4. The pixel circuit of claim 1, wherein, The pixel circuit further comprises a light-emitting control module, the light-emitting control module is connected between the first power supply line and the first electrode of the double-gate transistor.

5. The pixel circuit of claim 4, wherein, The light-emitting control module comprises a third transistor, a gate of the third transistor is connected with a light-emitting control signal line, a first electrode of the third transistor is connected with the first power supply line, and a second electrode of the third transistor is connected with the first electrode of the double-gate transistor.

6. The pixel circuit of claim 1, wherein, The data writing module comprises a fourth transistor, the compensation control module comprises a fifth transistor, and the light-emitting module comprises a light-emitting diode. A gate of the fourth transistor is connected with a second scanning line, a first electrode of the fourth transistor is connected with the data line, a second electrode of the fourth transistor is connected with the first gate, a gate of the fifth transistor is connected with a first scanning line, a first electrode of the fifth transistor is connected with the first electrode of the double-gate transistor, and a second electrode of the fifth transistor is connected with the second gate. A first electrode of the light-emitting diode is connected with the second electrode of the double-gate transistor, and a second electrode of the light-emitting diode is connected with the second power supply line.

7. The pixel circuit according to any one of claims 1 to 6, characterized in that, The pixel circuit further comprises a second initialization module, the second initialization module is connected with a second initialization signal line, and the second initialization module is configured to transmit a second initialization voltage on the second initialization signal line to the second electrode of the double-gate transistor in a data writing stage.

8. The pixel circuit of claim 7, wherein, The second initialization module comprises a sixth transistor, a gate of the sixth transistor is connected with a third scanning line, a first electrode of the sixth transistor is connected with the second initialization signal line, and a second electrode of the sixth transistor is connected with the second electrode of the double-gate transistor.

9. The pixel circuit of claim 8, wherein, The second initialization module has the same on duration as the data writing module.

10. The pixel circuit of claim 9, wherein, The first initialization signal line is multiplexed as the second initialization signal line.

11. A driving method of a pixel circuit, characterized by, A pixel circuit as claimed in any one of claims 1-10 is driven. A driving method of the pixel circuit comprises: In an initialization stage, the first initialization module is controlled to transmit a first initialization voltage on the first initialization signal line to the first gate of the double-gate transistor and a first end of the light-emitting module. In the compensation stage, the compensation control module is controlled to control the voltage of the second gate of the double-gate transistor to compensate the threshold voltage of the double-gate transistor, and the storage module is controlled to store the associated information of the threshold voltage of the double-gate transistor; In the data writing stage, the data writing module is controlled to transmit the data voltage output by the data line to the first gate of the double-gate transistor; In the light emitting stage, the driving module is controlled to drive the light emitting module to emit light.

12. The driving method of the pixel circuit according to claim 11, wherein The pixel circuit further comprises a second initialization module connected between the second initialization signal line and the second electrode of the double-gate transistor; In the data writing stage, the driving method of the pixel circuit further comprises: The second initialization module is controlled to transmit the second initialization voltage on the second initialization signal line to the second electrode of the double-gate transistor.

13. The driving method of the pixel circuit according to claim 12, wherein The pixel circuit further comprises a light emitting control module connected between the first power supply line and the first electrode of the double-gate transistor; In the initialization stage, the first initialization module, the light emitting control module and the compensation control module are controlled to be turned on; In the compensation stage, the first initialization module, the driving module and the compensation control module are controlled to be turned on; In the data writing stage, the data writing module is controlled to be turned on; In the light emitting stage, the light emitting control module and the driving module are controlled to be turned on.

14. A display panel, characterized by The pixel circuit comprises any one of the pixel circuits according to claims 1-10.

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