Charge pump circuit

Abstract

This disclosure provides a charge pump circuit. The charge pump circuit according to this disclosure includes one or more cascaded boost units and output units having the same structure. Each boost unit has a dual-branch structure with top and bottom symmetry and connected to two sets of four-phase clock signals with opposite clock phases. By adjusting the phase relationship of the four-phase clocks, the rise time of the gate voltage of the transfer transistor can be delayed by advancing the falling edge of the driving clock of the secondary capacitor and delaying its rising edge. This ensures that the transfer transistor is in the off state at the moment of high-low phase switching, thereby avoiding the problem of reduced charge transfer efficiency caused by reverse charge flow between the input and output nodes of the boost unit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a charge pump circuit for boosting an input voltage. Background Technology

[0002] A charge pump circuit is a circuit that generates higher voltage by utilizing the accumulation and transfer of charge in a capacitor. The charge storage characteristic of a capacitor is that if the voltage level at one end of the capacitor changes, the voltage level at the other end will also change accordingly to maintain a constant stored charge. Therefore, the voltage across the capacitor can be changed by periodically charging and discharging it. Using a clock signal to charge and discharge the capacitor in a charge pump circuit is well known in the art.

[0003] Charge pump circuits can generate positive or negative voltages with amplitudes higher than the input voltage, and are therefore widely used in semiconductor devices such as non-volatile memory, liquid crystal driver integrated circuits (ICs), and DC-DC converters. For example, in non-volatile memory, charge pump circuits can provide positive voltages higher than the supply voltage, even up to 10V or 20V or higher, or negative voltages below 0V, to perform various operations on memory cells, such as read, program, erase, or write operations.

[0004] However, as the supply voltage decreases, the threshold voltage loss and transistor substrate bias effect of the charge transport transistor become increasingly severe, leading to a sharp decline in the charge transport efficiency of existing charge pump circuits. Therefore, a high-efficiency charge pump circuit suitable for low supply voltages is needed. Summary of the Invention

[0005] The information disclosed above in the "Background Art" section is only for understanding the background of the inventive concept and may therefore contain information that does not constitute prior art.

[0006] To address the aforementioned problems in the prior art, this disclosure proposes a charge pump circuit for boosting input voltage.

[0007] According to one aspect of the present disclosure, a charge pump circuit is provided, including: first to K boost units configured to be serially connected in sequence, where K is a natural number greater than or equal to 1, and each of the first to K boost units includes: a first switching element connected between a first input node and a first output node; a second switching element connected between a second input node and a second output node; a first capacitor connected between the first output node and a first clock node; a second capacitor connected between the second output node and a second clock node; a third capacitor connected between a third clock node and a first internal node; a fourth capacitor connected between a fourth clock node and a second internal node; a third switching element connected between the first input node and the second internal node; a fourth switching element connected between the second input node and the first internal node; a first inverter whose input terminal is connected to the first output node and outputs a first switching signal for controlling the on and off of the first switching element and the third switching element; and a second inverter whose input terminal is connected to the second output node and outputs a second switching signal for controlling the on and off of the second switching element and the fourth switching element, where the phase of the first clock signal is opposite to the phase of the second clock signal, the phase of the third clock signal is opposite to the phase of the fourth clock signal, and the phase of the first clock signal is the same as the phase of the third clock signal, where the first clock nodes of each of the odd-numbered boost units among the first to K boost units are commonly connected to the first clock signal, the second clock nodes of each of the odd-numbered boost units among the first to K boost units are commonly connected to the second clock signal, the third clock nodes of each of the odd-numbered boost units among the first to K boost units are commonly connected to the fourth clock signal, and the fourth clock nodes of each of the odd-numbered boost units among the first to K boost units are commonly connected to the third clock signal, where the first clock nodes of each of the even-numbered boost units among the first to K boost units are commonly connected to the second clock signal, the second clock nodes of each of the even-numbered boost units among the first to K boost units are commonly connected to the first clock signal, the third clock nodes of each of the even-numbered boost units among the first to K boost units are commonly connected to the third clock signal, the fourth clock nodes of each of the even-numbered boost units among the first to K boost units are commonly connected to the fourth clock signal, where the first input node and the second input node of the first boost unit are commonly connected to an input terminal for receiving an input voltage, and where, when 1 < i ≤ K, the first input node of the i-th boost unit is connected to the first output node of the i-1-th boost unit, and the second input node of the i-th boost unit is connected to the second output node of the i-1-th boost unit;And an output unit, connected between the Kth boost unit and the output terminal, is configured to output the higher of the voltage of the first output node and the voltage of the second output node of the Kth boost unit to the output terminal.

[0008] The charge pump circuit disclosed herein employs a symmetrical dual-branch structure, which effectively improves the charge transfer efficiency and boost capability of the charge pump circuit, reduces the operating power consumption of the charge pump circuit, and thus makes it suitable for lower power supply voltages. Furthermore, by connecting the dual-branch structure to two sets of four-phase clock signals with opposite clock phases and adjusting the phase relationship of the four-phase clocks, the problem of reduced charge transfer efficiency caused by reverse charge flow between the input and output nodes of the boost unit can be avoided, thereby further improving the charge transfer efficiency and boost capability of the charge pump circuit.

[0009] However, the effects of this disclosure are not limited to those described above, and various extensions can be made without departing from the spirit and scope of this disclosure. It should be understood that the general description above and the detailed description below are exemplary and illustrative, and not intended to limit the scope of this disclosure. Attached Figure Description

[0010] The accompanying drawings are provided to offer a further understanding of this disclosure. The drawings illustrate exemplary embodiments of this disclosure and, together with the description, serve to explain the concept of this disclosure.

[0011] Figure 1 This is a schematic block diagram illustrating a charge pump circuit for boosting a positive input voltage according to an embodiment of the present disclosure.

[0012] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 The circuit diagram of the charge pump circuit is shown.

[0013] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 1 The circuit diagram of the i-th boost unit of the charge pump circuit shown is shown.

[0014] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 1 The circuit diagram of the output unit of the charge pump circuit shown.

[0015] Figure 5 This is a circuit diagram illustrating a first-stage charge pump circuit for boosting a positive input voltage according to an embodiment of the present disclosure.

[0016] Figure 6 This is a schematic diagram showing the signal waveforms of each node of a first-stage charge pump circuit for boosting a positive input voltage according to an embodiment of the present disclosure.

[0017] Figure 7 This is a circuit diagram illustrating an i-th boost unit that uses a transistor gate capacitor to implement a capacitor according to an embodiment of the present disclosure.

[0018] Figure 8 A circuit diagram is shown of a charge pump circuit for boosting a positive input voltage using transistor gate capacitors to implement capacitors in each boost unit, according to an embodiment of the present disclosure.

[0019] Figure 9 This is a circuit diagram illustrating a first-stage charge pump circuit for boosting a positive input voltage, wherein a capacitor is implemented using a transistor gate capacitor according to an embodiment of the present disclosure.

[0020] Figure 10 This is a graph showing the capacitance-voltage characteristic of the gate capacitance of an NMOS transistor.

[0021] Figure 11 This is a graph showing the capacitance-voltage characteristics of NMOS transistors at different thresholds.

[0022] Figure 12 This is a circuit diagram illustrating a charge pump circuit driven using a four-phase clock according to an embodiment of the present disclosure.

[0023] Figure 13 It is shown Figure 12 The diagram shows a waveform representation of an example of a four-phase clock used in the charge pump circuit.

[0024] Figure 14 It is shown Figure 12 The waveform diagram shows another example of a four-phase clock used in the charge pump circuit shown. Detailed Implementation

[0025] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough and complete understanding of the various exemplary embodiments of this disclosure. As used herein, the term "implementation" should be understood as a non-limiting example of an apparatus or method employing one or more of the concepts disclosed herein. However, it should be noted that various embodiments may be implemented without these specific details or with one or more equivalent configurations. Furthermore, the various embodiments may be different, but not necessarily exclusive. For example, specific configurations and features of other embodiments may be used or implemented in some embodiments without departing from the concept of this disclosure.

[0026] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the scope of this disclosure. Unless the context clearly indicates otherwise, the singular terms “a” and “the” as used herein should also include the plural forms. Furthermore, the terms “comprising” and / or “including” as used herein are intended to indicate the presence of the stated features, quantities, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, and / or combinations thereof. It should also be noted that the terms “substantially,” “about,” and other similar terms used herein should be understood as indicating similarity rather than degree, and therefore can take into account inherent deviations in measurements, calculations, and / or provided numerical values ​​that are generally recognized by those skilled in the art.

[0027] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements are not limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element, and vice versa.

[0028] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0029] In this document, some embodiments are illustrated in the accompanying drawings in the form of functional blocks, units, and / or modules. Those skilled in the art will understand that these functional blocks, units, and / or modules can be physically implemented by electronic circuits, such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., and they can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Furthermore, without departing from the scope of this disclosure, each functional block, unit, and / or module of some embodiments can be physically further divided into two or more interactive and discrete functional blocks, units, and / or modules. Moreover, without departing from the scope of this disclosure, the functional blocks, units, and / or modules of some embodiments can be physically combined into more complex functional blocks, units, and / or modules.

[0030] The charge pump circuits according to various embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0031] Figure 1 A schematic block diagram of a charge pump circuit 10 for boosting a positive input voltage according to an embodiment of the present disclosure is shown. Figure 2 Embodiments according to this disclosure are shown. Figure 1The circuit diagram of charge pump circuit 10 is shown.

[0032] like Figure 1 and Figure 2 As shown, according to an embodiment of this disclosure, the charge pump circuit 10 can be a charge pump circuit that boosts a positive input voltage. For example... Figure 1 and Figure 2 As shown, according to an embodiment of this disclosure, the charge pump circuit 10 may have an input terminal Nin for receiving an input voltage Vin and an output terminal Nout for providing an output voltage Vout. According to an embodiment of this disclosure, the input voltage Vin may be a positive voltage, i.e., a voltage higher than the ground voltage Vss (0V), and its amplitude may be the same as or different from the amplitude of the power supply voltage Vcc. Specifically, according to an embodiment of this disclosure, the amplitude of the input voltage Vin may be greater than the amplitude of the power supply voltage Vcc. According to an embodiment of this disclosure, the output voltage Vout may be obtained by boosting the input voltage Vin through the charge pump circuit 10, i.e., increasing the amplitude of the input voltage Vin. In other words, the amplitude of the output voltage Vout is greater than the amplitude of the input voltage Vin.

[0033] like Figure 1 and Figure 2 As shown, according to an embodiment of this disclosure, the charge pump circuit 10 may include K boost units, namely the first to the Kth boost units 1011 to 1012. K , where K is a natural number greater than or equal to 1. For ease of description, Figure 2 Only the first to third boost units 1011 to 1013 are shown, but those skilled in the art can conceive of the circuit structure and connection method of each boost unit after the third boost unit 1013 based on the teachings of this disclosure.

[0034] like Figure 1 and Figure 2 As shown, according to embodiments of this disclosure, the first to Kth boost units 1011 to 101 K They can be connected in series. According to embodiments of this disclosure, the first to the Kth boost units 1011 to 101... K They can have the same circuit structure as each other, which will be combined below. Figure 3 A more detailed description would follow. Additionally, as... Figure 1 and Figure 2 As shown, according to an embodiment of this disclosure, the K boost units 1011 to 101 in the charge pump circuit 10 can be driven by a pair of clock signals with opposite phases, namely a first clock signal CLKA and a second clock signal CLKB with a phase opposite to the first clock signal CLKA. K .

[0035] like Figure 1 and Figure 2 As shown, the charge pump circuit 10 may further include an output unit 102, which is connected between the Kth boosting unit 101 K and the output terminal Nout, and is configured to provide an output voltage Vout at the output terminal Nout. The output unit 102 will be described in more detail below in conjunction with Figure 4 this.

[0036] Next, in conjunction with Figure 3 this, Figure 1 and Figure 2 the boosting units 1011 to 101 of the charge pump circuit 10 shown in K will be described in more detail. Figure 3 FIG. shows the Figure 1 circuit diagram of the ith boosting unit 101 of the charge pump circuit 10 shown in i accordance with an embodiment of the present disclosure, where 1 ≤ i ≤ K.

[0037] As Figure 3 shown, according to an embodiment of the present disclosure, the ith boosting unit 101 i may adopt a double-branch structure that is symmetric up and down but has opposite clock phases, including an upper branch and a lower branch. As Figure 3 shown, according to an embodiment of the present disclosure, the upper branch of the ith boosting unit 101 i has a first input node NI1 i and a first output node NO1 i , and the lower branch of the ith boosting unit 101 i has a second input node NI2 i and a second output node NO2 i . In addition, as Figure 3 shown, according to an embodiment of the present disclosure, the ith boosting unit 101 i may further have a first clock node NC1 i and a second clock node NC2 i for receiving the first and second clock signals CLKA and CLKB.

[0038] Referring back to Figure 1 and Figure 2 , according to an embodiment of the present disclosure, the first input node NI11 and the second input node NI21 of the first boosting unit 101 are commonly connected to the input terminal Nin for receiving the input voltage Vin. In addition, according to an embodiment of the present disclosure, when 1 < i ≤ K, the first input node NI1 i of the ith boosting unit 101 i and the second input node NI2 i are respectively connected to the first output node NO1 of the i - 1th boosting unit i-1Second output node NO2 i-1 Furthermore, according to embodiments of this disclosure, the Kth boost unit 101 K First output node NO1 K Second output node NO2 K The first input node NI1 of the output unit 102 is connected respectively. O Second input node NI2 O .

[0039] like Figure 3 As shown, according to an embodiment of this disclosure, the i-th boost unit 101 i The upper branch may include: a first switching element M1 i It is connected to the first input node NI1 i and the first output node NO1 i Between; First capacitor C1 i It is connected to the first output node NO1 i and the first clock node NC1 i Between; the third capacitor C3 i It is connected to the second clock node NC2 i and the first internal node NP1 i Between; the third switching element M3 i Connected to the first input node NI1 i and the second internal node NP2 in the lower branch i Between; and the first inverter S1 i Its input is connected to the first output node NO1. i And the output is used to control the first switching element M1 i and the third switching element M3 i The first switching signal SW1 for turning on and off i .

[0040] Similarly, such as Figure 3 As shown, according to an embodiment of this disclosure, the i-th boost unit 101 i The lower branch may include: a second switching element M2 i It is connected to the second input node NI2 i Second output node NO2 i Between; the second capacitor C2 i It is connected to the second output node NO2 i Second clock node NC2 i Between; fourth capacitor C4 i It is connected to the first clock node NC1 i Second internal node NP2 i Between; the fourth switching element M4i It is connected to the second input node NI2 i and the first internal node NP1 in the upper branch i Between; and the second inverter S2 i Its input is connected to the second output node NO2. i And the output is used to control the second switching element M2 i and the fourth switching element M2 i The second switch signal SW2 that turns on and off i .

[0041] Return to reference Figure 1 and Figure 2 According to embodiments of this disclosure, the first to the Kth boost units 1011 to 101 K Odd-numbered boost unit 101 2j-1 (where j is a natural number greater than 0, and j≤[(K+1) / 2], where [] represents the floor function) The first clock node NC1 of each of the following is a given clock node. 2j-1 They are all connected to the first clock signal CLKA, and the first to the Kth boost units 1011 to 101 K Odd-numbered boost unit 101 2j-1 The second clock node NC2 of each 2j-1 They are all connected to the second clock signal CLKB. Furthermore, as... Figure 1 and Figure 2 As shown, according to embodiments of this disclosure, the first to Kth boost units 1011 to 101 K Even-numbered boost unit 101 2j The first clock node NC1 of each 2j They are all connected to the second clock signal CLKB, and the first to the Kth boost units 1011 to 101 K Even-numbered boost unit 101 2j The second clock node NC2 of each 2j They are all connected to the first clock signal CLKA.

[0042] Those skilled in the art should recognize that, Figure 1 and Figure 3 In the middle, the i-th boost unit 101 i It is shown as its first clock node NC1 i Connected to the second clock signal CLKB and its second clock node NC2 i Connected to the first clock signal CLKA, therefore the i-th boost unit 101 i It is an even-numbered boost unit. However, this is merely an example used for ease of description; the i-th boost unit 101i It can also be an odd-numbered boost unit, in which case its first clock node NC1 i Connected to the first clock signal CLKA and its second clock node NC2 i Connect to the second clock signal CLKB.

[0043] Similarly, those skilled in the art should recognize that, Figure 1 In the middle, the Kth boost unit 101 K It is shown as its first clock node NC1 K Connected to the first clock signal CLKA and its second clock node NC2 K Connected to the second clock signal CLKB, therefore the Kth boost unit 101 K It is an odd-numbered boost unit. However, this is merely an example for ease of description; the Kth boost unit is 101. K It can also be an even-numbered boost unit, in which case its first clock node NC1 K Connected to the second clock signal CLKB and its second clock node NC2 K Connect to the first clock signal CLKA.

[0044] like Figure 3 As shown, according to an embodiment of this disclosure, the first switching element M1 i and the third switching element M3 i These can be NMOS transistors, whose gates are connected to the first inverter S1. i The output terminal. Furthermore, such as... Figure 3 As shown, according to an embodiment of this disclosure, the second switching element M2 i and the fourth switching element M4 i Alternatively, they can be NMOS transistors, whose gates are connected to the second inverter S2. i The output terminal.

[0045] exist Figure 3 In the middle, the i-th boost unit 101 i The first switching element M1 i Second switching element M2 i It can be used to connect the first input node NI1 i Second input node NI2 i The voltages are respectively transmitted to the first output node NO1 i Second output node NO2 i Therefore, it is used in this paper to implement the first switching element M1. i Second switching element M2 i NMOS transistors can also be referred to together as "transmission transistors".

[0046] exist Figure 3 In the middle, the i-th boost unit 101 i The first capacitor C1 i Second capacitor C2 i It can be used to perform a boost function, and therefore can also be referred to herein as the "main capacitor". According to embodiments of this disclosure, the i-th boost unit 101 i The first capacitor C1 i Second capacitor C2 i They can have the same capacitance value.

[0047] exist Figure 3 In the middle, the i-th boost unit 101 i The third capacitor C3 i and the fourth capacitor C4 i It can be used to ensure the i-th boost unit 101 i The first switching element M1 i Second switching element M2 i Completely on or off, therefore they can also be referred to herein as the "secondary capacitor". According to an embodiment of this disclosure, the i-th boost unit 101 i The third capacitor C3 i and the fourth capacitor C4 i They can have the same capacitance value. Furthermore, according to embodiments of this disclosure, in order to improve the driving capability of the charge pump circuit and reduce area overhead, the i-th boost unit 101... i The third capacitor C3 i and the fourth capacitor C4 i The capacitance value can be less than or equal to that of the first capacitor C1. i Second capacitor C2 i The capacitance value.

[0048] In addition, Figure 3 In the middle, the i-th boost unit 101 i The third switching element M3 i and the fourth switching element M4 i It can be used to charge the secondary capacitor, and therefore is used in this paper to implement the third switching element M3. i and the fourth switching element M4 i NMOS transistors can also be referred to as "charging transistors".

[0049] like Figure 3 As shown, according to an embodiment of this disclosure, the i-th boost unit 101 i The first inverter S1 in i It may include an NMOS transistor SN1 iand a PMOS transistor SP1 i NMOS transistor SN1 i and PMOS transistor SP1 i The gate is connected to the first output node NO1 i NMOS transistor SN1 i and PMOS transistor SP1 i The drain is connected to form the first switching element M1 i and the third switching element M3 i The gate of the NMOS transistor, NMOS transistor SN1 i The source is connected to the first input node NI1 i And PMOS transistor SP1 i The source and (e.g., NW) substrate (not shown) are connected to the first internal node NP1. i .

[0050] Similarly, such as Figure 3 As shown, according to an embodiment of this disclosure, the i-th boost unit 101 i The second inverter S2 in i It may include an NMOS transistor SN2 i and a PMOS transistor SP2 i Among them, NMOS transistor SN2 i and PMOS transistor SP2 i The gate is connected to the second output node NO2. i NMOS transistor SN2 i and PMOS transistor SP2 i The drain is connected to form the second switching element M2. i and the fourth switching element M4 i The gate of the NMOS transistor, NMOS transistor SN2 i The source is connected to the second input node NI2. i And PMOS transistor SP2 i The source and (e.g., NW) substrate (not shown) are connected to the second internal node NP2. i .

[0051] although Figure 3 Not shown in the diagram, but according to embodiments of this disclosure, the i-th boost unit 101 i The substrate of all NMOS transistors (e.g., PW) can be connected to ground voltage VSS or power supply voltage VCC.

[0052] As mentioned above, refer to Figure 3 i-th boost unit 101 iA dual-branch structure with symmetrical upper and lower branches but reversed clock phases can be adopted. According to an embodiment of this disclosure, the i-th boost unit 101... i The upper and lower branches can be composed of a charge transport module and a gate bias module, respectively. According to an embodiment of this disclosure, the charge transport module of the upper branch can be composed of a transport transistor M1. i and main capacitor C1 i The charge transport module that constitutes the lower branch can be composed of the transport transistor M2. i and main capacitor C2 i The configuration is used to turn on the transmission transistor of the current branch when the phase of the clock signal (first clock signal CLKA or second clock signal CLKB) connected to the main capacitor of the current branch (upper branch or lower branch) is low (at which time the phase of the clock signal (second clock signal CLKB or first clock signal CLKA) connected to the main capacitor of the relative branch (lower branch or upper branch) is high), so that the transmission transistor of the current branch (first input node NI1) is turned on. i Or the second input node NI2 i For the output node (first output node NO1) i Or the second output node NO2 i (Charge)

[0053] Furthermore, according to embodiments of this disclosure, the gate bias module of the upper branch can be composed of an inverter S1. i Secondary capacitor C3 i and charging transistor M3 i The gate bias module of the lower branch can be configured by inverter S2 i Secondary capacitor C4 i and charging transistor M4 i This configuration is used to, when the phase of the clock signal (first clock signal CLKA or second clock signal CLKB) connected to the main capacitor of the current branch (upper branch or lower branch) is low (at which time the phase of the clock signal (second clock signal CLKB or first clock signal CLKA) connected to the secondary capacitor of the current branch is high), set the internal node (first internal node NP1) connected to the secondary capacitor of the current branch to be... i Or the second internal node NP2 i A high-level signal is transmitted to the gate of the charge transfer transistor in the current branch to control its conduction, while simultaneously controlling the charging transistor to conduct to charge the secondary capacitor of the opposite branch (lower or upper branch), so that the internal node (second internal node NP2) of the opposite branch is charged. i Or the first internal node NP1 i ) Charge to the input node of the current branch (first input node NI1) i Or the second input node NI2 iThe level at the same location; and when the phase of the clock signal (first clock signal CLKA or second clock signal CLKB) connected to the main capacitor of the current branch (upper branch or lower branch) is high, the input node (first input node NI1) of the current branch is set to the same level; i Or the second input node NI2 i The voltage level at point (NO1) is transmitted to the gate of the transfer transistor in the charge transfer module of the current branch to control it to be completely turned off, thus preventing the output node (first output node NO1) of the current branch from being turned off. i Or the second output node NO2 i The high level of ) to the input node (first input node NI1) i Or the second input node NI2 i (Reverse flow)

[0054] As described above, according to embodiments of the present disclosure, the charge pump circuit 10 may further include an output unit 102. Figure 4 Embodiments according to this disclosure are shown. Figure 1 The circuit diagram shown is of the output unit 102 of the charge pump circuit 10. According to an embodiment of this disclosure, the output unit 102 is connected to the Kth boost unit 101. K Between the output terminal Nout and the output terminal Nout, the Kth boost unit 101 is used to... K First output node NO1 K The voltage of the second output node NO2 K The higher voltage of the voltage is output to the output terminal Nout.

[0055] like Figure 4 As shown, according to an embodiment of this disclosure, the output unit 102 may include a first PMOS transistor MP1, the drain of which is connected to the first input node NI1 of the output unit 102. O Its gate is connected to the second input node NI2 of the output unit 102. O And its source and (e.g., NW) substrate (not shown) are connected to the output terminal Nout. Furthermore, as... Figure 4 As shown, according to an embodiment of this disclosure, the output unit 102 may further include a second PMOS transistor MP2, the drain of which is connected to the second input node NI2. O Its gate is connected to the first input node NI1 O And its source and (e.g., NW) substrate (not shown) are connected to the output terminal Nout. Furthermore, as... Figure 4 As shown, according to an embodiment of this disclosure, the output unit 102 may further include a voltage stabilizing capacitor C. L It is connected between the output terminal Nout and the ground voltage Vss. For example... Figure 4As shown, according to an embodiment of this disclosure, the first input node NI1 of the output unit 102 O It can be connected to the Kth boost unit 101 K First output node NO1 K And the second input node NI2 of the output unit 102 O It can be connected to the Kth boost unit 101 K The second output node NO2 K .

[0056] like Figure 4 As shown, according to an embodiment of this disclosure, the output unit 102 may include a pair of cross-coupled PMOS transistors MP1 and MP2 and a voltage regulator capacitor C. L This is used to control the two PMOS transistors MP1 or MP2 to alternately turn on in order to power the Kth boost unit 101. K First output node NO1 K The voltage of the second output node NO2 K The higher voltage of the voltage is output to the output terminal Nout.

[0057] To further illustrate the concept of this disclosure, the following is combined with... Figure 5 The operating principle of the charge pump circuit according to this disclosure will be described in more detail. Figure 5 A circuit diagram of a first-stage charge pump circuit 20 for boosting a positive input voltage according to an embodiment of the present disclosure is shown. Figure 5 In, with Figures 1 to 4 The same elements shown are represented by the same reference numerals. For example... Figure 5 As shown, the charge pump circuit 20 includes a boost unit 101 (i.e., K=1) and an output unit 102. Since the first-stage charge pump circuit 20 only includes one boost unit 101, therefore... Figure 5 The subscript is omitted for brevity.

[0058] As described above, the first input node NI1 and the second input node NI2 of the boost unit 101 are both connected to the input terminal Nin that receives the input voltage Vin, and the first output node NO1 and the second output node NO2 of the boost unit 101 are respectively connected to the first input node NI1 of the output unit 102. O Second input node NI2 O .

[0059] like Figure 5 As shown, the boost unit 101 and the output unit 102 can be connected in series to form a first-stage charge pump circuit 20. Figure 5 In the middle, resistor R LThis can represent the equivalent load resistance of the load circuit connected to the output terminal Nout of the charge pump circuit 20. For example... Figure 5 As shown, according to an embodiment of this disclosure, when the second clock signal CLKB jumps to a high level (i.e., the level of the power supply voltage Vcc), the first clock signal CLKA jumps to a low level (i.e., the level of the ground voltage Vss). At this time, the upper branch of the boost unit 101 is in a low clock phase state, and the lower branch is in a high clock phase state. According to an embodiment of this disclosure, the first output node NO1 of the upper branch and the second internal node NP2 of the secondary capacitor C4 of the lower branch jump downwards with the first clock signal CLKA, with a jump amplitude of -Vcc to maintain a constant voltage difference between the main capacitor C1 and the secondary capacitor C4; and the second output node NO2 of the lower branch and the internal node NP1 of the secondary capacitor C3 of the upper branch jump upwards with the second clock signal CLKB, with a jump amplitude of +Vcc to maintain a constant voltage difference between the main capacitor C2 and the secondary capacitor C3. According to the embodiments of this disclosure, under the above-described bias conditions, the PMOS transistor SP1 in the inverter S1 of the upper branch is turned on, and the NMOS transistor SN1 is turned off. This transmits the high level of the first internal node NP1 of the secondary capacitor C3 to the gate of the transmission transistor M1 to control its conduction. Meanwhile, the first output node NO1, which was at a low level, is pulled high to the same level as the input voltage Vin at the first input node NI1. Simultaneously, the charging transistor M3 in the upper branch is turned on, causing the second internal node NP2 of the secondary capacitor C4 in the lower branch to also be charged to the same level as the input voltage Vin.

[0060] As analyzed above, the low levels of the first output node NO1 and the second internal node NP2 of the boost unit 101 are both at the level of the input voltage Vin. According to the principle of symmetry, the low levels of the second output node NO2 and the first internal node NP1 of the boost unit 101 are also at the level of the input voltage Vin. When the second clock signal CLKB jumps to a high level (rising edge), the second output node NO2 and the first internal node NP1 jump upwards to +Vcc, i.e., Vin + Vcc. At this time, the PMOS transistor MP2 in the lower branch of the output unit 102 is turned on, and power flows from the second output node NO2 of the boost unit 101 (via the second input node NI2 of the output unit 102)... O For the voltage regulator capacitor C LThe charging process generates a high voltage Vout at the output terminal Nout of the charge pump circuit 20, which is higher than the input voltage Vin and close to Vin+Vcc. Similarly, when the second clock signal CLKB jumps to a low level (falling edge), the voltage at the first output node NO1 and the second internal node NP2 of the boost unit 101 jumps to Vin+Vcc, causing the PMOS transistor MP1 in the upper branch of the output unit 102 to turn on, and the voltage from the first output node NO1 of the boost unit 101 (via the first input node NI1 of the output unit 102) increases. O For the voltage regulator capacitor C L The charge pump circuit 20 generates a high voltage Vout at its output terminal Nout, which is higher than the input voltage Vin and close to Vin+Vcc.

[0061] Those skilled in the art will recognize that, due to the interaction between the main capacitor C1 or C2 in the boost unit 101 and the voltage regulator capacitor C in the output unit 102, L Charge sharing effect between and load resistor R L The discharge consumption results in a voltage loss ΔV between the output voltage Vout of the charge pump circuit 20 and the first and second output nodes NO1 and NO2 of the boost unit 101 electrically shorted therewith. That is, the output voltage Vout of the charge pump circuit 20 is Vin + Vcc - ΔV, where ΔV can be represented by the following formula (1).

[0062] ΔV=-I L ×T 1 / 2CLK / C (1)

[0063] Among them, I L This indicates that the load resistor R L The load current formed on it, T 1 / 2CLK The first and second clock signals CLKA and CLKB represent the half-cycle time, and C represents the capacitance value of the main capacitor C1 or C2. In other words, the high level of the first and second output nodes NO1 and NO2 of the boost unit 101 is reduced due to the current consumption of the load connected to the charge pump circuit 20; the larger the load current, the lower the high voltage that the charge pump circuit 20 can generate. In contrast, the first and second internal nodes NP1 and NP2 of the boost unit 101 are disconnected from the load of the charge pump circuit 20 when at a high level and are not affected by the load current I. L Due to the influence of this, it is able to maintain a high voltage of Vin+Vcc.

[0064] Figure 6 A schematic diagram showing the signal waveforms of each node of a first-stage charge pump circuit 20 for boosting a positive input voltage according to an embodiment of the present disclosure is illustrated. Figure 6In the diagram, VNP1 and VNP2 represent the voltages at internal nodes NP1 and NP2, respectively, and VNI1 and VNI2 represent the voltages at output nodes NO1 and NO2, respectively.

[0065] like Figure 6 As shown, according to an embodiment of this disclosure, by switching the high voltages of the first and second internal nodes NP1 and NP2 in the boost unit 101 to generate the gate voltage controlling the conduction of the transfer transistor M1 or M2 in the boost unit 101, it is possible to avoid the load current I... L The resulting voltage drop increases the overdrive gate voltage and conduction capability of the transfer transistors M1 and M2, thereby significantly improving the charge transfer efficiency and boost capability of the charge pump circuit 20, and thus enabling its application to lower power supply voltages.

[0066] According to embodiments of this disclosure, by... Figure 5 Based on the first-stage charge pump circuit 20 shown, by cascading more boost units between the first boost unit 1011 and the output unit 102, the following can be obtained: Figure 2 The K-stage charge pump circuit 10 shown in the diagram allows each boost unit to sequentially generate a higher voltage based on the previous stage, thereby generating a high voltage Vin + K × Vcc at the output of the K-stage charge pump circuit 10. According to embodiments of this disclosure, when K > 1, the operating principle of the second to Kth boost units is the same as described above. Figure 5 The working principle of the first boost unit described is the same.

[0067] According to Equation 1 above, the boosting capability and driving capability of the charge pump circuit are related to the voltage flowing through the load capacitor R. L Load current I L And it is closely related to the capacitance value C of the main capacitor in the boost unit. According to embodiments of this disclosure, Figure 3 The i-th boost unit 101 shown i The first to fourth capacitors C1 i To C4 i This can be achieved using the gate capacitance of a MOS transistor. Figure 7 An i-th boost unit 101 according to an embodiment of the present disclosure is shown, wherein a capacitor is implemented using a transistor gate capacitor. i The circuit diagram, and Figure 8 A circuit diagram of a charge pump circuit 30 for boosting a positive input voltage, which uses transistor gate capacitors to implement the capacitors in each boost unit according to an embodiment of the present disclosure, is shown. Figure 7 In, with Figure 3 The same elements shown are represented by the same reference numerals. Figure 8 In, with Figure 2The same elements shown are represented by the same reference numerals.

[0068] like Figure 7 As shown, according to an embodiment of this disclosure, the i-th boost unit 101 i The NMOS transistor MC1 in the middle is used to implement the first capacitor (main capacitor). i The source and drain are connected together to the first clock node NC1. i And the gate is connected to the first output node NO1. i In addition, such as Figure 7 As shown, according to an embodiment of this disclosure, the i-th boost unit 101 i The NMOS transistor MC2 in the middle is used to implement the second capacitor (main capacitor). i The source and drain are connected together to the second clock node NC2. i And the gate is connected to the second output node NO2. i In addition, such as Figure 7 As shown, according to an embodiment of this disclosure, the i-th boost unit 101 i The NMOS transistor MC3 is used to implement the third capacitor (secondary capacitor). i The source and drain are connected together to the second clock node NC2. i And the gate is connected to the first internal node NP1 i In addition, such as Figure 7 As shown, according to an embodiment of this disclosure, the i-th boost unit 101 i The NMOS transistor MC4 is used to implement the fourth capacitor (secondary capacitor). i The source and drain are connected together to the first clock node NC1. i And the gate is connected to the second internal node NP2. i According to embodiments of this disclosure, the i-th boost unit 101 is respectively used to implement... i NMOS transistor MC1 in the first to fourth capacitors i To MC4 i The (e.g., PW) substrate can be connected to the ground voltage Vss.

[0069] According to embodiments of this disclosure, to ensure the symmetry of the upper and lower branches, the first and second capacitors can be capacitors formed using the gate capacitance of NMOS transistors of the same size, and the third and fourth capacitors can also be capacitors formed using the gate capacitance of NMOS transistors of the same size. Specifically, according to embodiments of this disclosure, the NMOS transistor MC1 is used to implement the main capacitor. i and MC2 iThe dimensions can be the same, and the NMOS transistor MC3 is used to implement the secondary capacitor. i and MC4 i The dimensions can also be the same. Furthermore, as described above, according to embodiments of this disclosure, in order to improve the driving capability of the charge pump circuit and reduce area overhead, the capacitance value of the secondary capacitor can be less than or equal to the capacitance value of the primary capacitor. Therefore, accordingly, according to embodiments of this disclosure, the NMOS transistor MC3 used to implement the secondary capacitor... i and MC4 i The size can be smaller than or equal to that of the NMOS transistor MC1 used to implement the main capacitor. i and MC2 i The size.

[0070] like Figure 8 As shown, according to an embodiment of this disclosure, when K>1, that is, when the charge pump circuit has two or more boost units, in different boost units 1011 to 101 K Between them, the transistor MC1 is used to implement the main capacitor. i and MC2 i The types and sizes of the transistors can be the same, and the transistor MC3 is used to implement the secondary capacitor. i and MC4 i The type and size can be the same as each other. For example, according to an embodiment of this disclosure, each boost unit has a transistor MC1 for implementing the main capacitor. i and MC2 i And the transistor MC3 used to implement the secondary capacitor. i and MC4 i This can be achieved using the same type of high-voltage NMOS transistor.

[0071] Figure 9 A circuit diagram is shown of a first-stage charge pump circuit 40 for boosting a positive input voltage, wherein a transistor gate capacitor is used to implement a capacitor according to an embodiment of the present disclosure. Figure 9 In, with Figure 5 The same elements shown are represented by the same reference numerals. Figure 9 The first-stage charge pump circuit 40 shown is... Figure 5 The difference in the first-stage charge pump circuit 20 shown is that... Figure 9 The first-stage charge pump circuit 40 shown uses the gate capacitance of an NMOS transistor to implement the various capacitor elements.

[0072] According to the embodiments of this disclosure, in conjunction with the foregoing reference... Figure 5As can be seen from the working principle of the boost unit described, the transistors MC1 and MC2 used to realize the main capacitor and the NMOS transistors MC3 and MC4 used to realize the secondary capacitor all operate in an inverse state with the gate forward biased, that is, the gate voltage is higher than the source voltage and the drain voltage.

[0073] Specifically, in combination Figure 6 Reference Figure 9 Taking the NMOS transistor MC1 used to implement the first capacitor as an example, its operating state is analyzed. When the first clock signal CLKA driving transistor MC1 is high, both the source and drain of transistor MC1 are raised to the power supply voltage Vcc. Therefore, the gate connected to the first output node NO1 is first raised to the voltage Vin+Vcc and then gradually discharged to the voltage Vin+Vcc-ΔV. When the first clock signal CLKA driving transistor MC1 is low, both the source and drain of transistor MC1 are discharged to the ground voltage Vss, and the gate is charged to the power supply voltage Vcc. Thus, according to the embodiments of this disclosure, at any clock phase, the gate voltage of transistor MC1 is higher than the source-drain voltage and operates in an inversion state or a strong inversion state.

[0074] Figure 10 A graph showing the capacitance-voltage characteristic (CV characteristic) of an NMOS transistor is displayed. Figure 10 As shown, when the gate-source voltage V of the NMOS transistor GS From low to high, the gate capacitance of an NMOS transistor transitions sequentially through the accumulation region, depletion region, inversion region, and strong inversion region. The capacitance is highest in the accumulation and strong inversion regions, and decreases significantly in the depletion and inversion regions. For example... Figure 10 As shown, the boundary between the inversion region and the strong inversion region of an NMOS transistor is the gate-source voltage Vo of the NMOS transistor. GS Reaching its threshold voltage V TN To ensure that the MC1 transistor has sufficient capacitance, it should be avoided to operate in the depletion region and inversion region, and should be operated in the strong inversion region as much as possible. In other words, the MC1 transistor should be turned on as much as possible.

[0075] Therefore, increasing the size of the NMOS transistors MC1 and MC2 used to implement the main capacitor can increase their capacitance, thereby reducing the voltage loss of the corresponding output nodes NO1 and NO2 at high levels. This, in turn, increases the gate bias voltage of the NMOS transistors MC1 and MC2 used to implement the main capacitor to prevent them from operating in the depletion and inversion regions. However, increasing the size of the NMOS transistors MC1 and MC2 used to implement the main capacitor leads to a greater area overhead.

[0076] Therefore, according to embodiments of this disclosure, by reducing the threshold voltage of the NMOS transistors MC1 and MC2 used to realize the main capacitor, for example by using low threshold NMOS transistors (LVT-NMOS) or zero threshold transistors (ZVT-NMOS), their strong inversion regions can be shifted to lower gate voltages, thereby preventing them from operating in the depletion region and inversion region.

[0077] Figure 11 The figure shows the capacitance-voltage (CV) characteristics of NMOS transistors at different threshold values. Figure 11 As shown, by using low-threshold transistors or zero-threshold transistors, the NMOS transistors used to implement the main capacitor can have a larger capacitance value, thus making them suitable for lower supply voltages.

[0078] According to embodiments of this disclosure, a low-threshold transistor can be realized by reducing the threshold doping concentration of the NMOS transistor. Furthermore, according to embodiments of this disclosure, a depletion-type NMOS transistor, i.e., a zero-threshold transistor with a threshold voltage close to 0V, can be realized by removing the P-well implantation of the NMOS transistor and directly fabricating the NMOS transistor on a P-type substrate.

[0079] like Figure 8 As shown, when K>1, i.e., when the charge pump circuit has two or more boost units, the bias voltages of the output nodes NO11 and NO21 of the first boost unit 1011 are lower. The NMOS transistors MC11 and MC21 used to implement the main capacitor are more susceptible to the non-ideal gate capacitance effect described above, leading to a decrease in capacitance value. Compared to the first boost unit 1011, the intermediate stage (i.e., the second to Kth) boost units 1012 to 101... K Output nodes NO12 to NO1 K and NO22 to NO2 K The bias voltage is higher, and it is used to implement the main capacitor NMOS transistors MC12 to MC1 K and MC22 to MC2 K It can maintain a bias in the strong inversion region and thus have a larger capacitance value.

[0080] like Figure 8 As shown, according to an embodiment of this disclosure, when K>1, since the first boost unit 1011 and the intermediate boost units 1012 to 101... K The different operating bias points allow for the intermediate boost unit to be either 1012 or 101. K NMOS transistors MC12 to MC1 used to implement the main capacitor K and MC22 to MC2 KThe type or size of the NMOS transistors MC11 and MC21 used to implement the main capacitor in the first boost unit 1011 is different from the type or size of the NMOS transistors MC11 and MC21. For example, according to an embodiment of this disclosure, when K>1, the capacitance values ​​of the first capacitor and the second capacitor in the first boost unit 1011 can be greater than those in the second to Kth boost units 1012 to 1013. K The capacitance values ​​of the first capacitor and the second capacitor. Specifically, according to embodiments of this disclosure, the NMOS transistors MC11 and MC21 of the first boost unit 1011, which implement the main capacitor, can be larger than those of the intermediate boost units 1012 to 101. K NMOS transistors MC12 to MC1 used to implement the main capacitor K and MC22 to MC2 K The size.

[0081] Alternatively, according to embodiments of this disclosure, the NMOS transistors MC11 and MC21 of the first boost unit 1011, which implement the main capacitor, may be low-threshold transistors or zero-threshold transistors, and the intermediate boost units 1012 to 101... K NMOS transistors MC12 to MC1 used to implement the main capacitor K and MC22 to MC2 K It could be a transistor with a higher threshold.

[0082] For similar reasons, according to embodiments of this disclosure, intermediate stage boost units 1012 to 101 can be made... K NMOS transistors MC32 to MC3 used to implement the secondary capacitor K and MC42 to MC4 K The type or size of the NMOS transistors MC31 and MC41 used to implement the secondary capacitor in the first boost unit 1011 is different from the type or size of the NMOS transistors MC31 and MC41. For example, according to an embodiment of this disclosure, when K>1, the capacitance values ​​of the third and fourth capacitors of the first boost unit 1011 can be greater than those of the second to Kth boost units 1012 to 1013. K The capacitance values ​​of the third and fourth capacitors. Specifically, according to embodiments of this disclosure, the NMOS transistors MC31 and MC41 of the first boost unit 1011 used to implement the secondary capacitor can be larger than those of the intermediate boost units 1012 to 1013. K NMOS transistors MC32 to MC3 used to implement the secondary capacitor K and MC42 to MC4 K The size.

[0083] Alternatively, according to embodiments of this disclosure, the NMOS transistors MC31 and MC41 of the first boost unit 1011, which implement the secondary capacitor, may be low-threshold transistors or zero-threshold transistors, and the intermediate boost units 1012 to 101... K NMOS transistors MC32 to MC3 used to implement the secondary capacitor K and MC42 to MC4 K It could be a transistor with a higher threshold.

[0084] According to embodiments of this disclosure, the main capacitors C11 to C1... K and C21 to C2 K and secondary capacitors C31 to C3 K and C41 to C4 K The driving clock is configured with different phase signals.

[0085] Figure 12 A circuit diagram of a charge pump circuit 50 driven by a four-phase clock according to an embodiment of the present disclosure is shown. Figure 12 In, with Figure 2 The same elements shown are represented by the same reference numerals.

[0086] like Figure 12 As shown, according to an embodiment of this disclosure, Figure 12 The charge pump circuit 50 shown is... Figure 2 The charge pump circuit 10 shown differs in that the charge pump circuit 50 is driven by four-phase clock signals, namely, a first clock signal CLKA, a second clock signal CLKB, a third clock signal CLKC, and a fourth clock signal CLKD. According to an embodiment of this disclosure, the phase of the first clock signal CLKA is opposite to the phase of the second clock signal CLKB, the phase of the third clock signal CLKC is opposite to the phase of the fourth clock signal CLKD, and the phase of the first clock signal CLKA is the same as the phase of the third clock signal CLKC.

[0087] Correspondingly, unlike Figure 2 The charge pump circuit 10 shown is as follows: Figure 12 As shown, according to embodiments of this disclosure, the first to Kth boost units 1011 to 101 in the charge pump circuit 50 K Each boost unit 101 i (where 1≤i≤K) In the first capacitor C1 i Connected to the first output node NO1 i and the first clock node NC1 i Between, the second capacitor C2 i Connect to the second output node NO2 iSecond clock node NC2 i Between, the third capacitor C3 i Connected to the third clock node NC3 i and the first internal node NP1 i Between, and the fourth capacitor C4 i Connected to the fourth clock node NC4 i Second internal node NP2 i between.

[0088] like Figure 12 As shown, according to embodiments of this disclosure, the first to Kth boost units 1011 to 101 K Odd-numbered boost unit 101 2j-1 (where j is a natural number greater than 0, and j≤[(K+1) / 2], where [] represents the floor function) The first clock node NC1 of each of the following is a given clock node. 2j-1 Commonly connected to the first clock signal CLKA, the first to the Kth boost units 1011 to 101 K Odd-numbered boost unit 101 2j-1 The second clock node NC2 of each 2j-1 Commonly connected to the second clock signal CLKB, the first to Kth boost units 1011 to 101 K Odd-numbered boost unit 101 2j-1 The third clock node NC3 of each 2j-1 They are all connected to the fourth clock signal CLKD, and the first to the Kth boost units 1011 to 101 K Odd-numbered boost unit 101 2j-1 The fourth clock node NC4 of each 2j-1 They are all connected to the third clock signal CLKC.

[0089] In addition, such as Figure 12 As shown, according to embodiments of this disclosure, the first to Kth boost units 1011 to 101 K Even-numbered boost unit 101 2j The first clock node NC1 of each 2j Commonly connected to the second clock signal CLKB, the first to Kth boost units 1011 to 101 K Even-numbered boost unit 101 2j The second clock node NC2 of each 2j Commonly connected to the first clock signal CLKA, the first to the Kth boost units 1011 to 101 K Even-numbered boost unit 101 2j The third clock node NC3 of each2j They are all connected to the third clock signal CLKC, and the first to the Kth boost units 1011 to 101 K Even-numbered boost unit 101 2j The fourth clock node NC4 of each 2j They are all connected to the fourth clock signal CLKD.

[0090] In other words, according to the embodiments of this disclosure, each boost unit 101 can be... i The main capacitor C1 i and C2 i and secondary capacitor C3 i and C4 i The driving clock is configured as a clock signal with a different phase. Specifically, such as... Figure 12 As shown, the main capacitor C1 i and C2 i Driven by the first clock signal CLKA and its inverted signal, the second clock signal CLKB, and the secondary capacitor C3... i and C4 i It is driven by the third clock signal CLKC and its inverted signal, namely the fourth clock signal CLKD.

[0091] Figure 13 It shows Figure 12 The diagram shows an example waveform of a four-phase clock used in the charge pump circuit 50. (See also...) Figure 13 As shown, according to an embodiment of this disclosure, the first clock signal CLKA and the third clock signal CLKC are set to be in-phase clocks, and the third clock signal CLKC and the fourth clock signal CLKD are set to be two-phase non-overlapping clocks that are mutually inverted, i.e., in every half clock cycle T 1 / 2CLK Within the clock signal, the falling edge td1 of the third clock signal CLKC or the fourth clock signal CLKD always arrives before the rising edge tr1 of the fourth clock signal CLKD or the third clock signal CLKC, in order to avoid the high levels of the two overlapping.

[0092] In addition, such as Figure 13 As shown, according to the embodiments of this disclosure, the first clock signal CLKA and the second clock signal CLKB are set as two inverse synchronous or non-overlapping clocks, that is, in every half clock cycle T 1 / 2CLK Within this timeframe, the falling edge td2 of either the first clock signal CLKA or the second clock signal CLKB always arrives no later than the rising edge tr2 of either the second clock signal CLKB or the first clock signal CLKA. Furthermore, as... Figure 13As shown, the falling edge td1 of the third clock signal CLKC or the fourth clock signal CLKD arrives no later than the falling edge td2 of the first clock signal CLKA or the second clock signal CLKB, and the rising edge tr1 of the fourth clock signal CLKD or the third clock signal CLKC arrives no earlier than the rising edge tr2 of the second clock signal CLKB or the first clock signal CLKA. In other words, as... Figure 13 As shown, according to the embodiments of this disclosure, the phases of the four-phase clocks, namely the first clock signal CLKA, the second clock signal CLKB, the third clock signal CLKC and the fourth clock signal CLKD, satisfy the following equations (2) and (3).

[0093] td1≤td2≤tr2≤tr1 (2)

[0094] td1 <tr1 (3)

[0095] According to the above reference Figures 3 to 6 For boost unit 101 i Description of the working principle, the transfer transistor M1 in the charge transfer module i and M2 i The high-level gate voltage is generated by the secondary capacitor C3. i and C4 i The storage node, namely the first internal node NP1 i Second internal node NP2 i The high-level signal is generated by switching the gate bias module. Therefore, according to the above reference... Figure 13 The described four-phase clock, namely the phase relationship of the first to fourth clock signals CLKA to CLKD, is determined by the advance secondary capacitor C3. i and C4 i The driving clock, namely the falling edge td1 of the third clock signal CLKC and the fourth clock signal CLKD, and delayed by its rising edge tr1, can delay the transmission transistor M1. i and M2 i The rise time of the gate voltage is determined to ensure the transmission transistor M1. i and M2 i It is in the off state at the moment of high-low phase switching, thereby avoiding charge in the boost unit 101. i The reverse flow between the input and output nodes causes a decrease in charge transfer efficiency.

[0096] According to embodiments of this disclosure, the waveforms of the first clock signal CLKA and the second clock signal CLKB can be further optimized. Figure 14 It shows Figure 12The diagram shows a waveform representation of another example of a four-phase clock used in the charge pump circuit 50. According to embodiments of this disclosure, during the transition periods of the first clock signal CLKA and the second clock signal CLKB, the rising edge of one clock signal CLKA and the falling edge of the other clock signal overlap at a level between high and low. Figure 14 As shown, the rising and falling edges of the first clock signal CLKA and the second clock signal CLKB can overlap in the interval between td2 and tr2.

[0097] In the prior art, the clock signal used for the charge pump (e.g., the first clock signal CLKA) and its inverted clock signal (e.g., the second clock signal CLKB) typically need to avoid crossover between the rising and falling edge intervals of these two inverted clock signals (e.g., Figure 6 The waveform shown) or overlapping (e.g., Figure 14 (The waveform shown) is used to reduce leakage current. In contrast, due to the boost unit 101 according to the embodiment of this disclosure as explained above... i The working principle of the present invention is that by introducing a third clock signal CLKC and a fourth clock signal CLKD, the charge pump according to the present disclosure can still avoid leakage current even when the first clock signal CLKA and the second clock signal CLKB have crossover or overlap between rising edge intervals and falling edge intervals, thereby improving the efficiency of the charge pump.

[0098] like Figure 14 As shown, according to an embodiment of this disclosure, a high-level clock signal can charge a low-level clock signal during the transition period of the first clock signal CLKA and the second clock signal CLKB.

[0099] For example, according to an embodiment of this disclosure, an equalization switch (not shown) can be added to the output stage of the driving circuits for the first and second clock signals CLKA and CLKB. At the instant of transition of the first and second clock signals CLKA and CLKB, i.e., during the time from td2 to tr2, the equalization switch is turned on to perform an equalization operation on the first and second clock signals CLKA and CLKB. That is, the high-phase clock signal CLKA (or CLKB) charges the low-phase clock signal CLKB (or CLKA), thereby effectively reducing the power consumption of the driving circuits for the first and second clock signals CLKA and CLKB, and thus improving the overall energy efficiency of the charge pump circuit.

[0100] The charge pump circuit according to the above embodiments of this disclosure adopts a symmetrical dual-branch structure, which can transmit the high level stored in the secondary capacitor or the low level output from the previous stage to the gate of the current stage's transfer transistor to control it to be fully turned on or completely turned off. This avoids the problem of gate voltage drop and threshold voltage loss of the transfer transistor caused by the charging of the previous stage node to the subsequent stage node in the existing charge pump circuit structure. It can effectively improve the charge transfer efficiency and boost capability of the charge pump circuit, reduce the operating power consumption of the charge pump circuit, and thus be applicable to lower power supply voltages.

[0101] As described above, the charge pump circuit according to embodiments of the present disclosure generates the gate voltage that controls the conduction of the transfer transistor by designing a gate bias module, which can enhance the conduction capability of the transfer transistor and is unaffected by load current. Compared with prior art charge pump circuits, the charge pump circuit according to embodiments of the present disclosure has the advantages of high charge transfer efficiency, low operating power consumption, strong boost capability, and large driving capability, thus making it suitable for lower power supply voltages.

[0102] Furthermore, the charge pump circuit according to the embodiments of the present disclosure can delay the rise time of the gate voltage of the transfer transistor by using a four-phase clock with a pre-set phase relationship to advance the drive clock of the secondary capacitor, thereby ensuring that the transfer transistor is in the off state at the moment of high-low phase switching, and further avoiding the problem of reduced charge transfer efficiency caused by reverse flow of charge between the input node and the output node of the boost unit.

[0103] Although this disclosure has been described with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes may be made to this disclosure without departing from the spirit and scope of the disclosure as disclosed in the appended claims.

Claims

1. A charge pump circuit comprising: first through Kth voltage boosting units configured to be connected in series sequentially, where K is a natural number greater than or equal to 1, wherein each of the first through Kth voltage boosting units includes: a first switching element connected between a first input node and a first output node; a second switching element connected between a second input node and a second output node; a first capacitor connected between the first output node and a first clock node; a second capacitor connected between the second output node and a second clock node; a third capacitor connected between a third clock node and a first internal node; a fourth capacitor connected between a fourth clock node and a second internal node; a third switching element connected between the first input node and the second internal node; a fourth switching element connected between the second input node and the first internal node; a first inverter having an input connected to the first output node and outputting a first switching signal for controlling turning on and off of the first switching element and the third switching element; and a second inverter having an input connected to the second output node and outputting a second switching signal for controlling turning on and off of the second switching element and the fourth switching element, wherein the first clock nodes of each of odd-numbered ones of the first through Kth voltage boosting units are commonly connected to a first clock signal, the second clock nodes of each of the odd-numbered ones of the first through Kth voltage boosting units are commonly connected to a second clock signal, the third clock nodes of each of the odd-numbered ones of the first through Kth voltage boosting units are commonly connected to a fourth clock signal, and the fourth clock nodes of each of the odd-numbered ones of the first through Kth voltage boosting units are commonly connected to a third clock signal, wherein the first clock nodes of each of even-numbered ones of the first through Kth voltage boosting units are commonly connected to the second clock signal, the second clock nodes of each of the even-numbered ones of the first through Kth voltage boosting units are commonly connected to the first clock signal, the third clock nodes of each of the even-numbered ones of the first through Kth voltage boosting units are commonly connected to the third clock signal, and the fourth clock nodes of each of the even-numbered ones of the first through Kth voltage boosting units are commonly connected to the fourth clock signal, wherein a phase of the first clock signal is opposite to a phase of the second clock signal, a phase of the third clock signal is opposite to a phase of the fourth clock signal, and the phase of the first clock signal is the same as a phase of the third clock signal; wherein the first input node and the second input node of the first voltage boosting unit are commonly connected to an input terminal that receives an input voltage, wherein, when 1 < i ≤ K, the first input node of an ith voltage boosting unit is connected to the first output node of an (i-1)th voltage boosting unit, and the second input node of the ith voltage boosting unit is connected to the second output node of the (i-1)th voltage boosting unit; and wherein the first input node of the Kth voltage boosting unit is connected to the first output node of a (K-1)th voltage boosting unit, and the second input node of the Kth voltage boosting unit is connected to the second output node of the (K-1)th voltage boosting unit. An output unit connected between the Kth voltage boosting unit and an output terminal is configured to output a higher voltage between a voltage of a first output node and a voltage of a second output node of the Kth voltage boosting unit to the output terminal.

2. The charge pump circuit of claim 1, wherein, The first to fourth clock signals are configured such that, within each half clock period: a falling edge of the first clock signal or the second clock signal arrives no later than a rising edge of the second clock signal or the first clock signal, a falling edge of the third clock signal or the fourth clock signal arrives earlier than a rising edge of the fourth clock signal or the third clock signal, the falling edge of the third clock signal or the fourth clock signal arrives no later than the falling edge of the first clock signal or the second clock signal, and a rising edge of the third clock signal or the fourth clock signal arrives no earlier than a rising edge of the first clock signal or the second clock signal.

3. The charge pump circuit of claim 1, wherein, During a transition period of the first clock signal and the second clock signal, a rising edge of one of the first clock signal and the second clock signal and a falling edge of the other clock signal exist at a level between a high level and a low level.

4. The charge pump circuit of claim 3, wherein, During the transition period of the first clock signal and the second clock signal, a clock signal at a high level charges a clock signal at a low level.

5. The charge pump circuit of claim 1, wherein, In each of the first to Kth voltage boosting units, the first switch element and the third switch element are NMOS transistors whose gates are connected to an output of a first inverter, and the second switch element and the fourth switch element are NMOS transistors whose gates are connected to an output of a second inverter.

6. The charge pump circuit of claim 5, wherein, In each of the first to Kth voltage boosting units, the first inverter includes an NMOS transistor and a PMOS transistor, wherein gates of the NMOS transistor and the PMOS transistor are connected to a first output node, drains of the NMOS transistor and the PMOS transistor are connected to gates of NMOS transistors constituting the first switch element and the third switch element, a source of the NMOS transistor is connected to a first input node, and a source and a substrate of the PMOS transistor are connected to a first internal node, and the second inverter includes an NMOS transistor and a PMOS transistor, wherein gates of the NMOS transistor and the PMOS transistor are connected to a second output node, drains of the NMOS transistor and the PMOS transistor are connected to gates of NMOS transistors constituting the second switch element and the fourth switch element, a source of the NMOS transistor is connected to a second input node, and a source and a substrate of the PMOS transistor are connected to a second internal node.

7. The charge pump circuit of claim 6, wherein, In each of the first to Kth voltage boosting units, a substrate of the NMOS transistor is connected to a ground voltage or a power supply voltage.

8. The charge pump circuit of claim 1, wherein, In each of the first to Kth voltage boosting units, the first capacitor and the second capacitor have the same capacitance value, and the third capacitor and the fourth capacitor have the same capacitance value.

9. The charge pump circuit of claim 8, wherein, In each of the first to Kth voltage boosting units, the capacitance value of the third capacitor and the fourth capacitor is smaller than the capacitance value of the first capacitor and the second capacitor.

10. The charge pump circuit of claim 8, wherein, When K > 1, capacitance values of the first and second capacitors of the first boost unit are greater than capacitance values of the first and second capacitors of the second to Kth boost units, and / or capacitance values of the third and fourth capacitors of the first boost unit are greater than capacitance values of the third and fourth capacitors of the second to Kth boost units.

11. The charge pump circuit of claim 8, wherein, In each of the first to Kth boost units, the first to fourth capacitors are formed by gate capacitances of NMOS transistors, and a substrate of the NMOS transistors used to form the first to fourth capacitors is connected to a ground voltage.

12. The charge pump circuit of claim 11, wherein, In each of the first to Kth boost units, the NMOS transistors used to form the first to fourth capacitors are NMOS transistors of the same type.

13. The charge pump circuit of claim 12, wherein, In each of the first to Kth boost units, the NMOS transistors used to form the first and second capacitors have the same size, and the NMOS transistors used to form the third and fourth capacitors have the same size.

14. The charge pump circuit of claim 12, wherein, When K > 1, the size of the NMOS transistors used to form the first and second capacitors of the first boost unit is greater than the size of the NMOS transistors used to form the first and second capacitors of the second to Kth boost units, and / or the size of the NMOS transistors used to form the third and fourth capacitors of the first boost unit is greater than the size of the NMOS transistors used to form the third and fourth capacitors of the second to Kth boost units.

15. The charge pump circuit of claim 11, wherein, When K > 1, the NMOS transistors used to form the first and second capacitors of the first boost unit are NMOS transistors of a first type, and the NMOS transistors used to form the first and second capacitors of the second to Kth boost units are NMOS transistors of a second type, and / or the NMOS transistors used to form the third and fourth capacitors of the first boost unit are NMOS transistors of the first type, and the NMOS transistors used to form the third and fourth capacitors of the second to Kth boost units are NMOS transistors of the second type, wherein the threshold voltage of the NMOS transistors of the first type is lower than the threshold voltage of the NMOS transistors of the second type.

16. The charge pump circuit of claim 1, wherein, The output unit includes: a first PMOS transistor having a drain connected to a first output node of the Kth boost unit, a gate connected to a second output node of the Kth boost unit, and a source and a substrate connected to the output terminal; a second PMOS transistor having a drain connected to the second output node of the Kth boost unit, a gate connected to the first output node of the Kth boost unit, and a source and a substrate connected to the output terminal; and a voltage stabilizing capacitor connected between the output terminal and a ground voltage.

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