Distance-Based Memory Disambiguation Prediction
The MDPT system addresses memory disambiguation violations in processors by tracking load and store instruction differences, forming dependencies to prevent stale data loading, thereby improving processor efficiency and reducing re-execution overhead.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-03-10
- Publication Date
- 2026-03-03
AI Technical Summary
Memory disambiguation violations in out-of-order execution processors lead to inefficiencies due to the processor loading stale data, requiring re-execution of instructions, which existing techniques struggle to accurately predict and prevent.
A memory disambiguation table (MDPT) tracks the difference between load and store instructions to form dependencies, using a two-pass mechanism to predict and prevent memory disambiguation violations by ensuring load instructions are executed only after their corresponding store instructions have completed.
This approach significantly improves processor efficiency by reducing memory disambiguation violations, enhancing accuracy over prior methods by utilizing load and store instruction differences, and minimizing re-execution of instructions.
Smart Images
Figure 2026507378000001_ABST
Abstract
Description
[Technical Field]
[0001] This specification relates to techniques for performing a predictive memory disambiguation process. [Background technology]
[0002] Loads from and stores to memory are performance-critical memory operations for a processor. The store queue in the load-store unit (LSU) can support out-of-order (OOO) execution of memory operations, which involves the processor executing memory operations in an order different from the original program. In this case, the processor uses the store queue to track in-progress store entries within a processing window to ensure the correctness of data written to memory by store instructions as part of the out-of-order (OOO) execution.
[0003] Memory disambiguation violations are a major source of inefficiency in OOO execution. Memory disambiguation violations can arise in part from the arithmetic address format supported by modern processors. Consider the following example assembly code shown in Table 1, which has a store instruction followed by a load instruction:
[0004] [Table 1]
[0005] The store instruction on line 1 stores the value of register 1, which is the address stored by register 4 plus an offset of 4. The load instruction on line 3 loads the value of register 2, which is the address stored by register 3 plus an offset of 8.
[0006] If the value of R4+4 turns out to be the same as the value of R3+8, a memory disambiguation violation may occur. However, it is not clear from the program code itself that this is the case. Rather, it is only during program execution that the address becomes disambiguated and the processor discovers an out-of-order violation due to that disambiguation. For example, if a load instruction completes while a store instruction is still in the store queue, the load instruction, along with any other instructions that depend on the data read by the load instruction, will need to be re-executed. Summary of the Invention
[0007] This specification describes a system for performing a predictive memory disambiguation process, which can significantly improve processor efficiency by preventing repeated memory disambiguation (MD) violations. As previously mentioned, a memory disambiguation violation occurs when a load instruction reads data before a previous store instruction to the same memory address has completed, which can cause the processor to load stale data from memory. When this occurs, the load instruction must be re-executed, as well as any other instructions that depend on the data read by the load instruction.
[0008] To address this issue, the system can maintain a memory disambiguation table (MDPT), which stores difference values for loads that previously underwent MD violations. Then, when a load instruction is encountered, the processor can introduce a dependency between the load instruction and the store instruction indicated by the difference value, such that the load is executed only after the store on which it depends.
[0009] Particular embodiments of the subject matter described in this specification can be implemented to realize one or more of the following advantages.
[0010] The technique using a memory disambiguation table described herein provides improved efficiency in preventing MD violations while being easier to implement than some prior techniques for predicting memory disambiguation. For example, tracking the program counters of both the load and store instructions involved in a memory disambiguation violation can be much more expensive to implement in hardware. Some other prior techniques track only the program counter of the load instruction involved in a memory disambiguation violation. Tracking the program counter of the load instruction is easier to implement in a processor, but is much less accurate because the processor relies on older store instructions to predict memory disambiguation violations, and inaccuracies in memory disambiguation predictions can result in high performance overhead.
[0011] In contrast, the techniques described herein can achieve high accuracy by utilizing the difference between load and store instructions to perform predictive memory disambiguation. A processor can populate a memory disambiguation table (MDPT) with information regarding the difference (e.g., distance) between memory locations of memory instructions, and the processor can determine that a received load instruction has an entry in the MDPT. The processor can then form a dependency between the received load instruction and a corresponding store instruction that previously conflicted with the load instruction, and the processor can predict a memory disambiguation violation. The processor can use prediction as part of a two-pass mechanism to prevent memory disambiguation violations. Thus, by using the MDPT table to track the program counter and distance information of load instructions, the processor can increase the efficiency of the store queue by effectively predicting and preventing memory disambiguation.
[0012] The details of one or more embodiments of the subject matter herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]
[0013] [Figure 1] FIG. 1 is a block diagram of an exemplary system. [Figure 2] FIG. 1 is a flow diagram of an exemplary process for entering data into an MDPT. [Figure 3] FIG. 1 is a flow diagram of an example process for performing a predictive disambiguation process. [Figure 4] FIG. 10 is a flow diagram of an example process for a two-pass mechanism for preventing memory disambiguation violations. DETAILED DESCRIPTION OF THE INVENTION
[0014] Like reference numbers and designations in the various drawings refer to like elements.
[0015] 1 illustrates an example of an exemplary system 100. System 100 is an example of a system in which the systems, components, and techniques described below may be implemented.
[0016] The system 100 includes a processor 102 coupled to a main memory 118, such as, for example, a random access memory (RAM) or a read-only memory (ROM).
[0017] Processor 102 includes a load store unit 106 and main execution logic 104. Processor 102 may perform a speculative memory disambiguation process by using load store unit 106 to process load instructions 112 received from main execution logic 104. Load instructions 112 include instructions to extract or read data and move the data from main memory 118 to processor 102.
[0018] The load store unit 106 includes a store queue 108 .
[0019] The store queue 108 can hold in-progress store instructions from a program. In some examples, the load instruction 112 also includes an address corresponding to an entry in the store queue 108 associated with the data. The store queue 108 tracks pending load instructions 112 and store instructions within a process window.
[0020] The processor 102 may perform a predictive memory disambiguation process on one or more of the entries of the load instruction 112 as part of a two-pass mechanism to prevent memory disambiguation violations. The two-pass mechanism includes a first pass that determines whether to execute the load instruction 112 based on the execution of a conflicting store instruction, and a second pass that determines whether the predictive memory disambiguation process was successful by avoiding a memory disambiguation violation. In particular, the processor 102 may use a memory disambiguation prediction table (MDPT) 110 to perform the predictive memory disambiguation process on one or more of the entries of the load instruction 112.
[0021] As will be described in more detail with reference to FIG. 2, the processor 102 can populate the MDPT 110 before performing predictive memory disambiguation processing by tracking the program counter of the load instruction 112. The program counter is a value representing the memory address of the instruction. The MDPT 110 includes the program counter of the received load instruction, a corresponding store queue difference value, and an index corresponding to the age of each load instruction. As will be described in more detail with reference to FIGS. 2, 3, and 4, the store queue difference value 116 represents the number of stores (e.g., entries for one or more store instructions) in the store queue 108 that were added after a store queue entry corresponding to a previously conflicting store. In other words, the difference value represents how many store instructions were added to the store queue after the store instruction that conflicted with the load instruction.
[0022] To perform the predictive disambiguation process, the processor 102 receives a load instruction 112 from the main execution logic 104. The load instruction 112 has a program counter and an address indicating where to read the data.
[0023] The processor 102 determines that the load instruction 112 has an entry in the MDPT 110 based on the program counter of the load instruction 112, and the processor obtains the store queue difference value 116 from the MDPT 110. The processor 102 then forms a dependency between the load instruction 112 and the conflicting store instruction indicated by the difference value. This process is described in more detail with reference to FIG. 3.
[0024] The processor 102 uses dependencies as part of a two-pass mechanism to prevent memory disambiguation violations. As part of the two-pass mechanism, the system determines whether the memory disambiguation process was successful. If the memory disambiguation process was successful, the processor 102 may retire the load instruction 112 along with the retired store 114. If the memory disambiguation process failed, the processor 102 uses the dependency information to roll back and re-execute the store instruction that conflicts with the load instruction 112.
[0025] Thus, the processor 102 forms dependencies to avoid repeated memory disambiguation violations, which can significantly improve the efficiency of the processor 102.
[0026] 2 is a flow diagram of an exemplary process for populating the MDPT. Generally, a processor populates the MDPT table by identifying memory disambiguation violations. The exemplary process can be performed by a processor suitably configured in accordance with this specification, such as, for example, processor 102 of FIG. 1.
[0027] The processor executes the store instruction and adds the store instruction to the store queue (202).
[0028] The processor determines that a newer load instruction has been executed that has the same address as the store instruction that executed before the store instruction completed (204). This situation means that the load value read by the load instruction may be outdated. Load and store instructions that access the same address (e.g., the same memory location) can have a stable distance relationship that is often encountered multiple times, especially when a code segment is repeatedly executed by the processor. Therefore, the processor can use the MDPT to track conflicting store instructions by tracking the program counter of the load instruction.
[0029] The processor determines a store queue difference value between the load instruction and the conflicting store instruction (206). The store queue difference value represents the number of entries in the store queue that were added between the load instruction and the conflicting store instruction. For example, the processor may count from the tail pointer of the store queue representing the most recent entry, sequentially through older stores, until it reaches the conflicting store queue. In some implementations, the processor calculates the difference in store queue identifiers. The store queue identifier is an index in the store queue that represents the order in which the store instructions were added. Thus, the processor may calculate the difference between the store queue identifier of the most recent entry and the store queue identifier of the conflicting store instruction.
[0030] For example, if a conflicting store instruction has a store queue identifier of 2 and there are two older entries corresponding to two other store instructions (e.g., one of the store instructions has a store identifier of 3 and the other of the store instructions has a store identifier of 4), the processor determines that the store queue differential value is 3. In other words, the store queue differential value indicates that the conflicting store instruction is the third newest entry in the store queue. Alternatively, the processor may calculate a store queue differential value of 2 to indicate that the conflicting store instruction is two entries behind the newest entry.
[0031] In some implementations, the store queue difference value represents a distance value between the reorder buffer identifier of a load instruction and the reorder buffer identifier of a conflicting store instruction. A reorder buffer is a buffer that helps a processor execute memory operations in order. The reorder buffer identifier is an index that represents the original order of execution of the load or store instructions.
[0032] The processor may populate the MDPT with the program counter value of the load instruction and the store queue difference value (208). In some implementations, the processor also stores the age of the load instruction. The age may be represented as a timestamp of the last instance that the load instruction was added to the MDPT. Then, when the MDPT is full and the processor needs to select a victim entry to replace, the processor may select the oldest entry according to the age attribute.
[0033] For example, Table 2 shows how a store instruction associated with a memory disambiguation violation has a load program counter value of 0x403200, a store queue delta value of 3, and a timestamp of 1678406405.
[0034] [Table 2]
[0035] In some examples, the processor may populate the MDPT with a hash value of the program counter value of the load instruction.
[0036] 3 is a flow diagram of an exemplary process for performing a predictive disambiguation process. For convenience, process 300 is described as being performed by a processor. For example, a processor suitably configured in accordance with this specification, such as processor 102 of FIG. 1, may perform process 300.
[0037] The processor receives a load instruction having a load value (302).
[0038] The processor determines that the load instruction has an entry in the MDPT based on the program counter of the load instruction (304). The processor retrieves the program counter from the MDPT. For example, the processor may retrieve the value 0x403200, as shown in Table 2.
[0039] The processor obtains the store queue differential value from an entry in the MDPT 306. For example, the processor may obtain a store queue differential value of 3 that is mapped to a program counter value of 0x403200, as shown in Table 2.
[0040] Next, the processor creates a dependency between the load instruction and the conflicting store instruction (308).
[0041] Specifically, the processor determines a predicted store queue identifier for the store instruction based on the store queue difference value. By identifying the conflicting store instruction, the processor can form a dependency relationship between the load instruction and the conflicting store instruction.
[0042] A dependency between a load instruction and a conflicting store instruction can prevent memory disambiguation violations. Specifically, the dependency causes the processor to execute the load instruction only after the conflicting store instruction has completed (e.g., after the processor has completed execution of the store instruction in the store queue).
[0043] 4 is a flow diagram of an exemplary process for a two-pass mechanism for preventing memory ambiguity violations. For convenience, process 400 is described as being performed by a processor. For example, a processor suitably configured in accordance with this specification, such as processor 102 of FIG. 1, may perform process 400.
[0044] The processor reads the load instruction in an instruction dispatch (402). The processor searches for a corresponding segment of code in the program that executes the load instruction while the program's instructions are in order (e.g., before the processor performs OOO execution).
[0045] The processor determines whether the load instruction is present in the MDPT (404). The processor may use the program counter of the load instruction to search for the entry of the load instruction in the MDPT.
[0046] If the processor determines (404) that the load instruction is not present in the MDPT, the processor may execute the load instruction normally (branch to 408).
[0047] If the processor determines that a load instruction is present in the MDPT (404), the processor determines whether the corresponding store instruction has completed (406). The processor may first identify the corresponding store instruction in the store queue using the store queue difference value. Because the store queue difference value indicates the number of store instructions added to the store queue after the conflicting store instruction and before the load instruction is executed, the processor may count the number of entries from the current head of the store queue to reach the entry corresponding to the store queue difference value.
[0048] If the processor determines 406 that the corresponding store instruction has not completed, the processor forms a load instruction dependency 410. The load instruction dependency ensures that the load instruction is not executed until the corresponding store instruction has completed.
[0049] Dependencies of load instructions can be enforced in several ways. For example, the processor can reissue the load instruction to the load-store unit. The processor can recycle the load instruction until the corresponding store completes. Specifically, the processor issues a load instruction to the load-store unit, and the processor refrains from executing the load instruction until the processor executes the corresponding store instruction.
[0050] Alternatively or additionally, the load store unit may block the load instruction until the corresponding store instruction has completed, e.g., the processor may only initiate the load instruction once the corresponding store instruction has completed.
[0051] One advantage of the techniques described herein is that load instructions are blocked only by the load-store unit, rather than the processor's entire issue queue, so other instructions are not blocked indefinitely by the blocked load instruction.
[0052] Once the store instruction has completed, the processor executes the load instruction 408. The load instruction is guaranteed to read the updated data when the corresponding store instruction has completed.
[0053] After executing the load instruction (408), the processor determines whether there was a memory disambiguation failure (412). In other words, the processor determines whether an older store was fetching data from the same address while the load instruction was executing. For example, this can occur if the load instruction is first encountered without the load instruction being represented in the MDPT yet. On the other hand, if the processor formed a dependency for the load instruction, there should be no MD violation.
[0054] If the processor determines that there was a memory disambiguation failure, the processor cancels and re-executes the load instruction and updates the MDPT 416. The processor can cancel all instructions that depended on the potentially stale data read by the load instruction, and re-executes the load instruction and all instructions that depended on it.
[0055] The processor can then populate the MDPT according to the MD failure event. For example, the processor can create a new entry in the MDPT that contains the program counter of the load instruction and the store queue difference value of the conflicting store instruction. Then, when the processor encounters a load instruction, it can process the load instruction by introducing a dependency relationship rather than immediately executing the load instruction.
[0056] If the processor determines that there was no MD failure, the processor retires the load instruction (414).
[0057] Embodiments of the subject matter and functional operations described herein can be implemented in digital electronic circuitry, tangibly embodied computer software or firmware, or computer hardware, including the structures disclosed herein and their structural equivalents, or one or more combinations thereof. Embodiments of the subject matter described herein can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a tangible, non-transitory storage medium for execution by or controlling the operation of a data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random-access or serial-access memory device, or one or more combinations thereof. Alternatively, or in addition, the program instructions can be encoded on an artificially generated transmitted signal, such as a machine-generated electrical, optical, or electromagnetic signal generated to encode information for transmission to an appropriate receiver apparatus for execution by a data processing apparatus.
[0058] The term "data processing apparatus" refers to data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing data, including, by way of example, a programmable processor, a computer, or multiple processors or multiple computers. An apparatus may be or further include special-purpose logic circuitry, such as an FPGA (field-programmable gate array) or an ASIC (application-specific integrated circuit). An apparatus optionally includes, in addition to hardware, code that creates an execution environment for a computer program (e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof).
[0059] A computer program, which may be called or described as a program, software, software application, app, module, software module, script, or code, can be written in any form of programming language, including compiled or interpreted, declarative or procedural, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. A program can be stored in part of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program, or in multiple cooperating files, e.g., files that store one or more modules, subprograms, or portions of code. A computer program can be deployed to run on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a data communications network.
[0060] The processes and logic flows described herein may be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows may also be performed by special purpose logic circuitry, such as an FPGA or an ASIC, or a combination of special purpose logic circuitry and one or more programmed computers.
[0061] A computer suitable for executing a computer program can be based on a general-purpose or special-purpose microprocessor, or both, or any other type of central processing unit. Typically, the central processing unit receives instructions and data from a read-only memory or a random-access memory, or both. The basic components of a computer are a central processing unit for executing instructions and one or more memory devices for storing instructions and data. The central processing unit and memory may be supplemented by, or incorporated in, special-purpose logic circuitry. Typically, a computer also includes, or is operatively coupled to, one or more mass storage devices for storing data, such as, for example, magnetic, magneto-optical, or optical disks. However, a computer need not include such devices. Furthermore, a computer can be incorporated in other devices, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device, such as a universal serial bus (USB) flash drive, to name just a few.
[0062] Computer-readable media suitable for storing computer program instructions and data include all types of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices, magnetic disks such as internal hard disks or removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks.
[0063] In addition to the above embodiments, the following embodiments are also innovative.
[0064] Embodiment 1 is a method for performing a predictive memory disambiguation process in a processor, the method including: receiving a load instruction having a load value; determining, based on a program counter of the load instruction, that the load instruction has an entry in a memory disambiguation table (MDPT); obtaining, from the entry in the MDPT, a store queue difference value that identifies a conflicting store instruction that previously conflicted with the load instruction; and forming a dependency relationship between the load instruction having an entry in the MDPT and the conflicting store instruction.
[0065] Embodiment 2 is the method of embodiment 1, wherein the store queue difference value represents a number of entries in the store queue that were added after the conflicting store instruction.
[0066] Embodiment 3 is the method of embodiment 1, wherein the store queue difference value represents a difference between a reorder buffer identifier of the load instruction and a reorder buffer identifier of the conflicting store instruction.
[0067] A fourth embodiment is the method according to any one of the first to third embodiments, wherein the dependency relationship causes the processor to execute the load instruction after the conflicting store instruction.
[0068] Embodiment 5 is a method according to any one of embodiments 1 to 4, wherein forming a dependency between the load instruction having an entry in the MDPT and the conflicting store instruction causes the load instruction to complete after the conflicting store instruction.
[0069] Embodiment 6 is a method according to any one of embodiments 1 to 5, further comprising: executing a store instruction having a store value; determining, before executing the store instruction, that a load value of an older load instruction having the same address is present in the store queue; determining a store queue difference value between the load value and the store value; and inputting the value of the program counter of the load instruction, the store queue difference value between the load value and the store value, and the elapsed time of the load value into the MDPT.
[0070] Example 7 is the method of example 6, further comprising: canceling the load instruction; and re-executing the load instruction.
[0071] An eighth embodiment is the method according to any one of the first to seventh embodiments, wherein forming the dependency includes blocking the load instruction until the store instruction is completed.
[0072] A ninth embodiment is the method according to any one of the first to seventh embodiments, in which forming the dependency includes reissuing the load instruction until the store instruction is completed.
[0073] Embodiment 10 is a method according to any one of embodiments 1 to 9, further comprising determining that the predictive memory disambiguation process is successful and retiring the load value of the load instruction from the store queue.
[0074] An eleventh embodiment is a system including a processor, the processor being configured to execute the method according to any one of the first to tenth embodiments.
[0075] Embodiment 12 is one or more storage media storing instructions operable, when executed by a data processing device, to cause the data processing device to perform the method according to any one of embodiments 1 to 10.
[0076] While the specification contains many specific implementation details, these should not be construed as limiting the scope of any invention or the scope of patentable subject matter, but rather as descriptions of features that may be unique to particular embodiments of a particular invention. Certain features described herein as separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented in multiple embodiments, either separately or in any suitable subcombination. Furthermore, even if features may be described above as functioning in a particular combination and originally claimed as such, one or more features from a claimed combination may, in some cases, be deleted from the combination, and the claimed combination may be directed to subcombinations or variations of the subcombination.
[0077] Similarly, while operations are illustrated in the figures and described in the claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order or sequential order shown, or that all of the operations shown be performed, to achieve desirable results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the program components and systems described may generally be integrated into a single software product or packaged into multiple software products.
[0078] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims may be performed in a different order and still produce desirable results. By way of example, the processes depicted in the accompanying figures do not necessarily require the particular order shown or sequential order to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.
Claims
1. 1. A method for performing a predictive memory disambiguation process on a processor, comprising: receiving a load instruction having a load value; determining, based on a program counter of the load instruction, that the load instruction has an entry in a memory disambiguation table (MDPT); obtaining a store queue difference value from the entry in the MDPT that identifies a conflicting store instruction that previously conflicted with the load instruction; forming a dependency between the load instruction and the conflicting store instruction having an entry in the MDPT; A method comprising:
2. The method of claim 1 , wherein the store queue difference value represents a number of entries in a store queue that were added after the conflicting store instruction.
3. 2. The method of claim 1, wherein the store queue difference value represents a difference between a reorder buffer identifier of the load instruction and a reorder buffer identifier of the conflicting store instruction.
4. The method of any one of claims 1 to 3, wherein the dependency causes the processor to execute the load instruction after the conflicting store instruction.
5. 5. The method of claim 1, wherein forming a dependency between the load instruction having an entry in the MDPT and the conflicting store instruction causes the load instruction to complete after the conflicting store instruction.
6. Executing a store instruction with a store value; determining, prior to executing the store instruction, that a load value of an older load instruction having the same address is present in the store queue; determining a store queue difference value between the load value and the store value; inputting the program counter value of the load instruction, the store queue difference value between the load value and the store value, and the elapsed time of the load value into the MDPT; The method of any one of claims 1 to 5, further comprising:
7. Canceling the load instruction; re-executing the load instruction; The method of claim 6 further comprising:
8. forming the dependency relationship A method according to any preceding claim, comprising blocking the load instruction until the store instruction has completed.
9. The method of any one of claims 1 to 7, wherein forming the dependency includes reissuing the load instruction until the store instruction completes.
10. determining that the predictive memory disambiguation process was successful; and retiring the load value of the load instruction from the store queue; The method of any one of claims 1 to 9, further comprising:
11. A system comprising a processor, said processor being configured to perform the method of any one of claims 1 to 10.
12. One or more storage media storing instructions operable, when executed by a data processing apparatus, to cause said data processing apparatus to perform the method of any one of claims 1 to 10.