SARS multi-channel memory

Abstract

A bonded structure is disclosed. The bonded structure may include a carrier. The bonded structure may include a first memory unit disposed on the carrier, the first memory unit including a first memory channel and a first plurality of memory dies directly hybrid bonded to each other. The bonded structure may further include a second memory unit including a second memory channel different from the first memory channel and a second plurality of memory dies directly hybrid bonded to each other. The second memory unit may be stacked on the first memory unit. The bonded structure may include a serializer-deserializer disposed in or on the carrier and electrically connected to the first and second memory channels of the first and second memory units. The serializer-deserializer may have an external channel configured to electrically connect the bonded structure to a processor.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to semiconductor device structures and methods, and some embodiments relate to multi-channel memories.

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 487,824, filed March 1, 2023, which is incorporated by reference in its entirety. [Background technology]

[0003] The approaches described in this section are approaches that could be achieved, but not necessarily approaches that have been conceived or achieved in the prior art. Thus, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their incorporation into this section.

[0004] Multiple semiconductor devices may be stacked in various applications, such as high bandwidth memory. Summary of the Invention

[0005] For purposes of outlining the disclosure and the advantages achieved over the prior art, certain specific objects and advantages of the disclosure are described herein. Not all such objects or advantages may be achieved in any particular embodiment. Thus, for example, as will be recognized by those skilled in the art, the invention can be embodied or practiced in a way that achieves or optimizes one advantage or group of advantages taught herein, without necessarily achieving other objects or advantages that may be taught or suggested herein.

[0006] All of these embodiments are within the scope of the invention disclosed herein. These and other embodiments will be readily apparent to those skilled in the art from the following detailed description of the preferred embodiments, which refers to the accompanying drawings, and the invention is not limited to any particular preferred embodiment disclosed.

[0007] In one embodiment, the bonded structure may include a carrier and a first memory unit disposed on the carrier, the first memory unit including a first memory channel, the first memory unit including a first plurality of memory dies directly hybrid bonded to each other, the bonded structure may include a second memory unit including a second memory channel different from the first memory channel, the second memory unit including a second plurality of memory dies directly hybrid bonded to each other, the second memory unit being stacked on top of the first memory unit, the bonded structure may include a serializer-deserializer disposed in or on the carrier and electrically connected to the first and second memory channels of the first and second memory units, the serializer-deserializer having an external channel configured to electrically connect the bonded structure to a processor.

[0008] In some embodiments, the carrier includes a logic die. In some embodiments, the bonded structure further includes a logic die, the carrier includes an interposer, and the logic die is disposed between the first memory unit and the interposer. In some embodiments, the bonded structure includes an encapsulant and the logic die, the carrier includes a redistribution layer, and the logic die is disposed between the first memory unit and the redistribution layer, and the first memory unit, the second memory unit, the logic die, and the serializer-deserializer are partially encapsulated in the encapsulant. In some embodiments, the bonded structure includes the logic die, and the carrier includes a printed circuit board (also called a printed wiring board), and the logic die is disposed between the first memory unit and the printed circuit board.

[0009] In some embodiments, the first memory unit is direct hybrid bonded to the second memory unit, in some embodiments, the first memory unit is direct hybrid bonded to the carrier, and in some embodiments, the serializer-deserializer is direct hybrid bonded to the carrier.

[0010] In another embodiment, a structure can have a first memory unit with a top surface and a bottom surface, the first memory unit including a first plurality of memory dies directly hybrid bonded to one another, the structure can have a second memory unit with a top surface and a bottom surface, the second memory unit including a second plurality of memory dies directly hybrid bonded to one another, the structure can have a logic die with a top surface and a bottom surface, and a serializer-deserializer with a top surface and a bottom surface, the second memory unit including a second plurality of memory dies directly hybrid bonded to one another, a bottom surface of the memory unit disposed on the top surface of the first memory unit, a bottom surface of the first memory unit disposed on the top surface of the logic die, a bottom surface of the serializer-deserializer disposed on the top surface of the logic die, the structure having a first number of internal channels electrically connecting the serializer-deserializer, the logic die, the first memory unit, and the second memory unit to each other, and the structure having a second number of external channels configured to electrically connect the structure to the processor, the first number being greater than the second number.

[0011] In some embodiments, the first number of internal channels is 2 and the second number of external channels is 1. In some embodiments, the technology described herein relates to a structure where the first number of internal channels is 4 and the second number of external channels is 1. In some embodiments, the second memory unit is direct hybrid bonded to the first memory unit.

[0012] In some embodiments, the first memory unit is direct hybrid bonded to the logic die. In some embodiments, the serializer-deserializer is direct hybrid bonded to the logic die. In some embodiments, the first internal channel is electrically connected to the active circuitry of the first memory unit, the second internal channel is electrically connected to the active circuitry of the second memory unit, and the second internal channel is not electrically connected to the active circuitry of the first memory unit.

[0013] In another embodiment, a structure can have a first memory unit with a top surface and a bottom surface, the first memory unit including a first plurality of memory dies directly hybrid bonded to one another, the structure can have a second memory unit with a top surface and a bottom surface, the second memory unit including a second plurality of memory dies directly hybrid bonded to one another, the structure can have a logic die with a top surface and a bottom surface, an interposer with a top surface and a bottom surface, and a serializer-deserializer with a top surface and a bottom surface, the second memory unit a bottom surface of the interposer disposed on the top surface of the first memory unit, a bottom surface of the first memory unit disposed on the top surface of the logic die, a bottom surface of the logic die disposed on the top surface of the interposer, a bottom surface of the serializer-deserializer disposed on the top surface of the interposer, the structure having a first number of internal channels electrically connecting the serializer-deserializer, the logic die, the first memory unit, and the second memory unit to each other, and the structure having a second number of external channels configured to electrically connect the structure to the processor, the first number being greater than the second number.

[0014] In some embodiments, the first number of internal channels is 2 and the second number of external channels is 1. In some embodiments, the first number of internal channels is 4 and the second number of external channels is 1.

[0015] In some embodiments, the second memory unit is direct hybrid bonded to the first memory unit. In some embodiments, the first memory unit is direct hybrid bonded to the logic die. In some embodiments, the serializer-deserializer is direct hybrid bonded to the interposer. In some embodiments, the logic die is direct hybrid bonded to the interposer.

[0016] In some embodiments, the first internal channel is electrically connected to the active circuitry of the first memory unit, the second internal channel is electrically connected to the active circuitry of the second memory unit, and the second internal channel is not electrically connected to the active circuitry of the first memory unit.

[0017] In some further embodiments, a structure can include a first memory unit having a top surface and a bottom surface, the first memory unit including a first plurality of memory dies directly hybrid bonded to one another, the structure can include a second memory unit having a top surface and a bottom surface, the second memory unit including a second plurality of memory dies directly hybrid bonded to one another, the structure can include a logic die having a top surface and a bottom surface, a redistribution layer, and a serializer-deserializer having a top surface, a bottom surface, and an encapsulant, the bottom surface of the second memory unit being disposed on the top surface of the first memory unit, the bottom surface of the first memory unit being disposed on the top surface of the logic die, the first memory unit, the second memory unit, the logic The logic die and the serializer-deserializer are at least partially encapsulated in an encapsulant, a top surface of the logic die and a top surface of the serializer-deserializer are exposed, a redistribution layer is formed covering the top surface of the serializer-deserializer and the top surface of the logic die, the redistribution layer electrically connects the serializer-deserializer and the logic die, and the redistribution layer is configured to electrically connect the serializer-deserializer to a processor, the structure has a first number of internal channels electrically connecting the serializer-deserializer, the logic die, the first memory unit, and the second memory unit to each other, and the structure has a second number of external channels configured to electrically connect the structure to the processor, the first number being greater than the second number.

[0018] In some embodiments, the first number of internal channels is 2 and the second number of external channels is 1. In some embodiments, the first number of internal channels is 4 and the second number of external channels is 1. In some embodiments, the second memory unit is direct hybrid bonded to the first memory unit. In some embodiments, the first memory unit is direct hybrid bonded to the logic die.

[0019] In some embodiments, the redistribution layer is evaporated. In some embodiments, the redistribution layer is direct hybrid bonded to the logic die and the serializer-deserializer.

[0020] In some embodiments, the first internal channel is electrically connected to the active circuitry of the first memory unit, the second internal channel is electrically connected to the active circuitry of the second memory unit, and the second internal channel is not electrically connected to the active circuitry of the first memory unit.

[0021] In another embodiment, a structure can have a first memory unit having a top surface and a bottom surface, the first memory unit including a first plurality of memory dies direct hybrid bonded to one another, the structure can have a second memory unit having a top surface and a bottom surface, the second memory unit including a second plurality of memory dies direct hybrid bonded to one another, the structure can have a logic die having a top surface and a bottom surface, a substrate, and a serializer-deserializer having a top surface and a bottom surface, the bottom surface of the second memory unit being a first memory unit. a logic die, a top surface of the logic die, a bottom surface of the first memory unit, the top surface of the logic die, the bottom surface of the logic die, the bottom surface of the substrate, the serializer-deserializer embedded in the substrate, the serializer-deserializer electrically connected to the logic die, the structure having a first number of internal channels electrically connecting the serializer-deserializer, the logic die, the first memory unit, and the second memory unit to each other, the structure having a second number of external channels configured to electrically connect the structure to a processor, the first number being greater than the second number.

[0022] In some embodiments, the first number of internal channels is 2 and the second number of external channels is 1. In some embodiments, the first number of internal channels is 4 and the second number of external channels is 1.

[0023] In some embodiments, the second memory unit is directly hybrid bonded to the first memory unit, and in some embodiments, the first memory unit is directly hybrid bonded to the logic die.

[0024] In some embodiments, the first internal channel is electrically connected to the active circuitry of the first memory unit, the second internal channel is electrically connected to the active circuitry of the second memory unit, and the second internal channel is not electrically connected to the active circuitry of the first memory unit. In some embodiments, the substrate includes a printed circuit board.

[0025] In another embodiment, a bonded structure can include a carrier and a first memory unit disposed on the carrier, the first memory unit including a first memory channel and a first plurality of memory dies directly hybrid bonded to each other, the bonded structure can include a second memory unit including a second memory channel different from the first memory channel and a second plurality of memory dies directly hybrid bonded to each other, the second memory unit being stacked on top of the first memory unit, the bonded structure can include a serializer-deserializer directly hybrid bonded to the carrier and electrically connected to the first and second memory channels of the first and second memory units, the serializer-deserializer having an external channel configured to electrically connect the bonded structure to a processor.

[0026] In some embodiments, the bonded structure has a first plurality of internal channels electrically connecting the serializer-deserializer, the carrier, the first memory unit, and the second memory unit to one another, and a second number of external channels configured to electrically connect the structure to the processor, the first number being different from the second number.

[0027] In some embodiments, the carrier includes a logic die. In some embodiments, the bonded structure further includes a logic die, the carrier includes an interposer, and the logic die is disposed between the first memory unit and the interposer. In some embodiments, the bonded structure further includes an encapsulant and a logic die, the carrier includes a redistribution layer, and the logic die is disposed between the first memory unit and the redistribution layer, and the first memory unit, the second memory unit, the logic die, and the serializer-deserializer are partially encapsulated in the encapsulant. In some embodiments, the bonded structure further includes a logic die, the carrier includes a printed circuit board, and the logic die is disposed between the first memory unit and the printed circuit board.

[0028] In some embodiments, the first memory unit is direct hybrid bonded to the second memory unit, hi some embodiments, the first memory unit is direct hybrid bonded to the carrier.

[0029] In another embodiment, a bonded structure may include a carrier and a first memory unit including a first memory channel and a second memory channel different from the first memory channel, the second memory unit being stacked on top of the first memory unit, the first memory unit and the second memory unit being provided on the carrier, the first memory unit including a first plurality of memory dies directly hybrid bonded to each other, the second memory unit including a second plurality of memory dies directly hybrid bonded to each other, a serializer-deserializer provided on or at least partially embedded in the carrier and electrically connected to the first and second memory channels of the first and second memory units, the serializer-deserializer having an external channel configured to electrically connect the bonded structure to a processor.

[0030] In some embodiments, the bonded structure has a first number of internal channels electrically connecting the serializer-deserializer, the carrier, the first memory unit, and the second memory unit to each other, and a second number of external channels configured to electrically connect the bonded structure to the processor, the first number being different from the second number. In some embodiments, the serializer-deserializer is hybrid bonded to the carrier.

[0031] In some embodiments, the carrier includes a logic die. In some embodiments, the bonded structure further includes a logic die, the carrier includes an interposer, and the logic die is disposed between the first memory unit and the interposer. In some embodiments, the bonded structure further includes an encapsulant and a logic die, the carrier includes a redistribution layer, and the logic die is disposed between the first memory unit and the redistribution layer, and the first memory unit, the second memory unit, the logic die, and the serializer-deserializer are partially encapsulated in the encapsulant. In some embodiments, the bonded structure further includes a logic die, the carrier includes a printed circuit board, and the logic die is disposed between the first memory unit and the printed circuit board.

[0032] In some embodiments, the first memory unit is direct hybrid bonded to the second memory unit, hi some embodiments, the first memory unit is direct hybrid bonded to the carrier.

[0033] These and other features, aspects, and advantages of the present disclosure will be described with reference to drawings of certain embodiments, which are intended to illustrate, but not limit, the present disclosure. It should be understood that the accompanying drawings, which are incorporated into and form a part of this specification, are for the purpose of illustrating the concepts disclosed herein and are not drawn to scale. [Brief explanation of the drawings]

[0034] [Figure 1] 1 is a schematic diagram of a prior art implementation of a high bandwidth memory; [Figure 2] FIG. 1 is a schematic diagram of another prior art high-bandwidth memory implementation; [Figure 3] FIG. 1 is a diagram illustrating an example of a multi-channel memory module. [Figure 4] FIG. 1 is a schematic diagram illustrating an example of a multi-channel memory utilizing a serializer-deserializer according to some embodiments. [Figure 5A] FIG. 1 is a schematic diagram illustrating another example of a multi-channel memory utilizing a serializer-deserializer according to some embodiments. [Figure 5B] FIG. 1 is a schematic diagram illustrating another example of a multi-channel memory utilizing a serializer-deserializer according to some embodiments. [Figure 5C] FIG. 1 is a schematic diagram illustrating another example of a multi-channel memory utilizing a serializer-deserializer according to some embodiments. [Figure 5D] FIG. 1 is a schematic diagram illustrating another example of a multi-channel memory utilizing a serializer-deserializer according to some embodiments. [Figure 6A] FIG. 1 is a diagram illustrating a direct bonding process according to some embodiments. [Figure 6B] FIG. 1 is a diagram illustrating a direct bonding process according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0035] Although several embodiments, examples, and illustrations are disclosed below, those skilled in the art will understand that the invention described herein extends beyond the specifically disclosed embodiments, examples, and illustrations and also includes other uses of the invention and obvious modifications and equivalents thereof. Examples of the invention are described with reference to the drawings of the invention, where like reference numerals refer to like elements throughout the specification. The terminology used in the description provided herein is not intended to be construed in any limited or restrictive manner, simply because it is used in connection with the detailed description of several specific embodiments of the invention. In addition, embodiments of the invention may have several novel features, and no single feature is solely responsible for desirable attributes or is essential to practicing the invention described herein.

[0036] There is a high demand for higher memory bandwidth and higher memory capacity. Providing high-speed, high-bandwidth connectivity between memory and processors can be important for some applications. For example, when training artificial intelligence or machine learning models, performing complex graphics manipulations, or other data-intensive tasks, processors such as central processing units (CPUs), graphical processing units (GPUs), field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc., may spend significant amounts of time in an idle state waiting for data, which can negatively impact performance and increase the time it takes to complete computing tasks.

[0037] Conventional high-bandwidth memory (HBM) implementations use stacked memory located near the processor. For example, memory dies (e.g., dynamic random access memory (DRAM) dies) may be stacked on top of each other and connected to a memory controller in the processor (e.g., a GPU or CPU) via a carrier (e.g., a silicon interposer). In some implementations, a controller die may also be present in the stack. A typical HBM stack may include multiple (e.g., four) DRAM dies and a logic layer (e.g., a controller die). In some implementations, the memory dies may be stacked directly on the processor and connected to the processor using through-silicon vias.

[0038] HBM offers several advantages over technologies that use discrete memory socketed or soldered to a PCB. For example, it can lower power consumption, reduce form factors, and significantly increase bandwidth. However, current HBM implementations have several drawbacks and limitations. For example, memory dies are typically fabricated separately, with contact pads formed on the memory die. The contact pad dimensions may be, for example, approximately 25 micrometers, with a pitch of approximately 55 micrometers. These large feature sizes may limit the total number of interconnects that can be formed in a given area. Additionally, to achieve high bandwidth and low latency, it is important to place the memory die as close as possible to the processor. For example, while socketed memory in a desktop or server may be several centimeters away from the processor, HBM modules are typically within a few millimeters of the processor; greater distances may significantly degrade performance. These limitations may negatively impact both HBM capabilities and available bandwidth.

[0039] FIG. 1 illustrates a conventional HBM 100 approach in which stacked memory modules 102 (e.g., four stacked memory modules) are arranged around a processor 104 (e.g., a CPU or GPU). FIG. 2 illustrates another HBM 200 implementation using a similar approach to that shown in FIG. 1. However, the implementation shown in FIG. 2 suffers from a significant drawback. While the number of memory modules 102 (e.g., memory stacks) doubles from FIG. 1 to FIG. 2, the additional memory modules 102 are located a greater distance from the processor 104, thereby negatively impacting performance. Thus, there is a need for an approach that can increase memory capacity while maintaining or even improving performance.

[0040] Some implementations described herein can significantly improve HBM bandwidth, capacity, or both. Advantageously, some embodiments herein can improve bandwidth, capacity, or both without requiring a large area, significantly increasing the distance between the processor and the memory die, and / or significantly impacting power consumption.

[0041] One approach may be to vertically stack HBM memory units (e.g., a stack of four DRAM dies) on top of each other, as described in U.S. Patent Application No. 18 / 052,399, filed November 3, 2022, which is incorporated herein by reference in its entirety. Two or more memory units may be stacked on top of each other to form a memory module. To support a large number of memory units in a single memory module using a large number of input / output connections, small contacts and a small pitch may be important. Therefore, rather than forming connections using relatively large metal bumps as in conventional approaches, electrical connections between components of the memory module may be bonded using direct hybrid bonding, as described in detail herein.

[0042] FIG. 3 illustrates an example embodiment of a memory module 302 (e.g., an HBM module) having two memory units 306, each of which includes multiple (e.g., four) memory dies (e.g., DRAM dies) 308 hybrid-bonded and stacked together. As shown in FIG. 3, the memory units 306 may be stacked one on top of the other and may be stacked on a logic layer 310. The memory module 302 may be electrically connected to a processor 304 (e.g., a CPU or GPU). This design may increase density and bandwidth by utilizing modifications to the processor 304 since the number of input / output connections has doubled (and may triple, quadruple, etc., depending on how many memory units are stacked together to form the memory module).

[0043] In some embodiments, it may be desirable to increase memory capacity without requiring an increase in the number of input / output connections to the processor. This simplifies the interconnects and reduces or eliminates the need to modify the processor design to accommodate memory modules with different input / output connections than more traditional HBM modules. Therefore, some implementations may use a serializer-deserializer (SerDes) in place between the processor 304 and the memory 306. In some implementations, the SerDes may be integrated into the multi-channel memory module, although not all implementations may have the SerDes as part of the memory module. To the processor 304, the multi-channel memory module 302 appears and behaves as a traditional HBM design example processor 304 with a single channel.

[0044] Such an approach offers several advantages. In addition to being provided as a single module, the memory module 302 may be configured to utilize multiple internal channels to improve performance. For example, a memory module 302 with two memory units 306 may have two internal channels 314, one connected to the first memory unit 306a and the other connected to the second memory unit 306b. In some embodiments, the module may be configured to read and write from both memory units simultaneously. Thus, with two memory units 306a, the module's internal bandwidth can be significantly increased, e.g., nearly doubled.

[0045] FIG. 4 illustrates an exemplary multi-channel memory module 402 according to some embodiments. In FIG. 4, the memory module 402 includes two memory units 406 (e.g., a first memory unit 406a and a second memory unit 406b), each including four memory (e.g., DRAM) dies 408 hybrid-bonded to one another. The memory dies 408 may also be stacked on top of one another. The first memory unit 406a may have a top surface 430 and a bottom surface 432 opposite the top surface 430. The second memory unit 406b may have a top surface 434 and a bottom surface 436 opposite the top surface 434. The memory units 406 may be vertically stacked on top of a logic die 410 (e.g., a memory controller configured to manage the flow of data to and from the memory units). The logic die 410 may have a top surface 438 and a bottom surface 440. In some embodiments, the bottom surface 436 of the second memory unit 406b may be disposed on the top surface 430 of the first memory unit 406a. Additionally, the bottom surface 432 of the first memory unit 406a may be disposed on the top surface 438 of the logic die 410.

[0046] A SerDes 412 may be provided in the memory module 402, positioned in the electrical path between the memory units 406 and the processor 404. The SerDes 412 may receive signals (e.g., data) from both memories 406 and combine the data into a single stream, which may then be sent to the processor 404. In some embodiments, the SerDes 412 may accept a single stream from the processor 404, and the memory controller 410 (e.g., the logic shown in FIG. 4) may be configured to split and transmit the data to the memory units 406. The SerDes 412 may have a top surface 442 and a bottom surface 444 opposite the top surface 442. In some embodiments, the bottom surface 444 of the SerDes 412 may be provided on the top surface 438 of the logic die 410.

[0047] Because a large number of interconnects are present, for example, in the memory module 402 shown in FIG. 4, it can be important to provide small feature sizes (e.g., small contact pads and small pitch). For example, in the example configuration shown in FIG. 4, one externally connected channel 414 (e.g., for coupling to a processor) and two internal channels 416 (e.g., one channel for each memory unit) can be provided. Adding more memory units can significantly increase the number of interconnects. For example, there can be two internal channels for each external channel, or another ratio, such as 4:1, 8:1, 16:1, 32:1, etc. In general, the number of internal channels can be greater than the number of external channels. In some embodiments, direct hybrid bonding can be used to bond components of the memory module 402 (e.g., to bond the DRAM dies 408 to each other, bond the memory units 406 to each other, bond the memory units 406 to the logic die 410, bond the SerDes 412 to the logic die 410, etc.).

[0048] Multi-channel memory can be implemented using various approaches. Figures 5A-5D show an example implementation of a multi-channel memory using SerDes 512. In Figure 5A, memory units 506 are stacked on top of logic die 510. SerDes 512 is attached (e.g., direct hybrid bonded) to logic die 510, and signals between processor 504 and memory units 506 pass through SerDes 512. In Figure 5B, memory module 502 can include memory units 506 and logic units 510, and SerDes 512 can be mounted on interposer 512 outside memory module package 520. Interposer 518 can have a top surface 546 and a bottom surface 548 opposite top surface 546. The interposer 518 may comprise any suitable type of interposer, such as a semiconductor or dielectric substrate, an integrated device die or wafer, a reconfigurable element (e.g., one or more encapsulated dies with routing and bonding layers implemented), a package substrate with a direct bonding layer applied, etc. The memory module 502 may be bonded (e.g., direct hybrid bonded) to the interposer 518. A bottom surface 540 of the logic die 510 may be disposed on a top surface 546 of the interposer. Additionally, a bottom surface 544 of the serializer-deserializer 512 may be disposed on a top surface 548 of the interposer. As in FIGS. 5A and 5B , signals between the processor 504 and the memory unit 506 may pass through the SerDes 512.

[0049] FIG. 5C illustrates an example of a fan-out package according to some embodiments. Unless otherwise noted, components in FIG. 5C may be identical or nearly identical to identically numbered components in FIGS. 5A-5C, and these components may combine and / or operate in a generally similar manner. The fan-out package enables the connection of memory units to an interface, such as a processor. The fan-out configuration may be designed to optimize the transfer of data between the memory units and an external memory controller or host system. In FIG. 5C, a memory stack 522 (i.e., a memory module) may include memory units 506 and a logic die 510. The memory stack 522 may be embedded in an encapsulant 524. The SerDes 512 may also be embedded in the encapsulant 524. In various embodiments, the encapsulant 524 may be comprised of one or multiple dielectric layers, such as one or multiple inorganic dielectric layers (e.g., silicon oxide, silicon nitride, silicon oxycarbonitride, etc.). In some embodiments, the encapsulant 524 may be comprised of an organic insulating material, such as molding compound or epoxy. A redistribution layer 526 may be formed (e.g., deposited) over the exposed surface of the SerDes 512 and the logic die 510, thereby providing electrical connections between the SerDes 512 and the logic die 510, as well as external connections that interface with the processor 504. In some embodiments, the redistribution layer 526 may be deposited or direct hybrid bonded (e.g., by a transfer bonding process). In FIG. 5D , the SerDes 512 may be embedded in a substrate 528 (e.g., a printed circuit board). The substrate 528 may be comprised of an organic, ceramic, or inorganic substrate and may include a cavity that can accommodate the SerDes element 512. A memory module 502, which may include the logic die 510 and memory unit 506, may be electrically connected to the SerDes 512, which may be connected to the processor 504.

[0050] As mentioned above, the use of serializer-deserializers (SerDes) in place between any of the processors and memories described herein can improve the performance of multi-channel modules because they can look and behave like a traditional HBM module design with a single channel. Memory modules are preferably configured to utilize multiple internal channels to improve performance. Memory modules can simultaneously read and write from two or more memory units, thus increasing the internal bandwidth of the memory module.

[0051] Direct Bonding Various embodiments disclosed herein relate to direct-bonded structures in which two or more elements can be directly bonded to one another without an intervening adhesive. Such processes and structures are referred to herein as "direct bonding" processes or "direct-bonded" structures. Direct bonding allows for the bonding of one material on one element to one material on another element without traditional adhesives (also referred to herein as a "homogeneous" direct bond), in which case the materials on the different elements do not need to be identical. Direct bonding also allows for the bonding of multiple materials on one element to multiple materials on another element (e.g., hybrid bonding).

[0052] In some embodiments (not shown), each bonding layer comprises a single material. In these uniform direct bonding processes, only one material on each component is directly bonded. Exemplary uniform direct bonding processes include ZIBOND® technology, commercially available from Adeia, Inc., San Jose, California. The materials of opposing bonding layers on different components can be the same or different, and these materials can be elemental or compound. For example, in some implementations, a non-conductive bonding layer can be a blanket deposited on a base substrate portion without patterning conductive features (e.g., pad-less). In other embodiments, bonding layers can be patterned on one or both components, and these bonding layers can be the same or different, but one material on each component is directly bonded across the entire surface of the component (or across the entire surface of the smaller component if the components are of different sizes) without adhesive. In another embodiment of uniform direct bonding, one or both of the non-conductive bonding layers may include one or more conductive features, but the conductive features are not included during bonding. For example, in some embodiments, opposing non-conductive bonding layers may be uniformly direct bonded to each other, and after bonding, through-substrate vias (TSVs) may then be formed through one of the devices, thereby enabling electrical communication to the other device.

[0053] In various embodiments, bonding layers 608a and / or 608b may be comprised of a non-conductive material, such as a dielectric or undoped semiconductor material, e.g., undoped silicon, including native oxides. Dielectric bonding surfaces or materials suitable for direct bonding include, but are not limited to, inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or materials containing carbon, such as silicon carbide, silicon oxycarbonitride, low-K dielectrics, SiCOH dielectrics, silicon carbonitride, or diamond-like carbon or diamond surfaces. Such carbon-containing ceramic materials may be considered inorganic despite the carbon content. In some embodiments, the dielectric at the bonding surface does not include a polymeric material, such as an epoxy (e.g., an epoxy adhesive, a cured epoxy, or an epoxy composite, e.g., FR-4), a resin, or a molding compound.

[0054] In other embodiments, the bonding layer may be made of an electrically conductive material, such as a vapor-deposited conductive oxide material, such as indium tin oxide (ITO), as disclosed in U.S. Provisional Patent Application No. 63 / 524,564, filed June 30, 2023, the entire contents of which are incorporated herein by reference for providing examples of conductive bonding layers without shorting contacts through the interface.

[0055] Direct bonding allows a first element and a second element to be directly bonded to each other without adhesive, which differs from a vapor deposition process and results in a structurally different interface compared to that achieved by vapor deposition. In one application, the width of the first element in the bonded structure is approximately the same as the width of the second element. In some other embodiments, the width of the first element in the bonded structure differs from the width of the second element. The width or area of ​​the larger element in the bonded structure may be at least 10% larger than the width or area of ​​the smaller element. Furthermore, the interface between directly bonded structures, unlike the interface beneath the vapor deposition layer, may contain defective regions where nanometer-scale voids (nanovoids) exist. Nanovoids may form due to activation of one or both of the bonding surfaces (e.g., exposure to plasma, as described below).

[0056] The bond interface between non-conductive bonding surfaces may contain a higher concentration of material from the activation and / or final chemical treatment process compared to the bulk of the bonding layer. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak may form at the bond interface. The nitrogen peak may be detectable using secondary ion mass spectrometry (SIMS). In various embodiments, for example, a nitrogen termination treatment (e.g., exposing the bonding layer to a nitrogen-containing plasma) can replace OH groups on a hydrolyzed (OH-terminated) surface with NH molecules, resulting in a nitrogen-terminated surface. In embodiments utilizing oxygen plasma for activation, an oxygen peak may form at the bond interface. In some embodiments, the bond interface may be comprised of silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond comprises a covalent bond, which is stronger than van der Waals bonds. The bonding layer may further have a polished surface that is planarized to a high degree of smoothness.

[0057] In direct bonding processes, such as uniform direct bonding and hybrid bonding, two components are bonded together without an intervening adhesive. In non-direct bonding processes that use adhesives, an intervening material is typically applied to one or both components to achieve a physical bond between the components. For example, in some adhesive-based processes, a flowable adhesive (e.g., an organic adhesive, such as an epoxy), which may contain a conductive filler material, may be applied to one or more components and cured to form a physical bond (rather than a chemical or covalent bond) between the components. Typical organic adhesives do not form strong chemical or covalent bonds with either component. In such processes, the bond between the components is weak and / or easily destroyed by, for example, reheating or defluxing.

[0058] In contrast, direct bonding processes join two elements together by forming strong chemical bonds (e.g., covalent bonds) between opposing non-conductive materials. For example, in direct bonding processes between non-conductive materials, one or both non-conductive surfaces of two elements are planarized and chemically pretreated (e.g., activated and / or terminated) so that when the elements are brought into contact with each other, strong chemical bonds (e.g., covalent bonds) are formed, which are stronger than van der Waals or hydrogen bonds. In some embodiments (e.g., between opposing dielectric surfaces, e.g., between opposing silicon oxide surfaces), chemical bonds may spontaneously form at room temperature upon contact. In some embodiments, the chemical bonds between the opposing non-conductive materials may be strengthened after the elements are annealed.

[0059] As mentioned above, hybrid bonding is a type of direct bonding in which both non-conductive features are directly bonded to non-conductive features and conductive features are directly bonded to conductive features of the components being bonded. The non-conductive bonding materials and interfaces can be as described above, while the conductive bond can be formed, for example, as a direct metal-to-metal bond. In a conventional metal bonding process, a fusible metal alloy (e.g., solder) can be placed between the conductors of two components, heated to melt the alloy, and cooled to form a bond between the two components. The resulting bond often has a sharp interface with the conductors from both components, which can be reversed by reheating. In contrast, direct metal bonding used in hybrid bonding does not require molten or semi-fusible metal alloys, and as a result, strong mechanical and electrical bonds can be obtained without the extremely high temperatures and pressures of thermocompression bonding, and interdiffusion of bonded conductive features is often observed, with grain growth occurring across the bonding interface between the elements.

[0060] 6A and 6B schematically illustrate cross-sectional side views of first and second elements 602, 604, respectively, before and after a process for forming a direct-bonded structure, particularly a hybrid-bonded structure, according to some embodiments. In FIG. 6B, the bonded structure 600 has the first and second elements 602, 604 directly bonded to one another at a bond interface 618 without an intervening adhesive. A conductive feature 606 a of the first element 602 may be electrically connected to a corresponding conductive feature 606 b of the second element 604. In the illustrated hybrid-bonded structure 600, the conductive feature 606 a is directly bonded to the corresponding conductive feature 606 b without an intervening solder or conductive adhesive.

[0061] In the illustrated embodiment, the conductive features 606a, 606b are embedded within the first bonding layer 608a of the first element 602 and the second bonding layer 608b of the second element 604, respectively, making the conductive features 606a, 606b part of the bonding layers 608a, 608b. The field regions of the bonding layers 608a, 608b extend between and partially or completely surround the conductive features 608a, 608b. The bonding layers 608a, 608b may comprise a layer of non-conductive material suitable for direct bonding, as described above, and the field regions are directly bonded to each other without adhesive. The non-conductive bonding layers 608a, 608b may be provided on the front surfaces 614a, 614b of the base substrate portions 610a, 610b, respectively.

[0062] The first and second elements 602, 604 may comprise microelectronic elements, e.g., semiconductor elements, including, for example, integrated device dies, wafers, passive devices, discrete active devices such as power switches, MEMS, etc. In some embodiments, the base substrate portion may include device portions, e.g., bulk semiconductor (e.g., silicon) portions of the elements 602, 604, and back-end-of-line (BEOL) interconnect layers over such semiconductor portions. The bonding layers 608a, 608b may be provided as part of such BEOL layers during device fabrication, as part of a redistribution layer (RDL), or as special bonding layers added to an existing device, with bond pads extending from underlying contacts. Active devices and / or circuit components may be patterned and / or otherwise provided in or on base substrate portions 610a, 610b, and may be in electrical communication with at least some of the conductive features 608a, 608b. The active devices and / or circuit components may be provided at or near the front surfaces 614a, 614b of base substrate portions 610a, 610b and / or at or near the opposite back surfaces 616a, 616b of base substrate portions 610a, 610b. In other embodiments, base substrate portions 610a, 610b may not include active circuit components, but may instead include a dummy substrate, a passive interposer, a passive optical element (e.g., a glass substrate, a grating, a lens), or the like. Although bonding layers 608a, 608b are shown as being provided on the front side of the device, similar bonding layers may additionally or alternatively be provided on the back side of the device.

[0063] In some embodiments, the base substrate portions 610a, 610b may have significantly different coefficients of thermal expansion (CTE), and bonding elements including such different base substrate portions may form a heterogeneous bonded structure. The difference in CTE between the base substrate portions 610a, 610b, particularly the bulk semiconductor (typically single-crystalline) portions of the base substrate portions 610a, 610b, may be greater than 5 ppm / °C or greater than 10 ppm / °C. For example, the difference in CTE between the base substrate portions 610a, 610b may be in the range of 5 ppm / °C to 100 ppm / °C, 5 ppm / °C to 40 ppm / °C, 10 ppm / °C to 100 ppm / °C, or 10 ppm / °C to 40 ppm / °C.

[0064] In some embodiments, one of the base substrate portions 610 a, 610 b may be made of an optoelectronic single crystal material useful for opto-piezoelectric or pyroelectric applications, while the other of the base substrate portions 610 a, 610 b is made of a more conventional substrate material, for example, one of the base substrate portions 610 a, 610 b is made of lithium tantalate (LiTaO) or lithium niobate (LiNbO), and the other of the base substrate portions 610 a, 610 b is made of silicon (Si), quartz, fused silica, sapphire, or glass. In other embodiments, one of the base substrate portions 610a, 610b may be comprised of a single III-V semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other of the base substrate portions 610a, 610b may be comprised of a non-III-V semiconductor material, such as silicon (Si), or another material with a similar CTE, such as quartz, fused silica, sapphire, or glass. In yet other embodiments, one of the base substrate portions 610a, 610b may be comprised of a semiconductor material, and the other of the base substrate portions 610a, 610b may be comprised of a packaging material, such as glass, an organic, or ceramic substrate.

[0065] In some configurations, the first element 602 may comprise a singulated element, such as a singulated integrated device die. In other configurations, the first element 602 may comprise a carrier or substrate (e.g., a semiconductor wafer) containing multiple (e.g., tens, hundreds, or more) device regions that, when singulated, form multiple integrated device dies, although in other embodiments, such a carrier may comprise a packaging substrate or a passive or active interposer. Similarly, the second element 604 may comprise a singulated element, such as a singulated integrated device die. In other configurations, the second element 604 may comprise a carrier or substrate (e.g., a semiconductor wafer). Accordingly, embodiments disclosed herein are applicable to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In a W2W process, two or more wafers may be directly bonded together (e.g., direct hybrid bonding) and then singulated using an appropriate singulation process. After singulation, the side edges of the singulated structure (e.g., the side edges of the two bonded elements) may be substantially coplanar (substantially aligned x-y dimensions) with one another, and / or the edges of the bonding interfaces for both bonded and singulated elements may be coextensive, and these edges may include indicia indicative of the common singulation process for the bonded structure (e.g., saw marks if a saw singulation process is used).

[0066] Although only two elements 602, 604 are shown, any suitable number of elements can be stacked in the bonded structure 600. For example, a third element (not shown) can be stacked on the second element 604, a fourth element (not shown) can be stacked on the third element, and so on. In such an embodiment, through-substrate vias (TSVs) can be formed to enable vertical electrical communication between and / or among the vertically stacked elements. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to each other along the first element 602. In some embodiments, the laterally stacked additional elements can be smaller than the second element. In some embodiments, the bonded structure can be encapsulated in an insulating material, such as an inorganic dielectric (e.g., silicon oxide, silicon nitride, silicon oxycarbonitride, etc.). One or more insulating layers can be provided on the bonded structure. For example, in some embodiments, a first insulating layer can be conformally deposited on the bonded structure, and a second insulating layer (which can comprise the same or a different material as the first insulating layer) can be provided on the first insulating layer.

[0067] To achieve direct bonding between the bonding layers 608a, 608b, the bonding layers 608a, 608b can be prepared for direct bonding. The non-conductive bonding 612a, 612b at the top or outer surfaces of the bonding layers 608a, 608b can be prepared for direct bonding by polishing, for example, chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces 612a, 612b can be less than 15 Å rms. For example, the roughness of the bonding surfaces 612a, 612b can be in the range of approximately 0.1 Å rms to 15 Å rms, 0.5 Å rms to 10 Å rms, or 1 Å rms to 5 Å rms. Additionally, the polishing can be optimized to leave the conductive features 606a, 606b recessed relative to the field regions of the bonding layers 608a, 608b.

[0068] Pretreatment to enable direct bonding may further include cleaning one or both of the bonding surfaces 612a, 612b and exposing them to a plasma and / or an etchant to activate at least one of the surfaces 612a, 612b. In some embodiments, one or both of the surfaces 612a, 612b may be terminated with chemical species after or during activation (e.g., during a plasma and / or etch process). Without being bound by theory, in some embodiments, the activation process may be performed to break chemical bonds at the bonding surfaces 612a, 612b, and the termination process may provide additional chemical species at the bonding surfaces 612a, 612b that alter the chemical bonds and / or improve bonding energy during direct bonding. In some examples, activation and / or termination are performed in the same step, e.g., in a plasma, thereby activating and terminating the surfaces 612a, 612b. In other embodiments, one or both of the bonding surfaces 612a, 612b may be terminated in a separate process to provide additional chemical species for direct bonding. In various implementations, the terminating species may comprise nitrogen. For example, in some embodiments, the bonding surfaces 612a, 612b may be exposed to a nitrogen-containing plasma. Other terminating species may be suitable for improving bonding energy, depending on the material of the bonding surfaces 612a, 612b. Furthermore, in some embodiments, the bonding surfaces 612a, 612b may be exposed to fluorine. For example, one or more fluorine concentration peaks may be present at or near the bond interface 618 between the first element 602 and the second element 604. Typically, the fluorine concentration peaks occur at the interface between material layers.Additional examples of activation and / or termination treatments are described in U.S. Pat. No. 9,391,143 at column 5, line 55 to column 7, line 3; column 8, line 52 to column 9, line 45; column 10, lines 24 to 36; column 11, lines 24 to 32, lines 42 to 47, lines 52 to 55, and lines 60 to 64; column 12, lines 3 to 14, lines 31 to 33, and lines 55 to 67; and column 14, lines 38 to 40. and lines 44-50 of US Patent No. 10,434,749, and at column 4, lines 41-50, column 5, lines 7-22, lines 39, lines 55-61, column 8, lines 25-31, lines 35-40, lines 49-56, and column 12, lines 46-61, which U.S. patent applications are incorporated by reference and their teachings on activation and termination are incorporated herein by reference.

[0069] Thus, in the direct-bonded structure 600, the bond interface 618 between the two non-conductive materials (e.g., bonding layers 608a, 608b) may have a relatively high nitrogen (or other terminating species) content and / or a very smooth interface with a fluorine concentration peak at the bond interface 618. In some embodiments, the nitrogen and / or fluorine concentration peak can be detected using various types of inspection techniques, such as SIMS techniques. The polished bonding surfaces 612a, 612b may be slightly rough after the activation process (e.g., about 1 Å rms to 30 Å rms, 3 Å rms to 20 Å rms, or even rougher). In some embodiments, a slightly smoother surface can be achieved as a result of activation and / or termination prior to bonding, for example, if a plasma treatment preferentially erodes high points on the bonding surface.

[0070] The non-conductive bonding layers 608a, 608b can be directly bonded to one another without adhesive. In some embodiments, the elements 602, 604 are brought together at room temperature, without the need for an applied voltage and without the need for external pressure or force beyond that used to prevent the two elements 602, 604 from contacting one another. Contact alone can result in direct bonding (e.g., covalent dielectric bonding) between the non-conductive layer surfaces of the bonding layers 608a, 608b. Subsequent annealing of the bonded structure 600 can directly bond the conductive features 606a, 606b to one another.

[0071] In some embodiments, prior to direct bonding, the conductive features 606 a, 606 b are recessed relative to the surrounding field region, resulting in a total gap between opposing contacts after dielectric bonding and before annealing of less than 15 nm, or even less than 10 nm. Because the recess depth of the conductive features 606 a, 606 b can vary across each element due to process variations, this gap may represent the maximum or average gap (before annealing) between corresponding conductive features 606 a, 606 b of two joining elements. Upon annealing, the conductive features 606 a, 606 b can expand and contact each other, thereby forming a direct metal-to-metal bond.

[0072] During annealing, the conductive features 606 a, 606 b (e.g., metallic material) can expand while the direct bonds between the surrounding non-conductive materials of the bonding layers 608 a, 608 b resist separation of the elements, resulting in thermal expansion increasing the internal contact pressure between the opposing conductive features. Annealing can also induce metal grain growth across the bonding interface, resulting in grains from one element migrating at least partially across the bonding interface into the other element, and vice versa. Thus, in some hybrid bonding embodiments, the opposing conductive materials are joined without heating above the melting temperature of the conductive materials, resulting in bonds that can occur at lower annealing temperatures compared to solder or thermocompression bonding.

[0073] In various embodiments, the conductive features 606 a, 606 b may comprise separate pads, contacts, electrodes, or traces at least partially embedded within non-conductive field regions of the bonding layers 608 a, 608 b. In some embodiments, the conductive features 606 a, 606 b may comprise exposed contact surfaces of TSVs (e.g., through silicon vias).

[0074] As mentioned above, in some embodiments, in the devices 602, 604 of FIG. 6A prior to direct bonding, a portion of each of the conductive features 606 a, 606 b may be recessed below the non-conductive bonding surface 611 a, 611 b, e.g., by less than 30 nm, less than 20 nm, 15 nm, or less than 10 nm, e.g., by a range of 2 nm to 20 nm, or a range of 4 nm to 10 nm. Due to process variations, both the dielectric thickness and the conductor recess depth may vary across an device. Thus, the recess depth ranges described above may apply to individual conductive features 606 a, 606 b, or may apply to the average recess depth for local non-conductive field regions. Even for individual conductive features 606a, 606b, the vertical recess depth may vary throughout the conductive feature, and therefore may be measured at or near the lateral midpoint or center of the cavity formed in a given conductive feature 606a, 606b, or may be measured at the side of the cavity.

[0075] Beneficially, the use of hybrid bonding technology (e.g., Direct Bond Interconnect, or DBI® technology, commercially available from Adair, Inc., San Jose, California) enables the realization of high densities (e.g., small or fine pitch for conventional arrays) of interconnections between conductive features 606a, 606b across the direct bond interface 618.

[0076] In some embodiments, the pitch p of the conductive features 606a, 606b, e.g., conductive traces embedded within the bonding surface of one of the bonded elements, may be less than 40 μm, less than 20 μm, less than 10 μm, less than 5 μm, less than 2 μm, or even less than 1 μm. For some applications, the ratio of the pitch of the conductive features 606a, 606b to one of the lateral dimensions (e.g., diameter) of the bonding pad is less than 20, less than 10, less than 5, or less than 3, and in some cases, desirably, less than 2. In various embodiments, the conductive features 606a, 606b and / or traces may be comprised of copper or a copper alloy, although other metals, such as nickel, aluminum, or alloys thereof, may be suitable. The conductive features disclosed herein, e.g., the conductive features 606a, 606b, may be comprised of metal particulates (e.g., copper particulates). Additionally, the larger lateral dimension (eg, pad diameter) may also be small, for example, in the range of 0.25 μm to 30 μm, in the range of about 0.25 μm to 5 μm, or in the range of about 0.5 μm to 5 μm.

[0077] For hybrid bonded devices 602, 604, the orientation of one or more conductive features 606a, 606b as viewed from the opposing device may be opposite, as shown. As is known in the art, conductive features generally have sidewalls at a near-perpendicular angle, particularly when the conductor sidewalls are formed directly by directional reactive ion etching (RIE) through the conductive material or indirectly by etching the surrounding insulator in a damascene process. However, some slight taper to the conductor sidewall may exist, with the conductor tapering away from the surface initially exposed to the etch. The taper may be even more pronounced when the conductive sidewalls are formed directly or indirectly with an isotropic wet or dry etch. In the illustrated embodiment, at least one conductive feature 606b (and / or at least one internal conductive feature, e.g., a back-end electronics feature) in the bonding layer 608b of the upper device 604 may taper or taper upward, away from the bonding surface 612b. In contrast, at least one conductive feature 606a (and / or at least one internal conductive feature, e.g., a BEOL feature) in the bonding layer 608a of the lower element 602 may taper or narrow downwardly away from the bonding surface 610a. Similarly, any bonding layers (not shown) on the backsides 616a, 616b of the elements 602, 604 may taper or narrow downwardly away from the backside, with an opposite taper sense relative to the frontside conductive features 606a, 606b of the same elements.

[0078] As described above, during the annealing phase of bonding, the conductive features 606a, 606b can expand and contact each other, thereby forming a direct metal-to-metal bond. In some embodiments, the materials of the conductive features 606a, 606b of the opposing elements 602, 604 can interdiffuse during the annealing process. In some embodiments, metal grains grow and interdigitate across the bond interface 618. In some embodiments, the metal is or includes copper, which may have grains oriented along 111 crystallographic planes to enhance copper diffusion across the bond interface 618. In some embodiments, the conductive features 606a, 606b may include a nanotwinned copper crystal structure, which can aid in the coalescence of the conductive features during high-temperature annealing. Substantially no gaps develop between the non-conductive bonding layers 608a, 608b at or near the bonded conductive features 606a, 606b. In some embodiments, a barrier layer may be provided below or laterally surrounding the conductive features 606a, 606b (which may comprise copper, for example), however, in other embodiments, there may not be a barrier layer below the conductive features 606a, 606b.

[0079] In the foregoing specification, the systems and processes have been described with reference to these specific embodiments. It will be apparent, however, that various modifications and changes can be made to such embodiments without departing from the broad spirit and scope of the embodiments disclosed herein. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

[0080] While the systems and processes have been disclosed in connection with certain specific embodiments and examples, those skilled in the art will understand that various embodiments of the systems and processes extend beyond the specifically disclosed embodiments to other variations and / or systems and processes, as well as obvious modifications and equivalents thereof. Additionally, while several variations of the system and process embodiments have been shown and described in detail, other modifications within the scope of the present disclosure will be readily apparent to those skilled in the art based on this disclosure. Furthermore, various combinations or subcombinations of specific features of the embodiments and specific embodiments may be made and still fall within the scope of the present disclosure. It should be understood that various features of the disclosed embodiments and various embodiments may be combined with or substituted for one another to form various modes of implementing the disclosed systems and processes. Any methods disclosed herein need not be performed in the order described. Thus, the scope of the systems and processes disclosed herein should not be limited by the specific embodiments described above.

[0081] It will be recognized that each of the systems and methods of the present disclosure has several innovative embodiments, and no single one of these embodiments will be responsible for or required to achieve the desired attributes disclosed herein. The various features and processes described above can be used independently of one another or can be combined in various ways. All possible combinations and subcombinations are within the scope of the present disclosure.

[0082] Certain features described in this disclosure in the context of separate embodiments can also be embodied in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be embodied in multiple embodiments separately or in any suitable subcombination. Furthermore, while features may be described above as operative in certain combinations and may initially be claimed as such, one or more features from a claimed combination may in some cases be excluded from the combination, and the claimed combination may relate to subcombinations or variations of the subcombination. No single feature or group of features is required or essential to each and every embodiment.

[0083] Additionally, as used herein, conditional terms, particularly "can," "could," "might," "may," "for example," and the like, unless otherwise specified and understood differently within the context in which they are used, are generally intended to mean that certain embodiments include certain features, elements, and / or steps, and that other embodiments do not include certain features, elements, and / or steps. Thus, such conditional terms are generally intended to mean that features, elements, and / or steps are required in any way by one or more embodiments, or that one or more embodiments necessarily include logic for determining, with or without author input or direction, whether those features, elements, and / or steps are included or performed in any suitable embodiment. In the original specification, terms such as "comprising," "including," and "having" are synonymous and are used inclusively in an open-ended manner, not excluding additional elements, features, acts, or operations. Additionally, the term "or" is used in its inclusive sense (not its exclusive sense), and thus, for example, when used to conjunctively connect a list of elements, the term "or" may refer to one, some, or all of the elements in the list. Additionally, the articles "a," "an," and "the" used in the original specification and the appended claims should be construed to mean "one or more" or "at least one or more" unless expressly specified otherwise. Similarly, while operations may be described in a particular order in the figures, it should be recognized that such operations need not be performed in the particular order or sequential order shown to achieve desirable results, and that not all illustrated operations need be performed. Additionally, the figures may illustrate one or more example processes generally in the form of a flow chart, although other operations not shown may be included in the example methods and processes illustrated generally.For example, one or more additional operations may be performed before, after, concurrently with, or between any of the illustrated operations. In addition, operations may be rearranged or reordered in other embodiments. In addition, other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.

[0084] Furthermore, various modifications and variations can be made to the methods and devices described herein, specific examples of which are shown in the drawings and described in detail herein. However, it should be understood that these embodiments are not limited to the specific forms or methods disclosed; rather, the embodiments cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as described in the various embodiments and claims. Furthermore, any particular feature, aspect, method, characteristic, feature, quality, attribute, element, etc., associated with an embodiment or embodiment, if disclosed herein, can be used in all embodiments or embodiments described herein. Methods disclosed herein need not be performed in the order described. Although methods disclosed herein may include certain actions performed by a practitioner, such methods may further include any third-party direction of those actions, either explicitly or by implication. Furthermore, ranges disclosed herein include any and all overlaps, subranges, and combinations thereof. For example, terms such as "up to," "at least," "more than," "less than," and "between" are inclusive of the recited numbers. For example, a number preceded by "about" or "approximately" is inclusive of the stated number and should be interpreted in accordance with the context (e.g., as precisely as reasonably possible under the circumstances, e.g., ±5%, ±10%, ±15%, etc.). For example, "about 3.5 mm" means "including 3.5 mm." Phrases preceded by the term "substantially" are inclusive of the stated number and should be interpreted in accordance with the context (e.g., as precisely as reasonably possible under the circumstances). For example, "substantially constant" includes "constant." Unless otherwise specified, all measurements are taken at standard conditions, including temperature and pressure.

[0085] As used herein, the phrase "at least one of" a list of items refers to any combination of such items, where such combination contains only one element. By way of example, "at least one of A, B, or C" includes A, B, C, A·B, A·C, B·C, and A·B·C. Conjunctions, such as "at least one of X, Y, and Z," are understood in their commonly used context to mean that an item, term, etc., can be at least one of X, Y, or Z, unless otherwise specified. Thus, such conjunctions do not imply that a particular embodiment must have at least one of X, at least one of Y, and at least one of Z. Headings provided herein, if any, are provided for convenience only and do not necessarily affect the scope or meaning of the devices and methods disclosed herein.

[0086] Thus, the claimed invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the inventions, principles, and novel features disclosed herein.

Claims

1. 1. A bonded structure comprising: having a carrier, a first memory unit disposed on the carrier, the first memory unit including a first memory channel, the first memory unit including a first plurality of memory dies directly hybrid bonded to one another; a second memory unit including a second memory channel different from the first memory channel, the second memory unit including a second plurality of memory dies directly hybrid bonded to one another, the second memory unit being stacked on top of the first memory unit; a serializer-deserializer disposed in or on the carrier and electrically connected to the first and second memory channels of the first and second memory units, the serializer-deserializer having an external channel configured to electrically connect the bonded structure to a processor.

2. The bonded structure of claim 1 , wherein the carrier comprises a logic die.

3. further comprising a logic die; the carrier includes an interposer; The bonded structure of claim 1 , wherein the logic die is disposed between the first memory unit and the interposer.

4. encapsulants, and further comprising a logic die; the carrier includes a redistribution layer; the logic die is disposed between the first memory unit and the redistribution layer; The bonded structure of claim 1 , wherein the first memory unit, the second memory unit, the logic die, and the serializer-deserializer are partially encased in the encapsulant.

5. further comprising a logic die; the carrier includes a printed circuit board; 2. The bonded structure of claim 1, wherein the logic die is disposed between the first memory unit and the printed circuit board.

6. 6. The bonded structure according to claim 1, wherein the first memory unit is directly hybrid bonded to the second memory unit.

7. 6. The bonded structure according to claim 1, wherein the first memory unit is directly hybrid bonded to the carrier.

8. 6. The bonded structure according to claim 1, wherein the serializer-deserializer is directly hybrid bonded to the carrier.

9. A structure comprising: a first memory unit having a top surface and a bottom surface, the first memory unit including a first plurality of memory dies directly hybrid bonded to one another; a second memory unit having a top surface and a bottom surface, the second memory unit including a second plurality of memory dies directly hybrid bonded to one another; a logic die having a top surface and a bottom surface; a serializer-deserializer having a top surface and a bottom surface; the bottom surface of the second memory unit is disposed on the top surface of the first memory unit; the bottom surface of the first memory unit is disposed on the top surface of the logic die; the bottom surface of the serializer-deserializer is disposed on the top surface of the logic die; the structure has a first number of internal channels electrically connecting the serializer-deserializer, the logic die, the first memory unit, and the second memory unit to one another; the structure has a second number of external channels configured to electrically connect the structure to a processor; The first number is greater than the second number.

10. The structure of claim 9 , wherein the first number of the interior channels is two and the second number of the exterior channels is one.

11. 10. The structure of claim 9, wherein said first number of said interior channels is four and said second number of said exterior channels is one.

12. 12. The structure of claim 9, wherein the second memory unit is direct hybrid bonded to the first memory unit.

13. 13. The structure of claim 9, wherein the first memory unit is direct hybrid bonded to the logic die.

14. The structure of any one of claims 9 to 13, wherein the serializer-deserializer is direct hybrid bonded to the logic die.

15. 15. The structure of claim 9, wherein a first internal channel is electrically connected to the active circuitry of the first memory unit, a second internal channel is electrically connected to the active circuitry of the second memory unit, and the second internal channel is not electrically connected to the active circuitry of the first memory unit.

16. A structure comprising: a first memory unit having a top surface and a bottom surface, the first memory unit including a first plurality of memory dies directly hybrid bonded to one another; a second memory unit having a top surface and a bottom surface, the second memory unit including a second plurality of memory dies directly hybrid bonded to one another; a logic die having a top surface and a bottom surface; an interposer having a top surface and a bottom surface; a serializer-deserializer having a top surface and a bottom surface; the bottom surface of the second memory unit is disposed on the top surface of the first memory unit; the bottom surface of the first memory unit is disposed on the top surface of the logic die; the bottom surface of the logic die is disposed on the top surface of the interposer; the bottom surface of the serializer-deserializer is disposed on the top surface of the interposer; the structure has a first number of internal channels electrically connecting the serializer-deserializer, the logic die, the first memory unit, and the second memory unit to one another; the structure has a second number of external channels configured to electrically connect the structure to a processor; The first number is greater than the second number.

17. 17. The structure of claim 16, wherein the first number of the interior channels is two and the second number of the exterior channels is one.

18. 17. The structure of claim 16, wherein the first number of the interior channels is four and the second number of the exterior channels is one.

19. 19. The structure of claim 16, wherein the second memory unit is direct hybrid bonded to the first memory unit.

20. 20. The structure of claim 16, wherein the first memory unit is direct hybrid bonded to the logic die.

21. The structure of any one of claims 16 to 20, wherein the serializer-deserializer is direct hybrid bonded to the interposer.

22. The structure of any one of claims 16 to 21, wherein the logic die is direct hybrid bonded to the interposer.

23. 23. The structure of any one of claims 16-22, wherein a first internal channel is electrically connected to the active circuitry of the first memory unit, a second internal channel is electrically connected to the active circuitry of the second memory unit, and the second internal channel is not electrically connected to the active circuitry of the first memory unit.

24. A structure comprising: a first memory unit having a top surface and a bottom surface, the first memory unit including a first plurality of memory dies directly hybrid bonded to one another; a second memory unit having a top surface and a bottom surface, the second memory unit including a second plurality of memory dies directly hybrid bonded to one another; a logic die having a top surface and a bottom surface; A redistribution layer is provided. a serializer-deserializer with a top surface and a bottom surface and an encapsulant; the bottom surface of the second memory unit is disposed on the top surface of the first memory unit; the bottom surface of the first memory unit is disposed on the top surface of the logic die; the first memory unit, the second memory unit, the logic die, and the serializer-deserializer are at least partially encased in the encapsulant; the top surface of the logic die and the top surface of the serializer-deserializer are exposed; the redistribution layer is formed over the top surface of the serializer-deserializer and the top surface of the logic die; the redistribution layer electrically connects the serializer-deserializer and the logic die; the redistribution layer is configured to electrically connect the serializer-deserializer to a processor; the structure has a first number of internal channels electrically connecting the serializer-deserializer, the logic die, the first memory unit, and the second memory unit to one another; the structure has a second number of external channels configured to electrically connect the structure to a processor; The first number is greater than the second number.

25. 25. The structure of claim 24, wherein the first number of the interior channels is two and the second number of the exterior channels is one.

26. 25. The structure of claim 24, wherein said first number of said interior channels is four and said second number of said exterior channels is one.

27. 27. The structure of any one of claims 24 to 26, wherein the second memory unit is direct hybrid bonded to the first memory unit.

28. 28. The structure of any one of claims 24 to 27, wherein the first memory unit is direct hybrid bonded to the logic die.

29. The structure of any one of claims 24 to 28, wherein the redistribution layer is vapor deposited.

30. 30. The structure of any one of claims 24 to 29, wherein the redistribution layer is direct hybrid bonded to the logic die and the serializer-deserializer.

31. 31. The structure of any one of claims 24-30, wherein a first internal channel is electrically connected to the active circuitry of the first memory unit, a second internal channel is electrically connected to the active circuitry of the second memory unit, and the second internal channel is not electrically connected to the active circuitry of the first memory unit.

32. A structure comprising: a first memory unit having a top surface and a bottom surface, the first memory unit including a first plurality of memory dies directly hybrid bonded to one another; a second memory unit having a top surface and a bottom surface, the second memory unit including a second plurality of memory dies directly hybrid bonded to one another; a logic die having a top surface and a bottom surface; having a substrate, a serializer-deserializer having a top surface and a bottom surface; the bottom surface of the second memory unit is disposed on the top surface of the first memory unit; the bottom surface of the first memory unit is disposed on the top surface of the logic die; the top surface of the logic die is disposed on the bottom surface of the substrate; the serializer-deserializer is embedded in the substrate; the serializer-deserializer is electrically connected to the logic die; the structure has a first number of internal channels electrically connecting the serializer-deserializer, the logic die, the first memory unit, and the second memory unit to one another; the structure has a second number of external channels configured to electrically connect the structure to a processor; The first number is greater than the second number.

33. 33. The structure of claim 32, wherein said first number of said interior channels is two and said second number of said exterior channels is one.

34. 33. The structure of claim 32, wherein said first number of said interior channels is four and said second number of said exterior channels is one.

35. 35. The structure of any one of claims 32 to 34, wherein the second memory unit is direct hybrid bonded to the first memory unit.

36. 36. The structure of any one of claims 32 to 35, wherein the first memory unit is direct hybrid bonded to the logic die.

37. 37. The structure of any one of claims 32-36, wherein a first internal channel is electrically connected to the active circuitry of the first memory unit, a second internal channel is electrically connected to the active circuitry of the second memory unit, and the second internal channel is not electrically connected to the active circuitry of the first memory unit.

38. A structure according to any one of claims 32 to 37, wherein the substrate comprises a printed circuit board.

39. 1. A bonded structure comprising: having a carrier, a first memory unit disposed on the carrier, the first memory unit including a first memory channel and a first plurality of memory dies directly hybrid bonded to one another; a second memory unit including a second memory channel different from the first memory channel and a second plurality of memory dies directly hybrid bonded to each other, the second memory unit being stacked on top of the first memory unit; a serializer-deserializer direct hybrid bonded to the carrier and electrically connected to the first and second memory channels of the first and second memory units, the serializer-deserializer having an external channel configured to electrically connect the bonded structure to a processor.

40. 40. The bonded structure of claim 39, wherein the bonded structure has a first plurality of internal channels electrically connecting the serializer-deserializer, the carrier, the first memory unit, and the second memory unit to each other, and a second number of the external channels configured to electrically connect the structure to the processor, the first number being different from the second number.

41. 41. The bonded structure of claim 39 or 40, wherein the carrier includes a logic die.

42. further comprising a logic die; the carrier includes an interposer; 41. The bonded structure of claim 39 or 40, wherein the logic die is disposed between the first memory unit and the interposer.

43. encapsulants, and further comprising a logic die; the carrier includes a redistribution layer; the logic die is disposed between the first memory unit and the redistribution layer; 41. The bonded structure of claim 39 or 40, wherein the first memory unit, the second memory unit, the logic die, and the serializer-deserializer are partially encased in the encapsulant.

44. further comprising a logic die; the carrier includes a printed circuit board; 41. The bonded structure of claim 39 or 40, wherein the logic die is disposed between the first memory unit and the printed circuit board.

45. 45. The bonded structure of claim 39, wherein the first memory unit is directly hybrid bonded to the second memory unit.

46. 46. ​​The bonded structure of claim 39, wherein the first memory unit is directly hybrid bonded to the carrier.

47. 1. A bonded structure comprising: having a carrier, a first memory unit including a first memory channel and a second memory channel different from the first memory channel, the second memory unit being stacked on top of the first memory unit, the first memory unit and the second memory unit being provided on the carrier, the first memory unit including a first plurality of memory dies directly hybrid bonded to each other, and the second memory unit including a second plurality of memory dies directly hybrid bonded to each other; a serializer-deserializer disposed on or at least partially embedded in the carrier and electrically connected to the first and second memory channels of the first and second memory units, the serializer-deserializer having an external channel configured to electrically connect the bonded structure to a processor.

48. 48. The bonded structure of claim 47, wherein the bonded structure has a first number of internal channels electrically connecting the serializer-deserializer, the carrier, the first memory unit, and the second memory unit to one another, and a second number of the external channels configured to electrically connect the bonded structure to a processor, the first number being different from the second number.

49. 49. The bonded structure of claim 47 or 48, wherein the serializer-deserializer is hybrid bonded to the carrier.

50. 50. The bonded structure of any one of claims 47 to 49, wherein the carrier includes a logic die.

51. further comprising a logic die; the carrier includes an interposer; 50. The bonded structure of claim 47, wherein the logic die is provided between the first memory unit and the interposer.

52. encapsulants, and further comprising a logic die; the carrier includes a redistribution layer; the logic die is disposed between the first memory unit and the redistribution layer; 50. The bonded structure of any one of claims 47 to 49, wherein the first memory unit, the second memory unit, the logic die, and the serializer-deserializer are partially encased in the encapsulant.

53. further comprising a logic die; the carrier includes a printed circuit board; 50. The bonded structure of claim 47, wherein the logic die is provided between the first memory unit and the printed circuit board.

54. 54. The bonded structure of claim 47, wherein the first memory unit is directly hybrid bonded to the second memory unit.

55. 55. The bonded structure of claim 47, wherein the first memory unit is directly hybrid bonded to the carrier.

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