Identifying failures in the device core

Abstract

The exemplary system is for testing a device under test (DUT) comprising a first core and a second core. The system includes parallel channels for connecting to several pins on the DUT. The channels are for transmitting test data to the DUT and for receiving measurement data from the DUT based on the test data. The measurement data includes time-division multiplexing (TDM) data consisting of sequential data packets received from the DUT via the channels as part of a bitstream. Each data packet includes a first number of bits from the first core and a second number of bits from the second core. The circuit configuration associated with the channels is configured to compare the measurement data with expected data and to determine a pass / fail status for the first and second cores based on the comparison.

Description

Technical Field

[0001] This specification describes exemplary embodiments of systems and processes for identifying faults in a device core and for restricting the storage of data from one or more of the device cores after a predetermined number of faults.

Background Art

[0003] The DUT may include two or more cores. Exemplary cores include processing units within the DUT. The test system may receive measurement data from multiple cores in the DUT and determine whether each core passed or failed the test.

Summary of the Invention

Means for Solving the Problems

[0004] The exemplary system is for testing a device under test (DUT) comprising a first core and a second core. The system includes parallel channels for connecting to several pins on the DUT. The channels are for transmitting test data to the DUT and receiving measurement data from the DUT based on the test data. The measurement data includes time-division multiplexing (TDM) data consisting of sequential data packets received from the DUT via the channels as part of a bitstream. Each data packet contains a first number of bits from the first core and a second number of bits from the second core. The data packets are transmitted in parallel on several pins, with each time slot corresponding to the transmission of the bitstream. The TDM data is repeated in a pattern on the channels every predetermined number of time slots. The circuit configuration associated with the channels is configured to compare the measurement data with expected data and to determine a pass / fail status for the first and second cores based on the comparison. The system may include, alone or in combination, one or more of the following features:

[0005] The circuit configuration may be configured to determine a fail count, based on comparison, for the first and second cores, indicating how many times the first core or the second core has failed the test. The circuit configuration may be configured to limit the storage of subsequently received measurement data for the first or second core if the fail count exceeds a threshold number for the first or second core. Limiting storage may include ignoring subsequently received measurement data for the first or second core. Limiting storage may include not storing subsequently received measurement data for the first or second core in memory. Limiting storage may include limiting the number of failures in the first or second core, which affects how many cycles of subsequently received measurement data for the first or second core are stored in memory. One cycle may include one time slot, and one failure includes a single failure of the test.

[0006] The circuit configuration may be configured to output a fail count. At least several cycles of measurement data from the first and second cores may be stored in a result log in memory. One cycle may contain one time slot. The bits of the first number and the bits of the second number may be different and may be cumulatively different from the number of pins such that at least some of the portions of two different data packets are contained in the time slot. A given number of time slots may be greater than one time slot. The circuit configuration may be configured to determine the pass / fail status by accumulating pass / fail data associated with time slots in the current data frame with previous pass / fail data for time slots in previous data frames. One data frame may contain a given number of time slots. The pass / fail data may be based on the cumulative status across multiple repeated patterns of time slots for the first and second cores.

[0007] Determining the fail count may involve separately counting the number of times the first core or the second core failed the test. Counting may involve incrementing the memory address based on the time slot. Counting may involve incrementing the address of the first memory based on the time slot, which maps the time slot to the core number, and which core number addresses the second memory.

[0008] This system may include memory. The circuit configuration may be configured to store the fail count for each core in memory after a predetermined number of cycles of measurement data.

[0009] An exemplary system is for testing a DUT comprising a first core and a second core. The system includes parallel channels for connecting to several pins on the DUT. The channels are for transmitting test data to the DUT and for receiving measurement data from the DUT based on the test data. The measurement data includes TDM data, which consists of sequential data packets received from the DUT via the channels as part of a bitstream. Each data packet contains a first number of bits from the first core and a second number of bits from the second core. The data packets are transmitted in parallel on several pins, with each time slot corresponding to the transmission of the bitstream. The TDM data is repeated in a pattern on the channels every predetermined number of time slots. The circuit configuration associated with the channels is configured to compare the measurement data with expected data and to determine a fail count per time slot based on the comparison. The fail count indicates the number of times the first or second core failed the test. The system may include, individually or in combination, one or more of the following features:

[0010] The circuit configuration may be configured to compare measured data with expected data by summing pass / fail data associated with time slots in the current data frame with previous pass / fail data for time slots in previous data frames. One data frame may contain a predetermined number of time slots. Pass / fail data may be based on the cumulative status for each time slot. The circuit configuration may be configured to restrict the storage of subsequently received measured data for the first or second core if the fail count exceeds a threshold number. Restricting storage may include ignoring subsequently received measured data for the first or second core. Restricting storage may include not storing subsequently received measured data for the first or second core.

[0011] The exemplary system is for testing a DUT comprising a first core and a second core. The system includes parallel channels for connecting to several pins on the DUT. The channels are for transmitting test data to the DUT and for receiving measurement data from the DUT based on the test data. The measurement data includes TDM data, which consists of sequential data packets received from the DUT via the channels as part of a bitstream. Each data packet contains a first number of bits from the first core and a second number of bits from the second core. The data packets are transmitted in parallel on several pins, with each time slot corresponding to the transmission of the bitstream. The TDM data is repeated in a pattern on the channels every predetermined number of time slots. The circuit configuration is associated with the channels to mask data from the first or second core based on user input. Masking includes ignoring or not storing data from the first or second core in memory.

[0012] Any two or more of the features described herein, including those described in the summary section of this invention, may be combined to form embodiments not specifically described herein.

[0013] At least part of the devices, systems, and processes described herein may be configured or controlled by executing instructions stored in one or more non-temporary machine-readable storage media using one or more processing devices. Examples of non-temporary machine-readable storage media include read-only memory, optical disk drives, memory disk drives, and random-access memory. At least part of the devices, systems, and processes described herein may be configured or controlled using a computing system comprising one or more processing devices and memory that stores instructions executable by one or more processing devices to perform various control operations. The devices, systems, and processes described herein may consist, for example, of design, construction, configuration, placement, installation, programming, operation, activation, shutdown, and / or control.

[0014] Details of one or more embodiments are described in the accompanying drawings and the following description. Other features and advantages should become apparent from this specification, the drawings, and the claims. [Brief explanation of the drawing]

[0015] [Figure 1] This block diagram shows the components of an exemplary device under test (DUT) and the components of an exemplary test system on which the exemplary processes described herein may be performed. [Figure 2] This is an illustrative table showing how time-division multiplexed measurement data is transmitted and stored across multiple pins. [Figure 3] This is an illustrative version of the table in Figure 2, which shows actual data values. [Figure 4] This is an example table showing the expected measurement data associated with failing data. [Figure 5] This is an illustrative table demonstrating how to mask / not store data using pins. [Figure 6]This flowchart illustrates an exemplary process for not storing measurement data based on the DUT core that transmitted the measurement data. [Figure 7] Includes two illustrative tables showing the cumulative fail counts for the first and second cores of the DUT. [Figure 8] This is an exemplary table demonstrating how the core masks / does not store data. [Figure 9] An example circuit configuration is shown for determining whether the core failed in any time slot and for determining the fail count for the core. [Figure 10] This block diagram shows the components of an exemplary test system on which the exemplary processes described herein may be performed. [Modes for carrying out the invention]

[0016] Similar reference figures in different drawings indicate the same element.

[0017] This specification describes exemplary embodiments of a test system configured to test a device having multiple cores. Exemplary cores include processing units configured to read and execute computer program instructions, such as the cores of a microprocessor. Multiple cores may execute computer program instructions simultaneously and independently. A device under test (DUT) may comprise multiple cores that output time-division multiplexing (TDM) data. TDM data includes measurement data based on tests performed on the cores during the test. For example, a test system may transmit test data to the cores of the DUT and receive TDM data from the cores of the DUT based on the DUT's response to the test data. TDM data may consist of bits output across multiple test channels, where 1 or 0 represents a measurement based on tests performed on the DUT. This TDM is analyzed by the test system to identify faults in the cores.

[0018] TDM data is stored in a capture memory on or associated with a test system. The capacity of the capture memory is limited. The exemplary processes described herein can identify cores having a number of failures above a predetermined number. Once these cores are identified, the process deems them to have failed the test. Thus, the process can reduce the storage of TDM data from the failed cores in the capture memory. Thereby, the capture memory can store more TDM data for cores that are not failed. Alternatively, by reducing the need for storage, the test system may be able to use a capture memory that is smaller in size than prior art systems.

[0019] FIG. 1 is a block diagram showing an exemplary DUT 10 having two cores 12, 13 and a test system 15 configured to test the DUT 10. The DUT 10 can be any type of electronic device (e.g., a microprocessor, a microcontroller, etc.). Although two cores are shown in FIG. 1, the DUT may include three or more cores. The test system 15 interfaces with the DUT 10 via a set of four input pins 16 and four output pins 17 respectively corresponding to four input channels and four output channels. The pins of other DUTs may be fewer or more than the four input pins and four output pins. The input pins 16 provide test data 20 from the test system 15 to the DUT 10, and the output pins 17 provide measurement data 21 from the DUT 10 to the test system 15. In this example, a communication bus 22 extends through each core 12, 13 from the input pins 16 to the output pins 17 in the DUT 10. When data is streamed on the bus 22, each core 12, 13 can receive test data 20 from the bus 22 and return measurement data 21 on the bus 22.

[0020] Data is delivered to and received from DUT 10 based on clock cycles. For this reason, test system 15 may include one or more clock circuits 23 that control clocking. Test system 15 may provide test data to DUT 10 as a digital pattern burst. The digital pattern burst may be measured in clock cycles that increment continuously.

[0021] Test system 15 may test cores 12, 13 in parallel. Generally, during testing of a DUT, test system 15 transmits test data to the DUT in N-bit (N > 2) packets, where the first set of N bits of each packet is associated with a first core, the next set of N bits is associated with a second core, and so on. Test system 15 may receive measurement data from DUT 10 according to the same timing and configuration as when the test data is transmitted to DUT 10. For example, during testing of a DUT, the DUT transmits measurement data to the test system in N-bit packets at the same timing as the test data, where the first set of N bits of each packet is associated with a first core, the next set of N bits is associated with a second core, and so on.

[0022] FIG. 2 shows an example of how measurement data 21 from DUT 10 is received in test system 15 for a 5-bit packet and the four pins described with respect to FIG. 1. The measurement data 21 for different pin and packet configurations will be different from that shown in FIG. 2. As shown in FIG. 2, in each clock cycle 24, 1 bit of data from either core A 12 or core B 13 is transferred from DUT 10 to test system 15 on each output pin.

[0023] As described above, in the examples in Figures 1 and 2, during testing of DUT10, DUT10 transmits measurement data to the test system 15 in 5-bit packets, where the first 3 bits of each packet relate to core A12 and the last 2 bits relate to core B13. In this example, the five bits are annotated as A0, A1, A2, B1, and B2, where "A" refers to the bits received from core A12 and "B" refers to the bits received from core B13. Furthermore, each bit is annotated with an index indicating its packet number, so B1[8] indicates that this bit is the last bit of packet number 8 (index) and relates to core B.

[0024] In Figure 2, bits associated with core A12 are shaded green with horizontal lines, and bits associated with core B13 are shaded blue with vertical lines. The four pins can only transfer 4 bits 25 of the 5 bits of the data packet in the first clock cycle 24. The last bit 26 of the data packet, along with the 3 bits of the second data packet, is transferred in the next clock cycle 28. The remaining 2 bits of the second packet are transferred in the third cycle, and so on. In Figure 2, each data packet has a horizontal bar (e.g., bar 29) above the first bit. In this example, after 5 clock cycles 30, the first bit 32 of the packet (A0 in this example) is transferred again at the first pin (Pin1). This occurs every 5 clock cycles for this particular data packet and pin configuration.

[0025] This 5-cycle period is called a frame 31. Each cycle within a frame is called a time slot 33. Time slots and cycles contain the same data, but time slots are counted within a frame, and this count restarts with each new frame, while cycles are counted incrementing from zero without being renumbered. In this context, clock cycles, data frames, and time slots are numbered to indicate how the data is transferred over time. Data packets with different numbers of bits may have frames of different sizes.

[0026] Referring again to Figure 1, the test system 15 includes a time slot counter circuit 36 ​​configured to count clock cycles of the clock circuit 23 when data is output and received. The time slot counter circuit 36 ​​restarts its count each time the time slot counter counts the number of cycles in a frame. In this way, the time slot counter circuit 36 ​​maintains a time slot index with respect to the measurement data. The time slot counter circuit 36 ​​may be configured to specify the clock cycles in which the time slot counter starts and restarts. Thus, when constructing a test pattern to be used for testing the DUT, the test engineer can specify the cycles in which the time slot counter starts and restarts. In exemplary embodiments, a single shared time slot counter or multiple time slot counters may be instantiated for a given test data, such as a digital pattern burst.

[0027] Because there is a discrepancy between the number of pins and the number of bits per packet, each pin 17 does not transfer data in the order in which the bits occur within the packet. Therefore, in the example shown in Figure 2, for example, Pin1 transfers bits in the order A0, B1, B0, A2, and A1. For example, Pin2 transfers bits in the order A1, A0, B1, B0, and A2, and so on.

[0028] Figure 3 shows exemplary measurement data 38 (actual 1s and 0s) received in the test system 15 from DUT cores A12 and B13, in the case of a 4-pin, 5-bit packet as described in Figures 1 and 2. In Figure 3, the allocation of cycles, frames, and time slots to the two cores is the same as in Figure 2.

[0029] Figure 4 shows the data 40 expected to be received by the test system 15 from DUT cores A12 and B13 in the case of a 4-pin, 5-bit packet as described in Figures 1 to 3, where "H" indicates "high" or "1" and "L" indicates "low" or "0". The expected data is predetermined. For example, the expected data may include hardware and / or software in the DUT core, and may be the data that the DUT should provide if there are no errors in the DUT core. The test system 15 has a capture memory 29 or can access external memory for storing the received measurement data. The test system 15 may also have onboard memory 42 or can access external memory for storing the expected data. In this regard, the expected data may be received from the DUT manufacturer and pre-programmed into the test system.

[0030] In some cases, the measured data may not match the expected data, indicating a failure or "failure" of core A12 and / or core B13 of DUT10. In Figure 4, two examples of failures are labeled 49 and 51. For example, in Figure 3, the measured data 48 received from the DUT is "0" (low) in time slot 3 of frame 1, while in Figure 4, the expected data 49 in that frame and time slot is "H". In another example, in Figure 3, the measured data 50 received from the DUT is "1" (high) in time slot 1 of frame 1, while in Figure 4, the expected data 51 in that frame and time slot is "L". Such discrepancies between received data and expected data indicate a failure. Failures are shown in bold red.

[0031] The test system 15 may store failure data, i.e., data from failed transmissions such as 48 and 50 in Figure 2, in the capture memory 39 for later fault diagnosis. Since the capture memory 39 is a limited resource, it is not possible to capture all failure cycles. Conventionally, test systems have limited the storage of measurement data in the capture memory to a predetermined number of cycles captured by any one pin. The diagram in Figure 5 illustrates the storage of data cycles, including failures, in the capture memory in the prior art.

[0032] In the conventional technology example shown in Figure 5, the capture memory is limited to storing 5 failures per pin 47, regardless of which core the failure occurred in. Therefore, Pin 3 has reached its maximum storage limit of 5 failures 53-57 in the capture memory, while the other pins have not. As a result, failures 59 and 60 (see Figure 4) that occurred at Pin 3 in cycles 11 and 18 are not stored in the capture memory. Failure 61 that occurred at Pin 4 in cycle 13 is stored because that pin only has two fail counts in that cycle (the other failure at Pin 4 is in time slot 3 62 of frame 1).

[0033] By limiting storage based on the cumulative fail count of pins, it is ensured that pin data does not consume all of the capture memory. However, since pin data is related to multiple cores, this conventional storage method can mask failures in specific cores. For example, failure 60 (Figure 4) that occurred at Pin 3 in cycle 18 is the only failure related to Core B in this example, but according to the conventional storage method in Figure 5, the record of that failure is not stored in the capture memory.

[0034] Processes described herein, including process 65 and its variations, maintain a record of failures for each core. By maintaining a record of failures for each core, when a core is deemed to have failed, the process can limit (e.g., exclude) the storage of measurement data for that core, thereby increasing the memory storage capacity for data for other cores that were not determined to have failed. Exemplary process 65 may be performed in a test system such as the test system described herein, or other test systems not specifically described herein.

[0035] Referring to Figure 6, an exemplary process 65 includes receiving measurement data (e.g., TDM data) from multiple (e.g., two or more) cores of the DUT (65a). Process 65 may be executed once per cycle.

[0036] Measurement data is received in the test system from the DUT via multiple channels. These channels may be multiple pins, each corresponding to a channel, such as pin 17 in Figure 1. The measurement data consists of sequential data packets that are part of a bitstream. In this example, the measurement data includes a first number of bits from one core, such as core A12, and a second number of bits from a second core, such as core B13; however, the measurement data may include data from three, four, five, or more cores transmitted in the manner described herein. The measurement data is transmitted in parallel on the pins, as shown in Figure 2, with each time slot corresponding to the transmission of bits in the bitstream. The format of the measurement data (not necessarily the actual data itself, 1s and 0s) is repeated in the same pattern on each channel every frame. For example, as shown in Figure 2, in frame 0, time slot 0, A0(0) is transmitted on Pin1, A1(0) on Pin1, A2(0) on Pin3, and B0(0) on Pin1. Similarly, in frame 1, time slot 0, A0(4) is transmitted via Pin1, A1(4) via Pin1, A2(4) via Pin3, B0(4) via Pin1, and so on.

[0037] Process 65 compares the received measurement data with the corresponding expected data (65b) to determine pass / fail information for the first core A12 and the second core B13. In other words, the comparison of the expected data with the received measurement data identifies the bits in the measurement data that correspond to a failure in the core of the DUT. An example of such a failure is illustrated with reference to Figure 4 above. Failures may be stored in a table or other data structure in the capture memory 39 (or memory 42) on the test system.

[0038] Process 65 determines the fail count for each core (in this example, cores A12 and B13) (65c) and stores the fail count for each core in a table or other data structure in memory on the test system. This can be done by identifying and counting the number of times the bits for each core indicate failure at each pin. For example, if a failure is identified, the count associated with the current cycle for the core is incremented. Thus, the fail count for a core indicates how many times that core has failed the tests performed by the test system.

[0039] Figure 7 shows the per-core cumulative fail count 68a per pin for core A12 and the per-core cumulative fail count 68b for core B13. This information is accumulated based on the comparison (65b) described above and can be stored, for example, in a table or other data structure in the capture memory 39 (or memory 42) on the test system.

[0040] Process 65 compares the fail count at each pin for each core with a predetermined threshold for that core (65d). The threshold for each core may be set based on what the DUT manufacturer or test system operator considers to be an acceptable number of failures for that core. Different cores may have the same predetermined threshold or different predetermined thresholds. The predetermined thresholds may be stored in memory 42 on the test system and retrieved by process 65 to perform the comparison.

[0041] If the fail count is determined to be less than a predetermined threshold (65d), the measurement data is stored in the capture memory (65f). If the fail count is determined to be more than a predetermined threshold (65e), the measurement data is not stored in the capture memory (65g).

[0042] In some embodiments, the user may specify that core failures should be masked. In such embodiments, there is no need to compare measured data with expected data, and cycles are always considered to pass. Since there is no need to increment the fail count, no predetermined threshold is required to enable this masking. This may be useful when it is known that a core causes a large number of failures, and it is desirable not to record these failures. In some embodiments, masking involves ignoring all subsequently received measured data regarding the core. Data is received after the user has specified that core failures should be masked, in the sense that data received after that time is not stored.

[0043] In this regard, a software routine or circuit configuration may provide a way to indicate that one or more cores should not be involved in fault detection during a pattern burst. It is not necessary to modify the pattern itself to implement masking. For each channel, at each time slot index, the routine or circuit configuration indicates whether failures detected in that channel are masked. By indicating that all time slots associated with a given core of the DUT across all channels are masked, test engineers can prevent failures from that region from affecting the failure result. If the test program has already determined that one or more redundant DUT cores are failures, masking can exclude those DUT cores from further testing. By masking all time slots associated with all but one core, the failure is limited to that single DUT core, allowing for fault diagnosis when some of the functions described below are unavailable.

[0044] The repeating frame pattern described above facilitates the masking of subsequently received measurement data. By understanding where data related to core A occurs and where data related to core B occurs, that data can be masked. For example, referring to Figure 2, if data related to core A is masked after frame "0" 31, the circuit configuration understands the pattern related to core A in frames "1" 70, frame "2" 71, etc., because the pattern repeats. Therefore, by simply identifying the time slots in which the data for those frames is located based on the repetition of the pattern, the data for those subsequent frames can be masked, thereby reducing the amount of data stored in the capture memory.

[0045] In some embodiments, process 65 may be configured to generate a value indicating whether or not data for a time slot associated with a channel will be stored, based on a fail count for a core such as core A12 or core B13. The data may or may not be stored based on that value. In this regard, some time slots may store only a portion of the data in memory. For example, referring to Figure 2, if time slot 3 of frame 3 is subject to masking, and core A12 exceeds a predetermined number of failures, but core B13 does not, then only bits 74 and 75 for core A12 in that cycle will not be stored in capture memory.

[0046] Figure 8 illustrates how data storage in capture memory is limited based on the fail count per core. In Figure 8, cycles indicated by H or L are stored in capture memory. Referring to Figure 7, in cycle 18, the fail count for core B on pin 3 is 77 (Figure 7) which is 1, while in cycle 11, the fail count for core A on pin 3 is 79 (Figure 7) which is 6. In the example in Figure 8, the failure of core A on pin 3, cycle "11" 79 is not stored in capture memory because the fail count for core A, which is 6, exceeds the predetermined failure threshold of "5". However, the failure of pin 3, cycle "18" 77 is related to core B, and is stored in capture memory because the fail count does not exceed the failure threshold of core B, which is 5.

[0047] Process 65 may be carried out using a test system comprising one or more processing devices and / or a solid-state circuit configuration. An exemplary solid-state circuit configuration 80 that may be used to perform at least a portion of Process 65 is shown in Figure 9.

[0048] The circuit configuration 81 also includes two select values ​​("selects") 86, 87 that can be set to configure the function of the circuit. The two selects 86, 87 can be configured to determine whether the circuit configuration 140 is "by time slot" or "by core". That is, selects 86, 87 are configured to update the circuit configuration 140 when the core associated with the current cycle fails in a given cycle, or when the time slot associated with the current cycle fails in a given cycle. The circuit configuration 140 can be instantiated once per test channel, with the remaining circuit configurations in Figure 9 being common to all test channels.

[0049] The circuit configuration 80 includes a cycle counter 81 that receives a clock cycle, such as cycle 24 in Figure 2, and increments by one for each clock cycle to generate the current cycle count. The circuit configuration 80 stores a pre-programmed fixed frame length 82, which may be stored in memory or a register (not shown). The frame length 82 may be the number of time slots in a frame, such as 30 in Figure 2. The cycle count and frame length are combined by logic 127 to generate a modulo time slot value 84. The modulo time slot value indicates the current time slot of the received measurement data.

[0050] Memory 105 stores data that maps time slots to cores. The modulo time slot value 84 can be used in the lookup table in memory 105 to identify the core 129 corresponding to the current time slot. The multiplexer 90 selects an index value 89 corresponding to either the time slot identification information (modulo 84) or the core identification information (from memory 105) based on select 86. That is, if select 86 indicates "by time slot", the time slot identification information is used, and if select 86 indicates "by core", the core identification information is used. In each clock cycle, the index value 89 corresponding to the current time slot or core may or may not change based on selector 90 and the lookup table 105.

[0051] Memory 91 stores a lookup table or other data structure containing pass / fail values ​​that indicate whether at least one bit corresponding to the current time slot or current core is pass or fail (i.e., whether the bit matches the expected data). More specifically, this data is based on previous measurements of the time slot or core from past frames of the data. For example, the data may be an accumulation of previous measurements of the time slot or core based on past frames of the data, as described below.

[0052] The circuit configuration 80 also includes one or more comparator-like comparison circuits 93 and logic elements 94 such as OR gates. In each clock cycle, the circuit configuration 80 indexes the memory 91 based on the index value 89 and obtains an indexed value 100 from the memory with respect to the current time slot or core. In other words, a previous measurement of the current time slot or core based on past frames is obtained.

[0053] Furthermore, in each clock cycle, the comparison circuit configuration 93 compares the measurement data 95 for the current time slot and frame with the expected data 96 for the same time slot and frame to determine whether the measurement data for that clock cycle was acceptable or unacceptable.

[0054] The comparison result 99 is combined with the previously indexed value 100 from memory 91 and, for example, a logical OR is taken, and the result 101 is stored back in memory 91 as an updated (e.g., accumulated) value representing whether the time slot associated with that core or current cycle was a failure in previous cycles (e.g., previous frames) relating to that core or time slot. In other words, during each pattern cycle, the determined failure result is logically ORed with the memory contents at the current time slot or core location based on the index. Thus, the memory contents reflect the accumulated failure status of all previous cycles in that time slot.

[0055] In some examples, memory 91 may have a size / capacity that is roughly equal in depth to the maximum allowable number of time slots and roughly equal in width to the number of failing statuses collected in a single pattern cycle.

[0056] Circuit configuration 80 outputs a Boolean status 103 indicating a cumulative pass / fail value for a core or time slot. The cumulative pass / fail value continues to track whether a time slot or core has ever failed. The fail count continues to record how many times a time slot or core has failed. If a time slot is tracked, this information can be processed after a pattern burst to determine which area of ​​the DUT, for example, which core, failed. In other words, if a fail is stored for each time slot, by understanding the repeating pattern of the frame, the test system can identify which core of the DUT failed based on the fail in the time slot.

[0057] The circuit configuration 80 also includes logic 104 and memory 126 that stores a "fail count" indicating the number of failures related to the current time slot or core. The fail count indicates the number of failures that occurred in a given time slot or core. In each cycle, the output 107 of memory 126 reflects the number of times the time slot or core associated with the current cycle failed. Logic 104 is configured to use the pass / fail comparison result 99 to determine whether the value 108 to be updated in memory 126 is equal to the current value 125 in memory (for example, if there are no other failures in the time slot or core), or whether the value 125 is incremented by 1 (for example, if there was a failure on the time slot or core). If logic 104 determines that the current cycle failed based on the comparison result 99, logic 104 increments the current value 125 by 1 and outputs the resulting increment value 108 to memory 126. Otherwise, the logic outputs the current value 125 to memory 126. This time slot or per-core fail count may be used, as described herein, to limit the number of cycles stored in capture memory by core or by time slot.

[0058] The memory 126 may be indexed "by time slot" or "by core" based on the modulo time slot value 85 and core identification information 129, using the multiplexer 130 in the same manner as described above with respect to the multiplexer 90, based on the select 87.

[0059] Figure 10 is a block diagram showing the components of an exemplary ATE110, which comprises a test device / apparatus (also called a "tester") 110 and a control system 113. The ATE110 may be one embodiment of the test system 15 of Figure 1.

[0060] The ATE110 comprises a test head 115 and a device interface board (DIB) 116 physically and electrically connected to the test head 115. In this example, the DIB 116 comprises a circuit board having mechanical and electrical interfaces at site 118. One or more DUTs 120, such as DUT 10 (Figure 1), are connected to each of these sites for testing by the ATE. The DIB 116 may include, among other things, connectors, conductive traces, conductive layers, and circuit configurations for routing signals between the test equipment of the test head 115, the DUTs connected to the DIB sites, and other circuit configurations of the ATE. Power, including voltage, may be supplied to the DUTs connected to the DIB via one or more layers of the DIB.

[0061] The test head 115 comprises several test instruments 121a to 121n, each of which may be configured as appropriate to perform testing and / or other functions. Although only four test instruments are shown, the ATE 110 may include any appropriate number of test instruments, including one or more test instruments located outside the test head 15. A test instrument may be a hardware device comprising one or more processing devices and / or other circuit configurations. A test instrument may be configured (e.g., programmed) to output commands for testing the DUT held in the DIB. Commands for testing the DUT may be, or include, instructions, signals, data, parameters, variables, test patterns, and / or any other information designed to elicit a response from the DUT.

[0062] In some embodiments, commands for testing the DUT may be generated on the ATE110 by the ATE110 executing or interpreting a test program received from an external system. In one example, the test program may be, or include, a set of commands that are executed or interpreted by the ATE110 to generate commands that the ATE uses to test the DUT.

[0063] One or more (e.g., all) of the test equipment may be configured to receive responses from the DUT to commands sent from the ATE to the DUT. The responses include measurement data as described herein. The test equipment may be configured to analyze the response signals using one or more processing devices and / or circuit configurations 132 of Figures 1 and 9 to determine whether the DUT core has passed or failed the test, to store the data in the capture memory 130 or memory 131 according to process 65, and / or to send the response signals to the control system 113 for analysis according to process 65.

[0064] A test channel 123, including pins 16 and 17, is configured between the test head and the DIB to enable communication between the DUT and the test equipment.

[0065] The control system 113 is configured (e.g., by a program) to communicate with the test equipment 121a-121n to instruct and / or control the testing of the DUT. In some embodiments, this communication 129 may be via a computer network or via a direct connection such as a computer bus or optical medium. In some embodiments, the computer network may be or include a local area network (LAN) or a wide area network (WAN). The control system may be or include a computing system comprising one or more processing devices 124 (e.g., microprocessors) and memory 125 for storage. The control system 113 may be configured to provide the test equipment 121a-121n of the test head with test programs and / or commands that the test equipment uses to test the DUT. The control system 113 may also be configured to receive DUT response signals (e.g., measurement data) from the test equipment, determine whether the DUT core passed or failed the test, and store the data in capture memory 151 or memory 152 according to process 65.

[0066] All or part of the test systems and processes described herein, as well as various modifications thereof, may be configured or controlled at least partially by one or more computers, such as a control system 113, using one or more computer programs tangibly embodied in one or more information carriers, such as one or more non-temporary machine-readable storage media. The computer programs may be written in any form of programming language, including compiled or interpreted languages, and may be deployed in any form, such as as standalone programs or as modules, parts, subroutines, or other units suitable for use in a computing environment. The computer programs may be deployed to run on one computer, or at one site, or on multiple computers distributed across multiple sites and interconnected by a network.

[0067] Actions relating to the configuration or control of the test systems and processes described herein may be performed by one or more programmable processors running one or more computer programs for controlling or performing all or part of the operations described herein. All or part of the test systems and processes may be configured or controlled by dedicated logic circuit configurations such as FPGAs (Field Programmable Gate Arrays) and / or ASICs (Application-Specific Integrated Circuits), or embedded microprocessors localized in the equipment hardware.

[0068] Processors suitable for executing computer programs include, for example, both general-purpose and dedicated microprocessors, as well as any one or more processors in any type of digital computer. Generally, a processor receives instructions and data from read-only storage, random-access storage, or both. The elements of a computer include one or more processors for executing instructions and one or more storage devices for storing instructions and data. Generally, a computer also includes data from, or is operablely coupled to, one or more machine-readable storage media for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or mass storage devices for storing data. Examples of non-temporary, machine-readable storage media suitable for realizing computer program instructions and data include semiconductor storage devices such as EPROM (erasable programmable read-only memory), EEPROM (electrically erasable programmable read-only memory), and flash storage devices; magnetic disks such as internal hard disks or removable disks; magneto-optical disks; and all forms of non-volatile storage, including CD-ROM (compact disk read-only memory) and DVD-ROM (digital multipurpose disk read-only memory).

[0069] Elements of the different embodiments described may be combined to form other embodiments not specifically described above. Elements may be omitted from the above-described system without adversely affecting the operation of the element or the overall operation of the system. Furthermore, various distinct elements may be combined with one or more individual elements to perform the functions described herein.

[0070] Other embodiments not specifically described herein are also included in the following claims.

Claims

1. A system for testing a device under test (DUT), The DUT comprises a first core and a second core. The aforementioned system, A parallel channel for connecting to several pins on the DUT, comprising a channel for transmitting test data to the DUT and for receiving measurement data from the DUT based on the test data, In order to compare the measurement data with expected data and to determine the pass / fail status of the first core and the second core based on the comparison, the circuit configuration related to the channel and Equipped with, The measurement data includes time-division multiplexing (TDM) data consisting of consecutive data packets received from the DUT via the channel as part of a bitstream, each data packet including a first number of bits from the first core and a second number of bits from the second core, the data packets being transmitted in parallel on several pins, with each time slot corresponding to the transmission of the bitstream, and the TDM data being repeated in a pattern on the channel for every predetermined number of time slots.

2. The system according to claim 1, wherein the circuit configuration is configured to determine a fail count for the first core and the second core based on the comparison, the fail count indicating how many times the first core or the second core has failed the test.

3. The system according to claim 2, wherein the circuit configuration is configured to restrict the storage of subsequently received measurement data relating to the first core or the second core when the fail count exceeds a threshold number relating to the first core or the second core.

4. The system according to claim 3, wherein limiting storage includes ignoring the subsequently received measurement data relating to the first core or the second core.

5. The system according to claim 3, wherein limiting storage includes not storing the subsequently received measurement data relating to the first core or the second core in memory.

6. The system according to claim 3, wherein limiting storage includes limiting the number of failures for the first core or the second core, which affects how many cycles of the subsequently received measurement data for the first core or the second core are stored in memory, with one cycle comprising one time slot and one failure comprising a single failure of the test.

7. The method according to claim 3, wherein the circuit configuration is configured to output the fail count.

8. Equipped with even more memory, The system according to claim 1, wherein at least several cycles of measurement data from the first core and the second core are stored in the memory in the results log, and one cycle comprises one time slot.

9. The system according to claim 1, wherein the bits of the first number and the bits of the second number are different and cumulatively different from the number of pins, and two different portions of data packets are included in at least some of the time slots.

10. The system according to claim 1, wherein the predetermined number of time slots is greater than one time slot.

11. The circuit configuration is configured to determine a pass / fail status by accumulating pass / fail data related to time slots in the current data frame with previous pass / fail data related to time slots in previous data frames, wherein one data frame includes a predetermined number of time slots, according to claim 1.

12. The system according to claim 11, wherein the pass / fail data is based on the cumulative status of the first core and the second core across multiple repeated patterns of time slots.

13. The system according to claim 2, wherein determining the fail count includes separately counting the number of times the first core or the second core failed the test.

14. The method according to claim 13, wherein counting includes incrementing a memory address based on a time slot.

15. The method according to claim 13, wherein counting includes incrementing the address of a first memory based on a time slot, the memory mapping the time slot to a core number, and the core number addressing a second memory.

16. Equipped with even more memory, The system according to claim 1, wherein the circuit configuration is configured to store the fail count per core in the memory after a predetermined number of cycles of the measurement data.

17. A system for testing a device under test (DUT), The DUT comprises a first core and a second core. The aforementioned system, A parallel channel for connecting to several pins on the DUT, comprising a channel for transmitting test data to the DUT and for receiving measurement data from the DUT based on the test data, In order to compare the measurement data with expected data, and to determine the fail count per time slot indicating how many times the first core or the second core failed the test based on the comparison, the circuit configuration related to the channel and Equipped with The measurement data includes time-division multiplexing (TDM) data consisting of consecutive data packets received from the DUT via the channel as part of a bitstream, each data packet including a first number of bits from the first core and a second number of bits from the second core, the data packets being transmitted in parallel on several pins, with each time slot corresponding to the transmission of the bitstream, and the TDM data being repeated in a pattern on the channel for every predetermined number of time slots.

18. The circuit configuration is configured to compare the measured data with expected data by summing the pass / fail data associated with the time slot in the current data frame with previous pass / fail data for the time slot in a previous data frame, wherein one data frame includes a predetermined number of time slots, according to claim 17.

19. The system according to claim 18, wherein the pass / fail data is based on the cumulative status for each time slot.

20. The system according to claim 17, wherein the circuit configuration is configured to restrict the storage of subsequently received measurement data relating to the first core or the second core when the fail count exceeds a threshold number.

21. The system according to claim 20, wherein limiting storage includes ignoring the subsequently received measurement data relating to the first core or the second core.

22. The system according to claim 20, wherein limiting storage includes not storing the subsequently received measurement data relating to the first core or the second core.

23. A system for testing a device under test (DUT), The DUT comprises a first core and a second core. The aforementioned system, A parallel channel for connecting to several pins on the DUT, comprising a channel for transmitting test data to the DUT and for receiving measurement data from the DUT based on the test data, A circuit configuration associated with the channel to mask data from the first core or the second core based on user input. Equipped with The measurement data includes time-division multiplexing (TDM) data consisting of consecutive data packets received from the DUT via the channel as part of a bitstream, each data packet including a first number of bits from the first core and a second number of bits from the second core, the data packets being transmitted in parallel on several pins, each time slot corresponding to the transmission of the bitstream, and the TDM data being repeated in a pattern on the channel every predetermined number of time slots. A system in which masking includes ignoring or not storing the data from the first core or the second core.

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