Apparatus, method, and computer program for collecting diagnostic information

Abstract

The device has a processing circuit for performing Single Instruction Multiple Data (SIMD) processing on an array having multiple data items, and the processing circuit supports SIMD processing for multiple array sizes. The processing circuit can select the array size for which to perform SIMD processing based on SIMD processing configuration information. A diagnostic information acquisition circuit is provided to collect diagnostic information about the software running on the processing circuit, and the diagnostic information acquisition circuit filters the collection of diagnostic information based on the SIMD processing configuration information.

Description

Technical Field

[0001] This technique relates to the field of data processing. More particularly, this technique relates to the collection of diagnostic information.

[0002] A data processing system may include a diagnostic information collection circuit for collecting diagnostic information regarding software executed on a processing circuit. This diagnostic information can be used, for example, to analyze software performance to identify portions of software programs that may be causing poor performance and possible reasons for any performance problems. The diagnostic information can be used by software engineers to optimize the software to reduce execution time and better utilize available resources within the data processing system.

[0003] At least some examples provide an apparatus comprising: a processing circuit operable to perform single instruction multiple data (SIMD) processing on an array including a plurality of data items, the processing circuit being configured to support SIMD processing for a plurality of array sizes and to select an array size for performing SIMD processing based at least in part on SIMD processing configuration information; and a diagnostic information collection circuit for collecting diagnostic information regarding software executed by the processing circuit, the diagnostic information collection circuit being configured to filter the collection of diagnostic information based on the SIMD processing configuration information.

[0004] At least some examples provide a computer-readable medium for storing computer-readable code for fabricating the apparatus described above.

[0005] At least some examples provide a method for collecting diagnostic information, the method comprising collecting diagnostic information about software running on a processing circuit, the processing circuit being operable to perform single-instruction multiple data (SIMD) processing on an array containing multiple data items, the processing circuit supporting SIMD processing for multiple array sizes, the processing circuit being configured to select an array size for performing SIMD processing based at least in part on SIMD processing configuration information, and collecting diagnostic information comprising filtering the collection of diagnostic information based on SIMD processing configuration information.

[0006] At least some examples include providing a computer program that, when executed by a host data processing device, includes instructions that control the host data processing device to provide an instruction execution environment for executing target program code, wherein the computer program includes processing program logic that is operable to perform single-instruction multiple data (SIMD) processing on an array containing multiple data items, wherein the processing program logic supports SIMD processing for multiple array sizes, and the processing program logic is configured to select an array size for performing SIMD processing based at least in part on SIMD processing configuration information, and diagnostic information gathering program logic that collects diagnostic information about software running on the processing program logic, wherein the diagnostic information gathering program logic is configured to filter the collection of diagnostic information based on SIMD processing configuration information.

[0007] At least some examples provide computer-readable media for storing the aforementioned computer programs. These computer-readable media may also be non-temporary computer-readable storage media. [Brief explanation of the drawing]

[0008] Further aspects, features, and advantages of this technique will become clear when you read the following example in conjunction with the attached drawings. [Figure 1] An example of a device having a diagnostic information acquisition circuit is shown. [Figure 2] Examples of vector and matrix registers are shown. [Figure 3A] An example of SIMD processing configuration information is shown. [Figure 3B] An example of SIMD processing configuration information is shown. [Figure 4] This flowchart shows the process for selecting the array size for performing SIMD processing. [Figure 5] This flowchart shows the process of collecting or suppressing diagnostic information based on the operating mode of the processing circuit. [Figure 6] This table shows the dependence of the collection or suppression of diagnostic information on the operating mode of the processing circuit. [Figure 7] This flowchart shows the process of collecting or suppressing diagnostic information based on the array size specified by the SIMD processing configuration information. [Figure 8] An example of a performance monitoring circuit is shown. [Figure 9] An example of a device with a profiling circuit is shown. [Figure 10] This shows an example of multiple processors sharing a matrix processing circuit. [Figure 11] This figure shows an example of a simulation.

[0009] Before examining the example with reference to the attached drawings, the following explanation of the example is provided.

[0010] The techniques described herein provide processing circuits capable of performing single-instruction multiple-data (SIMD) processing. SIMD processing allows a single instruction to perform operations on data across an array containing multiple data items. While operations performed on different data items may be executed concurrently and in parallel using multiple processing elements, it should be understood that in some cases, SIMD processing can be achieved using iterative execution by a single processing element (or more generally, a number of processing elements less than the size of the array). In this sense, SIMD processing represents an architectural feature (i.e., an option available for specification by the program code), and the implementation of the microarchitecture may or may not use multiple processing elements to implement SIMD processing. Examples of SIMD processing include vector processing, which performs operations on a vector containing multiple elements logically arranged in one dimension, or matrix processing, which performs operations on a matrix containing multiple elements logically arranged in two dimensions, and possibly on a vector.

[0011] According to the techniques described herein, a processing circuit is configured to select an array size for performing SIMD processing, at least in part, based on SIMD processing configuration information. This SIMD processing configuration information may be accessible as a result of being stored in a memory-mapped register or a system register that can be modified using software. This allows software, and therefore the user, to control the array size used to perform SIMD processing.

[0012] However, regardless of the content of the SIMD processing configuration information, and therefore regardless of the array size, if diagnostic information is collected about a processing circuit, certain insights into the performance of the processing circuit may be lost. For example, if diagnostic information is used to count the number of cycles required to execute a particular algorithm using SIMD processing operations, the count may vary significantly depending on whether a small array size was used (in which case a large number of SIMD operations may be required) or a large array size was used (in which case fewer SIMD operations may be required). Therefore, being able to filter the collection of diagnostic information based on the array size being used can be useful in providing accurate insights into the operation of the device, particularly the operation of SIMD processing by the processing circuit. Furthermore, it may be difficult, or even impossible, to decompose diagnostic information collected for SIMD processing performed across a range of different array sizes, without depending on the array size being used. Diagnostic information associated with one array size may be obscured by the presence of diagnostic information collected while another array size was being used. For example, even if the number of SIMD processing operations performed is known along with the array size used during the software execution period, it may not be possible to determine the total number of data items processed without knowing how many operations were performed in each mode. For software engineers whose goal is to examine software execution, this can hinder them from gaining meaningful insights into software performance.

[0013] In some cases, a software engineer may only be interested in the execution of software associated with a specific value of SIMD processing configuration information, and therefore, by filtering the diagnostic information collected based on this SIMD processing configuration information, they may be able to select only the information of interest.

[0014] According to the techniques described herein, the apparatus thus comprises a diagnostic information acquisition circuit configured to filter the collection of diagnostic information based on SIMD processing configuration information.

[0015] In some cases, filtering the collection of diagnostic information includes collecting or suppressing the collection of diagnostic information depending on the SIMD processing configuration information. However, in some cases, filtering the collection of diagnostic information can take other forms. For example, basic diagnostic information may be collected regardless of the SIMD processing configuration information, and filtering may determine whether additional levels of diagnostic information should be collected based on the SIMD processing configuration information.

[0016] Diagnostic information can take several possible forms, but in some cases, diagnostic information is ●Cycle count, which measures the waiting time for a specific event during the processing of a sample operation. ● Clock cycle progress, ● Execution of an instruction (either a general instruction or a specific type of instruction) ● A memory access request is made (either a general, arbitrary memory access, or a specific type of memory access, such as load or store). ● Cache access, cache line fill, or cache miss may occur (which may be specific to a particular level or type of cache). ● A TLB access, TLB line fill, or TLB miss occurs (this can also be an event that is tracked for any TLB in general, or it can be specific to a particular TLB instance (e.g., data-side TLB or instruction-side TLB) or a particular TLB level (e.g., level 1 or level 2)). ● Occurrence of branch prediction errors ● The queue or buffer becomes full (variations of this may include providing specific buffers such as the instruction issue queue, load buffer, or store buffer), or ● Pipeline stalls caused by specific causes (e.g., cache misses, TLB misses, or the load or store buffer becoming full), ● The number of cycles required to execute a page table walk to fill the TLB, ● The number of cycles required to service a line fill request to put data into the cache following a cache miss, ● An indication of the current occupancy of a particular queue or buffer, indicating one or more of the above.

[0017] It will be understood that this list is not exhaustive and that a wide variety of different aspects of the operation of the processing circuit can be monitored.

[0018] In some examples, the processing circuit supports at least two operating modes associated with SIMD processing having different array sizes. More specifically, the processing circuit can operate in a first operating mode in which the processing circuit performs SIMD processing with an array size (i.e., number of elements) determined based on a first array size definition state, and a second operating mode in which the processing circuit performs SIMD processing with the array size based on a second array size definition state. In this case, the SIMD processing configuration information can indicate whether the SIMD processing circuit is operating in the first operating mode or the second operating mode. Thus, the diagnostic information collection circuit can filter the collection of diagnostic information (e.g., determine whether to collect diagnostic information or suppress the collection of diagnostic information) based on whether the processing circuit is operating in the first operating mode or the second operating mode. Thus, the SIMD processing configuration information does not directly define the array size itself, but the SIMD processing configuration information can be indirectly used to identify the array size used (e.g., by referring to the first array size definition state / the second array size definition state).

[0019] In addition to deciding whether to collect diagnostic information based on the operating mode of the processing circuit, or instead, the diagnostic information collection circuit may include in the collected diagnostic information an indication of the operating mode in which the processing circuit was operating during the period to which the diagnostic information pertains. The operating mode indication included in the diagnostic information may be used to provide insights into the behavior of the software in different operating modes, or to enable the calculation of values ​​that depend on the array size used for SIMD processing.

[0020] The diagnostic information acquisition circuit may also be configured to select the operating mode in which diagnostic information is acquired. To enable this, the device includes a mode filter configuration circuit for storing a mode filter configuration status. Based on the value of the mode filter configuration status, the diagnostic information acquisition circuit may determine whether diagnostic information should be acquired or suppressed for each operating mode. For example, in response to a mode filter configuration status having a first value, the diagnostic information acquisition circuit may acquire diagnostic information when the processing circuit is in a first operating mode and suppress the acquisition of diagnostic information when the processing circuit is in a second operating mode. Thus, a first value of the mode filter configuration status may be used to cause the diagnostic information acquisition circuit to acquire diagnostic information only when the processing circuit is operating in a first operating mode.

[0021] In some examples, a diagnostic information acquisition circuit may, in response to a mode filter configuration status having a second value, collect diagnostic information when the processing circuit is in a second operating mode and suppress the collection of diagnostic information when the processing circuit is in a first operating mode. Thus, a second value for the mode filter configuration status may be used to selectively collect diagnostic information only when operating in the second operating mode.

[0022] Therefore, these techniques can be used to select which operating modes should collect diagnostic information and to collect diagnostic information only for those operating modes. Thus, insights into the software's behavior when running in a specific operating mode can be obtained. Since operating modes are associated with different array size definition states, this can be used to ensure that diagnostic information is not collected for SIMD processes running on array sizes defined by different items in the array size definition state, which could obscure the collected information.

[0023] In some cases, it may be desirable to collect diagnostic information regardless of the operating mode. To support this, a diagnostic information collection circuit may collect diagnostic information in response to a mode filter configuration status having a third value when the processing circuit is in a first or second operating mode. In other words, the diagnostic information is therefore collected independently of the operating mode.

[0024] It should be understood that this technique is not limited to examples where only two operating modes are used. In fact, one or more additional operating modes may be provided in which the array size used for SIMD processing is defined based on one or more corresponding additional items in the array size definition state.

[0025] In some examples, instead of specifying the operating mode in the SIMD processing configuration information, or in addition to it, the SIMD processing configuration information specifies the array size to be used. This can take the form of the array size included in the SIMD processing configuration information, or it can be encoded (for example, by a value corresponding to the selection of a particular array size from a list of possible array sizes). The diagnostic information acquisition circuit can then determine how to filter the diagnostic information based on the array size on which the SIMD processing was performed (as can be established using the SIMD processing configuration information).

[0026] To support filtering diagnostic information based on a specified array size, the device may include an array size filter configuration storage circuit for storing an array size filter configuration status indicating one or more array sizes from which diagnostic information should be collected. The diagnostic information collection circuit can then collect diagnostic information regarding SIMD processes performed using one or more array sizes specified by the array size filter configuration status. Conversely, for SIMD processes performed using array sizes not specified by the array size filter configuration status, the diagnostic information collection circuit may be configured to suppress the collection of diagnostic information.

[0027] An example of a diagnostic information acquisition circuit that can implement this technique is a performance monitoring circuit. A performance monitoring circuit is provided for monitoring the performance of software running on a processing circuit. The performance monitoring circuit includes event counters, each maintaining its own event count value based on monitoring of events during software processing by the processing circuit. A control circuit for configuring the event counters based on counter configuration information is also provided. The counter configuration information may include event type assignment information indicating which types of events are assigned to be monitored by the event counters. Such a performance monitoring circuit can be useful in investigating possible causes of poor performance while the software is running on the processing circuit, because the event count values ​​can expose information about internal events occurring within the processing circuit while the software is running (such as cache misses, branch prediction misses, instruction stalls, and buffer fullness).

[0028] The configuration information may also include filter configuration information that can be used to select how the performance monitoring circuit should filter updates to event counters, depending on the SIMD processing configuration information. Therefore, one or more of the event counters may be specific to events occurring, for example, in a particular operating mode or using one or more specific array sizes. The performance monitoring circuit may, in response to filter configuration information for a given event counter having a first value, update the event counter for events occurring when the processing circuit is in a first operating mode, suppress updates to the event counter when the processing circuit is in a second operating mode, or filter updates to the event counter based on the SIMD processing configuration information. Similarly, the performance monitoring circuit may, in response to filter configuration information for a given event counter specifying one or more specific array sizes, update the event counter for events occurring when the processing circuit is performing SIMD processing on one of those specific array sizes, and suppress updates to the event counter when different array sizes are used. Thus, it is possible to maintain a count of events related to a period of interest, while events collected outside of that period are ignored for counting purposes.

[0029] In some examples, performance monitoring circuits can operate to scale updates to event counters by a scaling factor before the event counters are updated. If a particularly large number of events to be counted is expected, scaling can be used to reduce the amount by which the count in the event counter needs to be updated, thereby reducing the possibility of event counter overflow where the count becomes too high for the event counter to record, and reducing the requirements on the circuitry provided to handle the event counters (for example, by reducing the amount of circuitry required to add two counters together). Thus, performance monitoring circuits can scale updates to a particular event counter in response to counter configuration information specifying that a scaling factor should be applied to that particular event counter.

[0030] In some examples, the scaling factor may depend on the array size on which the processing circuit is performing SIMD operations. For example, counter configuration information might configure a particular event counter to count the number of data items that are computed. This number can become very large because, when the processing circuit performs SIMD operations, a single instruction can lead to the computation of multiple data items. Therefore, scaling can be used to scale the count maintained by a particular event counter to a more manageable size by a scaling factor. This scaling factor may be the size of the array used to perform the SIMD operations. If this scaling is done properly, the event counter may be incremented by the number of SIMD operations performed. It is possible to later reverse the scaling to recover the number of elements that were computed.

[0031] However, if the processing circuit can operate with different array sizes, it may not be possible to properly recover the number of computed elements because it is unknown which array size was used when the event was recorded. Therefore, by providing a performance monitoring circuit that can selectively filter events based on SIMD processing configuration information associated with the array size, this technique can enable the maintenance of event counters related to operations performed only for a specified array size / operating mode. This may allow unscaled counts (e.g., the number of computed data items) to be recovered from scaled counters.

[0032] Another situation in which this technique may be applied is for the statistical profiling of software. To perform software profiling, the apparatus may include a sampling circuit that selects a subset of instructions or microoperations as sample operations to be profiled. The profiling circuit may also be provided to acquire sample records containing diagnostic information about the operation type of the sample operation and the behavior of the sample operation directly attributable to the sample operation, in response to the processing of the instructions or microoperations selected as sample operations by the sampling circuit.

[0033] The information contained in the sample record can directly indicate events that occurred during the processing of the sample operation, such as whether a cache miss occurred at a given level of cache, whether a branch prediction miss occurred for a given branch, or it can indicate a cycle count that measures the waiting time for a particular event during the processing of the sample operation.

[0034] In this approach, since the sample record obtains information directly attributable to the sampling operation, it avoids the "skid" problem that can occur in interrupt-based profiling mechanisms that use counters to count specific events such as cache misses or branch prediction misses that may affect poor performance. When a given number of such events are detected, an interrupt can be generated to cause an exception handling routine to read the architecture state from registers or other diagnostic information, which can then be made accessible for diagnostic analysis. In such interrupt-based profiling mechanisms, there may be a "skid" delay between the time the interrupt is signaled and the exception handling routine reads the architecture state from registers or other performance monitoring information, and the time the exception handler begins to collect the obtained architecture state or diagnostic information.

[0035] Because the sampling circuit selects only a subset of instructions or microoperations as sample operations, the hardware and power overhead for collecting information about sample operations is significantly reduced. The sample records obtained for sample operations can provide a statistical view of the program's overall performance, rather than attempting to capture the behavior of all operations. Furthermore, by providing a sampling circuit that selects specific instructions or microoperations as sample operations to be profiled, it is possible to track events occurring at different stages of the pipeline as the sample operation progresses through the pipeline. This is not possible in examples where profiling is based on capturing the architecture state or counters at the time of a specific event, and the information may not be directly attributable to a specific operation but may be based on multiple different behaviors.

[0036] Sampling and profiling circuits can be useful in providing detailed information about the results and performance of specific operations being processed by processing circuits, which can be useful in identifying possible reasons for poor performance when running a given program. However, another aspect of profiling may be identifying which parts of program code are executed more frequently than others. Software developers may have limited time available for code optimization and may want to improve the performance of frequently executed code sections rather than less frequently executed code sections.

[0037] To enable insights into the operation of processing circuits that depend on the array size used for SIMD processing, the profiling circuit may be configured so that the collection of sample records depends on SIMD processing configuration information. The profiling circuit may therefore be configured to selectively filter the acquisition of sample records based on SIMD processing configuration information (e.g., whether the processing circuit is in a first operating mode, a second operating mode, or the array size being used).

[0038] The profiling circuit may also include indications of SIMD processing configuration information in the sample record, such as the operating mode of the processing circuit or the array size used when the sample operation was processed. This technique allows the collected information to be decomposed based on the operating mode / array size when the sample record is analyzed.

[0039] When SIMD processing configuration information indicates the operating modes used for SIMD processing, the first and second operating modes may correspond to the use of different elements of the circuit by the processing circuit to perform SIMD processing. Thus, the processing circuit may be configured to perform SIMD processing using a first SIMD processing circuit when in the first operating mode, and to perform SIMD processing using a second SIMD processing circuit when in the second operating mode. This may correspond, for example, to the use of a vector processing circuit and a matrix processing circuit, both of which can perform SIMD processing. For example, one of the first and second SIMD processing circuits may be a vector processing circuit, and the other of the first and second SIMD processing circuits may be a matrix processing circuit. In some examples, the matrix processing circuit may be operable to perform vector processing so that the processing circuit can utilize either the vector processing circuit or the matrix processing circuit for vector processing operations. However, the vector lengths (i.e., array sizes) used by the vector processing circuit and the matrix processing circuit when performing vector processing are based on different parts of the vector length that define the state, and therefore may differ. Therefore, by controlling the collection of diagnostic information depending on whether a vector processing circuit or a matrix processing circuit is used, relevant diagnostic information applicable to the SIMD processing circuit being used can be obtained. However, generally, the first and second SIMD processing circuits do not need to correspond to matrix and vector processing circuits. Both the first and second SIMD processing circuits can correspond to a vector processing circuit, a matrix processing circuit, or another form of SIMD processing circuit.

[0040] In some microarchitectures, at least one of a first SIMD processing circuit and a second SIMD processing circuit may be shared among multiple processors (e.g., a central processing unit (CPU), a graphics processing unit (GPU), and a neural processing unit (NPU)). For example, a processor may provide its own dedicated vector processing, as well as access to matrix processing circuits shared with other processors.

[0041] The first array size definition state and the second array size definition state, as well as the dependence of the array size on these states, can take several forms. For example, the first array size definition state and the second array size definition state may be stored in their respective registers, or in different areas of the same register.

[0042] In some examples, the first and second array size definition states directly specify the array size to be used so that the processing circuit performs SIMD processing at the specified array size. However, in some examples, the array size definition state specifies the requested array size to be used. However, the actual array size used may further depend on the array sizes supported by the hardware and / or software-configurable constraints on which array sizes can be selected.

[0043] Therefore, the processing circuit may be configured to determine the array size to use for SIMD processing based on the array size definition state for a particular operating mode, by preferentially using the requested array size for that mode. However, if the requested array size is unsuitable because it falls outside the range of either the software configuration or the maximum / minimum supported array sizes imposed by the hardware, the processing circuit may use a different array size supported for that operating mode.

[0044] Therefore, a device capable of supporting SIMD processing having a range of array sizes, which has the array size to be used controlled using SIMD processing configuration information, has been described. Thus, the array size used to perform SIMD processing may vary. To avoid the use of different array sizes that obscure the diagnostic information collected by the diagnostic information acquisition circuit, the collection of diagnostic information may be conditional on the array size being used, or more generally, on the SIMD processing configuration that governs the array size being used.

[0045] The device may include the processing circuit and diagnostic information acquisition circuit described above, as well as either or both of the first SIMD processing circuit and the second SIMD processing circuit.

[0046] A computer-readable medium can store computer-readable code for manufacturing the aforementioned device. As will be further explained below, this can provide an electronic representation of the circuit design, which can then be disseminated to another party (or a further party downstream in the manufacturing chain) to enable that party to manufacture the device.

[0047] The techniques described above can be implemented using hardware circuits provided for implementing the processing circuit and diagnostic information acquisition circuit described above.

[0048] However, the same technique may also be implemented within a computer program that runs on a host data processing unit to provide an instruction execution environment for the execution of target program code. Such a computer program may control the host data processing unit to simulate an architectural environment provided on a hardware device that actually supports the target code according to a particular instruction set architecture, even if the host data processing unit itself does not support its architecture. The computer program may have processing program logic that emulates the functionality of the processing circuit described above, and diagnostic information acquisition logic that emulates the functionality of the diagnostic information acquisition circuit described above. Such a simulation can enable software development of the target program code (e.g., debugging software targeting a device having the processing circuit and / or diagnostic information acquisition circuit described above) to begin before the hardware having the processing circuit and / or diagnostic information acquisition circuit is actually ready. By executing the target program code on the simulated execution environment, this can enable testing of the target code in parallel with the ongoing development of a hardware device that supports new features of the performance monitoring circuit. The simulation program may be stored on a storage medium, which may be a non-temporary storage medium.

[0049] Here, we will explain a specific example with reference to a diagram.

[0050] Figure 1 shows an example of a device 2 having a diagnostic information acquisition circuit 60. The data processing device has a processing pipeline 4 which includes several pipeline stages, each implemented by a corresponding circuit. In this example, the pipeline stages include a fetch stage 6 for fetching instructions from the instruction cache 8. A branch predictor 7 also provides predictions of the results of branch instructions, which are used by the fetch stage 6 to determine which instructions to fetch across branches. The pipeline stages also include a decode stage 10 for decode the fetched program instructions to generate microoperations (decoded instructions) to be processed by the rest of the pipeline stages; an issue stage 12 for checking whether the operands required for a microoperation are available in the register file 14 and, when the operands required for a given microoperation are available, for issuing a microoperation for execution; and an execute stage 16 for executing a data processing operation corresponding to the microoperation by processing the operands read from the register file 14 to generate a result value. The result value can then be written back to the register file 14. This is just one example of a possible pipeline configuration, and it will be understood that other systems may have additional stages or different configurations of stages. For example, an out-of-order processor may include a register renaming stage for mapping architectural registers specified by program instructions or microoperations to physical register specifiers that identify physical registers in the register file 14. In some examples, there may be a one-to-one relationship between program instructions decoded by the decoding stage 10 and corresponding microoperations processed by the execution stage. Alternatively, there may be one-to-many or many-to-one relationships between program instructions and microoperations; for example, a single program instruction may be split into two or more microoperations, or two or more program instructions may be merged so that they are processed as a single microoperation.

[0051] Execution stage 16 includes several processing units for performing different classes of processing operations. For example, the execution units may include a scalar processing unit 20 (e.g., equipped with a scalar arithmetic / logic unit (ALU) 20 for performing arithmetic or logical operations on scalar operands read from register 14), a vector processing unit 22 for performing vector operations on vectors containing multiple data elements, a matrix processing unit 24 for performing matrix operations on vectors and matrices, and a load / store unit 28 for performing load / store operations to access data in memory systems 8, 30, 32, and 34. Here, the vector processing unit 22 and the matrix processing unit 24 each represent an example of a SIMD processing circuit. The matrix processing unit 24 can perform matrix operations on matrix inputs, as well as operate to perform vector operations. In some examples, the matrix processing unit 24 provides all the functionality of the vector processing unit 22, however, the matrix processing unit 24 may implement only a subset of the vector processing operations supported by the vector processing unit 22. Other examples of processing units that can be provided in the execution stage include a floating-point unit for performing operations involving values ​​expressed in floating-point format, or a branch unit for processing branch instructions.

[0052] Device 2 also includes a diagnostic information collection circuit 60 for collecting diagnostic information regarding the operation of Device 2. The diagnostic information may include, for example, information regarding cache misses, branch prediction misses, instruction stalls, buffer fullness, and the count of executed instructions / operations.

[0053] Register 14 includes a scalar register 25 for storing scalar values, a vector register 26 for storing vector values, and a matrix register 27 for storing matrix values. Register file 14 also includes a SIMD processing configuration information register 66 for storing SIMD processing configuration information.

[0054] The SIMD processing configuration information may, in some cases, indicate an operating mode such that when operating in a first operating mode, the device 2 is configured to use the vector processing unit 22 to perform vector processing 22, and when operating in a second operating mode, the device is configured to use the matrix processing unit 24 for vector processing, as indicated by the SIMD processing configuration information 66. In such a case, the register file 14 also includes a first array size definition state register 62 containing a first array size definition state that specifies the array size used by the vector processing unit 22. The register file 14 also includes a second array size definition state register 64 containing a second array size definition state that specifies the array size used by the matrix processing unit 24.

[0055] In some cases, the SIMD processing configuration information 66 may directly specify the array size used when performing SIMD processing using either the vector processing unit 22 or the matrix processing unit 24.

[0056] As shown in Figure 1, the memory system includes a Level 1 data cache 30, a Level 1 instruction cache 8, a shared Level 2 cache 32, and main system memory 34. This is merely one example of a possible memory hierarchy, and it will be understood that other arrangements of caches are possible. The specific types of processing units 20-28 shown in execution stage 16 are merely examples, and other implementations may have different sets of processing units or include multiple instances of the same type of processing unit to handle multiple microoperations of the same type in parallel. Figure 1 is merely a simplified representation of some of the components of a possible processor pipeline configuration, and it will be understood that the processor may include many other elements not shown for brevity.

[0057] Figure 2 shows examples of a vector register 200 and a matrix register 210. The vector register 200 contains multiple elements 202-a, 202-b, ... 202-n (collectively referred to as elements 202). Each element 202 may be used to store a separate data item. A vector and / or matrix processing unit can then perform operations on the vector 200 as a whole by applying operations individually to the data items across the elements 202 of the vector 200. The operations may, in some cases, be applied to all elements 202 of the vector 200, but in some cases, predicate control may be employed to allow the operations to be selectively applied to only some of the elements 202 of the vector 200, depending on the value of a predicate stored in a predicate register. The matrix register 210 also comprises multiple elements 204-a, 204-b, ... 204-mn (collectively referred to as elements 204), each element 204 may be used to store a separate data item. The matrix processing unit 24 can perform operations on vector and / or matrix data, and then perform operations on the data items within each element 204.

[0058] Figures 3A and 3B schematically show possible forms of the SIMD processing configuration information 66. As shown in Figure 3A, the SIMD processing configuration information 66 includes SIMD mode information indicating whether the processing circuit 4 is operating in a first operating mode or a second operating mode. When the processing circuit 4 is operating in the first operating mode, the array size used by the processing circuit 4 is specified by a first array size definition state 62, and when the processing circuit 4 is operating in the second operating mode, the array size used by the processing circuit 4 is specified by a second array size definition state 64.

[0059] Figure 3B shows an example in which the SIMD processing configuration information 66 specifies the array size. The array size may be stored in the SIMD processing configuration information register 66, or it may be indicated by the SIMD processing configuration information register 66.

[0060] Figure 4 is a flowchart showing the process for selecting an array size for performing SIMD processing. The array size may correspond to the vector length used for vector processing or the matrix dimension used for matrix processing. After starting in step 302, the processing circuit 4 determines whether the requested array size, requested by the software (for example, by setting a value in the requested array size register or by indicating the requested size in the instruction field), is smaller than the minimum supported array size. The minimum supported array size may be the minimum size set by the software or the minimum array size supported by the hardware performing the SIMD processing.

[0061] If the requested array size is smaller than (or equal to) the minimum supported array size, the processing circuit 4 uses the minimum supported array size as the array size for the calculation in step 306.

[0062] If the requested array size is greater than the minimum array size, the flow proceeds to step 308 to determine if the requested array size is greater than the maximum supported array size. If the requested array size is greater than the maximum supported array size, the flow proceeds to step 310 to use the maximum supported array size. Otherwise, the requested array size is used in step 312.

[0063] Figure 5 is a flowchart showing the process of collecting or suppressing diagnostic information based on the operating mode of the processing circuit 4. After the process starts in step 402, the mode filter configuration status is checked in step 404. The mode filter configuration status allows for the selection of the operating mode in which diagnostic information should be collected.

[0064] If the mode filter configuration status has a first value (indicating that diagnostic information should only be collected for the first operating mode), the flow proceeds to step 406, where it is determined whether the processing circuit 4 is operating in the first operating mode. If the processing circuit 4 is operating in the first operating mode, the flow proceeds to step 410, where diagnostic information is collected. On the other hand, if the processing circuit 406 was operating in an operating mode other than the first operating mode, the flow proceeds to step 412, which corresponds to suppressing the collection of diagnostic information.

[0065] If the mode filter configuration status checked in step 404 instead has a second value, the flow proceeds to step 408 to determine whether the processing circuit is operating in the second operating mode. If processing circuit 4 is operating in the second operating mode, the flow proceeds to step 410 to collect diagnostic information. On the other hand, if processing circuit 406 is operating in an operating mode other than the second operating mode, the flow proceeds to step 412, which corresponds to suppressing the collection of diagnostic information.

[0066] If the mode filter configuration status has a third value used to indicate that diagnostic information should be collected regardless of the operating mode, the flow proceeds to step 410, where diagnostic information is collected without checking which mode the processing circuit 4 is operating in.

[0067] Figure 6 is a table showing the dependency of diagnostic information collection or suppression on the operating mode of the processing circuit 4. As shown in the table, the mode filter configuration status can be implemented using 2 bits, thereby providing four possible values ​​for the mode filter configuration status. When the mode filter configuration status has the value 0b00, the diagnostic information collection circuit is configured to collect diagnostic information regardless of the mode in which the processing circuit 4 is operating. When the mode filter configuration status has the value 0b01, the diagnostic information collection circuit is configured to collect diagnostic information only when the processing circuit 4 is operating in the first mode, and therefore suppresses the collection of diagnostic information when the processing circuit 4 is operating in the second mode. When the mode filter configuration status has the value 0b10, the diagnostic information collection circuit collects diagnostic information only when the processing circuit 4 is operating in the second mode (and does not collect it when the processing circuit 4 is operating in the first mode). Thus, the dependency of diagnostic information collection on the operating mode of the processing circuit 4 can be controlled using the mode filter configuration status. When the mode filter configuration status has the final possible value 0b11, the behavior of the diagnostic information collection circuit is undefined.

[0068] Figure 7 is a flowchart showing the process for collecting or suppressing diagnostic information based on the array size specified by the SIMD processing configuration information. In this example, after starting in step 702, in step 704, the array size used by the processing circuit 4 to perform the SIMD processing is compared with one or more array sizes specified by the array size filter configuration status, which indicates which array sizes for which diagnostic information should be collected.

[0069] The array size filter configuration status can indicate in several ways which array sizes should be used to collect diagnostic information. For example, the array size filter configuration status could be a bitmap where each bit indicates whether the corresponding array size is enabled or disabled for diagnostic information acquisition, or it could indicate a size threshold to specify whether diagnostic acquisition is enabled or disabled depending on a comparison between the current array size and the threshold.

[0070] If the processing circuit 4 is using the array size specified by the array size filter configuration status (which can be established by comparing the SIMD processing configuration information with the array size filter configuration status), diagnostic information is collected for processing in step 708. Otherwise, the collection of diagnostic information is suppressed in step 706.

[0071] Please understand that the collection / suppression of diagnostic information described with reference to Figures 5-7 represents one example of how the collection of diagnostic information can be filtered. In other examples, some basic diagnostic information is generated along with additional diagnostic information regardless of SIMD processing configuration information (e.g., operating mode), and the additional diagnostic information may provide more detailed information that is selectively generated based on SIMD processing configuration information, for example.

[0072] Figure 8 shows a performance monitoring circuit representing an example of a diagnostic information acquisition circuit 60 to which this technique may be applied. As shown in Figure 8, the performance monitoring circuit 70 includes several event counters 42, each maintaining a corresponding event count value 43. The performance monitoring circuit also includes a control circuit 44 that configures how the event counters behave based on counter configuration information 46 set by the user. For example, the counter configuration information 46 may be state information stored in the processor's registers 14 (e.g., system registers), and may be stored in memory-mapped registers implemented as separate hardware from the memory systems 30, 32, 34, or may be stored within the memory systems 30, 32, 34 themselves (if memory-mapped registers or data structures within the memory itself are used to provide the counter configuration information, the control circuit 44 may access those registers / structures based on a user-programmable base address). Thus, generally, a programming interface is provided that allows a user (e.g., a software developer performing debugging) to program the counter configuration information 46, and as a result, the event counters 42 may be configured to collect various types of performance monitoring information of interest when debugging a particular program running on the processing circuit 4. For example, debugging software may be executed to set counter configuration information. The target program being debugged can then be executed. While the target program is running, the performance monitoring circuit 70 operates according to the pre-configured counter configuration information.

[0073] The performance monitoring circuit 70 includes an event selection circuit 48 that receives several event signals 45 indicating the status of corresponding types of events from the processing circuit 4 or other parts of the data processing system 2. Although shown as a single logic block in Figure 8, the event selection circuit may have a separate event selector for each event counter, which independently selects the event signals 45 monitored by the corresponding event counter.

[0074] For example, event signals may be generated to indicate a wide variety of types of information about various components of the data processing device 2.

[0075] Some event signals may indicate the occurrence of a specific action (or a count of how many times that action has occurred). For example, such an action might be: ● Clock cycle progress, ● Execution of an instruction (either a general instruction or a specific type of instruction) ● A memory access request is made (either a general, arbitrary memory access, or a specific type of memory access, such as load or store). ● Cache access, cache line fill, or cache miss may occur (which may be specific to a particular level or type of cache). ● A TLB access, TLB line fill, or TLB miss occurs (this can also be an event that is tracked for any TLB in general, or it can be specific to a particular TLB instance (e.g., data-side TLB or instruction-side TLB) or a particular TLB level (e.g., level 1 or level 2)). ● Occurrence of branch prediction errors ● The queue or buffer becomes full (variations of this may include providing specific buffers such as the instruction issue queue, load buffer, or store buffer), or ●This may include any of the following: a pipeline stall caused by a specific reason (e.g., a cache miss, a TLB miss, or the load or store buffer becoming full).

[0076] Other event signals are quantitative status values ​​that indicate the characteristics of the event that occurred, i.e., ● Number of cycles required to perform a page table walk to satisfy the TLB, ● The number of cycles required to service a linefill request to put data back into the cache following a cache miss, or ●Quantitative information can be specified, such as an indication of the current occupancy of a particular queue or buffer.

[0077] The above list of event types is not exhaustive, and it should be understood that a wide variety of different event types can be monitored.

[0078] The counter configuration information 46 includes event type assignment information that specifies the event types monitored by each event counter 42. For example, each event counter 42 may have a corresponding event type field in the counter configuration information, which has coding to select which event signal 45 to use for a particular event counter 42. For each event counter, the event selection circuit 48 selects one of the event signals 45 based on the event type assignment information of that counter, and that event signal 45 is passed to the corresponding event counter 42 as an event status indication 47 representing the status of the event assigned to that event counter 42 by the counter configuration information 46.

[0079] The counter configuration information 46 also includes filter configuration information 52 to allow the user to filter updates to the event counter 42 based on SIMD processing configuration information that defines the array size to be used. The filter configuration information 52 may indicate, for example, the operating mode in which the performance monitoring circuit 70 counts events for a particular event counter 42 associated with an item in the mode filter configuration information 52, using the coding shown in Figure 6. When the processing circuit 4 is operating in the operating mode indicated by the mode filter configuration information 52 that counts are suppressed (or otherwise filtered), the performance monitoring circuit 70 refrains from incrementing the event count value 43 for one or more associated event counters 42. The filter configuration information 52 may further, or alternatively, specify a particular array size in which updates to the event counter 43 should be made, such that updates to the event counter 43 associated with other array sizes are suppressed.

[0080] The counter configuration information 46 also includes scale configuration information 54, which can be used by the user to indicate a scale factor applied to the count. Based on the scale configuration information 54, the performance monitoring circuit 70 can adjust the amount by which the event counter 42 is updated. Therefore, if it is anticipated that the event count will need to be updated frequently, or that the event count is likely to be particularly high, the count may be scaled down, for example, to avoid overflow of the event counter 42 and to reduce the requirements on downstream circuits that operate on the event count value. The scale factor may, in some cases, depend on the array size on which the processing circuit is operating. For example, if a count of the number of computed data items is maintained while performing SIMD processing, the count may be scaled by the array size used by the processing circuit to avoid excessively large updates to the event count value. This can be a convenient way to scale the count, since the performance monitoring circuit 70 only needs to count the number of SIMD operations performed by the processing circuit. However, if different array sizes are used by the processing circuit in the process of performing SIMD processing, recovering the number of computed data items from the scaled count may be difficult or impossible. Therefore, the application of a scaling factor may be used in combination with a filter, resulting in events being counted only in a specific operating mode or using a specific array size, and allowing information of interest to be more easily recovered from the scaled count.

[0081] For each event counter 42, a set of hardware circuit logic is provided, including a storage circuit for storing a corresponding event count value 43, and a counter control logic circuit (implemented in hardware) for updating the event count value as a function of an event status indication 47 provided to the counter 42 by an event selection circuit 48. For example, the increment value may be selected as a function of the event status indication 47, and the new value of the event counter value 43 may be calculated by adding the increment value to the previous value of the event counter value 43. Control signals 49 may be provided to each event counter 42 by the control circuit 44 based on counter configuration information 46. These control signals 49 may constitute how a given counter selects a function to be applied to the event status indication 47, and how the increment value should be selected based on the result of applying the function to the event status indication 47.

[0082] The performance monitoring circuit 70 provides an event counter read interface 50 that allows software to read the event count value of each counter 42. For example, the read interface 50 may be provided by exposing each event count value 43 to the software as a system register that can be read by a system register read instruction executed by the processing circuit 4. Alternatively, the event count value 43 of each event counter 42 may be exposed via a memory-mapped interface so that it can be read by software executing a load instruction that specifies a memory address mapped to a storage location that stores each event count value 43. In either case, debugging software can read the current value of each event count value to determine information about what happened when the target software was being processed by the processing circuit. During use, for example, debugging software may use breakpoints or watchpoints to trigger an exception when the target software reaches a desired point that needs investigation (e.g., a desired instruction address reached in the program flow, or a desired data address accessed by a memory access instruction). When an exception is triggered, an exception handler provided by the debugging software can read the event count value 43 and analyze the information provided by each event count value 43 to determine what happened. This is useful for diagnosing potential performance inefficiencies in the program code and can help identify possible improvements that can be made to the program code being executed to enable it to run more efficiently.

[0083] Figure 9 shows an example of a device 2 having a profiling circuit capable of implementing this technique. Many of the elements in Figure 9 are present in Figure 1, and a complete explanation of those elements will not be repeated here.

[0084] To support software development, device 2 is provided with hardware resources that enable the collection of profiling information regarding the behavior of instructions processed by the processing pipeline 4, which software developers can use to perform code optimization for the purpose of modifying the code. A sampling circuit 82 is provided to select specific instructions or microoperations as sample operations to be profiled by the profiling circuit 84. The sampling circuit 82 may select sample operations at different stages of the pipeline. For example, the sampling circuit 82 may select specific fetched instructions as sample operations and tag those fetched instructions in the fetch stage 6 to indicate that the profiling circuit 84 should collect information regarding the behavior of the sample operations as the instructions progress down the pipeline 4. Alternatively, the tagging of sample operation instructions by the sampling circuit may be performed in the decoding stage 10 or a later stage. Furthermore, sample operations can be selected at the granularity of individual microoperations rather than at the granularity of architecture program instructions fetched from memory.

[0085] The sampling circuit may use an interval counter to count instructions or microoperations and determine when the next sample operation should be selected. The sampling interval may be defined by a user-configurable parameter in a control register or may be fixed to a specific interval. The interval counter counts the number of operations processed by the processing circuit 4. The operations to be counted may be fetched instructions, decoded instructions, or decoded microoperations. When the sample interval has elapsed, the next operation (e.g., fetched instruction, decoded instruction, or decoded microoperation) is tagged as a sample operation. For example, a tag bit associated with an instruction may be set, and this tag bit may accompany the instruction or microoperation selected as a sample operation as it progresses down the pipeline 4. The sampling circuit 82 then resets the counter again based on the new sampling interval.

[0086] The advantage of selecting only a subset of operations as sample operations is that it significantly reduces the overhead of tracking information for profiling. For example, the sampling interval can be set long enough so that only a single operational in pipeline 4 at a time is selected as a sample operation, so that the profiling circuit 84 only needs to provide enough hardware resources to track the behavior of a single sample operation at a time. This avoids the overhead of having to store information for multiple operations based on an operation identifier associated with a particular sample operation, and having an index storage structure that selects which entries in the storage structure to update based on the information of a particular sample operation.

[0087] Nevertheless, other embodiments may opt to support multiple sample operations selected at once, which may result in higher hardware costs. In these embodiments, sampling a subset of operations as sample operations has the advantage of significantly reducing the amount of profiling information generated compared to embodiments that attempt to track every instruction, and makes it feasible to obtain a wider range of data for each sample operation and thus perform more meaningful profiling analysis.

[0088] The profiling circuit 84 is configured to collect information about the behavior of the sample operation selected by the sampling circuit 82. The monitoring circuit may include an event detection circuit to detect the occurrence of various types of events for the sample operation. The type of event detected may depend on the type of sample operation. For example, in the case of a branch operation selected as a sample operation, the event may track whether a branch prediction miss occurred or whether the branch predictor 7 correctly predicted the branch. In the case of a load / store operation, the event may include, for example, whether the load / store operation missed in a particular level of cache 30, 32, whether the address translation lookup for the load / store instruction missed in the TLB or a particular level of TLB, or whether an address failure occurred for the load / store instruction. Other types of events that may be monitored may include failures such as an instruction fetch missing in the instruction cache 8, an undefined instruction exception, or whether a particular instruction was delayed due to resource contention. The monitoring circuit can also obtain information about specific instructions, such as the instruction address of a sample operation, the target address of a load-store operation, or the branch target address of a branch operation, as well as architectural state items from register 14 obtained when the sample operation reaches a specific stage of processing (e.g., a context identifier that identifies the processing context in which the sample operation was processed). The monitoring circuit may also have a cycle counter that counts the number of processing cycles required for a specific operation to complete, such as measuring the latency of an address translation or a cache lookup, or, for example, the number of cycles of an operation progressing between a first processing point and a second processing point. Thus, it will be understood that the monitoring circuit can collect a variety of information.

[0089] The acquired monitoring information can be recorded in sample records stored in the sample record storage circuit (e.g., registers or buffers) of the profiling circuit 84. Within the sample record acquired for a given sample operation, the record can specify the type of operation associated with the sample operation (e.g., branching, load / store operations, or vector or matrix operations) and also provide various information directly attributable to the sample operation. The acquisition of sample records in the sample record storage is performed in hardware in the background of the processing performed on pipeline 4, and therefore, it is not necessary to execute any specific software instructions to collect information within the sample records.

[0090] The profiling circuit 84 may filter the collection of sample records in accordance with the SIMD processing configuration information 66. For example, the profiling circuit 84 may generate sample records depending on whether the processing circuit 4 is operating in a first operating mode (where the array size is determined by a first array size definition state 62) or a second operating mode (where the array size is determined using a second array size definition state 64), as described herein. The profiling circuit 84 may optionally filter the collection of sample records based on the array size in response to the SIMD processing configuration information 66 specifying the array size on which the processing circuit 4 performs SIMD processing. Here, filtering the collection of sample records may correspond to selectively suppressing or collecting sample records based on SIMD processing configuration information (e.g., array size / operating mode), or the profiling circuit 84 may determine the amount of information to include in the sample records in accordance with the SIMD processing configuration information.

[0091] The profiling circuit 84 may also include information about the array size on which the SIMD operation was performed in the sample record. The profiling circuit 84 may include indications of the operating mode or the array size used in the sample record.

[0092] Sample records can be made accessible for diagnostic analysis by writing them to profiling buffer structures stored in memory systems 30, 32, and 34. Writing sample records to the profiling buffers in memory can be done without interrupting processing on pipeline 4, and thus no specific software instructions are required to store the sample records in the memory system. Therefore, a certain number of sample records can be output to the profiling buffer without interruption until enough sample records are generated and written to the profiling buffer to risk overflowing, at which point a performance monitoring interrupt can be triggered to interrupt processing, and as a result, the exception handler can take action to ensure that the sample records previously stored in the profiling buffer remain accessible for diagnostic analysis. Alternatively, the sample record can be output to a trace buffer, which is a dedicated hardware structure separate from the memory systems 30, 32, 34 for storing diagnostic information on-chip and / or for outputting the acquired sample record via a trace output port (directly or via a trace buffer), the trace output port being a set of integrated circuit pins through which the sample record can be output to an external off-chip trace analyzer or storage device.

[0093] Figure 10 shows an example of multiple processors 945, 940 sharing a matrix processing circuit 950. As shown in Figure 10, there are two processors, CPU0 940 and CPU1 945. Each processor could include all the elements of Figure 1 and / or Figure 9, but only the execution circuits 16, 966 are shown in Figure 10. The execution circuits 16, 966 include scalar processing units 20, 970, vector processing units 22, 972, and load / store units 28, 978, as described above in relation to Figure 1. However, here the matrix processing functionality is provided by the matrix processing circuit 950, which is external to the individual processors 940, 945. The matrix processing circuit 950 is configured to perform matrix and vector processing and has vector registers 952 and matrix registers 956 for storing vector and matrix data, respectively, to support this processing. In some cases, the matrix processing circuit 950 can operate to perform all vector processing operations supported by the vector processing units 22 and 972; however, in some cases, the matrix processing circuit 950 may only support a more limited range of vector processing operations. Therefore, for those vector processing operations, each processor 940 and 945 may use either of their respective vector processing units 22 and 972, or use the matrix processing unit 950 via the matrix processing interfaces 924 and 974. The use of the vector processing units 22 and 972 may correspond to one operating mode as described herein, and the use of the matrix processing unit 950 may perform vector processing corresponding to another operating mode. Either or both of the vector processing units 22 and 972 and the matrix processing unit 950 may support a range of vector lengths (i.e., array sizes) for performing vector processing using the vector lengths used as indicated by the first and second array size definition states. It will be understood that processing units shared between processors do not necessarily have to be matrix processing units. For example, in some examples, each processor has its own dedicated vector processing unit and can access a shared vector processing unit.In fact, various configurations of SIMD processing units are possible, in which one or more SIMD processing units are shared among multiple processors.

[0094] The concepts described herein may be embodied in computer-readable code for the fabrication of devices that embody the described concepts. For example, computer-readable code may be used in one or more stages of a semiconductor design and fabrication process, including an electronic design automation (EDA) stage, to fabricate an integrated circuit comprising a device that embodies the concepts. The computer-readable code described herein may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices that embody the concepts described herein.

[0095] For example, computer-readable code for fabricating a device embodying a concept described herein may be embodyed by code that defines a Hardware Description Language (HDL) representation of the concept. For example, the code may define a Register-Transfer-Level (RTL) abstraction of one or more logic circuits for defining a device embodying the concept. The code may define the HDL representation of one or more logic circuits embodying the device in Verilog, SystemVerilog, Chisel, or an intermediate representation such as Very High-Speed ​​Integrated Circuit Hardware Description Language (VHDL) and FIRRTL. The computer-readable code may provide a definition that embodies the concept using a system-level modeling language such as SystemC and SystemVerilog, or other behavioral representations of the concept that can be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concept.

[0096] Additionally or alternatively, computer-readable code may define low-level descriptions of integrated circuit components that embody the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer-readable representations of integrated circuit components may be generated by applying one or more logic synthesis processes to the RTL representations to generate definitions used for fabricating devices that embody the invention. Alternatively or additionally, one or more logic synthesis processes may generate bitstreams from computer-readable code that are loaded into a Field Programmable Gate Array (FPGA) to configure the FPGA to embody the concepts described herein. The FPGA may be deployed for the purpose of verifying and testing the concept before fabrication in an integrated circuit, or the FPGA may be deployed directly into a product.

[0097] Computer-readable code may include a mixture of code representations for the fabrication of a device, for example, a mixture of one or more RTL representations, netlist representations, or other computer-readable definitions used in semiconductor design and fabrication processes for fabricating a device embodying the present invention. Alternatively or additionally, the concept may be defined as a combination of computer-readable definitions used in semiconductor design and fabrication processes for fabricating a device and computer-readable code that defines instructions to be executed by the device once it is fabricated.

[0098] Such computer-readable code may be placed on any known temporary computer-readable medium (such as wired or wireless transmission of code over a network) or on a non-temporary computer-readable medium such as a semiconductor, magnetic disk, or optical disk. An integrated circuit fabricated using computer-readable code may include components such as a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or one or more other components that individually or collectively embody a concept.

[0099] Figure 11 also illustrates possible simulator implementations. While the embodiments described above implement the invention in terms of devices and methods for operating specific hardware that supports the technique, it is also possible to provide an instruction execution environment according to the embodiments described herein, which are implemented using a computer program. Such a computer program is often referred to as a simulator, insofar as it provides a software-based implementation of a hardware architecture. Various simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 930, optionally running a host operating system 920 and supporting a simulator program 910. In some configurations, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or multiple different instruction execution environments may be provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that run at reasonable speeds, but such techniques may be justified in certain circumstances, such as when it is desirable to run native code on a different processor for reasons of compatibility or reuse. For example, a simulator implementation may provide an instruction execution environment with additional functionality not supported by the host processor hardware, or it may provide an instruction execution environment typically associated with a different hardware architecture. An overview of the simulation is provided in "Some Efficient Architecture Simulation Techniques," Robert Bedichek, 1990 Winter USENIX Conference, pp. 53-63.

[0100] While embodiments have been described so far with reference to specific hardware components or features, in simulated embodiments, equivalent functionality may be provided by suitable software components or features. For example, certain circuits may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware such as registers or caches may be implemented as software data structures in simulated embodiments. In configurations where one or more of the hardware elements referenced in the embodiments described above reside on host hardware (e.g., host processor 930), some simulated embodiments may, if preferred, utilize the host hardware.

[0101] The simulator program 910 can be stored on a computer-readable storage medium (which may be a non-temporary medium) and provides a program interface (instruction execution environment) to the target program code 900 (which may include an application, operating system, and hypervisor), which is the same as the interface of the hardware architecture modeled by the simulator program 910. Therefore, program instructions in the target code 900, including instructions for setting the operating mode, may be executed from within the instruction execution environment using the simulator program 910, and as a result, the host computer 930, which does not actually possess the hardware features of the device 2 described above, can emulate these features. The functions of the diagnostic information acquisition circuit 60 can be emulated by the corresponding program logic 916. By providing a simulation of the device shown in Figure 1 in software form, it is possible to develop debugging software to interact with the diagnostic information acquisition circuit 60 before the hardware is actually available.

[0102] Therefore, the simulator program 910 may have processing program logic 912 that simulates the state of the processing circuit 4 described above. For example, the processing program logic 912 may control transitions of the execution state (e.g., exception level, operating mode) in response to events occurring during the simulated execution of the target code 900. The instruction decoding program logic 914 decodes the instructions of the target code 900 and maps them to the corresponding instruction set in the native instruction set of the host device 930. The register simulation logic 913 maps register access requested by the target code to access the corresponding register-emulated data structure 933 maintained by the host hardware of the host device 930, such as by accessing the registers of the host device 930 or data in memory 932. The memory management program logic 915 implements address translation, page table walk, and access control checks in a manner corresponding to the MMU in hardware implementation embodiments, but also has the additional function of mapping simulated physical addresses obtained by the simulated MMU 915 to host virtual addresses used to access host memory 932. These host virtual addresses can themselves be translated to host physical addresses using the standard address translation mechanism supported by the host (the translation of host virtual addresses to host physical addresses is outside the scope of what is controlled by the simulator program 910). Thus, the simulated physical address space accessed by the target code 900 can be mapped to a region 934 of host memory 932 representing the simulated target memories 8, 30, 32, and 34 of the target processing unit 2 simulated by the simulation program 910. This simulated target address space 934 can be used, for example, to store diagnostic information 935 that is read from the diagnostic information stored on the chip and represented by the simulated diagnostic information storage 936 into the memory systems 8, 30, 32, and 34 in the corresponding hardware devices.

[0103] The simulator program 910 includes a diagnostic information acquisition program logic 916 that simulates the behavior of the diagnostic information acquisition circuit 60.

[0104] In this application, the phrase "configured to..." is used to mean that an element of the device has a configuration that enables it to perform a defined operation. In this context, "configuration" means the arrangement or interconnection of hardware or software. For example, the device may have dedicated hardware to provide the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that an element of the device must be modified in any way to provide the defined operation.

[0105] While exemplary examples of the present invention are described in detail herein with reference to the accompanying drawings, it will be understood that the present invention is not limited to these precise examples, and that various changes and modifications can be made to these examples by those skilled in the art without departing from the scope and spirit of the invention as defined by the accompanying claims.

Claims

1. It is a device, A processing circuit capable of performing single-instruction multiple data (SIMD) processing on an array containing multiple data items, which supports the SIMD processing for multiple array sizes, The processing circuit is configured to select an array size for performing the SIMD processing based at least partially on SIMD processing configuration information, and includes a processing circuit. A diagnostic information collection circuit that collects diagnostic information relating to the software executed by the processing circuit, The apparatus comprises a diagnostic information acquisition circuit configured to filter the collection of the diagnostic information based on the SIMD processing configuration information.

2. The apparatus according to claim 1, wherein filtering the collection of the diagnostic information based on the SIMD processing configuration information includes collecting or suppressing the collection of the diagnostic information according to the SIMD processing configuration information.

3. The processing circuit is capable of operating in a first operating mode in which the processing circuit is configured to perform the SIMD processing with an array size determined based on a first array size definition state, and a second operating mode in which the processing circuit is configured to perform the SIMD processing with an array size determined based on a second array size definition state. The SIMD processing configuration information indicates whether the SIMD processing circuit is operating in the first operating mode or the second operating mode. The apparatus according to claim 1 or 2, wherein the diagnostic information acquisition circuit is configured to filter the collection of the diagnostic information based on whether the processing circuit is operating in the first operating mode or the second operating mode.

4. The apparatus according to claim 3, wherein the diagnostic information acquisition circuit is configured to include in the diagnostic information acquired for the SIMD processing an indication of whether the processing circuit is operating in the first operating mode or the second operating mode.

5. The aforementioned device is The mode filter configuration memory circuit further stores the mode filter configuration status, The apparatus according to any one of claims 1 to 4, wherein the diagnostic information acquisition circuit acquires the diagnostic information when the processing circuit is in the first operating mode, and suppresses the acquisition of the diagnostic information when the processing circuit is in the second operating mode, in response to the mode filter configuration status having a first value.

6. The apparatus according to claim 5, wherein the diagnostic information acquisition circuit acquires the diagnostic information when the processing circuit is in the second operating mode, and suppresses the acquisition of the diagnostic information when the processing circuit is in the first operating mode, in response to the mode filter configuration status having a second value.

7. The apparatus according to claim 5 or 6, wherein the diagnostic information acquisition circuit acquires the diagnostic information in response to the mode filter configuration status having a third value, both when the processing circuit is in the first operating mode and when the processing circuit is in the second operating mode.

8. The processing circuit is configured to perform the SIMD processing with an array size specified by the SIMD processing configuration information. The apparatus according to any one of claims 1 to 7, wherein the diagnostic information acquisition circuit filters the collection of the diagnostic information based on the array size specified by the SIMD processing configuration information.

9. The apparatus according to any one of claims 1 to 8, wherein the diagnostic information acquisition circuit is configured to include the array size at the time the SIMD processing was performed in the diagnostic information acquired for the SIMD processing.

10. It further includes an array-size filter configuration storage circuit that stores the array-size filter configuration status, The diagnostic information acquisition circuit acquires the diagnostic information in response to the array size filter configuration status, which indicates that diagnostic information should be acquired for a specific array size on which the processing circuit is performing the SIMD processing. The apparatus according to any one of claims 1 to 9, wherein the diagnostic information acquisition circuit suppresses the collection of the diagnostic information in response to the array size filter configuration status which specifies that the processing circuit should collect diagnostic information for one or more array sizes other than the specific array size on which the SIMD processing circuit is running.

11. The diagnostic information acquisition circuit includes a performance monitoring circuit for monitoring the performance of the software executed on the processing circuit. The performance monitoring circuit comprises a plurality of event counters, each of which maintains its own event count value based on monitoring of events during the execution of the software on the processing circuit. The diagnostic information acquisition circuit includes a control circuit that configures the event counter based on counter configuration information, and the counter configuration information includes filter configuration information. The performance monitoring circuit is configured to filter updates to the given event counter for an event based on the filter configuration information and the SIMD processing configuration information. The apparatus according to any one of claims 1 to 10.

12. The aforementioned device is A sampling circuit that selects a subset of instructions or microoperations processed by the processing circuit as sample operations to be profiled, The apparatus according to any one of claims 1 to 11, further comprising: a profiling circuit that acquires a sample record including diagnostic information indicating the behavior of the sample operation in response to the processing of an instruction or microoperation selected as a sample operation by the sampling circuit.

13. The apparatus according to claim 12, wherein the profiling circuit is configured to include indications of at least a portion of the SIMD processing configuration information in the sample record.

14. The apparatus according to claim 12 or 13, wherein the profiling circuit is configured to selectively suppress the acquisition of sample records according to the SIMD processing configuration information.

15. The apparatus according to claim 3 or any dependent claim, wherein the processing circuit is configured to use a first SIMD processing circuit to perform the SIMD processing in the first operating mode and a second SIMD processing circuit to perform the SIMD processing in the second operating mode.

16. The apparatus according to claim 15, wherein the first array size definition state defines the array size of the first SIMD processing circuit, and the second array size definition state defines the array size of the second SIMD processing circuit.

17. At least one of the first array size definition state and the second array size definition state defines the software-requested array size for each of the SIMD processing circuits. Each of the aforementioned SIMD processing circuits has the requested array size and, Software-configurable maximum array size, Software-configurable minimum array size, Maximum hardware-supported array size, and The apparatus according to claim 15 or 16, configured to perform the SIMD process with an array size determined based on at least one of the minimum hardware-supported array sizes.

18. The apparatus according to any one of claims 15 to 17, wherein at least one of the first SIMD processing circuit and the second SIMD processing circuit is one of a vector processing circuit and a matrix processing circuit.

19. The apparatus according to any one of claims 15 to 18, wherein at least one of the first SIMD processing circuit and the second SIMD processing circuit is shared among a plurality of processors.

20. It is a device, The apparatus according to any one of claims 15 to 19, The first SIMD processing circuit and, An apparatus comprising the second SIMD processing circuit described above.

21. A computer-readable medium for storing computer-readable codes for manufacturing the apparatus according to any one of claims 1 to 20.

22. A method for collecting diagnostic information, This includes collecting the diagnostic information relating to the software running on the processing circuit, The processing circuit is operable to perform single-instruction multiple data (SIMD) processing on an array containing multiple data items, supports the SIMD processing for multiple array sizes, and is configured to select the array size for performing the SIMD processing based at least partially on the SIMD processing configuration information. A method for collecting the diagnostic information, comprising filtering the collection of the diagnostic information based on the SIMD processing configuration information.

23. A computer program that includes instructions to control the host data processing device to provide an instruction execution environment for executing target program code when executed by the host data processing device, wherein the computer program A processing program logic capable of performing single-instruction multiple data (SIMD) processing on an array containing multiple data items, which supports the SIMD processing for multiple array sizes, The processing program logic is configured to select an array size for performing the SIMD processing, at least partially based on SIMD processing configuration information. A diagnostic information collection program logic that collects diagnostic information relating to software executed on the aforementioned processing program logic, A computer program comprising: diagnostic information collection program logic configured to filter the collection of diagnostic information based on the SIMD processing configuration information.

24. A computer-readable medium for storing the computer program described in claim 23.

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