Dual Vector Arithmetic Logic Unit

Abstract

The processing system (100) executes wavefronts (302, 304) in multiple arithmetic logic unit (ALU) pipelines (232, 234) of a single instruction multiple data (SIMD) unit (230) in a single execution cycle. Each of the ALU pipelines includes several ALUs that execute instructions (310, 312, 314) on wavefront operands collected from vector general purpose process register (VGPR) banks (510, 511, 512, 513) in a cache (220) and output results of the executed instructions to the wavefront in a buffer (235). By storing the wavefronts provided by the VGPR banks in the cache, more wavefronts can be made available to the SIMD units without increasing the VGPR bandwidth, allowing multiple ALU pipelines to execute instructions during a single execution cycle.

Description

[Background technology]

[0001] A graphics processing unit (GPU) is a complex integrated circuit configured to perform graphics processing tasks. For example, GPUs perform graphics processing tasks required by end-user applications such as video game applications. GPUs are also increasingly being used to perform other tasks unrelated to graphics. In many applications, such as graphics processing on a GPU, a series of work items, also called threads, are processed to produce a final result. In many modern parallel processors, for example, execution units within a single instruction multiple data (SIMD) unit execute a set of work items synchronously. The set of work items generated by a common process is called a wavefront or warp.

[0002] During processing, one or more SIMD units execute multiple wavefronts simultaneously. Execution units of SIMD units, such as one or more ALU pipelines containing multiple arithmetic logic units (ALUs), execute wavefronts to perform graphics and vector processing operations. Wavefront execution terminates when all work items within the wavefront have completed processing. Each wavefront contains multiple work items processed in parallel using the same instruction set. In some cases, a wavefront is executed in a subset of the SIMD unit's ALU pipeline, while the rest of the SIMD unit's ALU pipeline is idle. If the number of work items in a wavefront exceeds the number of ALUs in the ALU pipeline, wavefront execution spans two or more execution cycles.

[0003] This disclosure will be better understood by referring to the accompanying drawings, and its many features and advantages may become apparent to those skilled in the art. The use of the same reference numerals in different drawings indicates similar or identical items. [Brief explanation of the drawing]

[0004] [Figure 1] This is a block diagram of a processing system according to several embodiments. [Figure 2] This is a partial block diagram of a processing system employing dual arithmetic logic unit (ALU) pipeline processing in several embodiments. [Figure 3] This figure shows a dual instruction for executing two single-instruction multiple-data (SIMD) ALU instructions in two ALU pipelines of a SIMD unit in a single cycle, according to several embodiments. [Figure 4] This figure shows a single instruction for executing a wavefront in two ALU pipelines of a SIMD unit in a single cycle, according to several embodiments. [Figure 5] This figure shows how to swizzle wavefront work items between vector general-purpose register banks according to several embodiments. [Figure 6] This flowchart illustrates, in several embodiments, a method for executing one or more instructions in two ALU pipelines of a SIMD unit in a single cycle. [Modes for carrying out the invention]

[0005] Figures 1-6 illustrate the technique for executing wavefronts in multiple arithmetic logic unit (ALU) pipelines of a single-instruction multiple data (SIMD) unit in a single execution cycle. Each ALU pipeline contains several ALUs (also referred to as "lanes") that execute instructions on wavefronts (operands) collected from a vector general-purpose register (VGPR) bank in the cache. The ALUs output the results of the instructions executed on the wavefronts to a buffer. By storing the wavefronts supplied by the VGPR bank in the cache, more wavefronts can be made available to SIMD units without increasing the VGPR bandwidth, enabling multiple ALU pipelines to execute instructions in a single execution cycle. The controller transfers the results, which are operands for subsequent instructions, to the cache.

[0006] In some embodiments, the wavefront includes either N work items or 2N work items, and each ALU pipeline includes N ALUs. In some embodiments, the wavefront includes either 32 work items (referred to herein as "wave 32") or 64 work items (referred to herein as "wave 64"), and each ALU pipeline includes 32 ALUs. Instructions executed in each ALU pipeline require a maximum of three operands per execution cycle. Therefore, in some embodiments, the cache is sized to store at least six operands to enable two ALU pipelines to execute either a single wave 64 instruction or two wave 32 instructions in a single execution cycle. In some embodiments, the work items of the wavefront are swizzled between VGPR banks to reduce the bandwidth required to access the work items in the ALU pipeline. The techniques described herein are used in various embodiments in any of the various parallel processors (e.g., vector processors, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), non-scalar processors, highly parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, and other multithreaded processing units).

[0007] Figure 1 is a block diagram of a processing system 100 according to several embodiments. The processing system 100 includes a central processing unit (CPU) 102 and a graphics processing unit (GPU) 104. In various embodiments, the CPU 102 includes one or more single-core CPUs or multi-core CPUs. In various embodiments, the GPU 104 includes any cooperating set of hardware and / or software that performs functions and calculations associated with accelerated graphics processing tasks, data-parallel tasks, and nested data-parallel tasks in an accelerated manner, in relation to resources such as conventional CPUs, conventional graphics processing units (GPUs), and combinations thereof. In the embodiment of Figure 1, the processing system 100 is formed on a single silicon die or package that combines the CPU 102 and GPU 104 to provide a unified programming and execution environment. This environment allows the GPU 104 to be used as flexibly as the CPU 102 for several programming tasks. In other embodiments, the CPU 102 and GPU 104 are formed separately and mounted on the same or different substrates. It should be understood that the processing system 100 may include more or fewer components than those shown in Figure 1. For example, the processing system 100 may further include one or more input interfaces, non-volatile storage, one or more output interfaces, a network interface, and one or more displays or display interfaces.

[0008] As shown in Figure 1, the processing system 100 includes a system memory 106, an operating system 108, a communication infrastructure 110, and one or more applications 112. Access to the system memory 106 is managed by a memory controller (not shown) connected to the system memory 106. For example, requests from the CPU 102 or other devices to read from or write to the system memory 106 are managed by the memory controller. In some embodiments, one or more applications 112 include various programs or commands for performing calculations that are also executed on the CPU 102. The CPU 102 sends selected commands for processing on the GPU 104. The operating system 108 and the communication infrastructure 110 will be discussed in more detail below. The processing system 100 further includes a device driver 114 and memory management units such as an input / output memory management unit (IOMMU) 116. The components of the processing system 100 are implemented as hardware, firmware, software, or any combination thereof. In some embodiments, the processing system 100 includes one or more software components, hardware components, and firmware components, in addition to or different from those shown in Figure 1.

[0009] Within the processing system 100, system memory 106 includes non-persistent memory such as DRAM (not shown). In various embodiments, system memory 106 stores processing logic instructions, constant values, variable values ​​during the execution of an application or other part of processing logic, or other desired information. For example, in various embodiments, parts of the control logic for performing one or more operations on the CPU 102 reside in system memory 106 during the execution of each part of the operation by the CPU 102. During execution, each application, operating system function, processing logic command, and system software resides in system memory 106. Control logic commands essential to the operating system 108 typically reside in system memory 106 during execution. In some embodiments, other software commands (e.g., a set of instructions or commands used to implement a device driver 114) reside in system memory 106 during the execution of the processing system 100.

[0010] The IOMMU116 is a multi-context memory management unit. In the present invention, the context takes into account the environment in which the kernel runs and the domains in which synchronization and memory management are defined. The context includes a set of devices, the memory accessible to those devices, the corresponding memory properties, and one or more command queues used to schedule the execution of kernels or operations on memory objects. The IOMMU116 contains logic for performing virtual-to-physical address translation for memory page access for devices such as the GPU104. In some embodiments, the IOMMU116 includes or has access to a translation lookaside buffer (TLB) (not shown). The TLB is implemented in content addressable memory (CAM) to accelerate the translation of logical (i.e., virtual) memory addresses to physical memory addresses for data in system memory 106 in response to requests made by the GPU104.

[0011] In various embodiments, the communication infrastructure 110 interconnects the components of the processing system 100. The communication infrastructure 110 includes one or more of the following: peripheral component interconnect (PCI) buses, extended PCI (PCI-E) buses, advanced microcontroller bus architecture (AMBA) buses, advanced graphics ports (AGP), or other such communication infrastructures and interconnections (not shown). In some embodiments, the communication infrastructure 110 includes an Ethernet® network or any other suitable physical communication infrastructure that meets the data transfer rate requirements of the application. The communication infrastructure 110 includes functions for interconnecting components, including the components of the processing system 100.

[0012] A driver, such as a device driver 114, communicates with a device (e.g., a GPU 104) via an interconnection or communication infrastructure 110. When a calling program invokes a routine within the device driver 114, the device driver 114 issues a command to the device. When the device returns data to the device driver 114, the device driver 114 invokes the routine of the original calling program. Generally, device drivers are hardware-dependent and operating system-specific in order to provide essential interrupt handling to any necessary asynchronously dependent hardware interfaces. In some embodiments, a compiler 120 is embedded within the device driver 114. The compiler 120 compiles the source code into program instructions necessary for execution by the processing system 100. During such compilation, the compiler 120 applies transformations to program the instructions at various stages of compilation. In other embodiments, the compiler 120 is a standalone application. In various embodiments, the device driver 114 controls the operation of the GPU 104 by providing an application programming interface (API) to software (e.g., application 112) running on the CPU 102, thereby accessing various functions of the GPU 104.

[0013] The CPU 102 includes one or more of the following: a control processor, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a digital signal processor (DSP) (not shown). The CPU 102 executes at least a portion of the control logic that controls the operation of the processing system 100. For example, in various embodiments, the CPU 102 runs an operating system 108, one or more applications 112, and a device driver 114. In some embodiments, the CPU 102 initiates and controls the execution of one or more applications 112 by allocating processing and other processing resources, such as a GPU 104, that are associated with one or more applications 112 across the CPU 102.

[0014] The GPU 104 executes commands and programs for selected functions, such as graphics operations and other operations, which are particularly well-suited for parallel processing. The GPU 104 is typically used to perform graphics pipeline operations such as pixel manipulation, geometric calculations, and rendering images to a display. In some embodiments, the GPU 104 performs computational operations (e.g., operations unrelated to graphics, such as video manipulation, physical simulations, computational fluid dynamics, etc.) based on commands or instructions received from the CPU 102. For example, such commands include special instructions not typically defined in the instruction set architecture (ISA) of the GPU 104. In some embodiments, the GPU 104 receives image geometry representing a graphics image, along with one or more commands or instructions for rendering and displaying the image. In various embodiments, the image geometry corresponds to a two-dimensional (2D) or three-dimensional (3D) computerized graphics image representation.

[0015] In various embodiments, the GPU 104 includes one or more computing units, such as one or more processing cores 122, each containing one or more SIMD units 124, each configured to execute a thread concurrently with the execution of other threads in the wavefront by other SIMD units 124, according to a SIMD execution model. A SIMD execution model is one in which multiple processing elements share a single program control flow unit and program counter, and thus can execute the same program but with different data. The processing cores 122 are also referred to as shader cores or streaming multi-processors (SMX). The number of processing cores 122 implemented in the GPU 104 can be freely selected at the design stage. Each processing core 122 includes one or more processing elements, such as scalar and / or vector floating-point units, arithmetic and logic units (ALUs). In various embodiments, the processing cores 122 further include special-purpose processing units (not shown), such as inverse square root units and sine / cosine units.

[0016] Each of the one or more processing cores 122 processes input data by performing an instantiation of a specific work item, and the basic unit of execution in one or more processing cores 122 is a work item (e.g., a thread). Each work item represents a single instance creation of a collection of parallel executions of kernels launched on the device by, for example, parallel-executing commands. A work item is executed in one or more processing elements as part of a work group executed in the processing cores 122.

[0017] The GPU 104 issues and executes work items that include a group of threads running concurrently as a “wavefront” on a single SIMD unit 124. A wavefront may also be interchangeably referred to as a warp, vector, or thread. In some embodiments, a wavefront includes an instance of parallel execution of a shader program, but each wavefront includes multiple work items running concurrently on a single SIMD unit 124 according to a SIMD paradigm (e.g., one instruction control unit executing multiple data and the same instruction stream). The scheduler 128 is configured to perform operations related to scheduling various wavefronts on different processing cores 122 and SIMD units 124, as well as other operations to coordinate various tasks on the GPU 104.

[0018] To reduce latency associated with off-chip memory access, various GPU architectures include a memory cache hierarchy (not shown) that includes, for example, an L1 cache and a local data share (LDS). The LDS is a high-speed, low-latency memory dedicated to each processing core. In some embodiments, the LDS is a full gather / scatter model, allowing workgroups to write anywhere within the allocated space.

[0019] The parallel processing provided by one or more processing cores 122 is suitable for graphics-related operations such as pixel value calculation, vertex transformation, tessellation, geometry shading operations, and other graphics operations. The graphics processing pipeline 130 receives graphics processing commands from the CPU 102 and, thereby, provides calculation tasks to one or more processing cores 122 for parallel execution. Some graphics pipeline operations, such as pixel processing and other parallel calculation operations, require that the same command stream or calculation kernel be executed on a stream or collection of input data elements. Each instance of the same calculation kernel is simultaneously executed on multiple SIMD units 124 in one or more processing cores 122 to process such data elements in parallel. As referred to herein, for example, a calculation kernel is a function that is declared in a program and includes instructions executed on the APD processing core 122. This function is also referred to as a kernel, shader, shader program, or program.

[0020] In a single execution cycle, to facilitate processing of either a single wave 64-wavefront instruction or two waves 32-wavefront instructions across two 32-lane ALU pipelines of the SIMD unit 124, the processing core 122 includes a cache for receiving from a vector general-purpose register (VGPR) bank and expanding the number of operands (wavefronts) available as inputs to each of the SIMD units 124, which will be described in more detail below with respect to FIG. ⒉ The results of the instructions executed by the ALU pipeline for a wavefront are output to a buffer (not shown). A controller (not shown) transfers the results, which are operands for subsequent instructions, to the cache.

[0021] In various embodiments, the processing system 100 can be a computer, laptop, mobile device, server, or any of various other types of computing systems or devices. Note that the number of components of the processing system 100 can vary from embodiment to embodiment. It is possible that there are more or fewer each component / sub-component than shown in FIG. 1. Also note that the processing system 100 can include other components not shown in FIG. 1. Additionally, in other embodiments, the processing system 100 can be constructed in ways other than those shown in FIG. 1.

[0022] FIG. 2 is a block diagram of a portion 200 of a GPU 104 of a processing system 100 that employs dual arithmetic logic unit (ALU) pipeline processing, according to some embodiments. A portion 200 of the GPU 104 includes a SIMD unit 230 that includes two ALU pipelines, ALU pipeline - 1 232 and ALU pipeline - 2 234, and a cache 220. The cache 220 receives a wavefront (operand) 222 from a set of VGPR banks 210, 211, 212, 213. The SIMD unit 230 receives a wavefront instruction (also simply referred to as an instruction) 255 from an instruction buffer 250 and executes operations on the wavefront 222 stored in the cache 220. The result of the executed instruction 255 is stored in a buffer 235, and a controller 240 transfers the result, which is an operand for subsequent instructions, to the cache 220 and the VGPR banks 210, 211, 212, 213.

[0023] Each of ALU pipeline-1 232 and ALU pipeline-2 234 contains N ALUs. In some embodiments, each of ALU pipeline-1 232 and ALU pipeline-2 234 supports the same type of wavefront instruction, and in other embodiments, ALU pipeline-2 234 supports a subset of the type of wavefront instruction supported by ALU pipeline-1 232. For example, in some embodiments, ALU pipeline-1 232 and ALU pipeline-2 234 support a fused multiply add (FMA) wavefront instruction to calculate the product of a and b and then add c to this product.

[0024] A set of VGPR banks, VGPR bank-0 210, VGPR bank-1 211, VGPR bank-2 212, and VGPR bank-3 213 (collectively, VGPR banks 210-213), receive inputs such as local data sharing return data, texture return data, and VGPR initialization inputs from a source (not shown) and provide wavefronts to a cache 220. In some embodiments, the cache 220 is sized to store at least six wavefronts and includes at least three read ports 224 for providing input operands 222 to ALU pipeline-1 232 and ALU pipeline-2 234. In some embodiments, each VGPR bank 210-213 may be accessed independently of the other VGPR banks 210-213. Each VGPR bank 210-213 contains N registers, the value of which varies from embodiment to embodiment. The size of the registers within VGPR banks 210-213 also varies according to the embodiment.

[0025] Vector ALU (VALU) instructions, such as instruction 255, are stored in instruction buffer 250 and transported from a gather instruction queue (not shown) to ALU pipeline-1 232 and ALU pipeline-2 234. ALU pipeline-1 232 and ALU pipeline-2 234 receive instruction 255 and wavefront operand 222 from cache 220 via read port 224 and execute the command indicated by instruction 255 for wavefront operand 222 in a single execution cycle. ALU pipeline-1 232 and ALU pipeline-2 234 output the results from instruction 255 to buffer 235. Controller 240 determines which of the results stored in buffer 235 is the source operand for a subsequent instruction and transfers the source operand to cache 220. Controller 240 can be implemented as hardware, firmware, software, or any combination thereof.

[0026] Figure 3 shows one embodiment 300 of the exemplary dual instruction 310 for executing two instructions for one or more wavefronts, such as wavefronts 302, 304, in a single cycle in two ALU pipelines of a single-instruction multiple data (SIMD) unit, according to several embodiments. In the illustrated example, each of wavefronts 302 and 304 has N work items, where N is a positive integer and N differs from embodiment to embodiment. Similarly, each of ALU pipeline-1 232 and ALU pipeline-2 234 contains N lanes (ALUs). In one embodiment, N is equal to 32.

[0027] The dual instruction 310 describes a pair of instructions, instruction - 1 312 and instruction - 2 314, which are independent of each other and are issued from one wave within a single cycle. The dual instruction 310 includes an indication that the wavefronts 302, 304 have the same number of work items as the number of ALUs in each of the ALU pipelines 232, 234. Instruction - 1 312 is issued to ALU pipeline - 1 232, and instruction - 2 314 is issued to ALU pipeline - 2 234. In some embodiments, each of instruction - 1 312 and instruction - 2 314 uses a maximum of two VGPR banks, and in some embodiments, the source operands of each of instruction - 1 312 and instruction - 2 314 use different VGPR banks.

[0028] Figure 4 shows an embodiment 400 of an exemplary single instruction 410 for executing a wavefront 402 in two ALU pipelines of a SIMD unit in a single cycle according to some embodiments. In the illustrated example, the wavefront 402 has 2*N work items, where N is a positive integer and N varies for each embodiment. In one embodiment, N is equal to 32. The first part of the wavefront 402 includes work items W0 to W N-1 and the second part of the wavefront 402 includes work items W N to W 2N-1 . The single instruction 410 includes an indication that the wavefront 402 has the same number of work items as the number of ALUs in both of the ALU pipelines 232, 234 added together. Further, the single instruction 410 is intended such that a single part of the wavefront 402, such as the part including work items W0 to W N-1 , is executed on the lanes ALU0 to ALU N-1 of the ALU pipeline - 1 232 in a given instruction cycle, and another part of the wavefront 402, such as the part including work items W N to W 2N-1 , is executed on the lanes ALU N to ALU 2N-1 of the ALU pipeline - 2 234 in the same instruction cycle.This indicates that it is intended to be executed above.

[0029] In one embodiment, N is 32, and the number of work items per wavefront is 64. In other embodiments, N may be a different value. In the embodiment where N is 32, each of ALU pipeline-1 232 and ALU pipeline-2 234 has lanes ALU0~ALU N-1 and ALU N ~ALU 2N-1 It includes 32 lanes (or ALUs) as shown.

[0030] Figure 5 shows one embodiment 500 of an example of swizzling wavefront work items between vector general-purpose register banks VGPR bank-0 510, VGPR bank-1 511, VGPR bank-2 512, and VGPR bank-3 513 (collectively, VGPR banks 510-513) according to several embodiments. The upper and lower halves of VGPR are placed in different banks to facilitate the execution of a wavefront containing 2*N work items in two ALU pipelines, each containing N lanes (or ALUs) in a single instruction cycle. In the illustrated example, N is 32, and the number of work items in the wavefront is 64. The lower half of the wavefront (corresponding to lanes 31-0) is configured such that bank[1:0]=VGPR[1:0], and the upper half of the wavefront (corresponding to lanes 63-32) is swizzled (i.e., swapped) such that bank[1:0]={VGPR[1],~VGPR[0]}.

[0031] Therefore, for example, V0(31~0) is located in VGPR bank-0 510, V0(63~32) is located in VGPR bank-1 511, V1(31~0) is located in VGPR bank-1 511, and V1(63~32) is located in VGPR bank-0 510. Similarly, V2(31~0) is located in VGPR bank-2 512, V2(63~32) is located in VGPR bank-3 513, V3(31~0) is located in VGPR bank-3 513, and V3(63~32) is located in VGPR bank-2 512. In this way, the wavefront work items are equally distributed between VGPR banks 510 and 513. By distributing the wavefront work items between VGPR banks by swizzling, the source can be read in one cycle for 64 lanes.

[0032] Figure 6 is a flowchart illustrating a method 600 for executing one or more instructions in two ALU pipelines of a SIMD unit in a single cycle, according to several embodiments. The method 600 is described with respect to an exemplary implementation in the processing system 100 of Figures 1 and 2. In block 602, the SIMD unit 124 receives instruction 255 from instruction buffer 250. In block 604, the SIMD unit 124 collects operands in cache 220. In block 606, the SIMD unit 124 determines whether instruction 255 is a dual instruction or a single instruction to be executed on the two ALU pipelines.

[0033] In block 606, if the SIMD unit 124 determines that the instruction is a dual instruction 310 containing instruction-1 312 and instruction-2 314, the method flow proceeds to block 608. In block 608, the SIMD unit 124 routes instruction-1 312 to ALU pipeline-1 232 and instruction-2 314 to ALU pipeline-2 234. In block 610, using the source operands stored in cache 220 in a single instruction cycle, ALU instruction pipeline-1 232 executes instruction-1 and instruction pipeline-2 234 executes instruction-2. The method flow then proceeds to block 616.

[0034] In block 606, if the SIMD unit 124 determines that the instruction is a single instruction 410 that is executed in both ALU pipeline-1 232 and ALU pipeline-2 234, the method flow proceeds to block 612. In block 612, the GPU 104 swizzles the work items of the source operand across the VGPR banks to evenly distribute the wavefront so that it can be read into cache 220 in a single instruction cycle. In block 614, both ALU pipeline-1 232 and ALU pipeline-2 234 execute instruction 410 using the source operand stored in cache 220 in a single instruction cycle. The method flow then proceeds to block 616.

[0035] In block 616, the SIMD unit 124 stores the result of the instruction in buffer 235. In block 618, the controller 240 transfers the result, which is the source operand for the subsequent instruction, from buffer 235 to cache 220 and VGPR banks 210, 211, 212, and 213. The method flow then continues back to block 602 for the next instruction.

[0036] In some embodiments, the above apparatus and technology are implemented in a system including one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the processing systems described above with reference to Figures 1 to 6. Electronic design automation (EDA) and computer-aided design (CAD) software tools can be used to design and manufacture these IC devices. These design tools are typically represented as one or more software programs. One or more software programs include computer-executable code for operating a computer system to operate with code representing the circuit of one or more IC devices in order to perform at least part of the process of designing or adapting a manufacturing system for manufacturing the circuit. This code may include instructions, data, or combinations of instructions and data. Software instructions representing the design or manufacturing tools are typically stored in a computer-readable storage medium accessible to the computing system. Similarly, code representing one or more stages of designing or manufacturing an IC device is stored in and accessed from the same or different computer-readable storage medium.

[0037] Computer-readable storage media include any non-temporary storage media or combination of non-temporary storage media that are accessible by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray® discs), magnetic media (e.g., floppy disks, magnetic tapes, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical system (MEMS) based storage media. Computer-readable storage media (e.g., system RAM or ROM) may be built into the computing system, computer-readable storage media (e.g., magnetic hard drives) may be permanently mounted to the computing system, computer-readable storage media (e.g., optical disks or Universal Serial Bus (USB) based flash memory) may be detachably mounted to the computing system, and computer-readable storage media (e.g., network-accessible storage (NAS)) may be connected to the computer system via a wired or wireless network.

[0038] In some embodiments, certain aspects of the technology described above are implemented by one or more processors of a processing system that executes the software. The software includes one or more sets of executable instructions, which are stored in a non-temporary computer-readable storage medium or otherwise clearly embodied. The software may also include instructions and specific data, which, when executed by one or more processors, operate the one or more processors to execute one or more aspects of the technology described above. Non-temporary computer-readable storage mediums may include, for example, magnetic or optical disk storage devices, solid-state storage devices such as flash memory, caches, random-access memory (RAM), or other non-volatile memory devices (one or more). Executable instructions stored in a non-temporary computer-readable storage medium can be implemented as source code, assembly language code, object code, or other instruction forms that can be interpreted or otherwise executed by one or more processors.

[0039] In addition to the foregoing, it should be noted that not all activities or elements described in the summary are required, and certain activities or parts of devices may not be required, and one or more additional activities may be performed, and one or more additional elements may be included. Furthermore, the order in which the activities are listed does not necessarily indicate the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and variations can be made without departing from the scope of the invention as described in the claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all of these variations are intended to fall within the scope of the invention.

[0040] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, benefits, advantages, solutions to problems, and features that may give rise to or manifest any benefits, advantages, or solutions are not to be construed as essential, necessary, or indispensable features to any or all of the claims. Furthermore, the disclosed invention can be modified and implemented in different but similar ways, in ways that are obvious to those skilled in the art who are interested in the teachings of this specification; therefore, the specific embodiments described above are merely illustrative. There are no limitations to the details of the configuration or design shown herein beyond those described in the appended claims. Accordingly, the specific embodiments described above may be modified or altered, and it is clear that all such modifications are within the scope of the disclosed invention. Accordingly, the protection sought herein is described in the appended claims.

Claims

1. It is a method, For execution in an execution unit comprising a first arithmetic unit (ALU) pipeline and a second ALU pipeline, each wavefront transfers a set of wavefronts containing several work items from a set of vector general-purpose register (VGPR) banks to a cache, In both the first ALU pipeline and the second ALU pipeline, in a first execution cycle, selective execution of either a single instruction or a dual instruction for a set of wavefronts, which are wavefronts containing a number of work items equal to the sum of the number of ALUs in the second ALU pipeline and the number of ALUs in the first ALU pipeline, is included. method.

2. The selective execution includes executing a single instruction in both the first ALU pipeline and the second ALU pipeline in the first execution cycle. The method according to claim 1.

3. This includes distributing the work items of any wavefront from the set of wavefronts evenly among the sets of VGPR banks. The method according to claim 2.

4. The result of the single instruction or the dual instruction is stored in a buffer, Depending on the instruction that depends on the aforementioned result, the result of the single instruction or the dual instruction is transferred from the buffer to the cache, The method according to any one of claims 1 to 3.

5. The number of work items in the wavefront is equal to the number of ALUs in the first ALU pipeline. The selective execution described above includes executing a dual instruction in a first execution cycle, which includes a first instruction to be executed on a first wavefront in the first ALU pipeline and a second instruction to be executed on a second wavefront in the second ALU pipeline. The method according to claim 1.

6. It is a method, Transferring a set of wavefronts from a set of vector general-purpose registers (VGPR) banks to the cache, Based on the set of wavefronts, in a first execution cycle, the system includes selectively executing either a single instruction or a dual instruction for performing an operation on a wavefront containing a number of work items equal to the sum of the number of ALUs in the first ALU pipeline and the number of ALUs in the second ALU pipeline, which comprises a first ALU pipeline comprising a first plurality of arithmetic logic units (ALUs). method.

7. This includes storing the values ​​read from the set of VGPR banks in the cache. The method according to claim 6.

8. The process includes storing the result of the single instruction or the dual instruction in a buffer. The method of claim 6 or 7.

9. In response to an instruction that depends on the aforementioned result, the process includes transferring the aforementioned result from the buffer to the cache, The method of claim 8.

10. The dual instruction includes, in the first execution cycle, a first instruction to be executed on a second wavefront in the first ALU pipeline, and a second instruction to be executed on a third wavefront in the second ALU pipeline. The number of work items in the second wavefront of the wavefront set is equal to the number of ALUs in the first ALU pipeline, and the number of work items in the third wavefront is equal to the number of ALUs in the second ALU pipeline. The method according to claim 6.

11. It is a device, A cache for storing a first set of wavefronts transferred from a set of vector general-purpose register (VGPR) banks, where each wavefront contains several work items, and An execution unit comprising a first arithmetic unit (ALU) pipeline and a second ALU pipeline, wherein in both the first ALU pipeline and the second ALU pipeline, in a first execution cycle, the execution unit selectively executes either a single instruction for performing an operation on a wavefront containing a number of work items equal to the sum of the number of ALUs in the first ALU pipeline and the number of ALUs in the second ALU pipeline, or a dual instruction for a first set of the wavefront, Each of the first ALU pipeline and the second ALU pipeline comprises a plurality of ALUs. device.

12. A buffer for storing the result from the single instruction or the dual instruction is provided. The device according to claim 11.

13. A controller is provided for transferring the result from the buffer to the cache in response to an instruction that depends on the result. The device according to claim 12.

14. The dual instruction includes, in the first execution cycle, a first instruction to be executed on a first wavefront in the first ALU pipeline, and a second instruction to be executed on a second wavefront in the second ALU pipeline. A device according to any one of claims 11 to 13.

15. The execution unit selectively executes a single instruction in both the first ALU pipeline and the second ALU pipeline during the first execution cycle. A device according to any one of claims 11 to 14.

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