Pulsed voltage plasma processing apparatus and method

Abstract

Embodiments provided herein generally include apparatus, plasma processing systems, and methods for generating waveforms for plasma processing of substrates in a processing chamber, wherein the processing chamber is configured to adjust the timing and characteristics of asymmetric voltage waveforms supplied to one or more electrodes or coils in the plasma processing chamber in order to improve control over various properties of the generated plasma and to control the ion energy distribution (IED) for plasma-generated ions interacting with the substrate surface during plasma processing. The methods and apparatus disclosed herein are configured to control and maintain the plasma formed in the processing area of ​​the plasma processing chamber without the need for supplying a radio frequency (RF) waveform during processing. The ability to synchronize and control waveform characteristics, such as frequency, slope of the portion of the voltage waveform, waveform shape, and applied voltage on time during the pulse period, of the voltage pulses supplied in each of the pulse voltage waveforms applied to different electrodes and / or coils enables improved control over the generated plasma.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to systems used in semiconductor device manufacturing. More specifically, embodiments of the present disclosure relate to plasma processing systems used to process substrates.

Background Art

[0002] Ensuring the creation of high aspect ratio features is one of the major technical challenges for next-generation semiconductor devices. One way to form high aspect ratio features is to use a plasma-assisted etching process to impact the material formed on the surface of the substrate through an aperture formed in a patterned mask layer formed on the substrate surface.

[0003] As technology nodes advance toward 2nm, the fabrication of smaller features with larger aspect ratios requires atomic precision for plasma processing. In etching processes where plasma ions play a crucial role, ion energy control has always been a driving force behind the development of reliable and repeatable device formation processes in the semiconductor equipment industry. In typical plasma-assisted etching processes, the substrate is placed on an electrostatic chuck (ESC) positioned in a processing chamber, and plasma is formed on the substrate using a radio frequency (RF) source coupled to electrodes positioned on or within the plasma processing chamber, with ions accelerated from the plasma towards the substrate, across the plasma sheath. Furthermore, RF substrate biasing methods, which require the use of a separate RF bias source in addition to the RF source used to start and maintain the plasma in the processing chamber, have not been able to control the properties of the plasma sheath as desired to achieve the desired plasma processing results that would enable the formation of these smaller device feature sizes. Conventional RF sources and RF biasing methods utilize sinusoidal RF waveforms to excite the plasma and form the plasma sheath. The use of RF waveforms, which requires the use of an RF matcher to adjust the output of the RF power supply to match the load impedance, has been shown to limit the RF system's ability to produce the desired pulse waveform shape due to the limitations in the speed at which the RF matching circuit in the RF system can respond to the changing impedance of the plasma load caused by the highs and lows brought about by the supply of pulse waveform shapes. Therefore, conventional methods of utilizing RF waveforms are difficult and often lead to inconsistent process results, as well as / or damage to supporting electrical and hardware components.

[0004] Therefore, in this field, there is a need for a pulsed voltage source and a biasing method that can enable the completion of a desired plasma-assisted process on a substrate. [Overview of the Initiative]

[0005] Embodiments provided herein generally include apparatus, plasma processing systems, and methods for generating waveforms for plasma processing of substrates in a processing chamber.

[0006] Embodiments of the present disclosure include a plasma processing system comprising a plurality of pulse voltage waveform generators and a plurality of electrodes or coils, each of which is arranged and configured to alter the properties of the plasma formed in the processing space of the plasma processing chamber of the plasma processing system when an asymmetric voltage waveform is supplied to the electrode or coil from one of the plurality of pulse voltage waveform generators, and each electrode or coil is coupled to a different pulse voltage waveform generator from the plurality of pulse voltage waveform generators, and a system controller configured to synchronize the supply of asymmetric voltage waveforms from those pulse voltage waveform generators to each of the electrodes or coils. The plurality of electrodes or coils may also include a first coil coupled to a first pulse voltage waveform generator from the plurality of pulse voltage waveform generators, the first pulse voltage waveform generator being configured to supply an asymmetric voltage waveform having a plurality of stages that fluctuate between a first voltage level and a second voltage level.

[0007] Embodiments of the present disclosure may further include a plasma processing system comprising a plurality of pulse voltage waveform generators, a plurality of electrodes or coils, each of which is arranged and configured to alter the properties of the plasma formed in the processing space of the plasma processing chamber of the plasma processing system when an asymmetric voltage waveform is supplied to the electrode or coil from one of the plurality of pulse voltage waveform generators, and each electrode or coil is coupled to a different pulse voltage waveform generator from the plurality of pulse voltage waveform generators, and a system controller configured to synchronize the supply of asymmetric voltage waveforms from those pulse voltage waveform generators to each of the electrodes or coils. In some embodiments, sinusoidal waveforms, such as RF waveforms, are not present in the processing space between the supply of the first asymmetric voltage waveform and the supply of the second asymmetric voltage waveform. In some embodiments, for substantially all of the plasma process performed on the substrate, the plasma is not maintained in the processing space by the use of sinusoidal waveforms. In some embodiments, during the process of supplying the first asymmetric voltage waveform and the supply of the second asymmetric voltage waveform, the first and second asymmetric voltage waveforms are the sole sources of electrical energy used to maintain the plasma.

[0008] To allow for a more detailed understanding of the features described above, a more detailed description of the disclosure, which has been briefly summarized above, may be made by reference to embodiments partially shown in the accompanying drawings. However, it should be noted that the accompanying drawings are illustrative embodiments only and should not be considered limiting in scope, as other equally valid embodiments may be recognized. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic diagram of a conventional plasma processing system. [Figure 2A] This is a schematic side cross-sectional view of a plasma processing system according to one or more embodiments configured to practice the methods described herein. [Figure 2B] This is a schematic side cross-sectional view of a plasma processing system according to one or more embodiments configured to practice the methods described herein. [Figure 2C] This is a simplified diagram of a pulse voltage (PV) waveform generator related to a control system, which may be configured in one or more embodiments to practice the methods described herein. [Figure 3A] This figure shows the synchronization waveform and the generated voltage waveform used in one or more methods described herein, according to one or more embodiments of the disclosure provided herein. [Figure 3B] This is an enlarged view of the generated voltage waveform shown in Figure 3A, according to one or more embodiments of the present disclosure provided herein. [Figure 3C] This figure shows the synchronization waveform and the generated voltage waveform used in one or more methods described herein, according to one or more embodiments of the disclosure provided herein. [Figure 4] This figure shows an example of a voltage waveform according to some embodiments of the present disclosure. [Figure 5A] This figure shows three different conventional sine waveforms, each with a different frequency. [Figure 5B] This figure shows three generated voltage waveforms, each configured to replace one of the corresponding sinusoidal waveforms shown in Figure 5A during processing, according to one or more embodiments of the present disclosure provided herein. [Figure 6A] This figure shows burst voltage pulses in a generated voltage waveform, used in one or more methods described herein, according to one or more embodiments of the disclosure provided herein. [Figure 6B] This figure shows zoomed-in, detailed sections of the generated voltage waveforms observed within different portions of the burst shown in Figure 6A, according to one or more embodiments of the present disclosure provided herein. [Figure 6C]A diagram showing a zoomed-in detailed section of the generated voltage waveforms found within different portions of the burst shown in FIG. 6A, according to one or more embodiments of the present disclosure provided herein. **DETAILED DESCRIPTION OF THE INVENTION**

[0010] For ease of understanding, where possible, the same reference numbers are used to designate identical elements common to the figures. It is contemplated that elements and features of one implementation may be beneficially incorporated into other implementations without further recitation.

[0011] Embodiments of the present disclosure generally relate to plasma processing methods and apparatuses configured to supply a plurality of asymmetric pulse voltage waveforms to a plurality of electrodes within a plasma processing chamber to control and maintain a plasma formed within a processing region of the plasma processing chamber. The plasma processing methods and apparatuses described herein are configured to improve control of various characteristics of the generated plasma and to control the ion energy distribution (IED) of plasma generated ions that interact with the surface of a substrate during plasma processing. Some embodiments of the present disclosure are configured to control and maintain a plasma formed within a processing region of a plasma processing chamber without the need to supply a high-frequency (RF) waveform during processing. The ability to synchronize and control waveform characteristics, such as the frequency, waveform shape, and applied voltage on-time during the pulse period, of each of the pulse voltage waveforms applied to different electrodes and / or coils enables improved control of the generated plasma. The embodiments disclosed herein also provide a reduction in system complexity and cost because the need for RF supplies and RF matching components and their often complex RF tuning algorithms is not required to perform a plasma process within a plasma processing chamber. As a result, greater precision for plasma processing can be achieved, as will be described in more detail herein.

[0012] Figure 1 is a schematic diagram of a conventional plasma processing system 19 adapted to process a substrate 13 disposed on a substrate support 36 by generating plasma 11 in a processing area 29 of a plasma processing chamber 99. The plasma processing system 19 is configured to form a capacitively coupled plasma (CCP), and the processing chamber 99 includes an upper electrode 23 disposed in the processing area 29 so as to face a lower electrode 46 also disposed in the processing area 29. The CCP plasma processing system includes a radio frequency (RF) source 71, which is electrically coupled to the upper electrode 23 through an RF matcher 72 and supplies a tuned RF signal, which is configured to ignite the plasma 11 formed in the processing area 29 and maintain the plasma 11. Generally, the lower electrode 46 is coupled to ground or to a second RF power supply, but in some configurations, as shown in Figure 1, the lower electrode is coupled to a pulse voltage (PV) waveform generator 75 through an RF filter 73. However, in conventional plasma processing configurations, such as that shown in Figure 1A, where a PV waveform and an RF signal are simultaneously supplied to one or more electrodes to form the plasma 11, the impedance of the composite load provided by the plasma 11 will fluctuate, at least partially, due to the fluctuating RF power levels and / or fluctuating voltages applied in each of the voltage pulses provided in the PV waveform supplied from the PV waveform generator 75. This leads to an inefficient supply of RF power to the composite load because, as described above, the RF matching components cannot quickly adjust their match points to compensate for the fluctuating impedance of the composite load. Furthermore, RF plasma-containing processes that require the use of RF matchers cannot quickly adjust to the changing RF power levels supplied during processing because the RF components cannot adjust and tune their match points, and are therefore limited in their ability to control various plasma characteristics that require control or fluctuation on a scale of less than 10 microseconds (μs).Conventional RF plasma processes are limited in impedance matching / frequency tuning convergence time (e.g., approximately 25-100 μs), making them unable to function at high RF pulsing speeds, and therefore the plasma process results are not repeatable at all.

[0013] Examples of plasma processing systems Figure 2A is a schematic cross-sectional view of a processing system 10 configured to carry out one or more of the plasma processing methods described herein. In some embodiments, the processing system 10 is configured for plasma-assisted etching processes, such as reactive ion etching (RIE) plasma processing. However, it should be noted that the embodiments described herein are also used in conjunction with processing systems configured for use in other plasma-assisted processes, such as plasma deposition processes, e.g., plasma chemical vapor deposition (PECVD), plasma physical vapor deposition (PEPVD), plasma atomic layer deposition (PEALD), plasma treatment processes, or plasma-based ion implantation processes, e.g., plasma doping (PLAD).

[0014] The processing system 10 generally includes a processing chamber 100, a lid assembly 176, a support assembly 136, and a system controller 126. As shown in the figure, the processing system 10 includes a plurality of plasma source assemblies, each adapted to supply an asymmetric voltage waveform to one or more electrodes and / or one or more coils disposed within the processing chamber 100. In one configuration example, as shown in Figure 2A, the processing chamber 100 includes four plasma source assemblies, such as a first capacitively coupled plasma (CCP) assembly 194, a second capacitively coupled plasma (CCP) assembly 195, a first inductively coupled plasma (ICP) assembly 196, and a second inductively coupled plasma (ICP) assembly 197, each containing a pulse voltage (PV) waveform generator 150 adapted to supply an asymmetric voltage waveform, which will be described in more detail below. In another configuration example, as shown in Figure 2B, the processing chamber 100 includes a first capacitively coupled plasma (CCP) assembly 194, a second capacitively coupled plasma (CCP) assembly 195, a third capacitively coupled plasma (CCP) assembly 198, and a fourth capacitively coupled plasma (CCP) assembly 199, each containing a pulse voltage (PV) waveform generator 150 adapted to supply an asymmetric voltage waveform.

[0015] The processing chamber 100 generally includes a chamber body 113 which includes one or more side walls 122 and a chamber base 124, and the one or more side walls 122 and the chamber base 124 together, together with the chamber lid 123 of the lid assembly 176, define the processing space 129. The one or more side walls 122 and the chamber base 124 generally include a material that is sized and shaped to form a structural support for the elements of the processing chamber 100 and is configured to withstand the pressure and added energy applied to the one or more side walls 122 and the chamber base 124 while the plasma 101 is generated in a vacuum environment maintained in the processing space 129 of the processing chamber 100 during processing. In one example, the one or more side walls 122 and the chamber base 124 are formed from a metal such as aluminum, an aluminum alloy, or a stainless steel alloy. A gas inlet 128, located through the chamber lid 123, is used to supply one or more processing gases to the processing space 129 from a processing gas source 119 that is fluidly connected to the processing space 129. The substrate 103 is loaded into and removed from the processing space 129 through an opening (not shown) in one or more side walls 122, which is sealed by a slit valve (not shown) during plasma processing of the substrate 103.

[0016] The system controller 126, also referred to herein as the processing chamber controller, includes a central processing unit (CPU) 133, memory 134, and support circuitry 135. The system controller 126 is used to control the process sequence used to process the substrate 103, including the substrate biasing method described herein. The CPU 133 is a general-purpose computer processor configured for use in an industrial setting to control the processing chamber and the subprocessors associated with the processing chamber. The memory 134 described herein, generally being non-volatile memory, may include random access memory, read-only memory, floppy or hard disk drives, or other preferred forms of local or remote digital storage. The support circuitry 135 is conventionally coupled to the CPU 133 and includes a cache, clock circuitry, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (programs) and data may be coded and stored in memory 134 to instruct the processor in the CPU 133. Software programs (or computer instructions) readable by the CPU 133 in the system controller 126 determine which tasks can be performed by the components in the processing system 10. Generally, a software program readable by the CPU 133 in the system controller 126 includes code that, when executed by the processor (CPU 133), performs tasks related to the plasma processing method described herein. The program may also include instructions used to control various hardware and electrical components within the processing system 10 to perform various process tasks and various process sequences used to implement the method described herein.

[0017] In some embodiments, the lid assembly 176 includes a chamber lid 123 and one or more plasma source assemblies, such as two inductively coupled plasma (ICP) assemblies 196, 197 shown in Figure 2A. As shown in Figure 2A, each inductively coupled plasma assembly 196, 197 includes coils 181, 182, respectively, configured to inductively couple the PV waveform generated by the PV waveform generator 150 to the plasma 101 formed in the processing space 129 of the processing chamber 100 during plasma processing. In this configuration, the chamber lid 123 includes a dielectric material configured to allow the electric field generated by the coils 181, 182 during the supply of an asymmetric voltage waveform by the PV waveform generator 150 to help generate and maintain the plasma 101 in the processing space 129.

[0018] In some other embodiments, as shown in Figure 2B, the lid assembly 176 includes a chamber lid 123 and one or more capacitively coupled plasma (CCP) assemblies, such as the two capacitively coupled plasma (CCP) assemblies 198, 199 shown in Figure 2B. As shown in Figure 2B, each CCP assembly 198, 199 includes electrodes 186, 187, respectively, configured to capacitively couple the PV waveform generated by the PV waveform generator 150 to the plasma 101 formed in the processing space 129 of the processing chamber 100 during plasma processing. In this configuration, the chamber lid 123 may include a dielectric or structural material (e.g., a metal) configured to withstand the vacuum introduced into the processing space 129 during processing.

[0019] The substrate support assembly 136, as shown in Figures 2A and 2B, includes a substrate support 105 (e.g., an ESC substrate support) and one or more lower electrodes coupled to a plasma source, such as capacitively coupled plasma (CCP) assemblies 194, 195. In some embodiments, the substrate support assembly 136 may further include a support base 107, an insulating plate 111, and a grounding plate 112. The support base 107 is electrically insulated from the chamber base 124 by the insulating plate 111, and the grounding plate 112 is inserted between the insulating plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to the support base 107 and disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 disposed on the substrate support 105 during substrate processing. Generally, the substrate support 105 is formed from a dielectric material such as a bulk sintered ceramic material, or a corrosion-resistant metal oxide or metal nitride material, such as aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in the dielectric material of the substrate support 105.

[0020] One or more lower electrodes may include a bias electrode 104 and / or an edge electrode 115, which are formed within a substrate support 105 and coupled to one or more plasma source assemblies, such as capacitively coupled plasma (CCP) assemblies, including two CCP assemblies 194, 195. CCP assembly 194 is coupled to the bias electrode 104, and CCP assembly 195 is coupled to the edge electrode 115, each configured to supply PV waveforms generated by a PV waveform generator 150 to the plasma 101 formed in the processing space 129 of the processing chamber 100 during plasma processing. In one embodiment not shown in Figures 2A-2B, the first PV waveform generator 150 of the first CCP assembly 194 is configured to bias both the bias electrode 104 and the edge control electrode 115, and therefore the CCP assembly 195 and its components are not required to supply PV waveforms to the bias electrode 104 and the edge control electrode 115.

[0021] In one configuration, the bias electrode 104 is a chucking electrode used to fix (i.e., chuck) the substrate 103 to the substrate support surface 105A of the substrate support 105 and to bias the substrate 103 with respect to the processing plasma 101 using one or more of the pulse voltage biasing schemes described herein. Generally, the bias electrode 104 is formed from one or more conductive parts, such as one or more metal meshes, foils, plates, or combinations thereof.

[0022] The CCP assemblies 194, 195 may also include a clamping network 116, each such as a high-voltage bias applied to the bias electrode 104 and / or the edge control electrode 115. In some embodiments, the bias electrode 104 is electrically coupled to the clamping network 116, and the edge electrode 115 is electrically coupled to the clamping network 116. The clamping network provides a chucking voltage to its electrodes, such as a static DC voltage between approximately -5000V and approximately +5000V, using an electrical conductor, such as a coaxial power supply line 106 (e.g., a coaxial cable). The clamping network 116 includes a bias compensation circuit element 116A, a DC power supply 155, and a bias compensation module blocking capacitor, also referred to herein as a blocking capacitor C5. The blocking capacitor C5 is positioned between the output of the pulse voltage (PV) waveform generator 150 and the bias electrode 104. Applying similarly configured PV waveforms and clamp voltages to the bias electrode 104 and edge control electrode 115 can improve plasma uniformity across the substrate surface during processing, and thus help improve the plasma processing process results.

[0023] As described above, in some embodiments, the substrate support assembly 136 includes an edge control electrode 115, which is positioned below the edge ring 114, surrounding the bias electrode 104, and / or positioned at a certain distance from the center of the bias electrode 104. Generally, for a processing chamber 100 configured to process a circular substrate, the edge control electrode 115 is annular in shape, made of a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments, such as those shown in Figures 2A-2B, the edge control electrode 115 is positioned within the region of the substrate support 105. In some embodiments, as shown in Figures 2A-2B, the edge control electrode 115 includes a conductive mesh, foil, and / or plate positioned at a similar distance (i.e., in the Z direction) from the substrate support surface 105A of the substrate support 105 to the bias electrode 104. In some other embodiments, the edge control electrode 115 includes a conductive mesh, foil, and / or plate disposed on or within a region of the quartz pipe 110 that surrounds at least a portion of the bias electrode 104 and / or substrate support 105. Alternatively, in some other embodiments (not shown), the edge control electrode 115 is disposed within or coupled to an edge ring 114, the edge ring 114 being disposed on and adjacent to the substrate support 105. In this configuration, the edge ring 114 is formed from a semiconductor or dielectric material (e.g., AlN).

[0024] The power supply line 157 electrically connects the output of the PV waveform generator 150 of the CCP assembly 194 to an optional filter assembly 151 and bias electrode 104. The following description mainly concerns the power supply line 157 of the first CCP assembly 194, which is used to couple the PV waveform generator 150 to the bias electrode 104, but the power supply line 158 of the CCP assembly 195, which couples the PV waveform generator 150 to the edge control electrode 115, will contain the same or similar components. The (one or more) electrical conductors in the various parts of the power supply line 157 may include (a) one or a combination of coaxial cables, such as a flexible coaxial cable connected in series with a rigid coaxial cable, (b) an insulated high-voltage corona-resistant hookup wire, (c) a bare wire, (d) a metal rod, (e) an electrical connector, or (f) any combination of the electrical elements in (a) to (e). An optional filter assembly 151 includes one or more electrical elements configured to substantially prevent currents generated by one or more of the plasma sources from flowing through the power supply line 157 and damaging the PV waveform generator 150.

[0025] In some embodiments, the processing chamber 100 further includes a quartz pipe 110 or collar that at least partially surrounds a portion of the substrate support assembly 136 to prevent the substrate support 105 and / or support base 107 from coming into contact with corrosive processing gases or plasma, cleaning gases or plasma, or their byproducts. Generally, the quartz pipe 110, insulating plate 111, and grounding plate 112 are surrounded by a liner 108. In some embodiments, a plasma screen 109 is positioned between the cathode liner 108 and a side wall 122 to prevent plasma from forming in the volume below the plasma screen 109 between the liner 108 and one or more side walls 122.

[0026] In some embodiments, the PV waveform generator 150 may be adapted to provide voltage waveforms to multiple electrodes and / or coils within a processing chamber 100. In some cases, the PV waveform generator 150 may be used within one or more of the plasma source assemblies 194-199. The PV waveform generator 150 will generally include a PV source controller 226 and at least one voltage source assembly, which includes a voltage source 220 configured to provide PV waveforms to at least one generator output 201 coupled to one or more of the electrodes and / or coils. In one example, as shown in Figure 2C, the PV waveform generator 150 includes a PV source controller 226 and two voltage source assemblies 221A, 221B configured to provide PV waveforms to two separate generator outputs 201. Two separate generator outputs 201 may be coupled to two source nodes SN1 and SN2, which are coupled to bias electrodes 104, edge electrodes 115, electrodes 186, 187, or coils 181, 182, which are capacitively or inductively coupled to a composite load 102. In some configurations, the PV waveform generator 150 includes three or more voltage source assemblies configured to provide PV waveforms to three or more separate generator outputs 201. The composite load 102 is shown as a standard electrical plasma model representing the plasma 101 as three circuit elements. The three circuit elements are (a) diodes and (b) current source I ion And, (c) Capacitor C SH These include, and each is present during the supply of at least a portion of the asymmetric voltage waveform provided to the electrode or coil by the PV waveform generator 150 during the plasma process. In some embodiments, the PV waveform generator 150 is a switch-mode power supply. In some embodiments, each of the PV waveform generators 150 is configured to supply DC power between 10 and 25 kilowatts (kW) to the electrode or coil.

[0027] Referring to Figure 2C, the two switches S1 and S2 in each of the voltage source assemblies 221A and 221B are coupled to and communicate with the PV source controller 226, as disclosed below, to enable the PV source controller 226 to independently open and close switches S1 and S2 in each of the two voltage source assemblies 221A and 221B at intervals desired to form an asymmetric voltage waveform. The illustrated switches S1 and S2 in each of the voltage source assemblies 221A and 221B may be implemented as unipolar, single-throw, normally-open switches controllable by electrical or optical signals provided by the PV source controller 226, or as MOSFET devices whose gates are controlled by signals provided by the PV source controller 226. The PV source controller 226 is also configured to control and / or adjust the voltage levels generated by each of the voltage sources 220 (e.g., DC sources) and provided to the generator outputs 201A and 201B based on commands received from the system controller 126. In some embodiments, the PV source controller 226 communicates directly with various asymmetric voltage waveform generating components within each of the voltage source assemblies of the PV waveform generator 150, such as switches S1, S2 and voltage sources 220A, 220B in each of the voltage source assemblies 221A, 221B shown in Figure 2C (not shown), and thus the asymmetric voltage waveforms provided to the generator output by the voltage source assemblies can be synchronized on much smaller time scales (e.g., nanosecond or microsecond scales). The improved ability to synchronize various asymmetric voltage waveforms on smaller time scales is generally due to direct communication signals (e.g., TTL signals, analog signals, etc.) provided between the waveform generating components in the voltage source assemblies 221A, 221B, rather than the need to transfer synchronization signals between separate conventional power supplies that utilize conventional communication protocols such as the Ethernet protocol to communicate.

[0028] In one or more embodiments disclosed herein, the PV waveform generator 150 includes a sensor assembly 205 positioned to measure the characteristics of the PV waveform generated at one or more of the generator outputs 201A, 201B. The sensor assembly 205 may include one or more electrical components configured to measure one or more electrical characteristics of the asymmetric voltage waveform provided by the PV waveform generator 150, such as voltage, current, and offset / phase, and to send one or more electrical characteristic data to the system controller 126. The electrical characteristic data received by the system controller 126 from each of the PV waveform generators 150 may be used together to synchronize the supply of other PV waveforms generated by each of the generator outputs 201 of the PV waveform generator 150 and to control the characteristics of the PV waveforms generated by each of the PV waveform generators 150, as further described below.

[0029] Therefore, the system controller 126 and the support circuit are configured to control and / or adjust the voltage waveform generated by the PV waveform generator 150. The PV waveform generator 150, the system controller 126, and the support circuit are capable of adjusting several electrical parameters used to change one or more of the voltage waveform characteristics of the provided asymmetric voltage waveform, such as frequency, waveform shape, and applied voltage on time during pulse period. Examples of several electrical parameters used to change one or more of the voltage waveform characteristics include, but are not limited to, changing the voltage ratio between electrodes or coils, adjusting the time delay in the supply of one or more pulses formed within the voltage waveforms provided by different PV waveform generators 150, and the direction of the current flowing through the electrodes or coils during the supply of a portion of the voltage waveform.

[0030] In some embodiments, the processing chamber 100 optionally includes a plasma ignition system 191 configured to supply a DC high voltage or RF signal to electrodes within the processing chamber 100, such as a support base 107, in order to initially generate (e.g., ignite) the plasma 101 in the processing space 129. In some embodiments, the plasma ignition system 191 includes an RF generator 118 configured to supply an RF waveform signal having a frequency greater than about 2 MHz or higher, such as 1 MHz or higher, or about 13.56 MHz or higher, through an RF matcher 160 connected to the RF electrode. In some embodiments, due to undesirable effects resulting from the interaction between the asymmetric voltage waveform provided by one or more of the plasma source assemblies 194-199 and the RF waveform provided by the RF generator 118 of the plasma ignition system 191, the RF waveform signal is supplied to the RF electrode only for very short intervals during the initial generation of the plasma 101 in the processing space 129.

[0031] Examples of plasma treatment methods Figure 3A shows exemplary voltage waveforms 302 and 303 supplied from two plasma source assemblies to one or more electrodes and / or one or more coils located in a plasma processing chamber. Figure 3B is a magnified view of a portion of the voltage waveform 302 shown in Figure 3A. Figure 3C shows exemplary voltage waveforms 302, 303 and 304 supplied from three plasma source assemblies to one or more electrodes and / or one or more coils located in a plasma processing chamber. Figure 4 shows an example of a voltage waveform established on the surface of a substrate during plasma processing based on the supply of waveform 303 to an electrode (e.g., bias electrode 104) disposed within a substrate support, according to some embodiments of the present disclosure. During plasma processing, voltage waveforms, such as voltage waveforms 302 and 303, may be synchronized by the use of a synchronization signal 301, which includes a plurality of signal pulses 305 supplied from a system controller 126 or from one or more of the PV waveform generators 150 in one of the plasma source assemblies to each of the PV waveform generators 150. In one example, waveforms 302 in Figure 3A and 302 and 304 in Figure 3C are generated by the use of one or more inductively coupled plasma source assemblies, such as inductively coupled plasma source assemblies 196 and 197, respectively. The supply of asymmetric voltage pulses to the inductive sources, such as coils 181 and 182, may be used to more precisely control the plasma generated in the processing space 129 of the processing chamber compared to conventional inductively coupled plasma source designs. Figures 3A-3B and 3C, and their related descriptions provided below, describe configurations in which two or three plasma source assemblies are used to supply asymmetric voltage waveforms to electrodes or coils in the upper and lower portions of the plasma processing chamber; however, this configuration is not limited to the scope of the disclosure provided herein, as any number of plasma sources, electrodes, and / or coils can be arranged in any desired portion of the plasma processing chamber without departing from the scope of the disclosure provided herein.As will be further explained below, the ability to adjust and synchronize the supply of voltage waveforms, including asymmetric voltage pulses, to different coils or regions of a coil can be used to adjust one or more plasma properties, such as plasma density and spatial plasma uniformity.

[0032] It is believed that the use of the asymmetric voltage waveform generation plasma source assemblies disclosed herein allows for better control of the characteristics of the generated plasma with greater precision and fidelity. The improved control and fidelity are believed to be partly attributable to the ability of the PV waveform generator in each plasma source assembly to perform nanosecond-level adjustments of the supplied voltage waveform, such as adjusting the voltage pulse shape (e.g., voltage magnitude), pulse-on time / duty cycle, pulse frequency, and rate of change (dV / dt), which are used to control plasma uniformity, plasma density, and enable high-speed synchronization of the voltage waveform provided by the PV waveform generator during plasma processing. Without limiting the disclosures provided herein, for comparison, current conventional plasma processing systems utilizing RF matching and RF generator components are limited to synchronization speeds on a 0.1 sec (s) to 1 millisecond (ms) (i.e., 10 to 1000 Hz) scale, whereas one or more configurations disclosed herein that do not include or utilize these components during plasma processing are considered capable of 1) achieving waveform synchronization speeds of at least less than 10 μs, such as 2.5 microseconds (μs) or less, and 2) achieving voltage waveform adjustment speeds on a nanosecond scale.

[0033] In one processing example, waveform 302 is generated by applying a voltage waveform by the PV waveform generator 150 of the first inductively coupled plasma assembly 196, and waveform 303 is generated by applying a waveform by the PV waveform generator 150 of the first CCP assembly 194. As shown in Figures 3A, 3B, and 3C, waveform 302 has a period T pincludes a series of pulses 310 each having. However, due to the plasma treatment results and to enable synchronization of the voltage waveforms provided by each of the plasma source assemblies, the period T of the applied voltage waveform p may be different and may desirably be integer multiples of each other. In one example, as shown in FIG. 3C, a plurality of asymmetric voltage pulses in the first waveform 304 provided to the first coil 181 are supplied at a frequency of 200 kHz, and a plurality of asymmetric voltage pulses in the second waveform 302 provided to the second coil 182 are supplied at a frequency of 400 kHz.

[0034] Due to the preprogrammed voltage waveform characteristics, each of the voltage waveform pulses can include a plurality of segments or steps provided to the electrodes or coils by the PV waveform generator 150 by use of commands received from the system controller 126 or provided from the PV source controller 226. In one example, as shown in FIGS. 3A - 3B, the pulses 310 each include a first step 311, a second step 312, a third step 313, and a fourth step 314. In this example, steps 311 and 313 include a voltage ramp that varies from one voltage level V1 to another voltage level V2, and steps 312 and 314 include portions of the voltage waveform 302 that are maintained at a constant voltage for a certain time period. It is believed that the steps of the pulse that include a variation of voltage over time (i.e., dV / dt) can be used to control and adjust the real - time and average plasma density generated in the plasma processing chamber. The plasma density is mainly controlled in the portion of the voltage pulse where there is a change in voltage over time because the ability of the electrons generated in the plasma to be accelerated and the rate of electron collisions with various gas atoms or molecules in the processing space 129 are controlled, so the slope of the waveform (e.g., ΔV 12 / ΔT 25 and ΔV 12 / ΔT 36 ) and the length of time during which the varying voltage is applied (e.g., ΔT 25 , ΔT 36) can be changed by adjusting the following. The ability of the system controller 126 and PV source assembly to control the waveform, and therefore the plasma generation characteristics, at different electrodes or coils in the processing space 129 allows the plasma uniformity in the processing space 129 to be adjusted and controlled by synchronizing and adjusting the voltage waveforms applied to each electrode or coil so that plasma uniformity and plasma density can be precisely controlled. The ability to perform nanosecond adjustments of the voltage waveform and enable high-speed synchronization of the generated voltage waveforms applied by the plasma source assembly can be used to improve the accuracy and fidelity of the plasma process compared to conventional plasma processing techniques, as described above. Steps 311 and 313 show an example involving a linear variation of the applied voltage over time, but the applied voltage applied during these steps may vary as a function of time, with a slope (e.g., dv / dt) 2 It is intended to include nonlinear curves having ) and therefore exponential, and quadratic, cubic, or higher-order shapes.

[0035] Referring again to Figures 3A and 3B, stages 312 and 314 include portions of the voltage waveform 303 that are maintained at a constant voltage, such as voltage V1 and voltage V2, respectively, for a certain period of time. Since these stages of the voltage pulse provide a constant voltage to the electrodes or coils, they are expected to allow for some decay in electron energy during these stages. However, these stages may be useful to help adjust the mean electron temperature and plasma density by spacing out the stages that involve voltage changes over time. The duration of stages 312 and 314 will generally be small enough to ensure that the plasma is maintained and does not extinguish.

[0036] Figure 3C shows three voltage waveforms 302, 303, and 304 supplied from three plasma source assemblies to one or more electrodes and / or one or more coils located in a plasma processing chamber. During plasma processing, waveforms 302, 303, and 304 may be synchronized by the use of a synchronization signal 301. In one example, waveforms 302 and 304 each include pulses 310 and 330, respectively, comprising first stages 311, 331, second stages 312, 332, third stages 313, 333, and fourth stages 314, 334, respectively. In this example, stages 311, 313, 331, and 334 include voltage ramps that fluctuate between voltage levels V1 and V2 and between V4 and V5, while stages 312, 332, 314, and 334 include portions of voltage waveforms 302, 304 that are maintained at a constant voltage for a period of time. In one configuration, the magnitude of the voltage difference between voltage levels V1 and V2 is different from the magnitude of the voltage difference between V4 and V5. In one example, voltages V1 and V2 are set to +5kV and -5kV relative to ground, and voltages V4 and V5 are set to +500V and -8kV relative to ground. Figures 3A and 3C show waveforms 302 and 304 fluctuating between positive and negative voltage levels, but this configuration does not limit the scope of the disclosure provided herein, as the voltage levels between which waveforms 302 and 304 fluctuate can both be negative or both be positive without departing from the basic scope of the disclosure provided herein. As shown in Figure 3C, waveform 304 includes two pulses 330, comprising a first stage 331, a second stage 332, a third stage 333, and a fourth stage 334, each having a period that is twice the period of each pulse 310 seen in waveform 302. In one embodiment, the waveform 304 also has a first time amount T from the start of the first stage 311 of the waveform 302. DThis offset results in a phase shift between electrodes and coils configured to receive waveforms 302 and 304, respectively. The ability to produce a voltage signal phase shift between different coils or regions of coils can be achieved by reversing the direction of the current flowing through the coil or region of coil, which can be used to tune one or more plasma characteristics, such as spatial plasma uniformity. Furthermore, the use of the PV waveform generator 150 allows for a phase offset between the voltage waveforms applied to the inner and outer coils, which should be used in conjunction with the coil current direction to provide more precise control of the plasma spatial distribution compared to conventional RF techniques.

[0037] In one method example, the supply of waveform 303 (Figure 3C) to electrodes within a substrate support assembly 136 is configured to produce a waveform 225 (Figure 4) that includes an ion current phase and a sheath collapse phase established on the substrate surface during plasma processing. At the beginning of the ion current phase, the drop in substrate voltage, brought about by the falling edge 323 of waveform 303, results in a high-voltage sheath that should form above the substrate, accelerating positive ions against the substrate. The positive ions that impact the substrate surface during the ion current phase deposit positive charge on the substrate surface, which, if uncompensated, causes a gradual positive increase in the substrate voltage during the ion current phase (i.e., a positive slope in the phase of the voltage waveform 225), as shown in Figure 4. However, the uncontrolled accumulation of positive charge on the substrate surface undesirably and gradually discharges the sheath capacitor and substrate support capacitor, slowly decreasing the sheath voltage drop and bringing the substrate potential closer to zero. The accumulation of positive charge creates a voltage droop (i.e., a positive slope in the phase) in the voltage waveform established on the substrate. The accumulation of positive charge on the substrate during the ion current stage can be compensated by several techniques, including adjusting the waveform 303 to have a negative slope (not shown) in the ion current portion 324 of the waveform 303. In some embodiments, a relatively high-frequency voltage waveform may be used to reduce the effect of this voltage rise (i.e., droop) introduced during the ion current stage.

[0038] At the end of the ion current phase and the start of the sheath collapse phase (e.g., sheath collapse portion 322), the rising edge 321 of the waveform 303 is brought by the PV source assembly, which forms part of a generally short and narrow positive pulse (Figure 4) that transitions from a negative voltage level to a positive voltage greater than 0 volts. The duration of the positive section of the pulse may vary, and in some embodiments, the waveform period (T P Waveform period (T) is between 5% and 15% of the period. P It falls between 1% and 20% of the range. In one example, the waveform period may be approximately 5 μs, and the frequency of waveform 303 may be approximately 200 kHz. In another example, the waveform period may be approximately 2.5 μs, and the frequency of waveform 303 may be approximately 400 kHz.

[0039] Waveform example Figure 5A shows three different conventional sinusoidal waveforms RF1, RF2, and RF3, each having a different sinusoidal frequency. In one example, sinusoidal waveforms RF1, RF2, and RF3 are RF waveforms having frequencies of 2 MHz, 13.56 MHz, and 40 MHz, respectively. Figure 5B shows three generated voltage waveforms, each configured to replace one of the corresponding sinusoidal waveforms shown in Figure 5A during processing, according to one or more embodiments of the present disclosure provided herein. As stated above, due to practical limitations in the available voltage waveforms that hardware can generate today, which prevent the generation of asymmetric voltage waveforms (>500 kHz) with periods of less than approximately 2 μs, it is not possible to generate voltage waveforms with frequencies greater than 13.56 MHz, such as frequencies greater than 2 MHz or greater than 40 MHz. As previously described, it is conceivable that waveform stages, including voltage fluctuations over time (i.e., dV / dt), can be used to control and adjust the real-time and average plasma density generated in the plasma processing chamber. Plasma density can be altered by adjusting the slope of the voltage waveform and the length of time the fluctuating voltage is applied, since the ability to accelerate electrons and increase the rate of electron collisions with gas atoms or molecules in the plasma is thought to be controlled by sections of voltage pulses where the voltage changes over time.

[0040] Referring to Figure 5B, the three voltage waveforms PVW1, PVW2, and PVW3 are voltage waveforms designed to replace the conventional sinusoidal waveforms RF1, RF2, and RF3 provided to the processing space 129 of the plasma processing chamber 100 in a conventional processing sequence. The three voltage waveforms PVW1, PVW2, and PVW3 may be supplied from at least one plasma source assembly to one or more electrodes and / or one or more coils located within the plasma processing chamber. In some cases, each of the three voltage waveforms PVW1, PVW2, and PVW3 may be supplied from one plasma source assembly at different times in the plasma processing sequence. In some other cases, at least two of the three voltage waveforms PVW1, PVW2, and PVW3 may be supplied from at least two different plasma source assemblies at the same time in the plasma processing sequence. Each of the three voltage waveforms PVW1, PVW2, and PVW3 includes an asymmetric pulse containing at least one or more sloped regions during a section of each pulse period intended to simulate one or more sloped regions of a sinusoidal waveform. In some embodiments, the simulated slope is selected so that it matches the slope of the sinusoidal waveform taken at the zero intersection of the sinusoidal waveform (e.g., angles 0, π, 2π, etc.). In one example, region 511 of the voltage pulse PVW1 is intended to simulate the average slope in the sloped region 501 of the sinusoidal waveform RF1 extending between peak 501A and peak 501B. In another example, region 521 of the voltage pulse PVW2 is intended to simulate the average slope in the sloped region 502 of the sinusoidal waveform RF2. In yet another example, region 531 of the voltage pulse PVW3 is intended to simulate the average slope in the sloped region 503 of the sinusoidal waveform RF3. Due to hardware relational limitations in the pulsed voltage (PV) waveform generator, each of the three voltage waveforms PVW1, PVW2, and PVW3 contains a voltage pulse period longer than the period of a common desirable RF type sinusoidal waveform used in the common plasma processing strategy they are intended to simulate.However, incorporating at least one simulated sloped region in a series of voltage pulses in a voltage waveform having a pulse repetition frequency in the kilohertz range, such as between 100 and 500 kHz, is considered useful for achieving a similar effect on controlling plasma properties, such that higher frequency RF-type sinusoidal waveforms (e.g., >1 MHz) will have on the formed plasma. General voltage pulse slope control provided by the PV waveform generator 150 can be performed in the range of 1 ns to 1000 ns, which is generally similar to the slope of the desired RF center frequency. In some embodiments, the first asymmetric voltage waveform includes a plurality of voltage pulses, each comprising a first pulse period and at least one sloped region having a first slope (dV1 / dt) intended to simulate a sinusoidal waveform. In this example, the first slope (dV1 / dt) is the slope (dV) of the sinusoidal waveform when measured at a phase angle where the sinusoidal waveform crosses 0 in the time axis. s The sine wave can be equal to ( / dt) and has a frequency between 1 MHz and 100 MHz and a peak voltage between 100 volts and 5000 volts.

[0041] Figure 6A shows a voltage waveform 601, which includes multiple bursts of generated voltage waveform pulses, utilized in one or more methods described herein, according to one or more embodiments of the Disclosure provided herein. As shown in Figure 6A, the voltage waveform 601 includes a plurality of positive voltage waveform pulse bursts 611 and 613 and a plurality of negative voltage waveform pulse bursts 612 and 614, each including a series of voltage pulses shown in Figures 6B and 6C. Figures 6B and 6C show zoomed-in detailed sections of the waveform pulse bursts 611 and 612, respectively, according to one or more embodiments of the Disclosure provided herein. During the positive voltage waveform pulse burst 611 and the negative voltage waveform pulse burst 612, the voltage waveform 601 has a period T POS A positive voltage section extending over period T NEG It includes multiple voltage pulses, each containing a negative voltage section extending over a certain distance. The period of each voltage pulse is TP This is equal to the sum of the time allocated to the positive voltage section and the negative voltage section (i.e., T P =T POS +T NEG ). If the positive and negative voltage swings observed in the voltage waveform 601, such as those shown in Figure 6A, are equal in magnitude, the proportion of time the waveform generator is generating a positive or negative voltage during each voltage pulse period will determine whether the waveform pulse burst has a positive or negative bias. In one example, as shown in Figure 6B, the positive section 622 of each pulse occupies approximately 85% of the pulse period, and the negative section 621 of each pulse occupies approximately 15%, and therefore burst 611 can be characterized as a positive-biased burst. In an alternative example, as shown in Figure 6C, the positive section 631 of each pulse occupies approximately 15% of the pulse period, and the negative section 632 of each pulse occupies approximately 85%, and therefore burst 612 can be characterized as a negative-biased burst. The determination and supply of waveform pulse bursts with a positive or negative bias can also be controlled based on the area under the voltage waveform 601 curve in each section of the voltage pulse (i.e., magnitude of the voltage in the section of the period × time). The ability to provide voltage pulses having both positive and negative sections, and bursts of pulses having both positive and negative sections at different voltage levels, is considered useful for controlling the properties of the generated plasma, such as controlling the plasma density and the energies of both positive and negative ions and electrons in the plasma. Therefore, in a burst, a certain state (T POS or T NEGWhen the duration and magnitude of the negative state in a burst are higher, the plasma processing mechanism with the oppositely charged species becomes more dominant. For example, when the negative state in a burst is provided for a longer duration and / or at a higher voltage, the plasma processing mechanism with the positively charged ions becomes more dominant than the negatively charged ions, and similarly, when the positive state in a burst has a longer duration and / or a higher voltage, the opposite is true for the negatively charged species and the positive state for the positively charged ions. The ability to control the properties of both positive and negative ions formed in the plasma provides an additional process control variable for conventional reactive ion etching (RIE) processes that control a certain type of ion (e.g., positively charged ions), as well as for other useful processes that require the interaction of the plasma with various component gases or reactive elements found within the processing area of ​​the substrate and / or plasma processing chamber.

[0042] In some embodiments, voltage pulses observed within two or more bursts of voltage waveform pulses have voltage polarity (e.g., positive or negative) and pulse period (T P ), negative section period T NEG , positive section period T POSIt includes one or more different voltage pulse characteristics, such as different slopes during the transition period between sections of the voltage pulse (e.g., regions 511, 521, 531), and / or other voltage waveform characteristics. The ability to control and supply multiple different voltage waveform frequencies in different sections of the voltage waveform 601 enables additional process control flexibility not available in conventional sine waveform processing systems, without the use of multiple waveform generation sources each configured to supply different basic sine wave frequencies (e.g., 1 MHz, 13.56 MHz, or 40 MHz) and the cost of utilizing them. Conventional sine waveform processing systems require different sine waveform generation sources for each different frequency utilized in plasma processing strategies. In fact, a single PV waveform generator 150 can generate an infinite number of pulsed voltage frequencies with different characteristics within a frequency range below the hardware limitations of the PV waveform generator 150.

[0043] By using a plasma source assembly configured to supply synchronized asymmetric voltage waveforms that are each adapted and can be combined with other supplied asymmetric voltage waveforms, the control of one or more plasma characteristics, such as plasma density, plasma uniformity, and plasma sheath properties, can be more accurately controlled without the problems commonly seen in conventional RF matching and RF power supply designs. Moreover, the ability to adjust the timing and characteristics of asymmetric voltage waveforms, such as waveforms 303 and 225, provided to each of one or more types of electrodes or coils in a plasma processing chamber has been found to improve the control of the ion energy distribution (IED) for the plasma-generated ions that interact with the surface of the substrate during plasma processing. The methods and apparatuses disclosed herein are configured to control and maintain a plasma formed in the processing region of a plasma processing chamber without the need for the supply of high-frequency (RF) waveforms during processing and the need for its supporting RF components. For example, during the process of supplying a first asymmetric voltage waveform to a first electrode and a second asymmetric voltage waveform to a second electrode, the process is carried out without another source of electrical energy (e.g., an RF waveform) to maintain the plasma and perform a plasma process on the substrate. In some embodiments, for substantially all of the plasma processes carried out on the substrate, the plasma is not controlled, not affected, or not maintained in the processing space by the use or supply of a sinusoidal waveform. The ability to synchronize and control waveform characteristics, such as the frequency of the voltage pulses provided in each of the pulsed voltage waveforms applied to different electrodes and / or coils, the slope of portions of the voltage waveform, the waveform shape, and the applied voltage on-time during the pulse period, enables improved control of the generated plasma. As a result, greater precision for plasma processing can be achieved.

[0044] The term “coupled” is used herein to refer to a direct or indirect connection between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, then objects A and C may still be considered coupled to each other, even if objects A and C are not in direct physical contact with each other. For example, a first object may be coupled to a second object even if the first object is never in direct physical contact with the second object.

[0045] The foregoing applies to embodiments of the present disclosure, but other and further embodiments of the present disclosure may be devised without departing from its basic scope, the scope of which is determined by the following claims.

Claims

1. A plasma processing system, Multiple pulse voltage waveform generators, A plurality of electrodes or coils, wherein each of the plurality of electrodes or coils is arranged and configured such that when an asymmetric voltage waveform is supplied to the electrode or coil from one of the plurality of pulse voltage waveform generators, the characteristics of the plasma formed in the processing space of the plasma processing chamber of the plasma processing system are altered, and each electrode or coil is coupled to a different pulse voltage waveform generator from the plurality of pulse voltage waveform generators, A system controller configured to synchronize the supply of the asymmetric voltage waveforms from their pulse voltage waveform generators to each of the electrodes or coils. A plasma processing system equipped with [the following features].

2. The plurality of electrodes or coils include a first coil coupled to a first pulse voltage waveform generator among the plurality of pulse voltage waveform generators, The first pulse voltage waveform generator is configured to supply an asymmetric voltage waveform having multiple stages that vary between a first voltage level and a second voltage level. The waveform generator according to claim 1.

3. The waveform generator according to claim 2, wherein the first voltage level is a positive voltage level and the second voltage level is a negative voltage level.

4. The plurality of electrodes or coils include a second coil coupled to a second pulse voltage waveform generator among the plurality of pulse voltage waveform generators, The second pulse voltage waveform generator is configured to supply an asymmetric voltage waveform having multiple stages that vary between a third voltage level and a fourth voltage level. The waveform generator according to claim 2.

5. The plurality of electrodes or coils further comprises a first electrode coupled to a second pulse voltage waveform generator among the plurality of pulse voltage waveform generators, The second pulse voltage waveform generator is configured to supply an asymmetric voltage waveform having multiple stages that vary between a third voltage level and a fourth voltage level. The waveform generator according to claim 2.

6. The waveform generator according to claim 5, wherein the third voltage level is a positive voltage level and the fourth voltage level is a negative voltage level.

7. The waveform generator according to claim 5, wherein when the asymmetric voltage waveform reaches the fourth voltage level, the fourth voltage level is configured to generate a plasma sheath after reaching the third voltage level in each asymmetric voltage pulse.

8. A plasma control method formed in a plasma processing system, Supplying a first asymmetric voltage waveform from a first pulse voltage waveform generator to a first electrode or a first coil, wherein the first asymmetric voltage waveform is configured to change the characteristics of the plasma formed in the processing space of the plasma processing chamber, Supplying a second asymmetric voltage waveform from a second pulse voltage waveform generator to a second electrode or a second coil, wherein the second asymmetric voltage waveform is configured to change the characteristics of the plasma formed in the processing space of the plasma processing chamber, Synchronizing the supply of the first asymmetric voltage waveform and the supply of the second asymmetric voltage waveform. Methods that include...

9. The first asymmetrical voltage waveform is supplied to the first coil, The second asymmetric voltage waveform is supplied to the second electrode. The first asymmetric voltage waveform and the second asymmetric voltage waveform each comprise a plurality of stages. The method according to claim 8.

10. The method according to claim 9, wherein the first asymmetric voltage waveform fluctuates between a first voltage level that is positive and a second voltage level that is negative.

11. The method according to claim 10, wherein the second asymmetric voltage waveform comprises a plurality of steps that vary between a third voltage level and a fourth voltage level.

12. The first asymmetrical voltage waveform is supplied to the first coil, The second asymmetric voltage waveform is supplied to the second coil, The first asymmetric voltage waveform and the second asymmetric voltage waveform each comprise a plurality of stages. The method according to claim 8.

13. The first asymmetric voltage waveform and the second asymmetric voltage waveform each include a voltage pulse comprising a first stage, a second stage, and a third stage. The second stage of the voltage pulse is positioned between the first stage and the third stage. The voltage of the voltage pulse in the first and third stages fluctuates linearly with time. The method according to claim 8.

14. The first asymmetric voltage waveform and the second asymmetric voltage waveform each include a voltage pulse comprising a first stage, a second stage, and a third stage. The second stage of the voltage pulse is positioned between the first stage and the third stage. The voltage of the voltage pulse in the first and third stages fluctuates nonlinearly with time. The method according to claim 8.

15. The first asymmetrical voltage waveform is supplied to the first coil, The first asymmetrical voltage waveform includes a voltage pulse comprising a first stage, a second stage, and a third stage. The second stage of the voltage pulse is positioned between the first stage and the third stage. The voltage of the voltage pulse in the first and third stages fluctuates over time. The method according to claim 8.

16. The first asymmetrical voltage waveform includes a plurality of voltage pulses that extend between a first voltage level and a second voltage level. The second asymmetric voltage waveform includes a plurality of voltage pulses that extend between a third voltage level and a fourth voltage level. At least one of the first voltage level, the second voltage level, the third voltage level, and the fourth voltage level is different. The method according to claim 8.

17. The first asymmetrical voltage waveform is The first pulse period and the first slope (dV １ Multiple voltage pulses each comprising at least one sloped region having ( / dt) Includes, The first inclination (dV １ The slope (dV) of the sinusoidal waveform is measured at a phase angle where the sinusoidal waveform crosses zero. ｓ The sinusoidal waveform is equal to ( / dt) and has a frequency between 1 MHz and 100 MHz and a peak voltage between 500 volts and 5000 volts. The method according to claim 8.

18. The method according to claim 8, wherein supplying the first asymmetric voltage waveform and supplying the second asymmetric voltage waveform are performed without requiring a separate electrical energy source to maintain the plasma.

19. The method according to claim 8, wherein a sinusoidal waveform is not present in the processing space between the supply of the first asymmetric voltage waveform and the supply of the second asymmetric voltage waveform.

20. The method according to claim 8, wherein the plasma is not maintained in the processing space by the use of a sinusoidal waveform.

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