Semiconductor package design with a top-side heat spreader and bottom-side flat leads.

Abstract

This disclosure relates to a semiconductor package. The semiconductor package includes a semiconductor die, a plurality of flat leads on a first side of the semiconductor package, and a heat spreader on a second side of the semiconductor package. The plurality of flat leads are electrically connected to the semiconductor die. The heat spreader has a thickness of at least 1.5 times the thickness of each individual lead of the plurality of leads.

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 491,500, filed Mar. 21, 2023, entitled "SEMICONDUCTOR PACKAGE DESIGN WITH TOP - SIDE HEAT SPREADER AND BOTTOM - SIDE STAMPED FLAT LEADS", the disclosure of which is hereby incorporated by reference in its entirety for all purposes. <9000007> This application relates to semiconductor device packages. In particular, some embodiments relate to semiconductor packages having a heat spreader on one side and flat leads on the other side, and related manufacturing methods.

Background Art

[0003] Semiconductor devices are used in a wide variety of applications. In some applications, semiconductor devices may be subject to high electrical loads that can result in significant heating of the semiconductor device. There may be technical problems associated with high electrical loads, such as harmful heating of the semiconductor device from high loads. Further, conductors that provide electrical connections to the semiconductor package can affect the cost and performance of the semiconductor package. ]

Summary of the Invention

[0004] The technological innovations described in the claims each have several aspects, and no single one of them alone bears the desirable attributes. Without limiting the claims, some of the prominent features of this disclosure are briefly described here

[0005] One aspect of the present disclosure is a semiconductor package comprising a semiconductor die, a plurality of flat leads on a first side of the semiconductor package, and a heat spreader on a second side of the semiconductor package. The plurality of flat leads are electrically connected to the semiconductor die. The second side is located on the opposite side from the first side, and the heat spreader has a thickness of at least 1.5 times the thickness of the individual leads of the plurality of leads.

[0006] In one embodiment, the heat spreader can occupy more than two-thirds of the surface area on the second side.

[0007] In one embodiment, the heat spreader can occupy more than 70% of the surface area on the second side.

[0008] In one embodiment, the thickness of the heat spreader can be at least twice the thickness of the individual leads.

[0009] In one embodiment, the thickness of the heat spreader can be less than 10 times the thickness of each individual lead.

[0010] In one embodiment, the heat spreader may contain copper.

[0011] In one embodiment, at least one of the multiple leads may include a flank that can be wetted.

[0012] In one embodiment, the semiconductor die may include a switch.

[0013] In one embodiment, the semiconductor die may include a field-effect transistor having a gate, a source, and a drain. In addition, the plurality of flat leads may include a gate lead connected to the gate, a source lead connected to the source, and a drain lead connected to the drain.

[0014] In one embodiment, the semiconductor package may include a molding compound (molding resin) surrounding the semiconductor die. Each of the multiple flat leads may extend beyond the molding compound such that the exposed portion of the lead is flat.

[0015] Another aspect of the present disclosure is a semiconductor package comprising a molding compound, a semiconductor die, a plurality of flat leads on a first side of the semiconductor package, and a die paddle on a second side of the semiconductor package. The semiconductor die may include a field-effect transistor having a source, a gate, and a drain. The semiconductor die is enclosed by the molding compound. The plurality of flat leads may include a source lead connected to the source, a gate lead connected to the gate, and a drain lead connected to the drain, with each flat lead extending outward from the molding compound. The second side is located opposite to the first side. The die paddle has a thickness of at least twice the thickness of the individual leads of the plurality of flat leads.

[0016] In one embodiment, the die paddle can be exposed on a second side of the semiconductor package and occupy at least two-thirds of the surface area on the second side.

[0017] In one embodiment, the die paddle can dissipate heat generated from the semiconductor die, and the die paddle contains copper.

[0018] In one embodiment, at least one of the multiple flat leads may include a flank that can be wetted on the outward-facing side of the molding compound.

[0019] In one embodiment, a field-effect transistor can switch signals having voltages in the range of 12 volts to 150 volts.

[0020] Another aspect of the present disclosure is a semiconductor assembly comprising a semiconductor package and a printed circuit board. The semiconductor package comprises a semiconductor die, a plurality of flat leads on a first side of the semiconductor package, and a heat spreader on a second side of the semiconductor package. The plurality of flat leads are electrically connected to the semiconductor die. The second side is located opposite to the first side, and the heat spreader has a thickness of at least 1.5 times the thickness of the individual leads of the plurality of leads. The semiconductor package is placed on the printed circuit board such that the first side faces the printed circuit board.

[0021] In one embodiment, at least one of the multiple flat leads may include a humidifiable flank. Furthermore, the humidifiable flank can be soldered to a corresponding contact on a printed circuit board.

[0022] In one embodiment, the heat spreader may include grooves.

[0023] In one embodiment, the semiconductor die may include a field-effect transistor.

[0024] For the purpose of summarizing this disclosure, specific aspects, advantages, and novel features of the technological innovation are described herein. It should be understood that not all such advantages can necessarily be achieved according to any particular embodiment. Thus, the technological innovation may be embodied or performed to achieve or optimize one or more advantages or groups of advantages as taught herein, without necessarily achieving other advantages that can be taught or suggested herein. [Brief explanation of the drawing]

[0025] These and other features, aspects, and advantages of this disclosure will be described with reference to the drawings of specific embodiments. It should be understood that the accompanying drawings incorporated herein and forming part of this specification are for illustrative purposes only and are not to scale.

[0026] [Figure 1A] It is a diagram of a semiconductor package according to some embodiments. [Figure 1B] It is a diagram of a semiconductor package according to some embodiments. [Figure 1C] It is a diagram of a semiconductor package according to some embodiments.

[0027] [Figure 2] It is a top view of an embodiment of the semiconductor package of FIG. 1A. [Figure 3] It is a bottom view of an embodiment of the semiconductor package of FIG. 1A.

[0028] [Figure 4] It is a cross-sectional view of an exemplary semiconductor package passing through the line indicated by F-F in FIG. 2.

[0029] [Figure 5] It is a side view of an exemplary semiconductor package according to an embodiment. <0​​​​​​​​​​​​​​​​​​​​​​​​​​​​​ [Figure 10B] This figure shows exemplary embodiments of a lead frame according to several embodiments. [Figure 10C] This figure shows exemplary embodiments of a lead frame according to several embodiments.

[0036] [Figure 11A] This figure shows an example of an integrated die paddle with a lead.

[0037] [Figure 11B] This figure shows exemplary mounting configurations of semiconductor packages according to some embodiments of this specification.

[0038] [Figure 12A] This figure shows an example of a "gullwing" semiconductor package design.

[0039] [Figure 12B] This figure shows an exemplary embodiment of a flat lead packaging design according to one embodiment, which can have a smaller induction loop area than the semiconductor package design in Figure 12A.

[0040] [Figure 13A] This is an exploded view of an assembly for manufacturing a semiconductor package according to several embodiments. [Figure 13B] This is an exploded view of an assembly for manufacturing a semiconductor package according to several embodiments.

[0041] [Figure 14] This figure shows an exemplary embodiment of a sheet comprising an array of support frames and lead frames.

[0042] [Figure 15A] This is a diagram of a semiconductor package before encapsulation, according to several embodiments.

[0043] [Figure 15B] This is a diagram of a semiconductor package assembled according to several embodiments.

[0044] [Figure 16] This figure shows an exemplary assembly fixture used in the manufacture of semiconductor packages.

[0045] [Figure 17] This figure shows exploded views of a semiconductor package according to several embodiments.

[0046] [Figure 18A] This is a side view of a semiconductor package according to several embodiments. [Figure 18B] This is a bottom view of a semiconductor package according to several embodiments.

[0047] [Figure 19A] This figure shows an exemplary embodiment of a die paddle according to several embodiments.

[0048] [Figure 19B] This figure shows an exemplary embodiment of a die paddle partially housed within a molding compound according to several embodiments.

[0049] [Figure 20A] This figure shows exploded views of a semiconductor package according to several embodiments.

[0050] [Figure 20B] This is a cross-sectional view of an exemplary embodiment of a semiconductor package.

[0051] [Figure 20C] This is a diagram of a semiconductor package assembled according to several embodiments.

[0052] [Figure 20D] This is a diagram of a semiconductor package assembled according to several embodiments.

[0053] [Figure 21A] This is a top view of a semiconductor package according to several embodiments.

[0054] [Figure 21B] Figure 21A is a bottom view of the semiconductor package.

[0055] [Figure 21C] Figure 21A is an exploded view of the assembled semiconductor package. [Modes for carrying out the invention]

[0056] The following detailed descriptions of specific embodiments present various descriptions of those specific embodiments. However, the technological innovations described herein can be implemented in numerous different ways, for example, as defined and encompassed by the claims. In this description, similar reference numerals and / or terms refer to drawings in which identical or functionally similar elements may be indicated. It will be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, it will be understood that a particular embodiment may include more elements and / or subsets of elements shown in the drawings than those shown. Furthermore, some embodiments may incorporate any suitable combination of features from two or more drawings. The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claims. Introduction

[0057] Electronic components, including one or more integrated circuit (IC) dies, can be deployed in a wide variety of applications and environmental conditions. For example, such components can form part of a power electronics system. In some cases, a power electronics system can be used to power an electric vehicle. In some embodiments, a power electronics system can be part of a fixed energy storage system, such as a system for storing solar energy or a system for powering a destination. These are just examples, and there are many other applications for such systems. In some cases, the components may include diode switches, field-effect transistors (FETs) such as metal-oxide-semiconductor FETs (MOSFETs) (e.g., GaN MOSFETs), insulated-gate bipolar transistors (IGBTs), other bipolar transistors, or any suitable combination thereof. These components can generate significant heat during operation.

[0058] Electronic systems, such as power electronics systems, can generate a significant amount of heat under both steady-state load conditions and surge conditions. Such heat can present serious problems. For example, excessive heat can lead to reduced performance, decreased reliability, and shortened lifespan. For instance, excessive thermal stress can weaken solder joints, damage semiconductor components, or both. In some applications, surge loads can result in rapid temperature increases. High surge loads can be encountered in various applications, such as when starting portable compressors, HVAC systems, refrigeration systems, electric motors, and power converters. The shape and height of conductive elements can also have harmful parasitic inductance effects at certain switching frequencies. Therefore, die packaging that can facilitate sufficient heat transfer between steady-state and surge load scenarios is required. Such die packaging can be designed using internal elements that are low-profile and close to printed circuit boards (PCBs) during implementation.

[0059] Certain conventional low-profile packaging designs have several drawbacks. For example, power dual flat no-lead (PDFN) packaging may have insufficient thermal mass to meet the requirements for heat absorption and / or transfer of surge loads. Furthermore, manufacturing certain PDFN semiconductor packages can be complex, costly, and time-consuming. For example, PDFN semiconductor packaging may include the use of gullwings, which can be formed by copper etching to achieve the desired shape. The use of PDFN semiconductor packaging typically involves copper thickness limitations (e.g., about 1.6 mm), block forming, ground surfaces to expose planar heat spreaders, and the use of sorting to form individual devices. As described herein, alternative methods may offer one or more of the following compared to conventional packaging: improved thermal performance, reduced costs, and reduced complexity. Package design

[0060] Aspects of this disclosure relate to semiconductor packages having a relatively small inductance loop area and relatively high surge load heat absorption. Such semiconductor packages may include a thick die paddle with an area edge that reaches close to the outer periphery within the limits of manufacturability and reliable feasibility. This can provide a heat spreader with a relatively large area (range or area). A semiconductor package design with a dedicated thick die paddle can provide a platform for steady-state heat transfer and transient heat load capability to tether die temperature within a manageable range for long-term reliability and performance. Due to the relatively large thickness and shape of the die paddle, molding operations within low-profile package manufacturing processes may be limited. Thinner, more shaping lead frames can provide electrical connections to the die back and the top surface of the semiconductor die. In embodiments disclosed herein, a pre-formed lead frame can pre-position and arrange conductors into a desired shape early in the assembly process.

[0061] Aspects of this disclosure may include flat lead frames that enable thinner profiles (e.g., low profiles) of semiconductor packages. For example, the flat lead frames disclosed herein can provide a thinner lead frame than lead frames having a gull-wing structure. Flat leads may refer to leads having a substantially flat portion that extends outside the molding material of the semiconductor package. Semiconductor packages disclosed herein may also include die paddles that are significantly thicker than flat lead frames. For example, die paddles may be at least 1.5 times thicker than flat lead frames. In some examples, the operating voltage range of the semiconductor components described herein may vary between 1 volt (V) and 150 V, for example, between 12 V and 150 V. In these examples, flat lead frames may function as electrical contacts (e.g., terminals) of the semiconductor package, and flat lead frames have an appropriate thickness to facilitate the transmission of the generated current. For example, the thickness of a flat lead frame may be as minimum as 5 mil or 0.127 mm.

[0062] The embodiments disclosed herein can achieve thin-profile and low-profile attributes similar to PDFN semiconductor packages while using high-volume and low-cost manufacturing processes. Such high-volume and low-cost manufacturing processes may include one or more of copper planarization, stamping, forging, individual cavity encapsulation molding, or punch-cut singulation. The embodiments disclosed herein can be manufactured without surface grinding.

[0063] In embodiments disclosed herein, heat transfer can be concentrated on the upper side of the semiconductor package. Depending on the lower mounting surface temperature, PCB layout, and / or features, upper cooling may be desirable in certain applications. The techniques disclosed herein can be applied to double-sided cooled semiconductor packages. Certain designs may have conductive elements exposed on the top and bottom and may have design features to maintain their position during assembly and molding encapsulation. This allows for control of molding burrs and resin bleeding. Thus, the need for grinding can be reduced or eliminated. In some examples, a die paddle (e.g., used for heat dissipation) can be exposed on the top surface of the packaged semiconductor. For example, more than 60% of the upper area of ​​the semiconductor package may be the exposed surface of the die paddle. In certain examples, the die paddle may occupy at least 2 / 3, 70%, or 80% of the upper surface area of ​​the semiconductor package.

[0064] Figure 1A shows a semiconductor package according to several embodiments. The semiconductor package 100 may include a source contact 102, a drain contact 104, and a gate contact 106. The source contact 102, drain contact 104, and gate contact 106 can provide various electrical connections. For example, the source contact 102, drain contact 104, and gate contact 106 may include a source contact, a drain contact, a gate contact, and a contact for monitoring the semiconductor package 100 (e.g., a contact for a temperature sensor such as a thermocouple). In some embodiments, the source contact 102, drain contact 104, and gate contact 106 may extend beyond the bulk of the semiconductor package 100. In some embodiments, the source contact 102, drain contact 104, and gate contact 106 may be coplanar with the outer surface of the semiconductor package 100. In some embodiments, the source contact 102, drain contact 104, and gate contact 106 may be concave in one or more directions from the outer surface of the semiconductor package 100. Figures 1B and 1C show an exemplary design in which the source contact 102 can be integrated to form a single component rather than multiple individual leads, as shown in Figure 1A.

[0065] In this disclosure, source contacts, drain contacts, and gate contacts are used for illustrative purposes only. Generally, punched leads can be used to provide source terminals, gate terminals, drain terminals, Kelvin source terminals, control terminals, input terminals, output terminals, sensor terminals, base terminals, emitter terminals, collector terminals, ground terminals, reference terminals, short-circuit terminals, or any other suitable electrical terminals.

[0066] The semiconductor packages shown in Figures 1A to 1C may include an upper heat spreader having a relatively large area. A top view 150A of the semiconductor package 100 is shown in Figure 1B. Figure 1B shows an example of the die paddle 200 and molding compound 202 of the semiconductor package 100. The die paddle 200 can generally be referred to as the heat spreader of the semiconductor package 100. The die paddle 200 can function as a heat spreader in any suitable embodiment disclosed herein. The molding compound 202 may surround the components of the semiconductor package 100. In some cases, the die paddle 200 can provide an upper heat spreader having a relatively large area. For example, the top area 220 (or top exposed area of ​​the die paddle 200) of the die paddle 200 may be at least 60%, 2 / 3, 70%, or 80% of the top area 215 of the semiconductor package 100. The die paddle 200 can be made of any suitable conductive material, such as copper or a copper alloy.

[0067] Figure 1B further illustrates an example of a bottom view 150B of the semiconductor package 100. As shown in Figure 1B, the bottom view 150B may include a source contact 102, a drain contact 104, and a gate contact 106. Figure 1C further illustrates an internal view 150C of the semiconductor package 100. Each of the source contact 102, drain contact 104, and gate contact 106 may have flat leads of a lead frame 600 that can extend outside the semiconductor package 100. The lead frame 600 (e.g., flat leads) may include punched leads. The thickness 252 of the lead frame 600 can be determined based on the operating voltage range of the semiconductor package 100, which may vary from 1 volt (V) to 150V, 12V to 150V, etc. In some examples, the thickness 252 of the lead frame 600 may be at least 5 mil or 0.127 mm. In some examples, each lead frame 600 may include a flank 112 (e.g., a humidifiable flank plate) on its outward-facing side, as shown in Figure 1B, for example.

[0068] Figure 1C shows an exploded view of a semiconductor package 100 according to several embodiments. As shown in Figure 1C, the semiconductor package 100 may include a lead frame 600. The lead frame 600 may include a source contact 102, a drain contact 104, and a gate contact 106 (shown in Figure 1B). An integrated circuit (IC) die 400 may be placed between the lead frame 600 and the die paddle 200. The IC die 400 can be called a semiconductor die if it contains one or more semiconductor devices. In some examples, one or more field-effect transistors (FETs), such as one or more metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., one or more GaN MOSFETs), may be mounted on the IC die 400. Thus, the IC die 400 may include terminals such as a drain, a source (and a Kelvin source), and a gate terminal. In some embodiments, the die paddle 200 may have a thickness 210 sufficient to dissipate heat from transient events. The thickness 210 of the die paddle 200 can be at least 1.5 times thicker than the thickness 252 of the individual leads of the lead frame 600. In certain applications, the thickness 210 of the die paddle 200 can be at least 2, 2.5, or 3 times the thickness 252 of the individual leads. The thickness 210 of the die paddle may be less than 10 or 5 times the thickness 252 of the individual leads. The respective thicknesses 210 and 252 of the die paddle 210 and individual leads are vertical dimensions in the drawing. These thicknesses are perpendicular to the top and bottom surfaces of the semiconductor package.

[0069] Figures 2 and 3 show a top view and a bottom view of the semiconductor package 100, respectively. Figure 2 shows an example of a top view of the semiconductor package 100. As shown in Figure 2, the top surface of the semiconductor package 100 may include a portion of the die paddle 200 (upper exposed die paddle 200) surrounded by the molding compound 700. In some examples, the portion of the die paddle 200 may consist of at least two-thirds of the top surface 310 of the semiconductor package 100. Figure 2 also shows the lead frame 600 (flat leads).

[0070] Figure 3 shows an example of a bottom view of a semiconductor package 100. As shown in Figure 3, the semiconductor package 100 may include a source contact 102, a drain contact 104, and a gate contact 106, each contact having a flat lead frame shape. In some cases, the semiconductor package 100 may include exposed conductors 110A, 110B that can assist in the assembly and molding process.

[0071] Figure 4 shows a cross-section of the semiconductor package 100 through the region indicated by FF in Figure 2. As shown in Figure 4, the semiconductor package 100 may include a die paddle 200, a die and lead mounting structure 300 (e.g., solder, solder preform, conductive epoxy, sintered paste, etc.), an IC die 400, a source and gate mounting structure 500 (e.g., solder, solder preform, solder bumping, conductive epoxy, sintered paste, etc.), a lead frame 600, and a molding compound 700. These components are described in more detail herein. The IC die 400 may be a power IC or any other type of integrated circuit. In some embodiments, instead of the IC die 400, discrete circuits such as operational amplifiers composed of individual transistors may be implemented. In some embodiments, the IC die 400 may include a combination of integrated and discrete components. In some embodiments, the package may be adapted for wire bonding. For example, the gate contact 106 may be molded to accommodate wire bonding. In some embodiments, the lead frame 600 may be molded to accommodate wire bonding. For example, the corners of the lead frame 600 can be removed to create a gap for wire bonding, or they can be added to create a wire bonding surface area.

[0072] In a typical flat, leadless package, the die paddle 200 occupies roughly the same area as the IC die 400. However, such an approach may limit the thermal performance of the die paddle 200. This limitation can present significant problems for power electronics. Such problems can be particularly pronounced under surge loads that can rapidly generate large amounts of heat. Therefore, in some embodiments, the die paddle 200 can extend substantially beyond the area of ​​the IC die 400, as shown, for example, in Figure 4. Features can be incorporated into the die paddle 200 to obstruct or prevent the flow of die attachment material (e.g., solder such as Sn-based solder, solder preform, conductive epoxy, sintered paste, etc.) to an area substantially outside the area of ​​the IC die 400, as will be described in more detail below.

[0073] In some embodiments, thermal extraction can be concentrated on one side of the semiconductor package 100. For example, the underside (e.g., on the lead frame 600 side of the IC die 400) may face a carrier such as a printed circuit board and therefore may not be ideal for thermal extraction because it is necessary to deal with constraints imposed by nearby components on the PCB, lead routing within the PCB, contact pads on the PCB, etc.

[0074] As shown in Figure 4, in some embodiments, the die paddle 200 can be thicker than the lead frame 600. This can help ensure that the IC die 400 is maintained within an acceptable temperature range both during steady-state operation and under surge load. In some embodiments, the die paddle 200 and the IC die 400 can be approximately the same thickness. In some embodiments, the die paddle 200 can be thinner than the IC die 400. For example, in some embodiments, the PCB may include a thermal conductive insert, which in the PCB industry is sometimes referred to as a "coin" (e.g., a copper coin) located beneath the semiconductor package 100 when it is mounted on the PCB. The coin can act as a heat sink, allowing heat to be effectively extracted through the bottom of the semiconductor package 100.

[0075] As further shown in Figure 4, the thickness 210 of the die paddle 200 can be at least 1.5 times, 2 times, 2.5 times, or 3 times thicker than the thickness 252 of the lead frame 600. Furthermore, the area of ​​the die paddle 200 (for example, the area corresponding to the length 200A and width of the die paddle 200) can be at least 60%, 2 / 3, 70%, or 80% of the top surface area (for example, the area corresponding to the length 410 and width of the semiconductor package shown in Figure 4).

[0076] Figure 5 shows a side view of a semiconductor package 100 having punched leads (flat leads) of a lead frame 600 (which may include, for example, one or more source contacts, one or more drain contacts, one or more gate contacts, and / or any other suitable electrical leads). The leads 600 will be described in more detail below with reference to Figure 7. Figure 6 shows a cross-section of the semiconductor package 100 through the line EE shown in Figure 5. As shown in Figure 6, the semiconductor package 100 includes a die paddle 200, a die and lead mounting structure 300, an IC die 400, a gate mounting structure 500, a lead frame 600, and a molding compound 700. As shown in Figure 6, the lead frame 600 can electrically contact the IC die 400 via the gate mounting structure 500. The lead frame 600 can be configured such that the source contact 102, drain contact 104, and gate contact 106 are in contact with the gate mounting structure 500, and the source contact 102, drain contact 104, and gate contact 106 are not covered by the molding compound 700, and can be mounted on a carrier such as a printed circuit board. As will be described in more detail below, in some embodiments the die and lead mounting structure 300 and / or gate mounting structure 500 may include solder, solder preform, conductive epoxy, sintered paste, etc. In some embodiments the die and lead mounting support frame 600 (see Figure 13A) and / or 650 (see Figure 13A) can be compressed or deformed during the molding process.

[0077] As further shown in Figure 6, the thickness 210 of the die paddle 200 can be at least 1.5 times, 2 times, 2.5 times, or 3 times thicker than the thickness 252 of the individual leads of the lead frame 600. Furthermore, the area of ​​the die paddle 200 (e.g., the area corresponding to the length 200A and width of the die paddle 200) can be at least 60%, 2 / 3, 70%, or 80% of the top area (e.g., the area corresponding to the length 410 and width of the semiconductor package shown in Figure 6). Furthermore, the semiconductor package in Figure 6 may include a flat lead frame 600 having flat leads extending outside the molded compound 700. The flat lead frame 600 may include punched flat leads.

[0078] Figure 7 shows diagrams of flat leads of a lead frame 600 according to several embodiments. In some embodiments, the flat leads can be punched out. As shown in Figure 7, the flat leads may have portions that lie coplanar with the semiconductor package 100. In some embodiments, the flat leads may have dimples 108. The dimples 108 can provide cavities into which solder can flow during mounting of the semiconductor package 100 to a carrier such as a printed circuit board. In some embodiments, the dimples 108 can enable inspection of solder joints and / or rework of solder joints.

[0079] Figure 8 shows the outer surface of the die paddle 200 of the semiconductor package 100 according to several embodiments. In some embodiments, the outer surface can be exposed to the environment. In some embodiments, the outer surface can be embedded in a molding compound. The die paddle 200 can function as a heat spreader, transferring heat from the IC die (e.g., IC die 400) to the outer surface of the die paddle 200.

[0080] Figure 9 shows a diagram of the inner surface 204 of the die paddle 200 of a semiconductor package 100 according to several embodiments. As shown in Figure 9, in some embodiments, the inner surface 204 may include grooves 206. Grooves 206 can offer several advantages in certain applications. For example, grooves 206 can function as solder stoppers to restrict or prevent solder flow to undesirable areas of the inner surface 204, or to confine a volume of solder within an area to maintain a desired solder thickness. In some embodiments, grooves 206 can act as molding locks to help hold the die paddle 200 in place relative to other components during the assembly process.

[0081] Figure 10A shows an example of a lead frame 600 according to several embodiments. The lead frame 600 may include a lower portion 604 and an upper portion 606. The lower portion 604 may be in contact with the gate mount 500. The upper portion may be in contact with the die and lead mount portion 300. In some embodiments, the upper portion 606 may be able to communicate with the IC die 400 via the die and lead mount portion 300 and the die paddle 200. As shown in Figure 10A, the lead frame 600 may include various recesses that can function as alignment features. A stepped feature 602 may help ensure that the components are secured by the molding compound during the manufacturing process and service life of the semiconductor package 100.

[0082] The lead connections to the die paddle can not only float above the edge of the die, but can also straddle, branch, or be positioned along the die. Figures 10B and 10C show exemplary embodiments of the lead frame according to several embodiments. As shown in Figure 10B, the lead frame may have die paddle connection forks 608. Such a configuration allows the width W of the die paddle strip 610 to be kept relatively thin, maximizing the area available to accommodate larger die sizes. The paddle connection forks 608 can extend around the sides of the IC die, thereby increasing the mass of copper (and / or other metals) adjacent to the die and improving thermal performance. In some embodiments, the metal of the lead frame 600 can extend over the IC die 400. In some embodiments, the die paddle fork structure can increase the rigidity of the die paddle. In some embodiments, the die paddle fork structure can improve the molding lock so that components such as the die paddle, lead frame, and molding compound are less likely to shift relative to each other during temperature cycles in service.

[0083] Figure 10C shows another exemplary embodiment of the lead frame. As shown in Figure 10C, additional thermal mass can be added by extending the paddle connecting fork 608 along the edge of the die. In some embodiments, a conductive rim 612 can be included in the lead frame. In some embodiments, the conductive rim 612 can add additional thermal mass to the lead frame. In some embodiments, the conductive rim 612 can be exposed. In some embodiments, the conductive rim 612 can be embedded in the molding compound. As shown in Figure 10C, each flat lead may include a flank 112 that can be wetted on the outward-facing side of the flat lead frame 600.

[0084] As described above, the design according to this disclosure can enable a larger die paddle 200 which can allow for improved heat transfer. Figure 11A shows an example of an integrated die paddle with leads. In such a design, a lead frame 1102 and a die paddle 1104 may be present. As shown in Figure 11A, the die paddle 1104 may have leads integrated therewith. The size of the die paddle is constrained because the die paddle does not extend over the leads. Figure 11B shows an exemplary embodiment according to some embodiments of this specification. As shown in Figure 11B, the die paddle 200 may be a separate component without leads. The die paddle 200 may substantially extend over the lead frame 600. For example, the die paddle 200 may substantially extend over the drain contact 104. This can provide an improved heat transfer surface area and thermal mass which can help maintain the IC die 400 at an appropriate temperature under both steady-state and surge load conditions.

[0085] As briefly explained above, inductance loops can cause significant problems in certain electronic devices. Conductors connected to a die can form loops, and their proximity and spatial coupling can cause undesirable electromagnetic effects, such as parasitic inductance related to switching voltage, current, and / or frequency. Therefore, it may be desirable to limit the area of ​​any inductance loop.

[0086] Figure 12A shows an example of a "gullwing" design. As shown in Figure 12A, the inductance loop 1202 formed by the current flowing from source 1206 and drain 1208 can have a relatively large area. The "gullwing" design may be the result of a manufacturing process that includes post-formation lead cutting and bending.

[0087] Embodiments disclosed herein, such as in Figure 12B, may have pre-formed conductors with low profiles and narrow clearances for isolation of the molded compound and structural integrity. Such structures can result in a reduction or minimization of the length and area of ​​parasitic inductance loops. The semiconductor package in Figure 12B has nearly flat leads outside the molded compound, unlike the gull-wing design leads in Figure 12A.

[0088] Figure 12B shows an exemplary embodiment of a packaging design that can have a smaller inductance loop area than the packaging design in Figure 12A. As shown in Figure 12B, when current flows from the source contact 102 to the drain contact 104, an inductance loop 1204 can be formed. The length and area of ​​the inductance loop 1204 can be substantially smaller than the length and area of ​​the inductance loop 1202, reducing undesirable inductance effects.

[0089] Conductors can be shaped to occupy an inductance loop area in order to reduce the total loop area. Current path length can be similarly affected as desired. Proximity, capacitance, and spatial coupling between conductors can affect electromagnetic field effects. Operating parameters such as switching frequency, voltage, current rise rate, current fall rate, and conductive path electrical resistance (one or more of these) can be well tuned by the shape of the conductors. Manufacturing and assembly

[0090] As briefly described above, certain semiconductor packaging may involve the use of processes that include complex formation, etching, grinding, sawing, lead formation, and other processes. This can make the manufacturing of semiconductor assemblies time-consuming, expensive, and prone to errors. Advantageously, some of the structures and packaging described herein can be manufactured using simpler processes that overcome one or more of these limitations.

[0091] The assembly of stacked subcomponents with individual variable thickness tolerances can utilize solder or paste bonding layers to absorb such tolerances and achieve a consistent overall stack height. Pre-formed lead frames may have stepped height elements that mimic the closing height of the forming tool, allowing the assembled stack to self-fill the gap between the lower and upper fixtures, and conform elastically and inelastically during assembly and / or overmolding. A consistent overall height on the opposing surfaces of the assembly stack may be desirable to minimize molding burrs during overmolding and, ideally, to limit the penetration of the forming compound into conductor surfaces that remain exposed, such as leads and heat transfer surfaces. Pre-formed (e.g., pre-stamped) lead frame structures with stepped heights can be fixed during assembly for die and lead bonding materials to absorb tolerance variations in the stacked components. Pre-stamped conductors disclosed herein can be molded to engage with other components, such as die paddles and IC dies, in a variety of ways and combinations.

[0092] Figures 13A and 13B are exploded views of assemblies according to several embodiments. Figure 13B shows the stacking / assembly orientation inverted relative to Figure 13A. As shown in Figures 13A to 13B, the assembly may include a die paddle 200, a die and lead mounting structure 300, an IC die 400, a gate mounting structure 500, and a lead frame 600. The die paddle 200 can be mounted on a support frame 250. The lead frame 600 can be mounted on a support frame 650. The support frames 250 and 650 may include, for example, sheets of metal (e.g., copper). In some embodiments, the die paddle 200, the lead frame 600, or both can be punched out. For example, a sheet of material (e.g., a copper sheet or another metal sheet) can be punched out to form the die paddle 200 and support frame 250 or the lead frame 600 and support frame 650. The support frame can be used to facilitate the easy assembly of the semiconductor package 100. The support frame can be removed (e.g., by stamping, sawing, etc.) to form individual semiconductor packages 100. By using stamping to form the die paddle 200 and / or lead frame 600, it is possible to manufacture low-profile designs without requiring etching, thereby enabling faster and cheaper manufacturing.

[0093] Figure 14 shows an exemplary embodiment of sheet 1400 including an array of support frames 650 and lead frames 600. The die paddles 200 and support frames 250 can be prepared similarly by stamping a sheet of a suitable metal (e.g., copper).

[0094] Figure 15A is an unassembled diagram of a semiconductor package according to several embodiments. Figure 15B is a diagram of a completed semiconductor package according to several embodiments. In Figure 15B, the components are wrapped on one or more sides by the molding compound 700. The components of the semiconductor package may have feature and / or assembly heights that differ from the final molded height. Furthermore, due to tolerances in the manufacturing process of the various components that make up the semiconductor package, there can be considerable variation in feature height from package to package. Uneven feature heights, assembly heights, and molded heights can result in overflow of the molding compound. Conventional manufacturing methods may include sacrificial material that can be polished or ground after molding to ensure that the molding material does not cover electrical contacts. This can add cost and complexity to manufacturing because additional material is used that is later removed, and usually requires additional manufacturing steps to ensure surface quality.

[0095] According to some embodiments of this specification, the design of the lead frame and die paddle can eliminate or substantially reduce the need for the use of sacrificial material and / or additional polishing or grinding steps.

[0096] Figure 16 shows an exemplary assembly fixture 1600. The assembly fixture 1600 may have a molding height M, which can be the final height of the semiconductor package after molding. As described above, the components (e.g., die paddle 200, IC die 400, and lead frame 600) may have various heights that fall within manufacturing tolerances. In some embodiments, the die and lead mounting structure 300 and / or the gate mounting structure 500 may include solder. In some embodiments, the die and lead mounting structure 300 and / or the gate mounting structure 500 may include a suitable paste or other bonding material. In some embodiments, the suitable paste or bonding material may be fluid or liquid during the assembly, fixing, curing, and / or reflow process. For example, the die and lead mounting structure 300 and / or the gate mounting structure 500 may include Sn-based solder, silver sintered paste, or epoxy containing metal particles. The conforming paste can allow the stack (e.g., die paddle 200, IC die 400, and lead frame 600) to "float" slightly (e.g., tens of micrometers) relative to one another. As described above, the components of the semiconductor package may include, for example, support frames 250 and / or support frames 650. One or more components of the semiconductor package may include locking features that reduce or prevent excessive movement of the components relative to one another. When clamping the assembly fixture 1600, the conforming paste or other bonding material including the die and lead mounting structure 300 and / or gate mounting structure 500 can be compressed so that the overall height of the package matches the height of the mold. Such a technique can minimize molding burrs that may appear on the outer surface of the lead frame 600 and / or leads (e.g., source contact 102, drain contact 104, and / or gate contact 106). In some embodiments, the die paddle 200 can be elastically and / or inelastically deformed to conform to the height of the mold.For example, the die paddle support frame (e.g., support frame 250) can bend during compression, for example, due to the action of assembly fasteners. Additional package design

[0097] The package design described above can have many advantages. However, this disclosure is not limited to the above design. The features, manufacturing processes, etc., described herein can be incorporated into other semiconductor packages.

[0098] Figure 17 shows an exploded view of a semiconductor package according to several embodiments. The semiconductor package 1700 can be broadly similar to the semiconductor package 100. The semiconductor package 1700 may be desirable for various components, such as bidirectional high electron mobility transistors (e.g., bidirectional GaN HEMTs). The semiconductor package may include a lead frame 1702. The lead frame 1702 is broadly similar to the lead frame 600, but there may be various differences. For example, the lead frame 1702 may have different heights so that it can make contact with either side of the IC die 1706. The lead frame elements of the semiconductor package may include additional conductors or contacts for other functions, such as connections to die features for sensing, such as contact 1707, and / or connections to die paddles for electrical short circuits, such as contact 1708.

[0099] Figures 18A and 18B show a side view and a bottom view of the semiconductor package 1700. As shown in Figure 18A, the semiconductor package 1700 may include an upper die connection 1812 and a die paddle connection 1814. As seen in Figures 18A and 18B, the source contact 1802 can contact both sides of the die 1706. For example, the source contact 1802 (first source contact) can contact the die 1706 and contact 1708, and contact 1708 can electrically contact the side of the die 1706 opposite to the side that contacts the source contact 1802 and other source contacts 1804 (e.g., second source contact). As shown in Figure 18B, various contacts may be included. For example, the semiconductor package 1700 may include a gate contact 1806A (e.g., first gate contact) and a Kelvin signal contact 1808A (first Kelvin signal contact). The semiconductor package 1700 may also include another gate contact 1806B (e.g., a second gate contact), another Kelvin signal contact 1808B (a second Kelvin signal contact), and a paddle contact 1810. In some examples, the paddle contact 1810 can provide internal connection to a source contact 1802 (a first source contact) or another source contact 1804 (a second source contact). In some embodiments, these contacts (1802, 1804, 1806A, 1806B, 1808A, 1808B, and 1810) may have a flat lead frame shape.

[0100] Figure 19A shows exemplary embodiments of the die paddle 1900 according to several embodiments. As shown in Figure 19A, in some embodiments the die paddle 1900 may have integrated contacts 1902 rather than being electrically connected to contacts which are separate components. In some embodiments the die paddle 1900 may include features such as pads 1904 which can help ensure that the die paddle 1900 is precisely positioned. In some embodiments the pads 1904 may be elastically or inelastically compressed at various stages of assembly or molding.

[0101] Figure 19B shows an example of a molded die paddle (e.g., die paddle 1900) according to several embodiments. As shown in Figure 19B, the die paddle 1900 can be partially housed in the molded product 1910. In some embodiments, the contact 1902 may have a wettable flank 1908. The wettable flank 1908 can assist in mounting the IC package to a circuit board (e.g., soldering).

[0102] Figures 20A to 20D show examples of packages according to several embodiments. Figure 20A is an exploded view of a package according to several embodiments. In Figure 20A, the package may include a die paddle 2000, a die and lead mounting structure 3000 (e.g., solder, solder preform, conductive epoxy, sintered paste, etc.), an IC die 4000, a gate mounting structure 5000 (e.g., solder, solder preform, conductive epoxy, sintered paste, etc.), and a lead frame 6000. The lead frame 6000 may be mounted on a support frame 6050, for example, to facilitate manufacturing. In some embodiments, the lead frame may have a coplanar area 6010 in which the lead frame 6000 contacts the IC die 4000 via the gate mounting structure 5000. The coplanar area 6010 may be a coplanar stencil print. As shown in Figure 20A, the top surface of the die paddle 2000 does not have to be of a single height. For example, the top surface of the die paddle 2000 may have a stepped structure. The Diapaddle 2000 can be used as a clip heat spreader.

[0103] Figure 20B is a side view of the semiconductor package shown in Figure 20A. As shown in Figure 20B, a multi-gauge structure can be provided by removing (or not forming) a notch region 2050 from the die paddle 2000. This notch region 2050 allows for the use of a large die paddle 2000 that extends near the edge of the package while maintaining structural integrity. Such a configuration can provide an increased surface area of ​​the die paddle 2000, thereby enabling better thermal performance. As shown in Figure 20C, the finished package can house the die paddle 2000, die and lead mounting structure 3000, IC die 4000, gate mounting structure 5000, and lead frame 6000 within a molding compound 7000. The molding compound 7000 can extend, at least partially, over the die paddle 2000. For example, the molding compound 7000 can occupy the notch region 2050.

[0104] As further shown in Figure 20C, the thickness 210 of the die paddle 2000 can be at least 1.5 times thicker than the thickness 252 of the lead frame 6000. Furthermore, the area of ​​the die paddle 2000 (e.g., the area corresponding to length 200A of the die paddle 2000) can be at least 60% of the top area (e.g., the area corresponding to length 410 of the semiconductor package shown in Figure 20B). Furthermore, the semiconductor package in Figure 20B may include flat leads of the lead frame 600 that extend outside the molded compound 7000.

[0105] Figure 20D shows a completed package according to several embodiments. As shown in Figure 20D, the die paddle 2000 can be partially exposed and partially covered by the molding compound 7000. The package may include a contact 2002. In some embodiments, the contact 2002 may include a wettable flank 2008, for example, as described above with respect to Figure 19B.

[0106] Figures 21A to 21C show examples of semiconductor packages 2100 that can mount die paddles and flat lead frames according to several embodiments. Semiconductor package 2100 is an example of a semiconductor package in which leads are included on the short side of the semiconductor package. In other embodiments described above, the leads are included on the long side of the semiconductor package. The leads can be located on any suitable side or a number of sides of the semiconductor package according to any suitable principles and advantages disclosed herein. Figure 21A shows a top view of semiconductor package 2100. Semiconductor package 2100 may include a molding compound 2110 that can surround the components of semiconductor package 2100. The molding compound 2110 can be made of a rigid molding resin.

[0107] Figure 21B shows a bottom view of the semiconductor package 2100. The semiconductor package 2100 may include drain contacts 2122, source contacts 2132, gate terminals 2142, and a Kelvin source terminal 2134.

[0108] Figure 21C shows an exploded view of the semiconductor package 2100 according to several embodiments. The semiconductor package 2100 is mounted on a frame 2352 and can be assembled with other semiconductor packages. In some embodiments, the frame 2352 can provide mechanical support and electrical contact within the assembly.

[0109] As shown in Figure 21C, the semiconductor package 2100 may include a layer of bonding material 2312, a die 2314, a layer of die mounting material 2316, a molded resin packaging structure 2310, and a die paddle 2320 (e.g., a die clip). In some examples, the layer of bonding material 2312 may be formed based on a pattern that includes multiple areas for providing electrical connections to corresponding die connection terminals (e.g., contact terminals) such as the source (including the Kelvin source), drain, and gate of the semiconductor component. For example, die mounting pads 2312A, 2312B, 2312C, and 2312D may provide electrical connections to the drain terminal, source terminal, gate terminal, and Kelvin source terminal of the die connection terminal, respectively. In some examples, the layer of die mounting material 2312 may be formed from a conductive material such as solder or conductive epoxy. Additional Embodiments

[0110] The above specification has described the present disclosure with reference to specific embodiments. However, it will be apparent that various modifications and changes can be made without departing from the broader spirit and scope of the present disclosure. Accordingly, this specification and the drawings should be considered illustrative rather than restrictive.

[0111] In fact, while this disclosure is in the context of specific embodiments and examples, it will be understood by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or the use of the present invention and its equivalents. Furthermore, while some variations of the embodiments have been shown and described in detail, other modifications within the scope of this disclosure will be readily apparent to those skilled in the art based on this disclosure. Also, various combinations or partial combinations of specific features and aspects of the embodiments may be made and may still be included within the scope of this disclosure. It should be understood that various features and aspects of the disclosed embodiments may be combined with or substituted for each other to form various forms of the embodiments disclosed herein. The methods disclosed herein do not need to be performed in the order listed. Accordingly, it is intended that the scope of this disclosure should not be limited by the specific embodiments described above.

[0112] Each of the systems and methods disclosed herein has several innovative aspects, and it will be understood that not just one of them is solely responsible for or requires the desirable attributes disclosed herein. The various features and processes described above may be used independently of each other or in various combinations. All possible combinations and partial combinations are intended to fall within the scope of this disclosure.

[0113] Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable partial combination. Furthermore, features may be described above as acting in a particular combination, or even being initially claimed as such, but one or more features from a claimed combination may, in some cases, be removed from the combination, and the claimed combination may be subject to partial combinations or variations of partial combinations. A single feature or group of features is not required or essential to each and all embodiments.

[0114] It should also be understood that, among other things, conditional language used herein, such as “can,” “could,” “might,” “may,” and “e.g.,” is generally intended to convey that a particular embodiment includes certain features, elements, and / or steps, but other embodiments do not, unless otherwise specified or understood in the context in which they are used. Therefore, such conditional language is not generally intended to imply that features, elements, and / or steps are required in one or more embodiments, or that one or more embodiments necessarily include logic for determining whether these features, elements, and / or steps are included in or performed within any particular embodiment, with or without author input or facilitation. Terms such as “comprising,” “including,” and “having” are synonyms and are used comprehensively and in an open-ended manner, without precluding additional elements, features, actions, operations, etc. Furthermore, the term “or” is used in its inclusive sense (rather than its exclusive sense), and for example, when used to connect a list of elements, the term “or” means one, some, or all of the elements in the list. Furthermore, the articles “a,” “an,” and “the” used in this application and the attached claims should be interpreted as meaning “one or more” or “at least one” unless otherwise specified. Similarly, while actions may be shown in a particular order in the drawings, it should be understood that such actions do not need to be performed in the particular order shown or in a sequential order, or that not all illustrated actions need to be performed, in order to achieve the desired result. Furthermore, drawings may schematically illustrate one or more exemplary processes in the form of flowcharts. However, other actions not illustrated may be incorporated into the exemplary methods and processes schematically shown. For example, one or more additional actions may be performed before, after, simultaneously with, or in between any of the illustrated actions. Furthermore, actions may be rearranged or reordered in other embodiments.In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the above embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged in multiple software products. Further embodiments are within the scope of the following claims. In some cases, the operations described in the claims may be performed in a different order and still achieve the desired results.

[0115] Furthermore, the methods and apparatus described herein may be subject to various modifications and alternative forms, specific examples of which are shown in the drawings and described in detail herein. However, it should be understood that this disclosure is not limited to any particular form or method disclosed, but rather encompasses all modifications, equivalents, and alternatives that fall within the spirit and scope of the various embodiments and appended claims described herein. Furthermore, any particular features, aspects, methods, characteristics, features, qualities, attributes, elements, etc., disclosed herein relating to an embodiment or embodiment may be used in all other embodiments or embodiments described herein. The methods disclosed herein do not need to be performed in the order listed. The methods disclosed herein may include certain actions performed by a professional. However, the methods may also include any third-party instructions for those actions, expressly or implicitly. The scope disclosed herein also encompasses any and all overlaps, sub-scopes, and combinations thereof. Language such as “up to,” “at least,” “greater than,” “less than,” and “between” includes the numbers listed. Numbers preceded by terms such as "approximately" or "about" should be interpreted based on the context, including the listed numbers, and to the extent reasonably accurate under the circumstances, e.g., ±5%, ±10%, ±15%. Phrases preceded by terms such as "substantially" should be interpreted based on the context, including the listed phrases, and to the extent reasonably accurate under the circumstances. For example, "substantially constant" includes "constant." Unless otherwise specified, all measurements are taken under standard conditions, including temperature and pressure.

[0116] Where used herein, the phrase “at least one” in a list of items refers to any combination of those items, including a single component. For example, “at least one of A, B, or C” is intended to include A, B, C, A and B, A and C, B and C, and A, B and C. Combinations such as the phrase “at least one of X, Y, and Z” are generally understood in their context of use to convey that an item, term, etc., may be at least one of X, Y, or Z, unless otherwise specified. Thus, such combinations are not generally intended to imply that a particular embodiment requires the presence of at least one X, at least one Y, and at least one Z. Headings provided herein, where present, are for convenience only and do not necessarily affect the scope or meaning of the apparatus and methods disclosed herein.

[0117] Accordingly, the claims are not intended to be limited to the embodiments shown herein, but should be given the broadest scope that is consistent with the disclosures, principles, and novel features disclosed herein.

Claims

1. Semiconductor die and A plurality of flat leads on the first side of a semiconductor package, wherein the plurality of flat leads are electrically connected to the semiconductor die, A heat spreader on a second side of the semiconductor package, wherein the second side is opposite to the first side, and the heat spreader has a thickness of at least 1.5 times the thickness of each individual lead of the plurality of flat leads, A semiconductor package equipped with the following features.

2. The semiconductor package according to claim 1, wherein the heat spreader occupies more than two-thirds of the surface area on the second side.

3. The semiconductor package according to claim 1, wherein the heat spreader occupies more than 70% of the surface area on the second side.

4. The semiconductor package according to claim 1, wherein the thickness of the heat spreader is at least twice the thickness of the individual leads.

5. The semiconductor package according to claim 1, wherein the thickness of the heat spreader is less than 10 times the thickness of the individual leads.

6. The semiconductor package according to claim 1, wherein the heat spreader contains copper.

7. The semiconductor package according to claim 1, wherein at least one of the plurality of flat leads has a flank that can be wetted.

8. The semiconductor package according to claim 1, wherein the semiconductor die includes a switch.

9. The semiconductor die comprises a field-effect transistor having a gate, source, and drain. The semiconductor package according to claim 1, wherein the plurality of flat leads include a gate lead connected to the gate, a source lead connected to the source, and a drain lead connected to the drain.

10. The semiconductor package according to claim 1, further comprising a molding compound surrounding the semiconductor die, wherein each of the plurality of flat leads extends beyond the molding compound such that the exposed portion of the lead is flat.

11. Molding compound and, A semiconductor die comprising a field-effect transistor having a source, gate, and drain, wherein the semiconductor die is surrounded by the molding compound, A plurality of flat leads on the first side of the semiconductor package, wherein the plurality of flat leads include a source lead connected to the source, a gate lead connected to the gate, and a drain lead connected to the drain, and each flat lead extends outward from the molding compound, A die paddle on the second side of the semiconductor package, wherein the second side is opposite to the first side, and the die paddle has a thickness of at least twice the thickness of the individual leads of the plurality of flat leads, A semiconductor package equipped with the following features.

12. The semiconductor package according to claim 11, wherein the die paddle is exposed on the second side of the semiconductor package and occupies at least two-thirds of the surface area on the second side.

13. The semiconductor package according to claim 11, wherein the die paddle is configured to dissipate heat generated from the semiconductor die, and the die paddle contains copper.

14. The semiconductor package according to claim 11, wherein at least one of the plurality of flat leads has a flank that can be wetted on the outward-facing side outside the molded compound.

15. The semiconductor package according to claim 11, wherein the field-effect transistor is configured to switch signals having a voltage in the range of 12 volts to 150 volts.

16. A semiconductor package, wherein the semiconductor package is Semiconductor die and A plurality of flat leads on the first side of the semiconductor package, wherein the plurality of flat leads are electrically connected to the semiconductor die, A semiconductor package comprising: a heat spreader on a second side of the semiconductor package, wherein the second side is opposite to the first side, and the heat spreader has a thickness of at least 1.5 times the thickness of each individual lead of the plurality of leads; A printed circuit board, wherein the semiconductor package is arranged on the printed circuit board such that the first side faces the printed circuit board, A semiconductor assembly comprising the above features.

17. The semiconductor assembly according to claim 16, wherein at least one of the plurality of flat leads has a humidifiable flank, and the humidifiable flank is soldered onto a corresponding contact of the printed circuit board.

18. The semiconductor assembly according to claim 16, wherein the heat spreader includes grooves.

19. The semiconductor assembly according to claim 16, wherein the semiconductor die comprises a field-effect transistor.

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