Support containing a charge trap layer, composite substrate containing such support, and related manufacturing methods

Abstract

The present invention relates to a support (1) for a composite substrate, the support (1) comprising an intermediate layer (3) disposed on a base substrate (2). The intermediate layer (3) is in contact with the base substrate (2) and comprises a trap layer (3a) made of a silicon-rich oxide containing a silicon atom concentration of 40% to 99.9%. The intermediate layer also comprises a dielectric layer (3b) in contact with the trap layer (3a). A transition zone disposed between the trap layer (3a) and the dielectric layer (3b) has a thickness of more than 50 nm and has a continuously changing silicon atom concentration. The present invention also relates to a composite substrate (S) incorporating such a support (1) and a method for manufacturing the support (1).

Description

Technical Field

[0004]

[0001] The present invention relates to a support having a charge trap layer, which is intended to receive a crystalline thin film by layer transfer technology. A composite substrate formed from such a support is applied in the field of integrated electronic components, particularly radio frequency (RF) components that process signals whose frequencies can typically be between 20 kHz and 300 GHz or higher. The thin film of the composite substrate may be composed of a semiconductor material such as silicon, or an insulating material such as a material having piezoelectric and / or ferroelectric properties. In addition to the support itself, the present invention also relates to a composite substrate including this support and having a thin film transferred thereon. The present invention also relates to a method for manufacturing the support and a method for manufacturing a composite substrate incorporating such a support.

Background Art

[0002] There is a wealth of prior art in this field.

[0003] Thus, as an example of a first approach, U.S. Patent No. 7,585,748 and U.S. Patent No. 9,293,473 propose forming a charge trap layer (and more simply designated as a "trap layer" in the remainder of this specification) in the form of a layer of polycrystalline silicon disposed on a base substrate made of silicon.

[0004] The boundaries of the silicon particles constituting the polycrystalline layer constitute traps for charge that can circulate. These traps can be formed by incomplete or dangling chemical bonds at these boundaries. This prevents conduction within the trap layer, resulting in a high resistivity typically exceeding 1000 Ω·cm.

[0005] In addition to polycrystalline silicon, the trap layer can more generally be formed from a non-monocrystalline layer having structural defects such as dislocations, grain boundaries, amorphous regions, voids, inclusions, pores, etc., which can trap charge.

[0006] Therefore, the trap layer may be formed by injecting a relatively heavy species such as argon into the surface thickness of the base substrate to form structural defects therein that constitute an electrical trap. As an example of this approach, U.S. Patent No. 10224233 proposes a trap layer formed of nanocavities located in the surface zone of the base substrate, which are obtained by injecting helium and nitrogen.

[0007] This layer can also be formed by porosifying the surface thickness of the base substrate. Accordingly, U.S. Patent No. 10290533 proposes a trap layer consisting of pores formed on the surface of a base substrate that is oxidized and filled with a semiconductor, polycrystalline, or amorphous material.

[0008] However, for the sake of simplifying implementation, the trap layer is generally formed by depositing a layer of polycrystalline silicon on a base substrate. To maintain the polycrystalline quality of this layer during heat treatment applicable to the support, an amorphous layer, for example, made of silicon dioxide, may be advantageously provided on the base substrate before the deposition of the charge trap layer, as proposed in U.S. Patents 8,765,571 and 9,129,800.

[0009] U.S. Patent Application Publication No. 2015115480 proposes forming a trap layer as a stack of amorphous or polycrystalline base polycrystalline layers. These base layers may, in particular, consist of silicon, germanium, or silicon-germanium. This multilayer is required to make the trap layer more robust to heat treatment than the support undergoes, particularly during the manufacturing process of composite substrates employing such supports.

[0010] U.S. Patent No. 11251265 proposes that, in a particular embodiment, a trap layer is formed from a polycrystalline main layer, and an intermediate layer is formed from a silicon-carbon alloy, which is inserted into this layer.

[0011] In International Publication No. 2021110513, a polycrystalline silicon carbide layer is formed directly on the base substrate before a polycrystalline trap layer is placed within it.

[0012] In European Patent No. 3195352, the trap layer is selected from the group consisting of carbon nitride, silicon carbonnitride, and combinations thereof.

[0013] In European Patent No. 3195353, an amorphous or crystalline trap layer is formed from a material having a wide band gap, particularly a material selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium, and boron nitride.

[0014] In European Patent No. 3189544, the trap layer is an amorphous layer of carbon-doped silicon. This layer is formed on a silicon-based substrate having a silicon oxide surface layer.

[0015] In European Patent No. 3266038, a nucleation layer made of silicon oxide, silicon nitride, or silicon oxynitride is formed before the deposition of a polycrystalline silicon layer. This nucleation layer is heat-treated to form holes within it.

[0016] U.S. Patent No. 10468295 discloses forming a silicon nitride layer or silicon oxynitride layer between a polycrystalline silicon trap layer and a silicon oxide dielectric layer. This layer can be obtained by depositing or nitriding / oxynitriding the trap layer, and the purpose of this layer is to maintain the resistivity of the trap layer and avoid its recrystallization.

[0017] Generally, this prior art highlights the need for a support for composite substrates containing a trap layer with high resistivity and stable temperature. Since the fabrication of composite substrates containing such a support typically involves heat treatment that raises the support temperature to over 1000°C, this temperature stability is a critical feature. This is because the desired properties of the support tend to be lost due to recrystallization of the layer and separation of structural defects in this layer. U.S. Patent Application Publication 20150287783 recognizes in its introduction that high-temperature annealing (1000°C to 1100°C, according to this document) leads to a reduction in the number of traps in the trap layer, which affects its performance. To overcome this challenge, this document proposes fabricating the trap layer by preventing the structure thus formed from being exposed to excessive temperatures (over 200°C to 400°C, according to this document) after the device has been manufactured.

[0018] The need for temperature stability is not limited to the robustness of the trap layer during the manufacturing of the composite substrate. It also relates to operational stability, temperature, and the integrated electronic components ultimately formed on the composite substrate. These components tend to degrade in RF performance with increasing temperature, especially when the temperature exceeds 100°C.

[0019] It will be recalled that the RF performance of a particular component can be evaluated by performing an RF characterization of the composite substrate (more specifically, the support for this composite substrate), or in the intended context of how that component is formed. As described in the January 2015 publication "White Paper - RFSOI Characterization" issued by SOITEC, the RF performance of a substrate can be characterized by a second harmonic distortion measurement HD2.

[0020] Therefore, it is generally required to form a support that includes a trapping layer, which enables the formation of a support with high RF performance and stability against temperature, and these performances are established by measurement HD2.

[0021] Of course, the manufacturing of this layer can also be done as simply and inexpensively as possible, which facilitates the search for solutions that lead to minimizing the thickness of the layer and making the surface as smooth as possible, for example, in order to avoid preparing this surface by polishing it as much as possible.

[0022] To limit the thickness of the trap layer without impairing the performance of this layer, and therefore to improve the production rate, the latter needs to have a high density of electrical traps. High trap density also allows for a reduction in the sensitivity of the substrate's RF performance to the diffusion of species into the trap layer, which tends to electrically passivate the traps. This could be, for example, the diffusion of hydrogen or lithium (especially when the thin film of the composite substrate is formed from a lithium-based piezoelectric material). [Overview of the project]

[0023] Objective of the present invention The present invention aims to address these problems at least partially. More specifically, one object of the present invention is to propose a support for a composite substrate, the support comprising a trap layer having a high-density trap for charge. Another object of the present invention is to propose a support comprising a trap layer, which can have a thinner thickness than a prior art trap layer while providing a support having similar RF performance. Another object of the present invention is to propose a support comprising a trap layer whose RF performance is more temperature-stable than that of a prior art support. Yet another object of the present invention is to propose a support comprising a trap layer, the trap layer being easier to manufacture than that of a prior art support.

[0024] Brief Description of the Invention To achieve this objective, the subject of the present invention proposes a support for a composite substrate including an intermediate layer disposed on a base substrate.

[0025] According to the present invention, the support is - A trap layer made of silicon-rich oxide that contacts the base substrate and contains a silicon atom concentration of 40% to 99.9%, - A dielectric layer made of silicon oxide having a stoichiometric atomic concentration of silicon, which contacts the trap layer, - A transition zone that is disposed between the trap layer and the dielectric layer, has a thickness exceeding 50 nm, and in which the silicon atom concentration varies continuously, <00​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​ - A transition zone directly placed on the trap layer, having a thickness exceeding 50 nm, and in which the silicon atom concentration changes continuously, - A dielectric layer made of silicon oxide having a stoichiometric atomic concentration of silicon, in contact with the transition layer. This includes the formation of "in situ".

[0030] According to other advantageous and non-limiting features of this embodiment of the present invention, either individually or in any technically feasible combination, - The steps of depositing the trap layer and depositing the dielectric layer are performed inside the chamber of the deposition apparatus. - The steps of depositing the trap layer and the dielectric layer are carried out in two different deposition chambers, and the sequence for forming the intermediate layer includes the movement of the support between the two deposition chambers. - The manufacturing method further includes a step of annealing the intermediate layer, which is advantageously carried out at a temperature of 750°C to 1100°C. - The dielectric layer includes at least a surface thickness of silicon dioxide. [Brief explanation of the drawing]

[0031] Further features and advantages of the present invention will become apparent from the following detailed description of the invention with reference to the accompanying drawings.

[0032] [Figure 1] The support according to the present invention is shown. [Figure 2] A composite substrate using the support according to the present invention is shown. [Figure 3a] The trap layers according to the present invention, with various crystal shapes, are shown. [Figure 3b] The trap layers according to the present invention, with various crystal shapes, are shown. [Figure 3c] The trap layers according to the present invention, with various crystal shapes, are shown. [Figure 4a] This graph shows the atomic concentration profile of silicon in the intermediate layer of the support according to the present invention. [Figure 4b] This graph shows the atomic concentration profile of silicon in the intermediate layer of the support according to the present invention. [Figure 5] The properties and size of crystalline silicon-containing materials that may be present in the trap layer according to the present invention are shown. [Figure 6] This shows an SRP type measurement performed on a support according to the present invention. [Figure 7] This shows a comparison of the change in RF performance of the support according to the present invention and the support of the prior art, measured with HD2, as measured by temperature. [Modes for carrying out the invention]

[0033] Description of the support Figure 1 shows a support intended to receive a crystalline thin film by layer transfer technology to form a composite substrate S shown in Figure 2. In a very common method, the support 1 includes an intermediate layer 3 disposed on a base substrate 2. The intermediate layer 3 includes a trap layer 3a in contact with the base substrate 2. The intermediate layer may also include a dielectric layer 3b disposed on and in contact with the trap layer 3a, as shown in Figure 1, although this dielectric layer 3b is entirely optional. In such a case, it should be noted that it is not essential for the intermediate layer 3 to have a steep interface between the trap layer 3a and the dielectric layer 3b. Therefore, the intermediate layer 3 may have novel transitions in its composition at its thickness, thereby defining the trap layer 3a and the dielectric layer 3b. This aspect of the present invention will be shown in the following chapter of this disclosure.

[0034] If the dielectric layer 3b is absent, the intermediate layer 3 consists entirely of the trap layer 3a.

[0035] Conventionally, the support 1 may be in the form of a circular wafer with a diameter of 100, 150, 200, 300, or 450 mm.

[0036] The base substrate 2 of the support 1 on which the intermediate layer 3 is placed typically has a thickness of several hundred micrometers. Preferably, the base substrate 2 has a high resistivity of more than 1000 Ωcm, more preferably more than 2000 Ωcm. The density of charges, holes, or electrons that can move within the base substrate 2 is limited. However, the present invention is not limited to a base substrate 2 having such a resistivity, and offers RF performance advantages when the base substrate 2 has a more suitable resistivity on the order of several hundred Ωcm, for example, less than 1000 Ω.cm, or less than 500 Ω.cm, or less than 10 Ω.cm.

[0037] For reasons of availability and cost, the base substrate 2 is preferably made of single-crystal silicon. It may be, for example, a CZ silicon substrate with a low interstitial oxygen content of 6-10 ppm, or a FZ silicon substrate that naturally has a very low interstitial oxygen content. It may also be a CZ silicon substrate with a high interstitial oxygen content of over 26 ppm (indicated as "high Oi"), which can be heat-treated to finally obtain the desired properties. Alternatively, the base substrate 2 may be formed from another material, such as sapphire, glass, quartz, silicon carbide, etc. In certain situations, particularly when the trap layer 3a is sufficiently thick, for example, more than 10 micrometers, the base substrate 2a may have a standard resistivity of less than 1 kΩ.cm.

[0038] To maintain the properties of the trap layer 3a during heat treatments that the support 1 may undergo, an amorphous layer made of silicon dioxide can optionally be provided, for example, by being directly inserted between the base substrate 2 and the trap layer 3a. If the base substrate 2 is made of silicon, this amorphous layer may be a naturally occurring oxide layer present on the surface of the substrate, or it may be intentionally formed by chemical or thermal oxidation of the base substrate. However, the trap layer 3a described herein is particularly stable with respect to temperature, and the presence of the amorphous layer is entirely optional.

[0039] According to important aspects of this specification, the trap layer 3a is a silicon-rich oxide layer. This silicon-rich oxide layer consists of silicon, oxygen, and optionally nitrogen.

[0040] The term "silicon-rich" means that the atomic concentration of silicon in the layer is between 40% or 50% and 99.9%. Oxygen, and optionally nitrogen, are present at quasi-stoichiometric atomic concentrations.

[0041] It should be noted that prior art trap layers made of polycrystalline silicon have an atomic oxygen concentration of less than 0.01% (and therefore an atomic silicon concentration of more than 99.99%). Therefore, the trap layers formed from silicon-rich oxides proposed herein have an atomic oxygen concentration at least 10 times higher than conventional trap layers. This distinguishes them from such layers and gives them very specific properties.

[0042] In particular, such layers have the advantage of having a particularly high defect density that forms traps for charges. Thus, they can exhibit very high resistivity up to about 10^12 Ω.cm. More generally, this resistivity is between 10^5 Ω.cm and 10^12 Ω.cm. For comparison, dielectric layers of silicon (stoichiometric) oxide have resistivity on the order of 10^15 Ω.cm, while trap layers of prior art in polycrystalline silicon have a typical resistivity on the order of 10^4 Ω.cm.

[0043] The composition of the trap layer can be determined by secondary ion mass spectrometry (so-called "SIMS" measurement). However, for reasons of accuracy, in this field, it is preferable to use a technique called "depth profiling by X-ray photoelectron spectroscopy," which is depth profiling by X-ray electron spectroscopy (XPS) in ion beam etching. These techniques allow for the determination of the atomic concentrations of silicon, oxygen, and nitrogen in the trap layer 3a.

[0044] The atomic concentrations of silicon, oxygen, and optionally nitrogen do not need to be constant across the thickness of the trap layer 3a. In certain embodiments, these concentrations can be varied while remaining within the concentration limits that give the layer the silicon-rich property.

[0045] To its advantage, the silicon-rich trap layer is not intentionally doped to impart its resistance properties. It contains no other species other than silicon, oxygen, and optionally nitrogen. If other species are incorporated into the layer, they are present in amounts no more than simple trace amounts, less than 0.1%.

[0046] The crystal quality of a silicon-rich layer is highly dependent on its atomic oxygen concentration and, optionally, its atomic nitrogen concentration. It also depends on the heat treatment the layer has undergone.

[0047] Generally, silicon-rich layers are formed from an amorphous matrix. This amorphous matrix may contain silicon crystalline inclusions or crystalline silicon particles, and the density and size of these inclusions and / or particles within the amorphous matrix depend on the relative proportions of oxygen, nitrogen, and silicon in the layer and the heat treatment the layer undergoes. In extreme cases, a silicon-rich layer may be entirely amorphous or entirely polycrystalline, and in the latter case, the amorphous matrix is ​​reduced to amorphous inclusions present between polycrystalline particles.

[0048] Therefore, when the atomic concentrations of oxygen and nitrogen are low, and thus the atomic concentration of silicon is quite high, for example, 99% or more, the silicon-rich layer takes the polycrystalline form shown in Figure 3a. Particles g, or some of them, can be coated with a thickness of amorphous material, and this amorphous material is located at the grain boundaries of the polycrystalline layer. The amorphous material may also be in the form of interparticle inclusions ia of the polycrystalline layer. These inclusions ia may have dimensions typically in the range of 10 nm to 100 nm, depending on the atomic concentrations of oxygen and, optionally, nitrogen in the layer. This amorphous material, which is rich in oxygen and / or nitrogen, consists of aggregates of species that make up the layer, such as aggregates of SiO, SiN, SiON and oxygen, and / or nitrogen precipitates.

[0049] The polycrystalline layer is formed from silicon particles g, and its size distribution has a peak (defining the average particle size) close to or less than 100 nm. This average size is much smaller than the average particle size of conventional trap layers made of polycrystalline silicon (on the order of 300 nm).

[0050] When the silicon atomic concentration in a silicon-rich layer is low, for example in the range of 40% to 90% or 50% to 90%, and it contains an oxygen concentration of 10% or more and optionally a nitrogen concentration, the latter mainly takes on an amorphous form. As shown in Figure 3b, it is composed of nanometer-sized components of Si, SiO, SiON, and SiN, which gives it this amorphous nature.

[0051] Between a polycrystalline state and a perfectly amorphous state, the crystalline quality of the layer can be intermediate. Therefore, as shown in Figure 3c, the silicon-rich layer may take the form of an amorphous matrix, with crystalline silicon-containing ICs embedded within it. These ICs may have a size of less than 10 nm, and in some cases, less than 5 nm.

[0052] By increasing the atomic concentration of silicon within the trap layer 3a, these inclusions ic tend to grow to form particles g, which are close to the polycrystalline structure presented above, with reference to Figure 3a.

[0053] It should be noted that amorphous, polycrystalline, or intermediate forms may be affected by heat treatment applied to this layer during or after its manufacture, or even during use of the support. Furthermore, limits on oxygen, nitrogen, and / or silicon concentrations are given only as examples. Those skilled in the art can adjust these concentrations using a series of experiments that are very easy to perform, thereby obtaining a trap layer 3a with the desired structural characteristics. In particular, the precise crystalline properties of the layer can be observed by microscopic examination, such as transmission electron microscopy (TEM) or Raman measurement.

[0054] Experiments conducted by the applicant demonstrated that a specific composition of the trap layer 3a, made of silicon-rich oxide, exhibits particularly stable temperature and dense trapping for charge. Therefore, such a layer can possess particularly interesting radio frequency performance.

[0055] Therefore, in a particular preferred embodiment, the trap layer 3a is - Silicon with an atomic concentration of 60% to 90%, preferably 70% to 90%, - 10% to 40%, preferably 10% to 30% of oxygen at atomic concentrations, It can be composed of.

[0056] In other preferred embodiments, the trap layer 3a is - Silicon with an atomic concentration of 30% to 77%, - Oxygen with an atomic concentration of 8% to 40%, - Nitrogen with an atomic concentration of 8% to 45%, It can be composed of.

[0057] "Temperature stable" means that after exposure to a minimum thermal budget of 850°C for 2 hours, the support 1 according to the present invention has resistivity characteristics measured by the HD2 technique (presented in the introduction) of less than -80 dB. Some products have higher requirements. Therefore, a support 1 of a silicon composite substrate on an insulator (formed from a layer of single-crystal silicon transferred to the support) is expected to have resistivity characteristics HD2 of less than -80 dB after exposure to a thermal budget of 1100°C for 2 hours. A support 1 of a piezoelectric composite substrate on an insulator (formed from a layer of piezoelectric single-crystal material transferred to the support) is expected to have resistivity characteristics HD2 of less than -80 dB after exposure to a thermal budget of 900°C for 2 hours.

[0058] In these preferred embodiments, the trap layer 3a takes the form of an amorphous matrix into which crystalline silicon-containing ICs are embedded. These ICs have a size of less than 10 nm, and in some cases less than 5 nm.

[0059] Generally, the trap layer 3a has a thickness that can be between 10 nm and 30 microns, typically between 20 nm and 5 microns. Preferably, this thickness is greater than 50 nm or 100 nm so that the amount of trapping is sufficient. Preferably, this thickness is less than 2 micrometers or less than 1 micrometer to limit the amount of material and the stress that this layer may impart to the support 1. Such stress could deform the support 1. However, this advantageous range of thickness is by no means limiting, and it is possible to choose to form a trap layer 3a of any appropriate thickness depending on the needs of the intended application.

[0060] In particular, measurements performed by the applicant (which are the subject of the last chapter of this specification) showed that thicknesses of 30 nm to 200 nm can contain a sufficient amount of trapping.

[0061] The trap layer 3a has a first surface that is in contact with the base substrate 2. The trap layer 3a has a second surface opposite to the first surface. In certain embodiments, particularly when the trap layer 3a is relatively thin, for example less than 500 nm, less than 100 nm, or less than 50 nm, or when the atomic oxygen concentration is relatively low, less than 10%, or depending on the deposition technique employed, the second surface of the trap layer 3 has low roughness such that it does not need to be treated to improve its surface condition. This roughness may be less than 0.6 nm when the root mean square value measured over a 1 micrometer × 10 micrometer area.

[0062] As described in the previous paragraph of this specification, the intermediate layer 3 may include, in addition to the trap layer 3a just described, a dielectric layer 3b that is placed on and in contact with the trap layer. The “dielectric layer” refers to a layer having a resistivity of the order of 10^10 Ω.cm or more. In any case, the resistivity of the dielectric layer 3b is greater than the resistivity of the trap layer 3a.

[0063] The dielectric layer 3b can generally have any properties and an appropriate thickness. However, advantageously, the support 1 according to this specification has a dielectric layer 3b composed of silicon, oxygen, and / or nitrogen, which is the same composition as that which can constitute the trap layer 3a. This feature allows the intermediate layer 3 to be formed in a single step, for example, by successively forming the trap layer 3a and the dielectric layer 3b in the same deposition apparatus "in situ".

[0064] Generally, "in situ" refers to the fact that support 1 is kept in a controlled atmosphere during the production of the intermediate layer, for example, by holding it within a single chamber of a deposition apparatus, or by passing the apparatus between multiple chambers while maintaining it in a sealed, controlled environment. This avoids contamination by contaminants from the atmosphere (e.g., boron or phosphorus), which can degrade the RF performance of the support.

[0065] The dielectric layer 3b is distinguished from the trap layer 3a in that its atomic silicon concentration is less than 40%. Its atomic concentration of oxygen, and optionally, its atomic concentration of nitrogen, can be at least one stoichiometric proportion.

[0066] The dielectric layer 3b typically has a thickness of 10 nm to 10 microns and is essentially determined by the need to apply the composite substrate S on which the support 1 is intended to be formed.

[0067] In the integrated approach of forming the intermediate layer 3 "in its original position," the exposed surface of this layer can benefit from the lower roughness previously presented relative to the trapped layer 3a. Thus, this intermediate layer 3 can have a free surface area of ​​less than 0.6 nm in mean squared values ​​measured over a region of 10 micrometers per 10 micrometers.

[0068] Advantageously, the dielectric layer 3b is made of silicon oxide or silicon nitride, at least partially, particularly in the surface portion. A support 1 is provided having an exposed surface whose properties of silicon oxide or silicon nitride are fully known. This surface may be prepared by polishing, cleaning, and activation, in particular, to transfer a thin film by layer transfer technique, depending on a controlled method, and thus form a composite substrate.

[0069] If the dielectric layer 2b is entirely made of silicon oxide or silicon nitride at the atomic concentration of stoichiometric silicon, this atomic concentration can change abruptly at the interface between the trap layer 3a and the dielectric layer 3b, i.e., where the transition zone is less than 50 nm. Such a configuration is shown in the graph of Figure 4a. In this graph, the change in the atomic concentration (%) of silicon CSi at the thickness D of the intermediate layer 3a is shown from the free surface (corresponding to the 0 (zero) depth on the x-axis D) toward the surface on which the base substrate 2 is placed. An abrupt transition between the dielectric layer 3b and the trap layer 3a is observed.

[0070] However, the atomic concentration of oxygen, and optionally the atomic concentration of nitrogen, may be specified to change continuously with respect to the thickness of the intermediate layer 3, and the transition zone may exceed 50 nm. The atomic concentration of silicon can be used to continuously decrease the thickness of the intermediate layer 3 as it moves away from the base substrate, in particular to form a surface portion of the intermediate layer 3 made of, for example, silicon oxide or silicon nitride. Such a configuration is shown in the graph of Figure 4b. If the atomic concentration of nitrogen in the trap layer 3a is not zero, the atomic concentration of nitrogen can be changed continuously or abruptly so that the atomic concentration of nitrogen is zero in the surface portion when the surface portion is made of silicon oxide.

[0071] Description of composite substrates As already mentioned, the purpose of the support substrate 1 is to accept the thin film 4 by transfer and thus form the composite substrate S shown exemplify in Figure 2. The thin film is generally crystalline, and advantageously, single-crystalline. The support substrate 1 has suitable properties (particularly in terms of surface roughness and deformation) or is pre-treated to accept such a thin film 4.

[0072] As is well known, this transfer is usually carried out by assembling the free surfaces of the donor substrate to the support substrate 1, preferably by molecular adhesion. This assembly is generally facilitated by the presence of an amorphous layer, for example, made of silicon dioxide or silicon nitride, on at least one of the surfaces to be assembled. When the intermediate layer 3 of the support surfacely has such an amorphous surface layer (which may be a trap layer 3a or a dielectric layer 3b), the donor substrate itself does not need to be provided as a single unit. However, this is not excluded, and it is also possible to provide the donor substrate with a thin amorphous thickness (for example, a silicon dioxide layer less than 150 nm thick).

[0073] The properties of the donor substrate are selected according to the desired properties of the thin film 4. Therefore, it may be a substrate formed from a single-crystal semiconductor, such as silicon, or a substrate formed from a single-crystal piezoelectric material, or a substrate including a surface layer of such a single-crystal piezoelectric material. In this case, it may be lithium tantalate or lithium niobate.

[0074] Furthermore, the donor substrate may have finished or semi-finished components, and the transfer aims to place these components onto the support 1 in order to utilize their radio frequency characteristics. However, in the preferred specification, the donor substrate lacks any components for transferring a thin film 4 made of a crystalline material, advantageously a single crystal.

[0075] Similar to support 1, the donor substrate may take the form of a circular plate whose dimensions correspond to those of the support.

[0076] Following this assembly step, which may include solidification annealing at a moderate temperature (below 600°C), the donor substrate is thinned to form a thin film 4. This thinning step can be carried out by mechanical or chemical thinning. Preferably, the thickness reduction of the donor substrate can be carried out by fracturing a pre-introduced brittle plane in the donor substrate, for example, by injecting a light species such as hydrogen and / or helium. This brittle plane, along with the free surface of the donor substrate, defines the thin film 4.

[0077] This thinning step, or preferably after the crushing step, can be followed by finishing steps for the thin film 4, such as polishing, heat treatment in a reducing or neutral atmosphere, or sacrificial oxidation. The finishing step includes exposing the composite substrate to a relatively high temperature exceeding 600°C for at least 1 hour. For example, when the additional thin film 4 is made of silicon, the composite structure S is exposed to a thermal budget of at least 1000°C for 1 hour. When the additional thin film 4 is made of piezoelectric material, the composite structure S is exposed to a thermal budget of at least 600°C for 1 hour.

[0078] In all cases, the trap layer 3a maintains a stable temperature, and the RF characteristics of the composite substrate S are not excessively altered by the heat treatment applied to it during the finishing steps.

[0079] At the end of these steps, a composite substrate S formed from a single-crystal thin film transferred onto a support 1 is available.

[0080] In a particularly interesting example of application, the thin film 4 is a single-crystal piezoelectric thin film directly attached to the trap layer 3a. In other words, the support does not have a dielectric layer 3a. The single-crystal piezoelectric thin film may be lithium tantalate or lithium niobate. Such composite substrates are particularly suitable for receiving surface wave acoustic devices. The trap layer 3a, due to its properties, has acoustic properties similar to the silicon dioxide layer commonly used in these devices. In such cases, the trap layer has a dual function: improving the radio frequency characteristics of the components and allowing acoustic waves to propagate properly.

[0081] In another interesting application example, the intermediate layer 3 has a dielectric layer 3b made of silicon dioxide, which may have a thickness between 10 nm and 10 microns. The thin film 4 is a layer of single-crystal silicon. The composite substrate S then forms a silicon-on-insulation substrate.

[0082] Method for manufacturing a support The fabrication of support 1, which was the subject of the previous chapter of this specification, is particularly simple and can be achieved using standard industrial deposition equipment.

[0083] For example, the base substrate 2 is placed in the chamber of a conventional deposition apparatus. As is well known, the base substrate 2 can be prepared before deposition to remove a layer of natural oxide from its surface. This step is not essential and allows for the preservation of this oxide. As previously mentioned, if the substrate 2 is made of silicon by chemical or thermal treatment, it is even possible to intentionally form a relatively thin amorphous layer, such as a layer of silicon oxide, on the surface of the base substrate 2.

[0084] Regardless of any processing applied to the base substrate 2 before or immediately after its introduction into the chamber of the deposition apparatus, the chamber is passed through by a flow of precursor gas that reacts to gradually form an intermediate layer 3 on the base substrate 2. Thus, the sequence for forming the intermediate layer 3 includes the step of depositing a silicon-rich oxide trap layer 3a directly onto the base substrate 2 having an amorphous layer or onto the base substrate 2 not having an amorphous layer, according to one of the preferred embodiments presented above.

[0085] As an example, the step of depositing the trap layer 3a may be carried out according to chemical vapor deposition, for example, according to PECVD (plasma-excited chemical vapor deposition) technique or LPCVD (low-pressure chemical vapor deposition) technique.

[0086] The deposition step involves introducing a first silicon precursor gas (e.g., silane of formula SiH4) and at least one second oxygen precursor gas (nitrous oxide or dioxygen), and optionally nitrogen (e.g., nitrous oxide of formula N2O), into the deposition chamber. These precursor gases can be supplemented with a carrier gas, e.g., nitrogen, argon, or helium. Clearly distinct precursor gases for oxygen and nitrogen can be provided naturally. As is well known, the precursor gases react in the deposition chamber under controlled pressure and temperature conditions to gradually form a trap layer 3a.

[0087] When deposition is carried out via PECVD technology, it is performed at moderate temperatures, typically 150°C to 600°C, and at atmospheric pressure, for example, a few Torres (i.e., several hundred Pascals). When carried out via LPCVD technology, deposition is typically performed at temperatures, typically 550°C to 750°C, and at atmospheric pressure, for example, a few Torres (i.e., several hundred Pascals).

[0088] Of course, the present invention is by no means limited to deposition or specific techniques of a particular precursor gas. As an alternative to the techniques already described, the formation of the intermediate layer 3 can be assumed by APCVD (Atmospheric Pressure Chemical Deposition) technique, typically in the temperature range of 1000°C to 1150°C. Alternatively, it may be HDP CVD (High Density Plasma Chemical Deposition) technique, typically carried out at a relatively low temperature of 100°C to 450°C and a pressure on the order of 10 m Torre (i.e., 1.33 Pascals). SACVD ("Sub-Atmospheric Chemical Deposition") technique can also be assumed. Furthermore, an epitaxy constructed to form this layer by general techniques of gas-phase deposition can also be used.

[0089] Regarding the precursors, regardless of the assumed deposition technology, in addition to the silane and nitrous oxide already described, dichlorosilane or trichlorosilane may be provided as silicon precursor gases. Dioxygen can be used as the oxygen precursor gas. It is not necessary to provide a nitrogen precursor gas. The carrier gas, generally a neutral gas, may consist of or contain nitrogen, hydrogen, and argon.

[0090] Regardless of the deposition technique selected, the atomic concentrations of silicon, oxygen, and nitrogen are chosen by controlling the flow of the precursor gases, particularly the ratio of the flow of the first silicon precursor gas to the flow of the second oxygen precursor gas and optionally the flow of nitrogen. A higher ratio results in lower atomic concentrations of oxygen and optionally nitrogen. By keeping this flow ratio constant, a silicon-rich oxide layer with constant atomic concentrations of oxygen and optionally nitrogen can be formed, although this ratio can also be varied. As shown in Figures 4a and 4b, this variation can be continuous or abrupt, depending on whether the marked interface is desirable for the intermediate layer 3.

[0091] The flow is held for a period of several minutes to several hours, long enough to form the desired thickness of the trap layer 3a.

[0092] Following the deposition step, the trap layer 3a can be annealed either directly within the deposition chamber or in another apparatus. This annealing can be carried out at a temperature of 50°C to 1100°C. Annealing may affect the crystallographic properties of the trap layer, as can be seen immediately after the deposition step.

[0093] For example, annealing can reveal nanometer-sized crystalline silicon inclusions ic within a deposited, completely amorphous trap layer 3a. These inclusions ic may change in size or density once they are present in the deposited trap layer 3.

[0094] Therefore, at the end of this first deposition step, the trap layer 3a is placed on the base substrate 2. The deposition can be controlled by its thickness or its components such that the layer has a particularly low roughness of 0.6 nm in mean squared values ​​measured over a 10 micrometer × 10 micrometer area.

[0095] In some variations, the sequence for forming the intermediate layer 3 includes a step of depositing a dielectric layer 3b after a step of depositing a trap layer 3a. This second step may be carried out in a different apparatus from the one used to deposit the trap layer 3a, and according to a different deposition technique than that used in the first step. As already mentioned, this allows for the formation of a dielectric layer 3b of any suitable properties.

[0096] However, advantageously, the step of depositing the dielectric layer 3b is carried out "in its original location". For example, the dielectric layer 3b made of silicon oxide or silicon nitride can also be formed in a single chamber using the same precursor gas.

[0097] In this approach, the flow of precursor gases, more precisely the ratio of these flows, is controlled during the formation sequence of the intermediate layer 3 to form the trap layer 3a abruptly or gradually, and then the dielectric layer 3b. The circulation of the precursor gas flow can be interrupted to apply a heat treatment step (or multiple heat treatment steps) during the formation of the intermediate layer 3. This heat treatment can also be carried out at the end of the formation of the intermediate layer 3, either "in its original location" within the chamber of the deposition apparatus or "ex situ" in an apparatus separate from the deposition apparatus.

[0098] In other words, the sequence for forming the intermediate layer 3 is controlled to change the atomic concentration of silicon continuously or abruptly. For example, the atomic concentration of silicon can be selected to continuously decrease the thickness of the intermediate layer 3 as it moves away from the base substrate 2. In this case, a trap layer 3a in contact with the base substrate 2 can be formed to create the intermediate layer 3 (having atomic concentrations of oxygen and "quasi-stoichiometric" nitrogen). The atomic concentration of one of these species is increased to form a dielectric layer 3b on top of the trap layer 3a, made of silicon dioxide or silicon nitride, for example, containing an atomic concentration of stoichiometric silicon.

[0099] Furthermore, it is also possible to choose to form the intermediate layer 3 using multiple deposition techniques. For example, the trap layer 3a may be formed in the first chamber of the deposition apparatus according to a first technique (e.g., by PECVD). The dielectric layer 3b may be formed in the second chamber according to a second technique different from the first technique (e.g., HDP). This approach allows us to benefit from the advantages of each of these techniques. In particular, the HDP technique allows for the formation of a layer with low roughness.

[0100] In this case, advantageously, by controlling the movement between the two chambers, these "in-place" steps can be performed within the same apparatus without exposing the support to the ambient atmosphere during this movement.

[0101] Advantageously, the dielectric layer 3b includes a surface thickness of silicon dioxide or silicon nitride. [Examples]

[0102] Example 1: A silicon-rich trap layer containing silicon, oxygen, and nitrogen. As an example, several supports described in previous chapters of this specification were prepared to illustrate these points.

[0103] All of the support base substrates had a high resistivity (3 kΩ.cm). A trap layer was formed using PECVD technology. The PECVD apparatus was introduced into the deposition chamber where the base substrates had previously been placed. A first silicon precursor gas consisting of silane (SiH4) and a second oxygen and nitrogen precursor gas consisting of nitrous oxide (N2O) were introduced. Nitrogen-containing gases were replenished to these precursor gases. The deposition chamber was maintained at a pressure of 3 Torre (i.e., 400 Pascals). The plasma (at 13.55 MHz) had a power of 300 W.

[0104] The ratio between the nitrous oxide flow and the silane flow (N2O / SiH4, measured at a standard cubic centimeter per minute) was controlled to a ratio of 0.05 to 0.5, and each was deployed accordingly: - A support (of type 1) having a trap layer composed of 76.5% silicon, 8.5% oxygen, and 15% nitrogen. - A support (of type 2) having a trap layer composed of 60.6% silicon, 19.2% oxygen, and 20.2% nitrogen. - A support (of type 3) having a trap layer composed of silicon at an atomic concentration of 30% to 60%, oxygen at an atomic concentration of 10% to 40%, and nitrogen at an atomic concentration of 10% to 45%.

[0105] These atomic concentrations were measured by XPS measurements using ion beam etching.

[0106] Maintaining the flow, a trap layer was formed with a thickness selected from 200 nm or 1 micrometer for Type 1 and Type 2 supports, and a thickness selected between 70 nm and 500 nm for Type 3 supports.

[0107] In some cases, a 200 nm silicon dioxide dielectric layer was formed at its original location on the trap layer by controlling the flow of nitrous oxide and silane with an N2O / SiH4 ratio of 5.

[0108] At the end of these deposition steps, the supports formed from the base substrate with the trap layer and, in some cases, the dielectric layer, were annealed in a neutral atmosphere at 900°C or 1100°C for 2 hours for Type 1 and Type 2 supports, and at 850°C for 2 hours for Type 3 supports.

[0109] The multiple supports manufactured in this manner consisted of a matrix of supports with diverse configurations, and were subjected to numerous characterization measurements.

[0110] Therefore, TEM microscopy observations were performed on Type 1 and Type 2 supports containing a 200 nm trap layer and lacking a dielectric layer, particularly on the trap layers of the Type 1 support containing 8.5% oxygen and the Type 2 support containing 19.2% oxygen, both annealed at 1100°C. These characterization measurements revealed that in both cases, the trap layer was formed from an amorphous matrix, as shown in Figure 3c, and that crystalline inclusions with a size of less than 10 nm were present.

[0111] TEM microscopy observations were performed on a type 3 support annealed at 850°C, revealing only that the trap layer was formed from an amorphous matrix with only a few crystalline inclusions. Similarly, the same measurements were performed on a 200 nm type 2 trap layer (containing 19.2% oxygen) annealed at 900°C, showing only that this layer was completely amorphous and therefore contained no detectable crystalline inclusions.

[0112] The assumption is that, within the range of atomic composition of the studied trap layers, these crystalline inclusions grow at temperatures around 900°C (depending on the atomic concentration of silicon) so that they become fully visible by TEM after annealing at 1100°C.

[0113] XRD characterization confirmed that these crystalline inclusions were formed from silicon microcrystals, which could have orientations of 110, 220, or 311. Figure 5 shows the distribution of these microcrystals and the dimensions of the three trap layers with different properties: - Layer "A": Type 1 support (8.5% oxygen) annealed at 900°C, - Layer "B": Type 1 support (8.5% oxygen) annealed at 1100°C, - Layer "C": Type 2 (19.2% oxygen) support annealed at 1100°C.

[0114] A series of measurements were also performed to electrically characterize the trap layer and support structure.

[0115] The first step is to measure the SRP for "diffusion resistance profiling." To perform this measurement, the support is polished to form a chamfer, making the various layers constituting the support accessible at their respective depths. The ends of two electrodes, spaced a certain distance apart and forming segments parallel to the chamfer, are applied to the chamfered portion of the substrate. A determined voltage is applied between the two electrodes, and the resistance between them is measured. From this measurement, the electrical resistivity of the support at the measurement depth is then subtracted. By performing this measurement at different distances from the chamfer (corresponding to different depths in the substrate), a resistivity profile curve showing resistivity as a function of depth in the substrate can be plotted. A more detailed explanation of this characterization can be found in the document "White Paper - RFSOI Characterization" presented in the introduction of this application.

[0116] In the graph in Figure 6, the x-axis represents the measurement depth (micrometers) in one of the matrix supports. This distance is taken from the exposed surface of the support, in this case, the exposed surface of the trap layer. The y-axis represents the resistivity (Ω.cm) measured by the measured SRP.

[0117] The support subjected to SRP measurement consisted of a high resistivity base substrate (3.5 kΩ.cm) and a trap layer obtained by PECVD technique by controlling the nitrous oxide / silane ratio to 0.15. The trap layer was composed of 76.5% silicon, 8.5% oxygen, and 15% nitrogen. The trap layer had a thickness of 1 micrometer. The resistivity measurement is reported by line TR in Figure 6. For comparison, line TR' corresponding to the maximum resistivity of a conventional trap layer made of polycrystalline silicon with a thickness of 2 micrometers is plotted. In Figure 6, we can see that the resistivity of the trap layer formed from silicon-rich oxide with resistivity measurements is much higher, it can exceed 10^6 Ω.cm. Such measurements are generally on the order of 10^4 for conventional trap layers.

[0118] While the characterization SRP measures the electrical performance of the trap layer itself, it cannot fully predict the RF performance of the support. This performance is actually affected not only by parameters related to the resistive characteristics of the trap layer, but also by parameters such as its thickness or the resistivity characteristics of the base substrate. The measurement HD2 presented in the introduction of this application allows for a more general evaluation of the support's RF performance when used as a support for a composite substrate that accepts RF components.

[0119] Therefore, HD2 measurements (with a 15 dBm input signal at 900 MHz) were performed on supports resulting from Type 1, 2, and 3 test matrices, particularly on supports of this matrix having a 200 nm dielectric surface layer. The expected HQF value (theoretical HD2 value for a "perfect" trap layer) is -95 dB. The results of these measurements are reproduced below. - Five Type 1 supports containing a 200nm trapping layer and annealed at 1100°C for 2 hours: The average of these five supports is -91dBm. - Eight Type 2 supports containing a 200nm trapping layer, annealed at 900°C for 2 hours: the average of these eight supports is -90dBm. - More than nine Type 3 supports annealed at 850°C for 2 hours: average -82 dBm, - Support containing a 1.7 micrometer polycrystalline silicon trapping layer (prior art): -67 dBm.

[0120] Compared to those obtained on supports with conventional trap layers, these measurements clearly demonstrate the advantages of the support according to the present invention, even when the trap layer is relatively thin, at 200 nm, which is much thinner than the 1.7 micrometer trap layer used for comparison.

[0121] Figure 7 compares the change in RF performance measured by HD2 of the support with respect to temperature. In particular, Figure 7 compares this change (indicated as T' in the figure) of a prior art support having a 1.7-micron polycrystalline silicon trap layer with a support having a 1-micrometer thick Type 1 support trap layer (indicated as T in the figure). The base substrates of the two supports were the same. Interestingly, it should be noted that the performance HD2 of the support according to the present invention is far less affected by temperature than that of the support according to the prior art.

[0122] In another series of experiments aimed at determining the robustness of the trap layer against lithium contamination, a composite substrate containing a thin film 4 made of single-crystal piezoelectric material (made of lithium tantalate) was fabricated using a Type 3 support, according to the layer transfer method described above. A silicon oxide dielectric layer (labeled "BOX" in the table below) was placed between the trap layer (labeled "TR" in this table) and the thin piezoelectric layer. During the steps of preparing the support and fabricating the composite substrate, the trap layer was exposed to a maximum temperature of 850°C for 2 hours.

[0123] The following table summarizes the characteristics of the composite substrates studied in these experiments, including both their RF performance (in HD2 measurements) and lithium concentration within the trapping layer.

[0124] [Table 1]

[0125] In comparison, a composite substrate containing a piezoelectric thin film transferred onto a support with a conventional layer of polycrystalline silicon traps, and equipped with a 250 nm dielectric layer, exhibits measured RF performance exceeding -70 dB for a lithium dose of 1 E12 at / cm².

[0126] Therefore, it should be noted that the trap layer of the Type 3 support tends to passivate its traps, but can incorporate a large amount of lithium without losing its RF properties (measured by HD2). It can be concluded that the trap layer of the Type 3 support contains a very high trap density and can incorporate a large amount of passivated species without affecting its performance.

[0127] At the end of these experiments, the charge trap layer consisting of silicon, oxygen, and nitrogen was in the following proportions, namely: - Silicon with an atomic concentration of 30% to 60%, - Oxygen with an atomic concentration of 8% to 40%, - Nitrogen at an atomic concentration of 8% to 45%, It should be noted that even after undergoing relatively high-temperature annealing, the RF performance can be incorporated into a temperature-stable support composition that exhibits satisfactory performance (below -80 dB in HD2 measurements).

[0128] This performance is also achieved for relatively thin thicknesses starting from 75nm.

[0129] These supports are also robust against contamination of electrical passivation elements. Therefore, they do not require a thick barrier dielectric layer between the thin film, which can provide its passivation elements, and the support. A 100 nm silicon oxide dielectric layer is sufficient, for example, in the case of a composite substrate containing a lithium-containing thin film.

[0130] Finally, it should be noted that these properties are obtained for a wide range of silicon, oxygen, and nitrogen compositions, which facilitates the fabrication of this trap layer as it does not require very precise control of its exact composition during manufacturing. [Examples]

[0131] Example 2: A silicon-rich trap layer made of silicon and oxygen. Another series of experiments attempted to evaluate the feasibility of using a silicon-rich trap layer consisting of silicon and oxygen (and therefore nitrogen-free).

[0132] A support (of type 4) having a trap layer, - Atomic concentrations of oxygen equal to 10%, 40%, 55%, and 60%, respectively, and atomic concentrations of silicon equal to 90%, 60%, 45%, and 40%, respectively. - With a thickness of 200nm to 1 micron, - Annealing at 900°C or 1100°C for 2 hours, It holds.

[0133] The (average) RF performance measurements, as a function of silicon concentration, measured using HD2 technology (15 dBm input signal at 900 MHz), are as follows:

[0134] [Table 2]

[0135] The measured HQF (theoretical value of HD2 relative to a "perfect" trap layer) is expected to be -88dB.

[0136] These measurements showed that Type 4 supports exhibited the same level of RF performance as measured by HD2, regardless of the thickness of the trap layer. Therefore, this thickness does not appear to affect this performance.

[0137] However, the table shows that this performance is determined by the composition of the trap layer.

[0138] TEM observations performed on these samples showed that satisfactory RF performance was associated with the presence of uniformly distributed microcrystals within the layer. Their size could be on the order of 5 nm immediately after the deposition of the trap layer, but under the influence of annealing, they could grow to over 10 nm afterward (especially after annealing at 1100°C for 2 hours).

[0139] At the end of the experiment, there is a temperature-stable silicon-rich trap layer consisting of the following: - Silicon with an atomic concentration of 60% to 90%, and - Oxygen with an atomic concentration of 10% to 40%.

[0140] Advantageously, it consists of silicon with an atomic concentration of 70% to 90% and oxygen with an atomic concentration of 10% to 30%.

[0141] Therefore, the characterization measurements presented here clearly demonstrate the advantages of the trap layer and support according to the present invention. Note that by preparing a trap layer thicker than the support layer of the test matrix (up to 1 micrometer), the RF performance (in HD2 measurements) can be easily improved compared to an exposed layer. As mentioned above, this thickness can be assumed to be between 10 nm and 30 microns.

[0142] Of course, the present invention is not limited to the embodiments described, and additional modified embodiments may be added without departing from the scope of the invention as defined in the claims.

Claims

1. A support (1) for a composite substrate (S), The support (1) includes an intermediate layer (3) disposed on a base substrate (2), The aforementioned intermediate layer (3) is - A trap layer (3a) made of a silicon-rich oxide containing a silicon atom concentration of 40% to 99.9% is in contact with the base substrate (2), - A dielectric layer (3b) made of silicon oxide having a stoichiometric atomic concentration of silicon is in contact with the trap layer (3a), - A transition zone is disposed between the trap layer (3a) and the dielectric layer (3b), having a thickness exceeding 50 nm, and in which the silicon atom concentration changes continuously. Support (1), including the support.

2. The aforementioned trap layer (3a) is a. Oxygen with an atomic concentration of 0.1% to 30%, b. Nitrogen with an atomic concentration of 0% to 40%, including, The support (1) according to claim 1.

3. The atomic concentration of the oxygen is 5% to 30%. The support (1) according to claim 2.

4. The intermediate layer (3) is made entirely of silicon and oxygen, or entirely of silicon, oxygen, and nitrogen. The support (1) according to any one of claims 1 to 3.

5. In the thickness of the intermediate layer (3), the atomic concentration of silicon decreases continuously as it moves away from the base substrate (2). The support (1) according to any one of claims 1 to 4.

6. A composite substrate (S) comprising a single-crystal thin film (4) disposed on a support (1) according to any one of claims 1 to 5.

7. The single-crystal thin film (4) is made of silicon or piezoelectric material. The composite substrate (S) according to claim 6.

8. A method for manufacturing a support (1) for a composite substrate (S), - The step of providing a base substrate (2) inside the chamber of the deposition apparatus, - A sequence for forming an intermediate layer (3) on the base substrate (2), Includes, The formation sequence is performed without exposing the support to the surrounding atmosphere. - A trap layer (3a) made of a silicon-rich oxide containing a silicon atom concentration of 40% to 99.9%, which is in contact with the base substrate (2). - A transition zone directly placed on the trap layer (3a), having a thickness exceeding 50 nm, in which the silicon atom concentration changes continuously, and - A dielectric layer (3b) made of silicon oxide having a stoichiometric atomic concentration of silicon, in contact with the transition layer. This includes the formation of the "in situ" of Manufacturing method.

9. The steps of depositing the trap layer (3a) and depositing the dielectric layer (3b) are performed inside the chamber of the deposition apparatus. The manufacturing method according to claim 8.

10. The steps of depositing the trap layer (3a) and the dielectric layer (3b) are carried out in two different deposition chambers, and the sequence for forming the intermediate layer (3) includes moving the support between the two deposition chambers. The manufacturing method according to claim 8.

11. The process further includes the step of annealing the intermediate layer (3), preferably at a temperature of 750°C to 1100°C. The manufacturing method according to any one of claims 8 to 10.

12. The dielectric layer (3b) includes at least the surface thickness of silicon dioxide. The manufacturing method according to any one of claims 8 to 11.

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