Quantum error correction using a stabilizer defined in real projective plane topology

Abstract

A quantum computing system comprises a classical computing entity, a controller, and a quantum processor. The controller is configured to control the operation of the quantum processor and communicate with the computing entity. The controller triggers the implementation of a syndrome circuit segment to generate a syndrome of logic qubits. The syndrome circuit segment is implemented, at least in part, by triggering the implementation of an interaction of a set of at least two physical qubits. The logic qubits comprise multiple data qubits logically organized in real projective plane topology, and the interaction of the set of at least two physical qubits is determined based on a stabilizer determined based on the real projective plane topology of the logic qubits. The classical computing entity determines at least one quantum error correction based on the syndrome. The classical memory of the controller or the classical computing entity is updated based on the syndrome and / or at least one quantum error correction.

Description

Technical Field

[0001] Cross - reference to related applications This application claims the priority of U.S. Application No. 18 / 605,140, filed on Mar. 14, 2024, which claims the priority of U.S. Application No. 63 / 491,612, filed on Mar. 22, 2023, the contents of which are hereby incorporated by reference in their entirety.

[0002] Various embodiments relate to quantum error correction using stabilizers defined using quantum error correction (QEC) codes with real projective plane topology.

Background Art

[0003] Complex quantum computations require levels of accuracy that are not possible with conventional quantum computers due to, for example, imperfect control and noise in gate operations between data qubits. Through dedicated effort, ingenuity, and technological innovation, many of the drawbacks of previous systems have been solved by deploying solutions constructed according to embodiments of the present invention, many examples of which are detailed herein.

Summary of the Invention

Means for Solving the Problems

[0004] Exemplary embodiments provide a method, a system, an apparatus, a computer program product for performing quantum error correction (QEC), a controller configured to control the operation of a quantum processor, etc. The stabilizer used in the implementation of the syndrome circuit segment is defined based on a surface QEC code having real projective plane topology. For example, in various embodiments, at least one syndrome circuit segment is implemented to determine or generate at least one syndrome of a logical qubit. The logical operations implemented as part of the syndrome circuit segment are determined based at least in part on stabilizers (also referred to herein as stabilizer operators) determined based on real projective plane topology.

[0005] For example, in various embodiments, each logic qubit comprises a plurality of physical data qubits logically organized based on a real projection plane topology. The topology of the plurality of data qubits defines and / or determines, at least in part, the stabilizer of the logic qubit. The stabilizer acts on the logic qubit (for example, on the data qubits of the logic qubit in the manner defined by the topology of the logic qubit) and is used to extract a syndrome from the logic qubit. In various embodiments, the syndrome is used to identify the error that occurred and / or that an error occurred, so that error correction can be determined and / or applied.

[0006] According to a first aspect, a method for performing quantum error correction is provided. In one exemplary embodiment, the method is performed by a quantum computing system comprising a classical computing entity, a controller, and a quantum processor. The controller is configured to control the operation of the quantum processor and communicates with the classical computing entity. In one exemplary embodiment, the method comprises the step of causing the controller to perform the implementation of at least one syndrome circuit segment to generate a syndrome of logic qubits. The at least one syndrome circuit segment is performed by causing the implementation of a set of at least two physical qubit interactions, at least in part. The logic qubits comprise a plurality of data qubits logically organized in real projection plane topology. The set of at least two physical qubit interactions is determined at least in part on one or more stabilizers determined on the real projection plane topology of the logic qubits. The method further comprises the step of causing the classical computing entity to determine at least one quantum error correction, at least in part on the syndrome of logic qubits, and the step of causing the controller to update a classical memory of at least one of the controller or the classical computing entity based on the syndrome or at least one of the quantum error corrections.

[0007] In one exemplary embodiment, each ballast of one or more ballasts comprises four instances of the same operator, and each of the four instances of the same operator acts on different data qubits of a plurality of data qubits.

[0008] In one exemplary embodiment, at least one of one or more ballasts comprises two instances of a first operator and two instances of a second operator, where each instance of the first operator and each instance of the second operator acts on different data qubits of a plurality of data qubits.

[0009] In one exemplary embodiment, each of the one or more ballasts is a ballast with a weight of 4.

[0010] In one exemplary embodiment, the method further comprises the step of having a controller apply at least one quantum error correction to a logical qubit.

[0011] In one exemplary embodiment, the step of ensuring that at least one quantum error correction is applied to a logical qubit comprises at least one of the following steps: (a) updating a classical qubit registry corresponding to the logical qubit based on at least one quantum error correction; (b) causing the implementation of a physical correction to one or more data qubits of the logical qubit; or (c) ensuring that a logical operation which will be implemented at least in part on one or more data qubits of the logical qubit is modified at least in part based on at least one quantum error correction.

[0012] In one exemplary embodiment, the implementation of at least one syndrome circuit segment comprises the implementation of multiple syndrome circuit segments.

[0013] In one exemplary embodiment, at least one interaction of at least two physical qubits among a series of interactions of at least two physical qubits includes an interaction of at least one auxiliary qubit with at least one data qubit among a plurality of data qubits of a logical qubit.

[0014] In one exemplary embodiment, the logic qubit is one of a plurality of logic qubits, and at least one auxiliary qubit is used to implement a syndrome circuit segment for two or more of the plurality of logic qubits.

[0015] In one exemplary embodiment, updating a classical memory based on a syndrome or at least one of at least one quantum error correction comprises tracking a syndrome of logical qubits in the classical memory.

[0016] In one exemplary embodiment, the coherence of multiple data qubits of a logic qubit is maintained during the implementation of at least one syndrome circuit segment.

[0017] In one exemplary embodiment, the method further comprises the steps of: causing the execution of a state-preparation circuit segment to prepare the state of each auxiliary qubit before causing the execution of at least one syndrome circuit segment; performing a series of at least two physical qubit interactions using each auxiliary qubit; and ensuring that each auxiliary qubit is read after the execution of the series of at least two physical qubit interactions, the logic qubit syndrome is generated on at least part of the results of the reading of each auxiliary qubit.

[0018] In another embodiment, a quantum computing system configured to perform quantum error correction is provided. In one exemplary embodiment, the quantum computing system comprises a classical computing entity, a controller, and a quantum processor. The controller is configured to control the operation of the quantum processor and communicates with the classical computing entity. In one exemplary embodiment, the controller is configured to trigger the implementation of at least one syndrome circuit segment to generate a syndrome of logic qubits. The at least one syndrome circuit segment is implemented by triggering the implementation of a set of at least two physical qubit interactions, at least in part. The logic qubits comprise a plurality of data qubits logically organized in real projection plane topology. The set of at least two physical qubit interactions is determined at least in part on one or more stabilizers determined based on the real projection plane topology of the logic qubits. The controller is further configured to determine at least one quantum error correction, at least in part on the syndrome of logic qubits, so that a classical memory of at least one of the controller or classical computing entities is updated based on the syndrome or at least one of the at least one quantum error correction.

[0019] In one exemplary embodiment, each ballast of one or more ballasts comprises four instances of the same operator, and each of the four instances of the same operator acts on different data qubits of a plurality of data qubits.

[0020] In one exemplary embodiment, at least one of one or more ballasts comprises two instances of a first operator and two instances of a second operator, where each instance of the first operator and each instance of the second operator acts on different data qubits of a plurality of data qubits.

[0021] In one exemplary embodiment, each of the one or more ballasts is a ballast with a weight of 4.

[0022] In one exemplary embodiment, the controller is further configured to cause at least one quantum error correction to be applied to a logical qubit.

[0023] In one exemplary embodiment, causing at least one quantum error correction to be applied to a logical qubit comprises at least one of: (a) updating a classical qubit registry corresponding to the logical qubit based on at least one quantum error correction; (b) causing a physical correction to be performed on one or more data qubits of the logical qubit; or (c) causing at least one logical operation, which is to be at least partially performed on one or more data qubits of the logical qubit, to be modified based at least in part on at least one quantum error correction.

[0024] In one exemplary embodiment, the implementation of at least one syndrome circuit segment comprises the implementation of a plurality of syndrome circuit segments.

[0025] In one exemplary embodiment, at least one two physical qubit interaction of a series of at least two physical qubit interactions includes an interaction of at least one ancillary qubit with at least one data qubit of a plurality of data qubits of a logical qubit.

[0026] In one exemplary embodiment, the logical qubit is one of a plurality of logical qubits, and at least one ancillary qubit is used to implement a syndrome circuit segment for two or more of the plurality of logical qubits.

[0027] In one exemplary embodiment, updating the classical memory based on at least one of a syndrome or at least one quantum error correction comprises tracking the syndrome of the logical qubit in the classical memory.

[0028] In one exemplary embodiment, during the implementation of at least one syndrome circuit segment, the coherence of a plurality of data qubits of a logical qubit is maintained.

[0029] In one exemplary embodiment, the controller causes the implementation of a state preparation circuit segment to prepare the state of each ancillary qubit before causing the implementation of at least one syndrome circuit segment, uses each ancillary qubit to perform a series of at least two physical qubit interactions, and is configured such that each ancillary qubit is read after the implementation of the series of at least two physical qubit interactions, and the syndrome of the logical qubit is generated based at least in part on the result of the read of each ancillary qubit.

[0030] In another embodiment, a controller is provided which is configured to control the operation of a quantum processor and to trigger the implementation of fault-tolerant quantum error correction using the physical transport of qubits. In one exemplary embodiment, the controller is configured to communicate with a classical computing entity. In one exemplary embodiment, the controller is configured (and / or programmed) to trigger the implementation of at least one syndrome circuit segment to generate a syndrome of logic qubits. The at least one syndrome circuit segment is implemented by triggering the implementation of a set of at least two physical qubit interactions, at least in part. The logic qubit comprises a plurality of data qubits logically organized in real projection plane topology. The set of at least two physical qubit interactions is determined at least in part on one or more stabilizers determined based on the real projection plane topology of the logic qubits. The controller is further configured to determine at least one quantum error correction, at least in part on the syndrome of logic qubits, so that a classical memory of at least one of the controller or classical computing entities is updated based on the syndrome or at least one of the at least one quantum error correction.

[0031] In one exemplary embodiment, each of one or more ballasts comprises four instances of the same operator, and each of the four instances of the same operator acts on different data qubits of a plurality of data qubits.

[0032] In one exemplary embodiment, at least one of one or more ballasts comprises two instances of a first operator and two instances of a second operator, where each instance of the first operator and each instance of the second operator acts on different data qubits of a plurality of data qubits.

[0033] In one exemplary embodiment, each of the one or more ballasts is a ballast with a weight of 4.

[0034] In one exemplary embodiment, the controller is further configured (and / or programmed) to apply at least one quantum error correction to a logical qubit.

[0035] In one exemplary embodiment, ensuring that at least one quantum error correction is applied to a logical qubit comprises at least one of the following: (a) updating a classical qubit registry corresponding to the logical qubit based on at least one quantum error correction; (b) causing the implementation of a physical correction to one or more data qubits of the logical qubit; or (c) ensuring that a logical operation which will be implemented at least in part on one or more data qubits of the logical qubit is modified at least in part based on at least one quantum error correction.

[0036] In one exemplary embodiment, the implementation of at least one syndrome circuit segment comprises the implementation of multiple syndrome circuit segments.

[0037] In one exemplary embodiment, at least one interaction of at least two physical qubits among a series of interactions of at least two physical qubits includes an interaction of at least one auxiliary qubit with at least one data qubit among a plurality of data qubits of a logical qubit.

[0038] In one exemplary embodiment, the logic qubit is one of a plurality of logic qubits, and at least one auxiliary qubit is used to implement a syndrome circuit segment for two or more of the plurality of logic qubits.

[0039] In one exemplary embodiment, updating a classical memory based on a syndrome or at least one of at least one quantum error correction comprises tracking a syndrome of logical qubits in the classical memory.

[0040] In one exemplary embodiment, the coherence of multiple data qubits of a logic qubit is maintained during the implementation of at least one syndrome circuit segment.

[0041] In one exemplary embodiment, the controller is further configured (and / or programmed) to trigger the execution of a state preparation circuit segment to prepare the state of each auxiliary qubit before triggering the execution of at least one syndrome circuit segment, to perform a series of at least two physical qubit interactions using each auxiliary qubit, and to read each auxiliary qubit after the execution of the series of at least two physical qubit interactions, and the logic qubit syndrome is generated based at least in part on the results of the reading of each auxiliary qubit.

[0042] In another embodiment, a computer program product is provided comprising at least one non-temporary computer-readable medium. The at least one computer-readable memory stores computer-executable instructions, which, when executed by a controller processing element, are configured to cause the controller to control the operation of a quantum processor and trigger the implementation of quantum error correction. In one exemplary embodiment, the computer-executable instructions, when executed by a controller processing element, are configured to cause the controller to trigger the implementation of at least one syndrome circuit segment to generate a logic qubit syndrome. The at least one syndrome circuit segment is implemented, at least in part, by triggering the implementation of a set of at least two physical qubit interactions. The logic qubit comprises a plurality of data qubits logically organized in real projection plane topology. The set of at least two physical qubit interactions is determined, at least in part, on one or more stabilizers determined based on the real projection plane topology of the logic qubits. The controller is further configured to determine at least one quantum error correction based at least in part on the logical qubit syndrome, and to update the classical memory of at least one of the controller or classical computing entities based on the syndrome or at least one of the quantum error corrections.

[0043] In one exemplary embodiment, each ballast of one or more ballasts comprises four instances of the same operator, and each of the four instances of the same operator acts on different data qubits of a plurality of data qubits.

[0044] In one exemplary embodiment, at least one of one or more ballasts comprises two instances of a first operator and two instances of a second operator, where each instance of the first operator and each instance of the second operator acts on different data qubits of a plurality of data qubits.

[0045] In one exemplary embodiment, each of the one or more ballasts is a ballast with a weight of 4.

[0046] In one exemplary embodiment, the computer executable instruction is further configured, when executed by the controller's processing element, to cause the controller to perform at least one quantum error correction on a logical qubit.

[0047] In one exemplary embodiment, ensuring that at least one quantum error correction is applied to a logical qubit comprises at least one of the following: (a) updating a classical qubit registry corresponding to the logical qubit based on at least one quantum error correction; (b) causing the implementation of a physical correction to one or more data qubits of the logical qubit; or (c) ensuring that a logical operation which will be implemented at least in part on one or more data qubits of the logical qubit is modified at least in part based on at least one quantum error correction.

[0048] In one exemplary embodiment, the implementation of at least one syndrome circuit segment comprises the implementation of multiple syndrome circuit segments.

[0049] In one exemplary embodiment, at least one interaction of at least two physical qubits among a series of interactions of at least two physical qubits includes an interaction of at least one auxiliary qubit with at least one data qubit among a plurality of data qubits of a logical qubit.

[0050] In one exemplary embodiment, the logic qubit is one of a plurality of logic qubits, and at least one auxiliary qubit is used to implement a syndrome circuit segment for two or more of the plurality of logic qubits.

[0051] In one exemplary embodiment, updating a classical memory based on a syndrome or at least one of at least one quantum error correction comprises tracking a syndrome of logical qubits in the classical memory.

[0052] In one exemplary embodiment, the coherence of multiple data qubits of a logic qubit is maintained during the implementation of at least one syndrome circuit segment.

[0053] In one exemplary embodiment, a computer executable instruction, when executed by a controller processing element, is configured to cause the controller to perform a state preparation circuit segment to prepare the state of each auxiliary qubit before causing the execution of at least one syndrome circuit segment, to perform a series of at least two physical qubit interactions using each auxiliary qubit, and to allow each auxiliary qubit to be read after the execution of the series of at least two physical qubit interactions, and the logic qubit syndrome is generated based at least in part on the results of the reading of each auxiliary qubit.

[0054] The present invention has been described in general terms as described above, and the attached drawings are referenced here, which are not necessarily drawn to scale. [Brief explanation of the drawing]

[0055] [Figure 1] This is a schematic diagram showing an exemplary logic qubit having a real projective plane topology that is logically organized to provide a QEC code for distance 3 and can be used to define a stabilizer in one exemplary embodiment. [Figure 1A] This is a schematic diagram showing the topology of the real projective plane. [Figure 2] This is a schematic diagram showing an exemplary logic qubit having a real projective plane topology that is logically organized to provide a QEC code for distance 5 and can be used to define a stabilizer in an exemplary embodiment. [Figure 3] This is a schematic diagram showing the real projective plane topology of an exemplary logical qubit logically organized to provide a QEC code having a distance p (where p is a positive integer), according to one exemplary embodiment. [Figure 4] This is a schematic diagram showing another logic qubit having a real projective plane topology, logically organized to provide an exemplary QEC code for distance 3, which can be used to define a stabilizer in a certain exemplary embodiment. [Figure 5] This is a schematic diagram illustrating an exemplary quantum computing system according to one exemplary embodiment. [Figure 6] This flowchart shows various processes, operations, and / or procedures performed by a quantum computing system, such as the quantum computing system in Figure 1, to implement a quantum circuit, according to various embodiments. [Figure 7] This is a schematic diagram of an exemplary controller configured to control the operation of a confinement device according to one exemplary embodiment. [Figure 8] This flowchart shows various processes, operations, and / or procedures performed by a controller, such as the controller in Figure 7, to determine the syndrome of logical qubits, according to various embodiments. [Figure 9] This is a schematic diagram of an exemplary computational entity that may be used according to an exemplary embodiment. [Modes for carrying out the invention]

[0056] The present invention will be described more fully later with respect to the accompanying drawings, which illustrate some, but not all, embodiments of the invention. In fact, the invention may be embodied in many different forms and should not be construed as being limited to the embodiments specified herein. Rather, these embodiments are provided to satisfy the legal requirements to which this disclosure is applicable. The term "or" (also written as " / ") is used herein in both an alternative and conjunctive sense unless otherwise indicated. The terms "illustrative" and "exemplary" are used as examples without indicating a level of quality. The terms "generally," "substantially," and "approximately" mean within processing and / or manufacturing tolerances and / or within the user's measurement capabilities, unless otherwise indicated. Similar numbers refer to similar elements as a whole.

[0057] Exemplary embodiments provide methods, systems, apparatus, computer program products, controllers configured to control the operation of a quantum processor, etc., for performing quantum error correction (QEC), where the stabilizers used in the implementation of the syndrome circuit segment are defined based on surface QEC codes having a real projection plane topology. For example, in various embodiments, at least one syndrome circuit segment is implemented to determine or generate at least one syndrome of a logic qubit. The logic operations implemented as part of the syndrome circuit segment are determined at least in part on a stabilizer (also referred to herein as a stabilizer operator) determined based on the real projection plane topology of the logic qubit.

[0058] In various embodiments, a quantum processor comprises a plurality of data qubits that are logically divided, clustered, and / or organized into a plurality of logic qubits. Each of the plurality of logic qubits is formed from each plurality of data qubits that are logically organized based on the real projection plane topology. The term “logically organized” is used herein to indicate that the operational relationships between the plurality of data qubits of a logic qubit are determined based on the real projection plane topology and / or configured to conform to the real projection plane topology. In at least one embodiment, the data qubits among the plurality of data qubits forming a logic qubit can move and / or transport independently of each other. Thus, the term “logically organized” is used herein to clarify that the plurality of data qubits forming a logic qubit do not need to be physically organized based on the real projection plane topology. In particular, the interactions between the data qubits of a logic qubit used to determine a stabilizer are managed, organized, and / or determined based on the real projection plane topology. In various embodiments, the mobility of the data qubits allows for any physical rearrangement of the data qubits so that a stabilizer can be determined (e.g., so that appropriate qubit interactions can be performed).

[0059] For example, in various embodiments, each logic qubit comprises a plurality of physical data qubits logically organized based on a real projection plane topology. The topology of the plurality of data qubits defines and / or determines, at least in part, the stabilizer of the logic qubit. The stabilizer acts on the logic qubit (for example, on the data qubits of the logic qubit in the manner defined by the topology of the logic qubit) and is used to extract a syndrome from the logic qubit. In various embodiments, the syndrome is used to identify which error occurred and / or that an error occurred, so that error correction can be determined and / or applied, and / or the effects of the error can be mitigated and / or reduced.

[0060] In various embodiments, the implementation of a quantum program, algorithm, or circuit (referred to herein as a quantum circuit) comprises the implementation of one or more quantum error correction cycles. For example, quantum error correction cycles may be implemented at various points before, during, and / or after the implementation of the quantum circuit.

[0061] During a quantum error correction cycle, one or more syndrome circuit segments are implemented to generate, determine, and / or extract syndromes from one or more logic qubits used in the implementation of the quantum circuit. In various embodiments, the logic qubit comprises a plurality of data qubits. The plurality of data qubits are logically organized based on real projection plane topology to form binary logic elements of a quantum processor (similar to bits in a classical semiconductor-based processor). In various embodiments, the quantum error correction cycle may further include determining one or more quantum error corrections based on the generated, determined, and / or extracted syndromes, and applying one or more quantum error corrections to each logic qubit.

[0062] In various embodiments, at least one syndrome circuit segment is implemented to generate a syndrome for each logic qubit. The at least one syndrome circuit segment is implemented, at least in part, by inducing the implementation of a series of interactions of at least two physical qubits (e.g., a two-qubit gate). The series of interactions of at least two physical qubits is determined based on the stabilizer of the logic qubit. At least one quantum error correction is determined and applied to the logic qubit, at least in part based on the syndrome of the logic qubit.

[0063] In various embodiments, quantum error correction comprises software correction, which is applied by tracking quantum errors experienced by logical qubits in a classical qubit registry corresponding to the logical qubits (for example, stored in a classical semiconductor-based memory of a controller configured to control the operation of a quantum processor), physically applying corrections to one or more data qubits of the logical qubit, and / or modifying logical operations performed on one or more data qubits of the logical qubit based at least in part on the determined quantum error correction.

[0064] In various embodiments, logic qubits are logically organized using real projective plane topology such that the logic relationships between the data qubits of a logic qubit are determined based on the real projective plane topology of the logic qubit. For example, the logic relationships between the data qubits of a logic qubit determine how gates are performed on the logic qubit, the stabilizers of the logic qubit, and how the values ​​of the logic qubit (e.g., |0> or |1>) are read and / or determined. For example, the logic relationships between the data qubits of a logic qubit determine which operations are performed on which data qubits of the logic qubit, which then result in a particular logic gate or operation being performed on the logic qubit.

[0065] The real projective plane is an unoriented two-dimensional manifold. Therefore, the real projective plane is one-sided. The real projective plane is a closed topological manifold obtained by adding a line at infinity and projecting a point on a plane from a fixed point that is not on the plane. The real projective plane can be described topologically by a construction based on a Möbius strip, and the projective plane can be obtained if the (single) edge of the Möbius strip can be glued in the correct direction (this is impossible in three-dimensional space where the surface does not intersect itself). Similarly, the projective plane can be obtained by gluing a disk along the boundary of a Möbius strip. Topologically, it has the Euler property 1, and is therefore a semi-group of 1 (unoriented group, Euler group).

[0066] For example, Figure 1A provides a diagram of the topology of the real projective plane, where opposite sides of square 6 are joined to each other with a half-twist, the portion of the square 6's edge corresponding to the tip of the dashed arrow is joined to each other, the portion of the square's edge corresponding to the tail of the dashed arrow is joined to each other, the portion of the square's edge corresponding to the tip of the solid arrow is joined to each other, and the portion of the square's edge corresponding to the tail of the solid arrow is joined to each other.

[0067] By logically organizing the data qubits of logical qubits based on real projection plane topology, the number of possible error combinations that cannot be detected, identified, and / or corrected is reduced compared to conventional QEC techniques.

[0068] Complex quantum computations require levels of precision unattainable by conventional quantum computers, for example, due to imperfect control and noise in gate operations between data qubits. Proposed methods for quantum error correction involve syndrome extraction, which generally includes the interaction of auxiliary qubits with data qubits. However, if not implemented carefully, such interactions between auxiliary and data qubits can catastrophically propagate errors, leading to logic errors that would otherwise be correctable considering the initial weights. Thus, there are technical problems regarding how to perform quantum computations with a level of precision sufficient to perform complex calculations. Furthermore, there are technical problems regarding how to extract the information needed to diagnose and correct errors from logic qubits without causing further error propagation.

[0069] Various embodiments provide technical solutions to such technical problems. For example, various embodiments provide implementations of quantum error correction using the interaction of a set of at least two qubits, determined based on a stabilizer defined based on a real projective plane topology. In particular, the topology of the stabilizer used for syndrome determination and / or extraction, as well as the topology of the logic qubits, determines the errors or combinations of errors to which the syndrome is sensitive. By organizing the data qubits of the logic qubits using a real projective plane topology, the number of possible error combinations that cannot be detected, identified, and / or corrected is reduced compared to conventional QEC techniques. Thus, more errors can be detected and corrected, computational fidelity is improved, and the number of circuits that need to be rerun due to error diffusion is reduced. Thus, various embodiments result in improvements over conventional quantum error correction methods.

[0070] Exemplary logic qubit and stabilizer topology Figure 1 shows an example of a logic qubit 100 at a distance of 3. The logic qubit comprises multiple data qubits 5 logically organized based on real projective plane topology. In the case of logic qubit 100, the multiple data qubits 5 contain 9 data qubits. In Figure 1, each data qubit of the multiple data qubits 5 is represented by a labeled circle, where circles with the same label point to the same data qubit. For example, each circle labeled 9 points to the same 9th data qubit. Therefore, by connecting the boundaries of the shown logic qubit 100 such that each of the circles with the same label overlaps (for example, to form a single point), we can see that the topology of the logic qubit is the topology of the real projective plane.

[0071] As can be seen by comparing Figure 1 and Figure 1A, the topology of logical qubit 100 is the topology of the real projective plane in which opposing edges are "glued" to each other with a half-twist.

[0072] Figure 1 also shows the stabilizers 105 (e.g., 105A-105H) for the logical qubit 100, where the shaded squares represent the Z stabilizer with weight 4, and the dotted squares represent the X stabilizer with weight 4. The stabilizers 105A-105H form a set of stabilizers for the logical qubit 100. For example, stabilizer 105A is the operator

[0073]

number

[0074] And in the formula,

[0075]

number

[0076] is the Pauli Z operator acting on the i-th qubit. Similarly, the ballast 105B is the operator

[0077]

number

[0078] And in the formula,

[0079]

number

[0080] is the Pauli X operator acting on the i-th qubit. Each of the ballasts 105C to 105H comprises four Pauli Z operators or Pauli X operators, respectively, acting on each data qubit indicated by labeled circles at the vertices / corners of the respective squares representing ballast 105. In one exemplary embodiment, a shaded square represents an X ballast with weight 4 (e.g., a ballast operator comprising four Pauli X operators), and a dotted square represents a Z ballast with weight 4 (e.g., a ballast operator comprising four Pauli Z operators). In one exemplary embodiment, the set of ballasts may include a Y ballast (e.g., a ballast containing a Pauli Y operator) instead of either an X ballast or a Z ballast.

[0081] The ballasts 105A to 105H form a set of ballasts for 100 logical qubits. In various embodiments, each ballast 105A to 105H in the set of 100 logical qubit ballasts is a ballast with a weight of 4. The weight of a ballast indicates the number of operators in the ballast. For example, a ballast with a weight of 4 contains four operators (e.g., four Pauli Z operators, four Pauli X operators, or combinations of Pauli X and Pauli Z operators containing a total of four operators).

[0082] In one exemplary embodiment, the logic qubit 100 is partially analogous to a logic qubit in a toroidal topology surface code. However, the boundary of the logic qubit 100 is redefined for the toroidal topology surface code. This boundary redefinition makes the stabilizer more sensitive to various errors and / or combinations of errors. In general, the stabilizer S is an operator configured to act on the wave function |ψ> of the logic qubit such that S|ψ>=|ψ>. Thus, <ψ|S|ψ>=1. When an error or combination of errors E occurs that is not commutative with the stabilizer S or is anticommutative (ES=-SE), the wave function of the logic qubit evolves into the wave function E|ψ>, and the action of the stabilizer becomes <ψ|ESE|ψ>=-1. Thus, evaluation of the stabilizer 105 allows for the identification and / or determination of when an error occurs for an error E that is not commutative with and / or anticommutative with at least one stabilizer of the logic qubit. The use of quantum error decoders allows for the identification of specific errors, specific combinations of errors, and / or the effects of errors, so that errors can be corrected and / or their effects can be mitigated and / or minimized.

[0083] Logical qubit 100 is a Calderbank-Shor-Steane (CSS) qubit. Generally, CSS qubits are defined such that each stabilizer contains only one type of Pauli operator (for example, stabilizer 105A contains only instances of the Pauli Z operator, stabilizer 105B contains only instances of the Pauli Z operator, and so on).

[0084] Figure 2 shows another logic qubit 200, which is a logic qubit at distance 5. The multiple data qubits of logic qubit 200 are logically organized based on real projective plane topology. The multiple qubits 5 used to form logic qubit 200 contain 25 data qubits. Logic qubit 200 is a CSS qubit. Logic qubit 200 defines a set of stabilizers 205 used to define the interaction of a set of at least two qubits used to extract syndromes from logic qubit 200 in various embodiments.

[0085] Figure 3 shows a generalized distance p logic qubit 300, where p is a positive integer, and the multiple logic qubits are logically organized based on real projective plane topology. The data qubit in the 0th row and jth column (1 ≤ j ≤ p) of logic qubit 300 is data qubit number p 2 -(j-1). The data qubits in the i-th row (1≦i≦p) and j-th column (1≦j≦p) of logical qubit 300 have data qubit number (i-1)p+j. The data qubits in the i-th row and (p+1) column of logical qubit 300 have data qubit number p 2 -(ip-1).

[0086] In particular, the distance p can be even or odd. Rotational toric codes can only use even distances. Thus, various embodiments offer greater flexibility in the size of the logical qubit, providing the technical advantage of being able to adjust the size of the logical qubit based on the hardware of the quantum processor (size, transport speed, topology, etc.).

[0087] The ballast for logical qubit 300, although not shown in the figure, is determined in a similar manner to that described above for logical qubit 100. For example, for each index i, j pair for 1 ≤ j ≤ p and 0 ≤ i ≤ p-1 (except when i=0 and j=p), squares are formed between the data qubits in row i and column j, row i+1 and column j, row i and column j+1, and row i+1 and column j+1. Each ballast is then assigned a type of ballast (e.g., X ballast or Z ballast) such that the squares sharing side 110 are of different types. For example, referring to Figure 1, the square representing ballast 105E shares side 110 with the square representing ballast 105A, and ballast 105A is of a different type than ballast 105E. For example, the diagonal and dotted square patterns of logical qubits 100 and 200 form a checkerboard pattern.

[0088] Figure 4 shows another exemplary logic qubit 400 comprising multiple data qubits 5 logically organized based on real projection plane topology. The logic qubit 400 is a distance 3 logic qubit containing 9 data qubits. The logic qubit 400 is a non-CSS qubit. For example, ballasts 405A, 405B, 405C, and 405D are the same as ballasts 105A, 105B, 105C, and 105D. However, the ballasts along the boundary of logic qubit 400 (e.g., 405E, 405F, 405G, 405H) are different from the ballasts along the boundary of logic qubit 100 (e.g., 105E, 105F, 105G, 105H). In particular, boundary ballasts 405E, 405F, 405G, and 405H are defined as a combination of the X ballast and the Z ballast. For example, boundary ballast 405E is, in one exemplary embodiment,

[0089]

number

[0090] That is the case.

[0091] In non-CSS logical qubit 400, the boundary itself does not realize the topological twist; rather, the combined or mixed boundary stabilizers 405E, 405F, 405G, and 405H realize the topological twist of the logical qubit 400. For example, the boundary of the logical qubit 400 corresponds to a torus topology. However, by mixing stabilizers along the boundary, a logical qubit 400 is obtained with data qubits 5 logically organized based on a real projective plane topology.

[0092] As is understood, the non-CSS logical qubit 400 is shown with distance p=3, but in various embodiments, non-CSS logical qubits with distance p greater than 3 are used.

[0093] The logical qubits 100, 200, 300, and 400 illustrate examples of logical qubits formed by organizing each of the multiple data qubits 5 of the logical qubit based on the real projective plane topology and defining and / or determining the stabilizer of the logical qubit based on the topology of the logical qubit. Various other logical qubits are logically organized based on the real projective plane topology in various other embodiments, and each set of stabilizers for each logical qubit is defined thereon. For example, various logical qubits may contain various numbers of data qubits, which may be at different distances, etc.

[0094] Exemplary quantum computing systems QEC technology can be used in various types of quantum processors, including quantum charge-coupled device (QCCD) based quantum processors, Josephson junction based quantum processors, superconducting based quantum processors, photonic based quantum processors, quantum object spin-based quantum processors, and semiconductor quantum dot based quantum processors. Figure 5 shows one example of a quantum computing system 500 configured to perform quantum error correction. As can be understood, various embodiments relate to various types of quantum computing systems. In various embodiments, the quantum processor comprises a plurality of physical qubits. The physical qubits include data qubits logically organized into logic qubits and auxiliary qubits used to mediate and / or perform interactions of at least two qubits used during syndrome extraction.

[0095] In some embodiments, the physical positions of at least some of the physical qubits of the quantum processor are fixed. In some embodiments, the physical positions of the data qubits of the quantum processor are not fixed (for example, the physical qubit registers are reconfigurable). For example, various embodiments relate to quantum computing systems that use ions, neutral atoms, quantum dots, quantum particles, etc., as qubits.

[0096] For example, Figure 5 shows an exemplary quantum computing system 500 comprising a classical computing entity 10 and a quantum computer 510. The quantum computer comprises a controller 30 and a quantum processor 515. In the illustrated embodiment, the quantum processor 515 is a quantum charge-coupled device (QCCD) based quantum processor. However, various embodiments of the quantum computing system 500 may include various types of quantum processors. The controller 30 and the classical computing entity 10 communicate with each other via direct wired and / or wireless connections, and / or via one or more wired and / or wireless networks 20.

[0097] In the embodiments shown, the (QCCD-based) quantum processor 515 includes a confinement device 520 used to confine manipulable objects so that various functions can be performed on the manipulable objects. For example, in various embodiments, the confinement device 520 is an ion trap. For example, in various embodiments, the manipulable objects are ions, multipolar molecules and / or charged molecules, charged particles, quantum objects, etc. In various embodiments, the manipulable objects are used as physical qubits of the quantum processor 515 (e.g., data qubits and auxiliary qubits). Various functions can be performed on the manipulable objects, such as state preparation, execution of logic gates, state reading / determination, cooling, and transport between different locations of the confinement device 520. In various embodiments, the logic gates performed on the manipulable objects include transversal gates. A transversal gate is a gate on which an error correction code can achieve a conversion to a logic qubit by applying the gate to each of the data qubits of the logic qubit. For example, in a 5-qubit code, if a logical Hadamard gate can be achieved for a logical qubit by applying Hadamard to each of the five data qubits of the logical qubit, then that Hadamard gate is a transversal gate. In various embodiments, logic gates that are not transversal gates are used. For example, logic gates can be implemented using lattice surgery and / or other logic gate techniques.

[0098] In various embodiments, the manipulable object comprises an auxiliary qubit and a plurality of data qubits that are logically divided and / or organized into one or more logic qubits. In various embodiments, the auxiliary qubit is used to examine the data qubits and / or logic qubits to determine one or more syndromes of them. For example, the auxiliary qubit is used to examine the data qubits and / or logic qubits such that the coherence of each data qubit of each logic qubit is maintained during the implementation of the syndrome circuit segment. This allows for the generation, determination, and / or tracking of syndromes of logic qubits without breaking the coherence of each data qubit of the logic qubit.

[0099] In various embodiments, the quantum system controller 30 is configured to control the quantum processor 515, including programming and other operations. For example, the quantum processor 515 includes a confinement device 520 configured to confine a plurality of manipulable objects. The quantum system controller 30 is configured to control the operation of the confinement device 520. In one exemplary embodiment, the quantum processor 515 includes a plurality of qubits (e.g., physical data qubits organized into logical qubits, auxiliary qubits, etc.). In various embodiments, the data qubits and auxiliary qubits are each embodied by the respective manipulable objects of the plurality of manipulable objects confined by the confinement device 520. In various embodiments, the quantum computer 510 includes, or communicates with, a database and / or programs (not shown) of quantum error decoders and / or quantum error correction decision applications, programs, etc. (e.g., stored by and / or running on the classical computing entity 10). For example, the database may be stored by one or more classical computing entities 10 communicating with the controller 30 via one or more wired and / or wireless networks 20, and / or in memory local to the controller 30.

[0100] In various embodiments, the quantum processor 515 includes means for controlling the development of quantum states of qubits. For example, in the exemplary embodiment shown, the quantum processor 515 comprises a cryostat and / or vacuum chamber 40 surrounding a confinement device 520 (e.g., an ion trap), one or more manipulators 60, one or more voltage sources 50, and / or one or more optical collection systems 70. For example, the cryostat and / or vacuum chamber 40 may be a chamber whose temperature and / or pressure are controlled. In one exemplary embodiment, one or more manipulators 60 may comprise one or more lasers (e.g., optical lasers, microwave sources, etc.). In various embodiments, one or more manipulators 60 are configured to manipulate and / or induce the development of controlled quantum states of one or more manipulable objects within the confinement device 520. In various embodiments, the manipulable objects within the confinement device 520 (e.g., ions trapped in an ion trap) behave as data qubits and / or auxiliary qubits of the quantum processor 515 of the quantum computer 510. For example, in an exemplary embodiment in which one or more operating sources 60 comprises one or more lasers, the lasers may provide one or more laser beams to an operable object confined by a cryostat and / or confinement device 520 in a vacuum chamber 40. For example, the operating source 60 may generate and / or provide laser beams configured to ionize the operable object, initialize the operable object in a defined two-state qubit space of a quantum processor, perform gates on one or more qubits of the quantum processor (e.g., logic gates on logic qubits and / or physical gates on physical qubits), read the quantum states of one or more qubits of the quantum processor, and so on.

[0101] In various embodiments, the quantum processor 515 and / or quantum computer 510 includes an optical collection system 70 configured to collect and / or detect photons generated by qubits (e.g., during a read procedure). The optical collection system 70 may comprise one or more optical elements (e.g., lenses, mirrors, waveguides, optical fiber cables, etc.) and one or more photodetectors. In various embodiments, the photodetectors may be photodiodes, photomultiplier tubes, charge-coupled device (CCD) sensors, complementary metal-oxide-semiconductor (CMOS) sensors, micro-electromechanical system (MEMS) sensors, and / or other photodetectors that sense light of the expected fluorescence wavelength of the data qubits and / or auxiliary qubits of the quantum computer 510. In various embodiments, the detectors may be in electronic communication with the quantum system controller 30 via one or more A / D converters 725 (see Figure 7), etc.

[0102] In various embodiments, the quantum processor 515 and / or quantum computer 510 comprises one or more voltage sources 50. For example, the voltage source 50 may comprise a plurality of voltage drivers and / or voltage sources, and / or at least one RF driver and / or voltage source. For example, in various embodiments, the voltage source 50 includes a plurality of arbitrary waveform generators (AWGs). In one exemplary embodiment, the voltage source 50 may be electrically coupled to a corresponding potential generating element (e.g., an electrode) of the confinement device 520.

[0103] In various embodiments, the classical computing entity 10 is configured to allow a user to provide input to the quantum computer 510 (for example, through the user interface of the computing entity 10) and to receive, view, and so on, outputs from the quantum computer 510. In various embodiments, the classical computing entity 10 is configured to perform one or more classical computations in real time or near real time in conjunction with the implementation of a quantum circuit by the quantum computer 510. For example, during the implementation of the quantum circuit, the controller 30 may provide one or more syndromes of one or more logic qubits, and the classical computing entity 10 determines and provides one or more corresponding quantum error corrections so that the controller 30 can perform quantum error correction in real time while the quantum circuit is being implemented.

[0104] The classical computing entity 10 performs classical computing operations using semiconductor-based hardware and is therefore referred to herein as “classical.” The classical computing entity 10 may communicate with the quantum system controller 30 of the quantum computer 510 via one or more wired or wireless networks 20, and / or via direct wired and / or direct wireless communications. In one exemplary embodiment, the classical computing entity 10 may perform conversions, configurations, and formats of information / data, quantum computing algorithms and / or circuits, etc., into a computational language, executable instructions, command sets, etc., that the quantum system controller 30 can understand and / or implement. For example, the controller 30 is configured to generate machine code-level commands that, when executed by the appropriate components of the quantum computer 510, are configured to trigger the implementation of quantum circuits by the quantum computer 510. In various embodiments, the classical computing entity 10 may provide quantum computing algorithms and / or circuits in a computational language that the quantum system controller 30 resolves into individual or set operations and / or machine code-level commands.

[0105] In various embodiments, the classical computing entity 10 and the controller 30 are coupled in a low-latency manner for communication. For example, the controller 30 may be configured to invoke classical operations, programs, modules, functions, etc., operating on the classical computing entity 10 (e.g., using a Foreign Function Interface (FFI), an Application Programming Interface (API), or other suitable interface). The results of these exchanges between the controller 30 and the classical computing entity 10 may be used to dynamically modify and / or act upon quantum circuits implemented by the quantum processor 515, in real time, in the circuit, etc. Thus, in one exemplary embodiment, the latency of communication between the classical computing entity 10 and the controller 30 is minimized.

[0106] In various embodiments, the quantum system controller 30 is configured to control a voltage source 50, a cryostat system and / or vacuum system that controls the temperature and pressure within the cryostat and / or vacuum chamber 40, an operating source 60, and / or other systems that control various environmental conditions (e.g., temperature, pressure, etc.) located within the cryostat and / or vacuum chamber 40 and / or configured to operate and / or induce a controlled deployment of the quantum state of one or more operable objects within the confinement device 520. For example, the quantum system controller 30 may induce a controlled deployment of the quantum state of one or more operable objects within the confinement device 520 in order to execute a quantum circuit and / or algorithm. For example, the quantum system controller 30 may, in some cases, induce the execution of a read procedure with coherent shelving as part of executing a quantum circuit and / or algorithm. In addition, the quantum system controller 30 is configured to communicate and / or receive input data from the optical collection system 70, corresponding to the reading of the quantum state of the physical data qubits and / or auxiliary qubits of the quantum computer 510. In various embodiments, the manipulable objects confined within the confinement device 520 are used as data qubits and / or auxiliary qubits of the quantum computer 510. In various embodiments, the data qubits are organized into logic qubits, and the auxiliary qubits are used to non-invasively examine the data qubits and / or logic qubits.

[0107] In various embodiments, the implementation of a quantum circuit comprises the implementation of one or more quantum error correction cycles. During a quantum error correction cycle, one or more syndrome circuit segments are implemented to generate and / or extract syndromes from one or more logic qubits used in the implementation of the quantum circuit. The syndrome circuit segments are implemented, at least in part, by inducing the implementation of a series of at least two physical qubit interactions, which are determined at least in part on a set of logic qubit stabilizers. The at least two physical qubit interactions between each auxiliary qubit and one or more data qubits of the logic qubits ensure that information about one or more data qubits of the logic qubit is encoded by the auxiliary qubit non-invasively (e.g., without breaking the coherence of one or more data qubits). Thus, the state of the auxiliary qubits can be used to determine and / or extract syndromes of logic qubits.

[0108] Exemplary Operation of a Quantum Computing System Figure 6 is a flowchart illustrating various processes, operations, and / or procedures performed by a quantum computing system, such as the quantum computing system 500, to implement a quantum circuit according to various embodiments. For example, the quantum circuit may be acquired by the controller 30 (e.g., accessed from memory 710, received via communication interface 720, etc. (see Figure 7)), compiled, etc. The controller 30 can then cause the quantum computing system 500 to start executing the quantum circuit (optionally via user input received via classical computing entity 10 and / or via the user interface of the controller 30).

[0109] Starting in step / operation 602, the physical qubit state is prepared. Hereinafter, the term "physical qubit" refers to a qubit embodied by each manipulable object. Each physical qubit is either a data qubit or an auxiliary qubit. For example, data qubits and auxiliary qubits are examples of physical qubits. One or more logical qubits each comprise a plurality of data qubits logically organized in real projective plane topology, each forming a binary logical element of the quantum processor.

[0110] In various embodiments, the controller 30 controls the operation of the voltage source 50 to generate and provide voltage signals that transport physical qubits into and out of respective interaction zones defined by the quantum processor 515 (for example, locations in the confinement device 520 configured to intersect the physical qubits with the respective operation signals so that the physical qubits located in the interaction zones are affected by the respective operation signals). The controller 30 further controls the operation of one or more operation signals 60 so that the respective operation signals are provided to the respective interaction zones defined by the quantum processor 515 to prepare the respective quantum states of each physical qubit. For example, in various embodiments, state preparation comprises bringing the quantum states of one or more physical qubits to known states in a defined two-state qubit space of the energy structure of each manipulable object.

[0111] In one exemplary embodiment, the state-preparation operation is not fault-tolerant. However, since the quantum information has not yet been encoded into data qubits at this point when the quantum circuit is being implemented (e.g., before the implementation of logic gates on the physical and / or logic qubits on which state-preparation is being performed has begun), the state-preparation operation may be implemented as a circuit segment that iterates until successful, ensuring in real time that the state of each qubit is fault-tolerantly prepared. For example, the execution of a syndrome circuit segment may be used to determine whether the state-preparation operation has been performed successfully.

[0112] In step / operation 604, one or more logic operations are performed on the logic qubits according to at least a portion of the quantum circuit. For example, the controller 30 may cause the quantum processor 515 to perform one or more logic operations on the logic qubits of the quantum processor 515 according to the quantum circuit. For example, in one exemplary embodiment, performing one or more logic operations on a logic qubit comprises, according to the quantum circuit, transporting one or more data qubits of the logic qubit into and / or out of their respective interaction zones, causing interactions between each data qubit of the logic qubit, and performing a single and / or at least two physical qubit gate (e.g., a gate causing interactions between two or more physical qubits) on each data qubit of the logic qubit. In various embodiments, the physical qubits (data qubits and auxiliary qubits) of the quantum computing system 500 may be physically transportable within the confinement device 520 so that any selected pair of physical qubits can be transported to the same interaction zone and interact with each other (e.g., so that two-qubit gates are performed on them). For example, the quantum circuit indicates which gates should be performed on which logic qubits and in what order.

[0113] In various embodiments, the gates implemented are transversal gates. For example, a single-qubit gate is implemented on a logic qubit by implementing a single qubit gate corresponding to each of the multiple data qubits of the logic qubit in series, in parallel, and / or a combination thereof. In various embodiments, a two-qubit gate is implemented on a first logic qubit and a second logic qubit by implementing a two-qubit gate corresponding to each pair of the first data qubit of the first logic qubit and the second data qubit of the second logic qubit.

[0114] In various embodiments, at least one non-transversal gate is used. For example, in one exemplary embodiment, the logic gates of a quantum circuit (e.g., a single logic gate and / or at least two logic qubit gates) and / or one or more gates of a syndrome circuit segment are non-transversal gates. For example, at least one gate (e.g., in a quantum circuit and / or syndrome circuit segment) may be used, in which case a first set of operators is applied to a first subset of the data qubits of the logic qubits and a second (different) set of operators is applied to a second subset of the data qubits of the logic qubits in order to perform the gate. For example, in one exemplary embodiment, a set of physical gates that result in the performance of each logic operation on one or more logic qubits is used to perform the logic operation.

[0115] At various points in time during the implementation of the quantum circuit, a syndrome of one or more logic qubits is generated, determined, and / or extracted. Specifically, in step / operation 606, auxiliary qubits are used to perform syndrome extraction. For example, one or more auxiliary qubits are used to non-invasively examine data qubits and / or logic qubits. For example, the interaction between each auxiliary qubit and one or more data qubits of a logic qubit ensures that information about one or more data qubits of a logic qubit is encoded by the auxiliary qubit non-invasively (e.g., without breaking the coherence of one or more data qubits). The interaction of at least two physical qubits used to generate, determine, and / or extract a syndrome of a logic qubit is determined based on the stabilization of the logic qubit. In other words, the interaction of a set of at least two physical qubits used to generate, determine, and / or extract a syndrome of a logic qubit is defined, at least in part, on the real projective plane topology of the logic qubit.

[0116] In various embodiments, syndrome extraction is performed through the implementation of a syndrome circuit segment. The implementation of the syndrome circuit segment comprises the implementation of a series of interactions of at least two physical qubits. Based on a logic qubit stabilizer, the interactions of at least two physical qubits are performed for each data qubit and auxiliary qubit so that information about the data qubit is encoded into the quantum state of the auxiliary qubit without disturbing the quantum state of the data qubit. In various embodiments, the implementation of the syndrome circuit segment may include performing various forms of lattice surgery and / or interactions between two or more auxiliary qubits.

[0117] In various embodiments, a syndrome circuit segment is implemented using one or more auxiliary qubits and one or more data qubits of a logic qubit to generate, determine, and / or extract a syndrome of a logic qubit. A syndrome circuit is a relatively short circuit (compared to a quantum circuit) configured to encode information about one or more data qubits of a logic qubit into the quantum states of one or more auxiliary qubits, such that the auxiliary qubits can be read to determine a syndrome of a logic qubit having one or more data qubits without destroying the coherence and / or quantum information stored in one or more data qubits of the logic qubit. For example, a syndrome of a logic qubit is configured to provide information about the occurrence, location, and / or type of errors that the logic qubit experiences.

[0118] For example, the implementation of a syndrome circuit includes the implementation of each stabilizer of a logic qubit (e.g., stabilizers 105A-105H of logic qubit 100, or stabilizers 405A-405H of logic qubit 400). For example, the implementation of a first syndrome circuit segment for generating, determining, and / or extracting a syndrome from logic qubit 100 includes stabilizer operator 105A, which involves a Pauli Z operator-based interaction between one or more auxiliary qubits and the first, second, fourth, and fifth data qubits of logic qubit 100.

[0119]

number

[0120] This includes the implementation and / or evaluation of the following. For example, one or more auxiliary qubits and the first, second, fourth, and fifth data qubits may be transported to perform a series of at least two physical qubit interactions (e.g., two-qubit gates) directed by the stabilizer operator 105A. For example, the data qubit and / or confinement device may be configured to enable transport operations such that any pairing of data qubits and / or auxiliary qubits can be performed.

[0121] In various embodiments, one or more quantum error correction cycles may be performed to generate, determine, and / or extract syndromes of one or more logic qubits in a fault-tolerant manner. Fault tolerance, as used herein, refers to a design principle that ensures that a fault does not spread too quickly within the quantum circuit to become an uncorrectable logic error. For example, each quantum error correction cycle includes the implementation of one or more syndrome circuit segments. In various embodiments, generating, determining, and / or extracting syndromes of one or more logic qubits in a fault-tolerant manner comprises performing multiple syndrome extraction cycles for each logic qubit and comparing the results of the multiple syndrome extraction cycles. For example, the fault tolerance of quantum error correction may be a probability-based fault tolerance.

[0122] Continuing with Figure 6, in step / operation 608, one or more quantum error corrections for one or more logic qubits are determined based on the respective syndromes generated, determined, and / or extracted from them. For example, one or more syndromes generated, determined, and / or extracted from logic qubits during a syndrome extraction step (e.g., step / operation 606) are provided to a quantum error decoder operating on the classical computation entity 10 and / or controller 30. The quantum error decoder is a program, application, etc., configured to determine one or more quantum error corrections for logic qubits based on one or more syndromes for the logic qubits. In one exemplary embodiment, the quantum error decoder is embodied as one or more lookup tables. In various embodiments, the quantum error decoder is configured to determine one or more quantum error corrections based on one or more syndromes with respect to receiving one or more syndromes as input.

[0123] In various embodiments and scenarios, the determined quantum error correction is the identity operation. For example, when no error is detected and / or when one or more syndromes for a logical qubit do not indicate the presence of an error, the determined quantum error correction is to make no adjustments or modifications to the qubit. For example, the determined quantum error correction may be to apply a software correction equivalent to applying the identity operator to the classical qubit registry corresponding to the logical qubit.

[0124] In step / operation 610, the classical qubit registry (for example, stored in memory 710 and / or memory 922, 924 (see Figure 9)) is updated based on the extracted syndrome and / or determined quantum error correction. For example, the controller 30 may ensure that the extracted syndrome and / or determined quantum error correction are tracked (for example, in classical memory). In an exemplary embodiment, the syndrome value (and flag, if important) and / or determined quantum error correction are stored for the entire implementation of the quantum circuit. In an exemplary embodiment, the syndrome value and / or determined quantum error correction are tracked for a time frame (for example, for a time frame of a set length of time, or for a time frame of a number of logic gates, until a trigger event is identified and the corresponding error correction is applied, etc.).

[0125] In step / operation 612, one or more quantum error corrections for a logic qubit are applied to the logic qubit. For example, the controller 30 controls the operation of various components of the quantum processor 515 (e.g., voltage source 50, operation source 60, etc.) so that one or more quantum error corrections are applied to the logic qubit. In various embodiments, the quantum error correction includes a software correction applied by tracking quantum errors experienced by the logic qubit in a classical qubit registry corresponding to the logic qubit (stored, for example, in the memory of the controller 30 and / or the memory of the classical computation entity 10), physically applying the correction to one or more data qubits of the logic qubit (e.g., through one or more single-qubit gates and / or two-qubit gates applied to various data qubits of the logic qubit), and / or modifying a logical operation performed on one or more data qubits of the logic qubit based at least in part on the determined quantum error correction.

[0126] In various embodiments, quantum error correction is not applied immediately after it is determined. For example, in various embodiments, the syndrome and quantum error correction are tracked (e.g., in memory 710 and / or memories 922, 924) for a period of time and / or until a triggering event is identified. For example, in one exemplary embodiment, the syndrome and / or quantum error correction are tracked in a classical qubit registry.

[0127] In one exemplary embodiment, a trigger event corresponds to a decision that a logic gate that does not commute with one or more quantum error corrections (e.g., a non-Clifford gate in one exemplary embodiment) will be performed on a logic qubit. For example, it may be decided that a controller is scheduled and / or a quantum circuit is instructed to perform a future execution of a logic gate that does not commute with one or more quantum error corrections (e.g., a non-Clifford gate in one exemplary embodiment) on a logic qubit. Once a trigger event is identified, any necessary physical corrections may be scheduled (before the execution of one or more gates that do not commute with quantum error corrections), and / or the execution of one or more gates that do not commute with quantum error corrections may be scheduled in a modified manner such that the execution of the gates is modified to consider and / or include one or more quantum error corrections.

[0128] As is understood, some quantum error correction involves updating the classical representation of the qubit's Pauli frame and applying it to logical qubits through updates to a classical qubit registry (e.g., software quantum error correction).

[0129] In various embodiments, the process of performing one or more logical operations on one or more logical qubits, performing syndrome generation / determination / extraction, determining quantum error correction, and applying quantum error correction is repeated multiple times until the logical operations of the quantum circuit are complete. For example, completing a quantum circuit may include preparing the physical qubits, performing logical operations, performing quantum error correction cycles, performing logical operations, performing quantum error correction cycles, performing logical operations, performing quantum error correction cycles, ..., and reading the logical qubits after all the logical operations of the quantum circuit have been performed. As is understood, in various embodiments, in an exemplary embodiment, the state preparation of auxiliary qubits is performed between each quantum error correction cycle and / or between the performance of quantum error correction cycles on different logical qubits.

[0130] Therefore, once it is determined that all logical operations of the quantum circuit have been performed, the process proceeds to step / operation 614. In step / operation 614, one or more logic qubits are read according to the quantum circuit. For example, the data qubits of the logic qubits may be transported (in series and / or parallel) to their respective read zones (which may or may not be the same physical parts of the confinement device 520 as the interaction zones). According to the quantum circuit and the reads, each data qubit may be rotated to a desired read frame.

[0131] For example, a read operation may involve an operation signal being incident on a physical qubit (e.g., a data qubit). Depending on which state the physical qubit is in in the two-state qubit space, the physical qubit either fluoresces or does not fluoresce in response to the operation signal incident on it. Based on the fluorescence observed (or not observed) by the optical collection system 70, the quantum state of the physical qubit is determined. Based on the quantum state of the data qubit of the logic qubit, the state of the logic qubit is determined. The state of the logic qubit is then used to determine the result of the quantum circuit.

[0132] In step / operation 616, in various embodiments, the last syndrome is extracted, the last correction is determined, and the last correction is applied. For example, the last syndrome of a logical qubit is determined based on the result of reading the data qubit of the logical qubit. For example, the distribution of the quantum states of the data qubit of the logical qubit provides an indication of the error the logical qubit will experience. The last syndrome of the logical qubit is then used (for example, by a quantum error decoder) to determine the last correction. In various embodiments, the last correction is a software quantum error correction. For example, since the data qubit has been read, the quantum information stored by the data qubit is corrupted. Therefore, a physical correction cannot be applied. For example, in one exemplary embodiment, the last correction is a software correction such as a Pauli frame rotation. The last correction is applied by updating the classical qubit registry corresponding to the logical qubit based on the last correction.

[0133] In step / operation 618, the output of the quantum circuit is provided after each of the last corrections has been applied to each of the logic qubits. For example, the controller 30 may provide the output of the quantum circuit to the classical computing entity 10. In another example, the classical computing entity 10 may provide an indication of the output of the quantum circuit via its user interface (e.g., display 916) and / or transmit an indication of the output of the quantum circuit to another computing entity (e.g., via transmitter 904 and / or network interface 920).

[0134] An exemplary controller for a quantum computing system In various embodiments, the quantum computer 510 comprises a quantum system controller 30 and a quantum controller 515. The quantum system controller 30 is configured to control various components of the quantum processor 515. For example, the controller 30 is configured to control the operation of components of the quantum processor 515 to trigger the implementation of a quantum circuit that includes multiple quantum error correction cycles. For example, various embodiments are configured to perform one or more quantum error corrections on one or more data qubits in real time and / or near real time in response to the occurrence of one or more quantum errors experienced by one or more data qubits, which can be evaluated as a conditional block.

[0135] In various embodiments, the quantum system controller 30 communicates with the optical collection system 70 so as to be configured to receive input data captured and / or generated by the optical collection system 70. The quantum system controller 30 is further configured to perform quantum error correction via software-based correction and / or via the physical application of quantum error correction to one or more qubits (for example, by controlling one or more voltage sources 50 and / or manipulator sources 60). In various embodiments, the quantum system controller 30 is further configured to control the cryostat system and / or vacuum system, controlling the temperature and pressure in the cryostat and / or vacuum chamber 40, the cooling system, and / or other systems that control environmental conditions (e.g., temperature, humidity, pressure, etc.) within the cryostat and / or vacuum chamber 40.

[0136] As shown in Figure 7, in various embodiments, the quantum system controller 30 may comprise various quantum system controller elements, including a processing element 705, a memory 710, a driver controller element 715, a communication interface 720, an analog-to-digital (A / D) converter element 725, and the like. In various embodiments, the quantum system controller 30 is configured to receive input data generated by the optical collection system via the A / D converter 725. In various embodiments, the processing element 705 is configured to operate as described herein. In various embodiments, the quantum system controller 30 may include additional quantum system controller elements configured to perform various functions described herein. In one exemplary embodiment, the controller 30 is similar to the controller described in U.S. Application No. 63 / 235,022 filed August 19, 2021, the entirety of which is incorporated herein by reference.

[0137] In various embodiments, the processing element 705 comprises one or more processing devices, such as a processor, a programmable logic device (CPLD), a microprocessor, a coprocessing entity, an application-specific instruction set processor (ASIP), an integrated circuit, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic array (PLA), a hardware accelerator, and other processing elements and / or circuits. The term "circuit" may refer to an entirely hardware embodiment or a combination of hardware and computer program products. In one exemplary embodiment, the processing element 705 of the quantum system controller 30 comprises and / or communicates with a clock.

[0138] In various embodiments, the memory 710 includes non-temporary memory such as volatile and / or non-volatile memory storage, such as one or more of the following: hard disk, ROM, PROM, EPROM, EEPROM, flash memory, MMC, SD memory card, memory stick, CBRAM, PRAM, FeRAM, RRAM, SONOS, racetrack memory, RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory, etc. In various embodiments, the memory 710 may store a queue of commands to be executed to cause quantum algorithms and / or circuits to be executed (e.g., executable queues) (classical), qubit records corresponding to qubits of a quantum computer (e.g., in a qubit record datastore, qubit record database, qubit record table, etc.), calibration tables, computer program code (e.g., code in one or more computer languages, such as a special quantum system controller language), etc. In one exemplary embodiment, the execution of at least a portion of the computer program code stored in memory 710 (for example, by processing element 705) causes the quantum system controller 30 to perform one or more steps, operations, processes, procedures, etc., for generating one or more sets of commands configured to cause the quantum processor 515 to perform at least a portion of a quantum circuit, update one or more qubit registries, etc. In one exemplary embodiment, the execution of at least a portion of the computer program code stored in memory 710 causes the quantum system controller 30 to perform one or more commands.

[0139] In various embodiments, the driver quantum system controller element 715 includes one or more drivers and / or quantum system controller elements, each configured to control one or more drivers. In various embodiments, the driver quantum system controller element 715 may comprise drivers and / or driver controllers. For example, a driver controller may be configured to operate one or more corresponding drivers according to executable instructions, commands, etc., generated, scheduled, and executed by the quantum system controller 30. For example, a processing element 705 may generate one or more commands that will be executed by a first driver.

[0140] In various embodiments, the driver controller element 715 enables the quantum system controller 30 to operate a voltage source 50, an operating source 60, a cooling system, a vacuum system, and the like. In various embodiments, the drivers may be a laser driver (for example, configured to operate and / or control one or more operating sources 60), a vacuum component driver, a driver for controlling the flow of current and / or voltage applied to electrodes used to maintain and / or control the trap potential of the confinement device 520 (for example, configured to operate and / or control one or more voltage sources 50) (and / or other devices for providing a sequence of driver activity to the potential generating elements of the confinement device), a cryostat and / or a vacuum system component driver, a cooling system driver, and the like.

[0141] Each driver controller element 715 corresponds to an endpoint in the system (e.g., a component of the operating source 60, a component of the voltage source 50 (radio frequency voltage source, arbitrary waveform generator (AWG), direct digital synthesizer (DDS), and / or other waveform generators), a component of the cooling and / or vacuum system, a component of the optical collection system 70, etc.). Each endpoint in the quantum computer 510 represents an individual hardware control device. In various embodiments, each endpoint has a unique set of accepted microcommands. Examples, but not limited to, include a voltage source 50 such as a direct digital synthesizer (DDS), a component of the optical collection system 70 such as a photomultiplier tube (PMT), a component of the operating source 60 such as a laser driver and / or optical modulator switch, and / or a general-purpose output (GPO). Individual commands for the DDS allow setting the power level, frequency, and phase of the control signals it generates. In various embodiments, commands for the PMT interface include starting / stopping photon counting and resetting the count. Commands for GPO endpoints include setting and / or clearing one or more output lines. These output lines can be used to control external hardware in a manner synchronized with quantum circuit execution.

[0142] In various embodiments, the quantum system controller 30 includes means for communicating and / or receiving signals from one or more optical receiver components (e.g., of the optical collection system 70). For example, the quantum system controller 30 may include one or more analog-to-digital (A / D) converter elements 725 configured to receive signals from one or more optical receiver components (e.g., photodetectors of the optical collection system 70), calibration sensors, etc. In various embodiments, the A / D converter elements 725 are configured to write input data generated by converting the received signals generated by one or more optical receiver components of the optical collection system 70 to a memory 710.

[0143] In various embodiments, the quantum system controller 30 may include a communication interface 720 for, for example, interface with and / or communicate with a classical computing entity 10. For example, the quantum system controller 30 may include a communication interface 720 for receiving executable instructions, command sets, etc., from the computing entity 10 and providing the computing entity 10 with outputs received from the quantum computer 510 (for example, from the optical collection system 70) and / or the results of processing those outputs. In various embodiments, the computing entity 10 and the quantum system controller 30 may communicate directly via wired and / or wireless connections, and / or via one or more wired and / or wireless networks 20.

[0144] Exemplary operation of a controller in a quantum computing system Figure 8 is a flowchart illustrating various processes, operations, and / or procedures performed by the controller 30 to determine, for example, the syndrome of a logical qubit, according to various embodiments. For example, in one exemplary embodiment, the processes, operations, and / or procedures in Figure 8 may be performed as part of step / operation 606.

[0145] When step / operation 802 is initiated, the controller 30 triggers the performance of a state-preparation operation on one or more auxiliary qubits. For example, performing a state-preparation operation on an auxiliary qubit sets the quantum state of the auxiliary qubit to a known state (e.g., a particular state in a two-state qubit space). For example, the controller 30 may control the operation of one or more voltage sources 50, manipulators 60, etc., to position one or more auxiliary qubits in the appropriate location in the confinement device 520 so that one or more manipulator signals are incident on each of the auxiliary qubits so that each of the quantum states of the one or more auxiliary qubits is in a known state.

[0146] In various embodiments, one or more auxiliary qubits may be used to generate, determine, and / or extract syndromes from a plurality of logic qubits. For example, in one exemplary embodiment, auxiliary qubits are used to implement a syndrome circuit segment for two or more logic qubits of a plurality of logic qubits. In such embodiments, previous syndrome values ​​are stored in a classical qubit registry (stored in memory 710 or memory 922, 924), and the auxiliary qubits can be reinitialized and reused through the implementation of a state-prepared operation. This reduces the overall number of physical qubits required to implement a quantum circuit, since each logic qubit does not need to have its own dedicated auxiliary qubit. In various embodiments, this technical improvement is enabled, at least in part, by the all-to-all connectivity of physical qubits.

[0147] In step / operation 804, the controller 30 triggers the implementation of a series of interactions of at least two physical qubits according to the syndrome circuit segment. In various embodiments, a particular series of interactions of at least two physical qubits is controlled, determined, and / or defined by a logic qubit stabilizer. As detailed elsewhere in this specification, a logic qubit stabilizer is defined and / or determined at least in part on the topology in which multiple data qubits of the logic qubit are logically organized. For example, in various embodiments, a series of interactions of at least two physical qubits is a physical implementation of one or more stabilizer operators. For example, a series of interactions of at least two physical qubits triggers an interaction between one or more auxiliary qubits and a particular data qubit of the logic qubit, thereby triggering the evaluation of one or more stabilizer operators. Thus, a series of interactions of at least two physical qubits is determined at least in part on the topology of the logic qubit (e.g., real projection plane topology). In various embodiments, the interaction of at least two physical qubits may be, according to the quantum circuit and / or syndrome circuit segment, an interaction of two or more auxiliary qubits, an interaction of two or more data qubits, an interaction of at least one auxiliary qubit and at least one data qubit, and so on.

[0148] At least two physical qubit interactions in a series of interactions between at least two physical qubits cause a non-invasive transfer of information about the quantum state of one or more data qubits to one or more auxiliary qubits (for example, such that the quantum information stored by the data qubits is not corrupted).

[0149] In step / operation 806, one or more auxiliary qubits are read. For example, auxiliary qubits may be separated from the data qubits of logic qubits. For example, in one exemplary embodiment, the data qubits may be transported outside the interaction zone containing the auxiliary qubits, and / or the auxiliary qubits may be moved to a read zone defined by the quantum processor 515. The controller 30 then controls the operation of one or more operation sources 60 so that one or more appropriate operation signals are incident on each of the auxiliary qubits. The controller 30 then controls the operation of the photo-collection system 70 to observe any fluorescence emitted by the auxiliary qubits so that the quantum state of each of the auxiliary qubits can be determined.

[0150] In step / operation 808, the syndrome of each logic qubit is determined based on the quantum state determined for the auxiliary qubit through the read operation. For example, the controller 30 determines the quantum state of each auxiliary qubit based on the signal received from the element of the optical collection system 70 corresponding to the location of each auxiliary qubit. For example, if a photodetector configured to fixate on the location of the first auxiliary qubit observes significant fluorescence during the read operation of the first auxiliary qubit, the first auxiliary qubit is determined to be in the first state of the two-state qubit space. If a photodetector configured to fixate on the location of the second auxiliary qubit does not observe significant fluorescence during the read operation of the second auxiliary qubit, the second auxiliary qubit is determined to be in the second state of the two-state qubit space. In one exemplary embodiment, the syndrome of each logic qubit depends on one or more quantum states of the auxiliary qubit. Thus, the controller 30 determines the syndrome for each logic qubit based on the respective determined quantum states of the auxiliary qubits.

[0151] In one exemplary embodiment, a syndrome circuit segment is performed more than once to determine whether the syndromes generated, determined, and / or extracted through multiple entities of the syndrome circuit segment are the same, and / or to determine a representative syndrome based on multiple entities performing the syndrome circuit segment. For example, in one exemplary embodiment, steps / operations 802-806 are performed multiple times, and step / operation 808 includes processing and / or analyzing the distribution of syndromes generated, determined, and / or extracted through multiple entities performing steps / operations 802-806 to determine the respective syndrome for each logic qubit. For example, a first syndrome circuit segment may be performed multiple times, and the distribution of syndromes generated, determined, and / or extracted may be analyzed and / or processed to determine a representative syndrome corresponding to the first syndrome circuit segment, such as one used to determine quantum error correction for each logic qubit, or one used to update the classical qubit registry for each logic qubit. For example, by repeating the first syndrome circuit segment multiple times, uncertainties in measurements, interactions of at least two physical qubits, and read operations can be "averaged."

[0152] In one exemplary embodiment, one or more syndromes generated, determined, and / or extracted from each logic qubit through the implementation of a syndrome circuit segment are stored in a classical qubit registry corresponding to each logic qubit (for example, stored in memory 710 and / or memories 922, 924), unlike the corresponding one or more syndromes stored in the classical qubit registry corresponding to each logic qubit, which is updated to reflect and / or include the most recently determined (representative) syndrome.

[0153] In various embodiments, several syndrome circuit segments are implemented to generate, determine, and / or extract multiple syndromes for each logic qubit. For example, different syndrome circuit segments are configured to identify and / or characterize different quantum errors that each logic qubit may experience. In one exemplary embodiment, each syndrome circuit segment corresponds to one stabilizer of a logic qubit, a subset of stabilizers in a set of stabilizers of a logic qubit, or each stabilizer in a set of stabilizers of a logic qubit. In various embodiments, the controller 30 is programmed to implement each of a defined set of syndrome circuit segments. In one exemplary embodiment, each of the syndrome circuit segments in the defined set of syndrome circuit segments is implemented during each quantum error correction cycle. In one exemplary embodiment, a first set of syndrome circuit segments is implemented, and based on the results, the controller 30 determines whether (and possibly which syndrome circuit segments) additional syndrome circuit segments in the defined set of syndrome circuit segments need to be implemented.

[0154] For example, in the case of logical qubits logically organized in a real projective plane topology with distance p (e.g., logical qubits 100, 200, 300, 400), the logical qubits are p 2 It contains data qubits, p 2 -1 ballast is defined. In one exemplary embodiment, p 2- A bit sequence consisting of the results of measuring one ballast is a syndrome. In various embodiments, the syndrome may be determined multiple times (e.g., 2 to p times in one exemplary embodiment) to generate multiple bit sequences consisting of the results of each occurrence of ballast measurements. Multiple bit sequences of ballast measurements (also called ballast volumes) are generated in one exemplary embodiment (e.g., via a controller 30 that controls the operation of various components of the quantum processor 510) and provided to the classical computing entity 10.

[0155] Exemplary Computational Entity Figure 9 provides a schematic diagram for illustrative purposes representing an exemplary classical computing entity 10 (also referred to herein as the computing entity) that may be used in conjunction with embodiments of the present disclosure. In various embodiments, the classical computing entity 10 is a classical (e.g., semiconductor-based) computer configured to allow a user to provide inputs to a quantum computer 510 (e.g., through the user interface of the computing entity 10) and to receive, display, analyze, etc., outputs from the quantum computer 510. In one exemplary embodiment, the classical computing entity 10 is part of a controller 30.

[0156] As shown in Figure 9, the classical computing entity 10 may include an antenna 912, a transmitter 904 (e.g., wireless), a receiver 906 (e.g., wireless), and a processing element 908 that provides signals to the transmitter 904 and receives signals from the receiver 906. The signals provided to the transmitter 904 and received from the receiver 906 may include information / data signaling in accordance with applicable wireless system air interface standards for communication with various entities such as the quantum system controller 30 and other computing entities 10. The computing entity 10 may also include a network interface 920 that can provide and receive signals in accordance with applicable network system interface standards for communication with various entities such as the quantum system controller 30 and other computing entities 10.

[0157] In this regard, the computing entity 10 may be capable of operating with one or more air interface standards, communication protocols, modulation types, and access types. For example, the computing entity 10 may be configured to receive and / or provide communications using wired data transmission protocols such as Fiber Distributed Data Interface (FDDI), Digital Subscriber Line (DSL), Ethernet, Asynchronous Transfer Mode (ATM), Frame Relay, Data Over Cable Service Interface Specification (DOCSIS), or any other wired transmission protocol.Similarly, computation entity 10 handles general packet radio service (GPRS), Universal Mobile Telecommunications System (UMTS), Code Division Multiple Access 2000 (CDMA2000), CDMA2000 1X (1xRTT), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), Time Division Synchronous Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Evolved Universal Terrestrial Radio Access Network (E-UTRAN), Evolution-Data Optimized (EVDO), High Speed ​​Packet Access (HSPA), High-Speed ​​Downlink Packet Access (HSDPA), IEEE 802.11 (Wi-Fi), Wi-Fi Direct, 802.16 (WiMAX), and ultra-wideband It may be configured to communicate over a wireless external communication network using any of the following protocols: UWB (Ultra-Wide Blocking), infrared (IR) protocol, near-field communication (NFC) protocol, Wibree, Bluetooth protocol, wireless universal serial bus (USB) protocol, and / or any other wireless protocol.Computational entity 10 may use protocols and standards such as Border Gateway Protocol (BGP), Dynamic Host Configuration Protocol (DHCP), Domain Name System (DNS), File Transfer Protocol (FTP), Hypertext Transfer Protocol (HTTP), HTTP over TLS / SSL / Secure, Internet Message Access Protocol (IMAP), Network Time Protocol (NTP), Simple Mail Transfer Protocol (SMTP), Telnet, Transport Layer Security (TLS), Secure Sockets Layer (SSL), Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Datagram Congestion Control Protocol (DCCP), Stream Control Transmission Protocol (SCTP), and HyperText Markup Language (HTML) to communicate.

[0158] Through these communication standards and protocols, the computing entity 10 can communicate with various other entities using concepts such as Unstructured Supplementary Service information / data (USSD), Short Message Service (SMS), Multimedia Messaging Service (MMS), Dual-Tone Multi-Frequency Signaling (DTMF), and / or Subscriber Identification Module Dialer (SIM Dialer). The computing entity 10 can also download changes, add-ons, and updates to its firmware, software (including, for example, executable instructions, applications, and program modules), and operating system.

[0159] The computational entity 10 may also include a user interface device comprising one or more user input / output interfaces (e.g., a display 916 and / or speaker / speaker driver coupled to the processing element 908, a touchscreen, keyboard, mouse, and / or microphone coupled to the processing element 908). For example, a user output interface may be configured to provide applications, browsers, user interfaces, interfaces, dashboards, screens, web pages, pages, and / or similar words used interchangeably herein, which run on and / or are accessible through the computational entity 10, in order to trigger the display or audible presentation of information / data, and for interaction with them via one or more user input interfaces. A user input interface may comprise any of several devices that enable the computational entity 10 to receive data, such as a keypad 918 (hard or soft), a touch display, a voice / speech or motion interface, a scanner, a reader, or other input device. In embodiments including a keypad 918, the keypad 918 may include (or trigger the display of) conventional numeric keys (0-9) and associated keys (#, *), as well as other keys used to operate the computational entity 10, and may include a complete set of alphanumeric keys, or a set of keys that can be activated to provide a complete set of alphanumeric keys. In addition to providing input, the user input interface may be used to enable or disable several functions, such as a screen saver and / or sleep mode. Through such input, the computational entity 10 can collect information / data, user interaction / input, etc.

[0160] The computation entity 10 may also include volatile storage or memory 922 and / or non-volatile storage or memory 924, which may be embedded and / or removable. For example, non-volatile memory may be ROM, PROM, EPROM, EEPROM, flash memory, MMC, SD memory card, memory stick, CBRAM, PRAM, FeRAM, RRAM, SONOS, racetrack memory, etc. Volatile memory may be RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory, etc. The volatile and non-volatile storage or memory may store databases, database instances, database management system entities, data, applications, programs, program modules, scripts, source code, object code, bytecode, compiled code, interpreted code, machine code, executable instructions, etc., in order to implement the functions of the computation entity 10.

[0161] In various embodiments, the classical computation entity 10 is configured to receive information from the controller 30 (e.g., auxiliary qubit values, data qubits and / or logical qubit values, syndromes corresponding to each logical qubit, etc.) and perform various operations based on it. For example, the classical computation entity 10 may receive auxiliary qubit values ​​and determine one or more syndromes for one or more logical qubits. For example, the classical computation entity 10 may be configured to operate a quantum error decoder and / or otherwise determine one or more quantum error corrections for one or more logical qubits based on one or more syndromes for each of the one or more logical qubits. For example, the classical computation entity 10 may determine one or more quantum error corrections for each logical qubit and provide (e.g., transmit) the quantum error corrections so that the controller 30 can receive the quantum error corrections and trigger their implementation. In one exemplary embodiment, the classical computation entity 10 stores and / or updates one or more qubit registries (e.g., in memories 922, 924) based on one or more quantum error corrections.

[0162] Technical advantages Complex quantum computations require levels of precision unattainable by conventional quantum computers, for example, due to imperfect control and noise in gate operations between data qubits. Proposed methods for quantum error correction involve syndrome extraction, which generally includes the interaction of auxiliary qubits with data qubits. However, if not implemented carefully, such interactions between auxiliary and data qubits can catastrophically propagate errors, leading to logic errors that would otherwise be correctable considering the initial weights. Thus, there are technical problems regarding how to perform quantum computations with a level of precision sufficient to perform complex calculations. Furthermore, there are technical problems regarding how to extract the information needed to diagnose and correct errors from logic qubits without causing further error propagation.

[0163] Various embodiments provide technical solutions to such technical problems. For example, various embodiments provide implementations of quantum error correction using the interaction of a set of at least two qubits, determined based on a stabilizer defined based on a real projective plane topology. In particular, the topology of the stabilizer used for syndrome determination and / or extraction, as well as the topology of the logic qubits, determines the errors or combinations of errors to which the syndrome is sensitive. By organizing the data qubits of the logic qubits using a real projective plane topology, the number of possible error combinations that cannot be detected, identified, and / or corrected is reduced compared to conventional QEC techniques. Thus, more errors can be detected and corrected, computational fidelity is improved, and the number of circuits that need to be rerun due to error diffusion is reduced. Thus, various embodiments result in improvements over conventional quantum error correction methods.

[0164] For example, in the case of a logic qubit logically organized according to a conventional rotating plane distance code with a distance of 3 and 9 data qubits, there are 24 intrinsic logic errors that cannot be detected even with the corresponding stabilization. For logic qubit 100, there are 18 intrinsic logic errors that cannot be detected even with the corresponding stabilization. For logic qubit 400, there are only 12 intrinsic logic errors that cannot be detected even with the corresponding stabilization. Thus, various embodiments provide a technical improvement over conventional quantum error correction by reducing the number of intrinsic logic errors that cannot be detected by the syndrome extraction of the exemplary embodiments compared to conventional syndrome extraction.

[0165] conclusion Many modifications and other embodiments of the invention as defined herein will be recalled by those skilled in the art to which the invention relates, who benefit from the teachings presented in the above description and the accompanying drawings. It should be understood that the invention is not to be limited to any particular embodiment disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Certain terms are used herein, but they are used comprehensively and not restrictively. [Explanation of symbols]

[0166] 5 data qubits 10 Classical Computation Entities 20 Wired / Wireless Networks 30 controllers 40 Cryostat / Vacuum Chamber 50 Voltage source 60 Operation source 70 Light Collection System 100 logical qubits 105 Ballast 110 sides 200 logical qubits 205 Ballast 300 logical qubits 400 logical qubits 500 Quantum Computing Systems 510 Quantum Computer 515 Quantum Processors 520 Confinement device 705 Processing elements 710 memory 715 Driver Controller Element 720 Communication Interfaces 725 A / D converter elements 904 Transmitter 906 Receiver 908 Processing elements 912 Antenna 916 displays 918 Keypad 920 Network Interfaces 922 Volatile memory 924 Non-volatile memory

Claims

1. A method carried out by a quantum computing system comprising a classical computing entity, a controller, and a quantum processor, wherein the controller is configured to (a) control the operation of the quantum processor and (b) communicate with the classical computing entity, and the method The steps include: causing the controller to perform the implementation of at least one syndrome circuit segment to generate a logic qubit syndrome, wherein the at least one syndrome circuit segment is performed by at least partly causing the implementation of a series of interactions of at least two physical qubits, the logic qubit comprising a plurality of data qubits logically organized in real projection plane topology, and the interaction of the series of at least two physical qubits being determined at least partly based on one or more stabilizers determined based on the real projection plane topology of the logic qubit; The steps include determining at least one quantum error correction by the classical computation entity based at least part on the syndrome of the logical qubit, A method comprising the step of causing the controller or the classical computing entity to update a classical memory of at least one of the controller or the classical computing entity based on the syndrome or at least one of the at least one quantum error correction.

2. The method according to claim 1, wherein each of the one or more ballasts comprises four instances of the same operator, and each of the four instances of the same operator acts on different data qubits of the plurality of data qubits.

3. The method according to claim 1, wherein at least one of the one or more ballasts comprises two instances of a first operator and two instances of a second operator, and each instance of the first operator and each instance of the second operator acts on different data qubits of the plurality of data qubits.

4. The method according to claim 1, wherein each of the one or more ballasts is a ballast with a weight of 4.

5. The method according to claim 1, further comprising the step of causing the controller to apply the at least one quantum error correction to the logical qubit.

6. The method according to claim 5, wherein the step of applying the at least one quantum error correction to the logical qubit comprises at least one of the following steps: (a) updating a classical qubit registry corresponding to the logical qubit based on the at least one quantum error correction; (b) causing the implementation of a physical correction to one or more data qubits of the logical qubit; or (c) causing a logical operation to be performed at least in part on one or more data qubits of the logical qubit to be modified at least in part based on the at least one quantum error correction.

7. The method according to claim 1, wherein the implementation of the at least one syndrome circuit segment comprises the implementation of a plurality of syndrome circuit segments.

8. The method according to claim 1, wherein at least one interaction of at least two physical qubits among the series of interactions of at least two physical qubits includes an interaction of at least one auxiliary qubit with at least one data qubit among the plurality of data qubits of the logical qubit.

9. The method according to claim 8, wherein the logic qubit is one of a plurality of logic qubits, and the at least one auxiliary qubit is used to implement a syndrome circuit segment for two or more logic qubits of the plurality of logic qubits.

10. The method according to claim 1, wherein updating the classical memory based on the syndrome or at least one of the at least one quantum error correction is to track the syndrome of the logical qubits in the classical memory.

11. The method according to claim 1, wherein the coherence of the plurality of data qubits of the logic qubit is maintained during the implementation of the at least one syndrome circuit segment.

12. The method according to claim 1, further comprising: causing the execution of a state preparation circuit segment to prepare the state of each auxiliary qubit before causing the execution of the at least one syndrome circuit segment; performing the series of at least two physical qubit interactions using each of the auxiliary qubits; and ensuring that each of the auxiliary qubits is read after the execution of the series of at least two physical qubit interactions, wherein the syndrome of the logic qubit is generated based at least in part on the results of the reading of each of the auxiliary qubits.

13. A controller for a quantum computing system, wherein the controller is configured to (a) control the operation of the quantum processor, and (b) comprises a processing element and a memory for storing executable instructions, and when an executable instruction is executed by the processing element, the controller provides at least To generate a logic qubit syndrome, the implementation of at least one syndrome circuit segment is triggered, the at least one syndrome circuit segment is implemented by at least partly triggering the implementation of a series of interactions of at least two physical qubits, the logic qubit comprises a plurality of data qubits logically organized in real projection plane topology, and the interaction of the series of at least two physical qubits is determined at least partly based on one or more stabilizers determined based on the real projection plane topology of the logic qubit, Based at least part on the syndrome of the logical qubit, at least one quantum error correction is determined. A controller configured to cause a classical memory of at least one of the controllers or the classical computing entities to be updated based on the syndrome or at least one of the at least one quantum error correction.

14. The controller according to claim 13, wherein each of the one or more ballasts comprises four instances of the same operator, and each of the four instances of the same operator acts on different data qubits of the plurality of data qubits.

15. The controller according to claim 13, wherein at least one of the one or more ballasts comprises two instances of a first operator and two instances of a second operator, and each instance of the first operator and each instance of the second operator acts on different data qubits of the plurality of data qubits.

16. The controller according to claim 13, wherein each of the one or more ballasts is a ballast with a weight of 4.

17. The controller according to claim 13, wherein when the executable instruction is further executed by the processing element, the controller is configured to cause at least the at least one quantum error correction to be applied to the logical qubit.

18. The controller according to claim 17, wherein applying the at least one quantum error correction to the logical qubit comprises at least one of the following: (a) updating a classical qubit registry corresponding to the logical qubit based on the at least one quantum error correction; (b) causing the implementation of a physical correction to one or more data qubits of the logical qubit; or (c) causing a logical operation to be implemented at least in part on one or more data qubits of the logical qubit to be modified at least in part based on the at least one quantum error correction.

19. The controller according to claim 13, wherein updating the classical memory based on the syndrome or at least one of the at least one quantum error corrections is to track the syndrome of the logical qubits in the classical memory.

20. The controller according to claim 13, wherein the coherence of the plurality of data qubits of the logic qubit is maintained during the implementation of the at least one syndrome circuit segment.

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