A method for manufacturing an LED array precursor having electrical contacts on the same side, a corresponding precursor, an LED array, and a device having the same.

Abstract

The present invention provides a method for manufacturing a light-emitting diode (LED) array precursor, an LED array precursor, an LED array, and a device having the same. The method involves preparing a substrate, forming one or more first layers on the epitaxial surface side of the substrate, each of which has at least a first semiconductor layer, and if present, further having one or more buffer layers laminated between the substrate and the first semiconductor layer, selectively masking the one or more first layers by depositing one or more masking layers thereon, forming a plurality of openings in the unmasked portions of the one or more first layers, forming a microstructure within at least a portion of the plurality of openings, the microstructure being in physical contact with the first semiconductor layer and forming one or more active layers that at least partially cover the microstructure, and forming both anode and cathode electrical contacts on the epitaxial surface side of the substrate.

Description

[Technical Field]

[0001] The present invention generally relates to light-emitting structures, and more specifically to light-emitting diode (LED) array precursors, methods for manufacturing the same, LED arrays, and devices having the same. In particular, the present invention relates to manufacturing methods that are more homogeneous, result in better pixel yield, have an improved hybridization process and a reduced number of processing steps, as well as LED array precursors, LED arrays, and devices having improved luminosity, improved control of the polarization direction of emitted light, high energy efficiency, high brightness, and compact dimensions. [Background technology]

[0002] LEDs are typically semiconductor-based light sources that emit light when an electric current is applied. An LED array is a single LED chip with multiple emitters. Each emitter has two connections, a cathode and an anode, which allows each emitter to be individually addressable. Due to their advantageous characteristics, such as long lifespan, low power consumption, small size, fast switching time, and shock resistance, LEDs are used in a wide range of applications, from everyday consumer products such as lamps and displays to highly specialized medical and military applications. For applications in solid-state lighting and backlights for liquid crystal displays (LCDs), conventional inorganic semiconductor LEDs, particularly those made from Group III materials, are a common choice. For more advanced applications, microLEDs are commonly used due to their higher brightness and emitter density. Typically, microLEDs have array sizes of 100 × 100 emitters or less, with emitters measuring approximately 100 μm × 100 μm or less.

[0003] Novel applications for micro-LED arrays, particularly in augmented reality (AR) and virtual reality (VR), demand an increase in the number of emitters while simultaneously reducing the array size, i.e., improving pixel density. For applications where the light from the emitters needs to be visible in daylight, such as AR smart glasses and head-up displays, further improvements in characteristics such as energy efficiency, brightness, and contrast ratio are especially desirable.

[0004] Conventional manufacturing of such LED arrays requires several complex manufacturing processes. This makes cost-effective and time-efficient mass production difficult when pixel control and yield requirements must be met simultaneously. To achieve the improvements in the characteristics and manufacturing of micro-LED arrays mentioned above, the design, manufacturing methods, and integration of micro-LEDs must be adapted.

[0005] Currently, two manufacturing strategies are employed to produce microLEDs. The conventional manufacturing method corresponds to that used for standard-sized LEDs, where arrays are assembled by pick-and-place individual components, and the manufacturing process is based on monolithic integration. The advantage of the conventional manufacturing method is that LEDs with different primary colors (emission wavelengths) can be assembled in a single array, even if grown under different conditions and / or on different substrates. Furthermore, defective components can be replaced, thereby achieving a high final yield for the array. On the other hand, pick-and-place components lead to increased production time and limit resolution and array size. By applying the monolithic integration manufacturing strategy, multiple emitters, and even passive elements, are formed on a single substrate, and the single emitters are intentionally spaced apart across the array in a specific pattern that allows for individual addressing.

[0006] Devices on substrates are typically formed by vacuum deposition techniques, such as chemical vapor deposition (CVD). In particular, metal-organic chemical vapor deposition (MOCVD) is used to grow complex semiconductor multilayer structures for LED applications. The formation of semiconductor multilayers for LED manufacturing is well documented in known technologies.

[0007] Interest in Group III nitrides has grown rapidly in recent years. One reason is the semiconductor properties of Group III nitrides that make them suitable for use in LEDs. The application of Group III nitride-based micro-LEDs is discussed in Matthew S. Wong et al. 2020 ECS J. Solid State Sci. Technol.9 015012.

[0008] British Patent No. 2575311 discloses a monolithic LED array and its precursor based on a Group III nitride structure. Primary and secondary electrical contacts are formed on the opposite side of the first semiconductor layer of the LED array precursor. This allows the solution disclosed in British Patent No. 2575311 to form the electrical contacts only after the substrate has been removed from the precursor. This has the obvious disadvantage of requiring an additional processing step. Furthermore, because the electrical contacts are located on the light-emitting surface of the LED precursor, it is not easy to mechanically stabilize the electrical contacts. Placing the secondary electrical contacts on the light-emitting surface also reduces the total area available for light emission or for arranging other optical elements on that surface.

[0009] SE537434C2 discloses the preparation of a group III nitride structure that has a structurally elongated pyramidal shape, providing a suitable position for quantum dots at the apex of the pyramidal structure. In this structure, the quantum dots function as light sources with sharp emission lines. In the case of the elongated pyramidal structure, the emission from the ridges of the elongated pyramidal structure is highly linearly polarized. SE537434C2 does not disclose how such a structure or a similar structure can be efficiently implemented in a monolithic manufacturing method, or how to obtain a novel LED array with improved emission characteristics and polarization generation. [Overview of the project]

[0010] One objective of the present invention is to eliminate at least some of the problems and drawbacks mentioned in the prior art regarding LED arrays and structures applicable thereto.

[0011] As used herein, the term “LED structure” may, within the scope of this application, refer to a single structural assembly, such as a microstructure, that enables and drives light emission when connected to a secondary electrical contact or electrical circuit.

[0012] The individual microstructures are of a micron size or smaller, for example, nanoscale structural elements. The microstructures can be, for example, pyramidal structures, elongated pyramidal structures, elongated truncated pyramidal structures, platelets, nanowires, or nanowires having a pyramidal apex.

[0013] A group of microstructures consists of multiple individual microstructures that are the same or different in shape.

[0014] In the scope of this application, the term “LED array precursor” refers to an LED array in which no secondary electrical contacts or electrical circuits for driving light emission are defined.

[0015] In the scope of this application, the terms “epitaxial surface side” or “epitaxial surface direction” refer to the side / direction on which or further material layers are deposited or deposited.

[0016] The light-emitting surface or light-extracting surface of an LED structure or LED array precursor is a surface intended for light emission or light extraction.

[0017] According to a first aspect of the embodiment described herein, a method is provided for forming an LED array precursor on a prepared substrate. The prepared substrate for the LED array precursor has an epitaxial surface. The method comprises the steps of: (i) preparing a substrate; (ii) forming one or more first layers on the epitaxial surface side of the substrate, wherein the one or more first layers have at least a first semiconductor layer, and if present, one or more further first layers have a buffer layer laminated between the substrate and the first semiconductor layer; (iii) selectively masking the one or more first layers by depositing one or more masking layers thereon, wherein the unmasked portions of the one or more first layers form a plurality of openings; (iv) forming a microstructure within at least a portion of the plurality of openings, wherein the microstructure is in contact with the first semiconductor layer; (v) forming one or more active layers that at least partially cover the microstructure; (vi) forming a second semiconductor layer that at least partially cover the microstructure and / or the one or more active layers; and (vii) forming both anode and cathode electrical contacts on the epitaxial surface side of the substrate.

[0018] A method according to the first embodiment, wherein step (vii) of forming both an anode and a cathode electrical contact on the epitaxial surface side of the substrate, (vii.i) Deposit one or more additional masking layers on the epitaxial surface side, (vii.ii) Pattern the further masking layer by selectively removing multiple portions of the further masking layer to create further openings, wherein at least a portion of the further openings has the microstructure formed under step (iv), (vii.iii) Depositing an electrode contact material on the patterned masking layer, (vii.iv) Optionally, removing at least a portion of the excess electrode contact material and / or the masking layer, comprising:

[0019] A method according to the first aspect, wherein the microstructure is one or more of a pyramid structure, a symmetric pyramid structure, an elongated pyramid structure, a truncated pyramid structure, a platelet, a nanowire, a nanowire having a pyramidal top, an etched structure, or any combination thereof.

[0020] A method according to the first aspect, wherein the active layer has one or more quantum structures such as quantum wells, quantum dots, quantum wires, or combinations thereof.

[0021] A method according to the first aspect, wherein the quantum structure has GaN, AlN, InN, and / or ternary and quaternary compounds thereof.

[0022] A method according to the first aspect, the method further comprising the step of at least partially removing the substrate from the LED array precursor or partially removing the substrate and the first layer.

[0023] A method according to the first aspect, the method further comprising forming an electrical contact between at least a portion of the anode and cathode electrical contacts of the LED array precursor and the backplane by chemically, physically, and / or mechanically bonding the electrical contact material to corresponding bonding pads on the backplane, thereby electrically contacting both the anode and cathode electrical contacts with the secondary electrical contacts of the backplane.

[0024] A method according to the first embodiment, wherein the electrical contact between the LED array precursor and the backplane is formed via a metal bump.

[0025] A method according to a first embodiment, the method further comprising the step of filling the gap between the LED array precursor and the backplane with a filler material.

[0026] According to a second aspect of the embodiments herein, an LED array precursor obtained according to the first aspect is provided. The luminous efficiency of the LED is increased through a combination of a microstructure exhibiting nonpolar or semipolar facets and an active layer having a quantum dot structure (QS). This is due to reduced built-in spontaneous electric fields and strain-induced piezoelectric electric fields compared to typical Group III nitride optoelectronic devices grown on planar substrates such as GaN·on-sapphire, for example, with (0001) orientation.

[0027] According to a third aspect of the embodiments herein, an LED array precursor is provided, which optionally comprises a substrate, (i) one or more first layers having at least a first semiconductor layer, and if present, one or more further first layers being buffer layers, (ii) optionally a masking layer at least partially covering the one or more first layers, the masking layer having a plurality of openings, (iii) a microstructure on the first semiconductor layer formed in at least a portion of the openings of the masking layer during a manufacturing process, (iv) an active layer at least partially covering the microstructure, (v) a second semiconductor layer at least partially covering the microstructure and / or the active layer, and (vi) anode and cathode electrical contacts, both formed on the epitaxial surface side.

[0028] A third embodiment of an LED array precursor, having a substrate on its epitaxial surface side comprising (i), (ii), (iii), (iv), (v), and (vi).

[0029] A third embodiment of an LED array precursor, wherein both the anode and cathode electrical contacts of (vii) on the epitaxial surface are formed within at least a portion of a further opening formed in a further masking layer, and at least a portion of the further opening has the microstructure of (iv).

[0030] Herein, according to a fourth aspect of the embodiment, an LED array having an LED array precursor according to the second or third aspect is provided.

[0031] According to a fifth aspect of the embodiments herein, a display device, communication device, optoelectronic device, interconnection device, cryptographic device, lighting device, or illumination device is provided, having an LED array according to the fourth aspect and / or an LED array precursor according to either the second or third aspect. By utilizing an LED array according to the fourth aspect and / or an LED array precursor according to either the second or third aspect, the device can be small in size, have high luminous intensity and low energy consumption, and may require fewer optical elements because the positioning and connection of the microstructure can compensate for various optical effects.

[0032] In view of the foregoing, the present invention provides a manufacturing method that is more homogeneous, results in a better pixel yield, has an improved hybridization process and a reduced number of processing steps, and also provides an LED array precursor, an LED array, and a device having the same, which have improved luminosity, high energy efficiency, high brightness, and compact dimensions.

[0033] Further objects and features of the present invention will become apparent from the following detailed description of embodiments of the present invention. Unless otherwise expressly indicated, each such embodiment may be combined with any one or more other embodiments. Any feature indicated as preferred or advantageous may be combined with any one or more other features indicated as preferred or advantageous. In particular, various microstructures, active layers having quantum structures, and architectures of LED array precursors and backplanes may be freely combined. [Brief explanation of the drawing]

[0034] The present invention will be described by referring to the attached drawings, including the following figures, as an example. [Figure 1a] A schematic example of an LED array precursor where both the anode and cathode electrical contacts are located on the epitaxial surface side of the substrate is shown. [Figure 1b] Another schematic embodiment of an LED array precursor having anode and cathode electrical contacts formed to at least partially include regions in which nanostructures are located is shown. [Figure 2a] Figures 2a-2c schematically show a backplane having metal contact bumps that contact each electrode metal contact of the LED array precursor. [Figure 2b] Figures 2a-2c schematically show a backplane having metal contact bumps that contact each electrode metal contact of the LED array precursor. [Figure 2c] Figures 2a-2c schematically show a backplane having metal contact bumps that contact each electrode metal contact of the LED array precursor. [Figure 3] Another embodiment of an LED array precursor is schematically shown, which has an additional masking layer that allows for the selective deposition of electrode contact material within further openings having at least partially microstructured structures. [Figure 4]An example of forming an electrical contact between an LED array precursor and a backplane by chemically, physically, and / or mechanically bonding electrical contacts to the bonding pads of the backplane via metal bumps is schematically shown. The direction of light emission is also indicated. [Figure 5] A schematic example of an LED array having an LED array precursor in which both the anode and cathode electrical contacts are electrically in contact with the backplane, and the gap between the LED array precursor and the backplane is filled with a filler material. [Figure 6a] Figures 6a–6i schematically show cross-sections of various examples of microstructures that may be used in LED arrays. [Figure 6b] Figures 6a–6i schematically show cross-sections of various examples of microstructures that may be used in LED arrays. [Figure 6c] Figures 6a–6i schematically show cross-sections of various examples of microstructures that may be used in LED arrays. [Figure 6d] Figures 6a–6i schematically show cross-sections of various examples of microstructures that may be used in LED arrays. [Figure 6e] Figures 6a–6i schematically show cross-sections of various examples of microstructures that may be used in LED arrays. [Figure 6f] Figures 6a–6i schematically show cross-sections of various examples of microstructures that may be used in LED arrays. [Figure 6g] Figures 6a–6i schematically show cross-sections of various examples of microstructures that may be used in LED arrays. [Figure 6h] Figures 6a–6i schematically show cross-sections of various examples of microstructures that may be used in LED arrays. [Figure 6i] Figures 6a–6i schematically show cross-sections of various examples of microstructures that may be used in LED arrays. [Figure 7a] Figures 7a–7h schematically show top views of various examples of microstructures that can be used in LED arrays. [Figure 7b]Figures 7a–7h schematically show top views of various examples of microstructures that can be used in LED arrays. [Figure 7c] Figures 7a–7h schematically show top views of various examples of microstructures that can be used in LED arrays. [Figure 7d] Figures 7a–7h schematically show top views of various examples of microstructures that can be used in LED arrays. [Figure 7e] Figures 7a–7h schematically show top views of various examples of microstructures that can be used in LED arrays. [Figure 7f] Figures 7a–7h schematically show top views of various examples of microstructures that can be used in LED arrays. [Figure 7g] Figures 7a–7h schematically show top views of various examples of microstructures that can be used in LED arrays. [Figure 7h] Figures 7a–7h schematically show top views of various examples of microstructures that can be used in LED arrays. [Figure 8a] Figures 8a–8f schematically show top views of various examples of aperture and electrode contact material patterns. [Figure 8b] Figures 8a–8f schematically show top views of various examples of aperture and electrode contact material patterns. [Figure 8c] Figures 8a–8f schematically show top views of various examples of aperture and electrode contact material patterns. [Figure 8d] Figures 8a–8f schematically show top views of various examples of aperture and electrode contact material patterns. [Figure 8e] Figures 8a–8f schematically show top views of various examples of aperture and electrode contact material patterns. [Figure 8f] Figures 8a–8f schematically show top views of various examples of aperture and electrode contact material patterns. [Modes for carrying out the invention]

[0035] The present invention is defined by the attached independent claims. Embodiments are described in the attached dependent claims and in the following description and drawings.

[0036] According to a first aspect of the embodiments herein, a method is provided for forming an LED array precursor 10 as illustrated in Figures 1 and 3. The method comprises several numbered steps that can be performed simultaneously or in parallel. A single step may be repeated several times, or the order of the steps may be changed in various combinations leading to a meaningful deposition of material. Several washing, drying, and / or heating steps may be performed before, during, and after the explicitly mentioned steps. Such additional preparation steps are well known in the art and may include washing with organic solvents or inorganic acids to remove contaminants such as excess material or impurities from the preceding steps.

[0037] Step (i) is to prepare the substrate 100. Further deposition of material is performed on the epitaxial surface side 102 of the substrate 100. Step (ii) is to form one or more first layers 120 on the epitaxial surface side 102 of the substrate 100, the one or more first layers 120 having at least a first semiconductor layer 120b. Further optional layers having a buffer layer 120a laminated between the substrate and the first semiconductor layer 120b may be formed. Step (iii) is to selectively mask the one or more first layers 120 by depositing one or more masking layers 140 thereon. The one or more masking layers 140 can be selectively deposited or patterned by optical lithography methods known in the art. Excess material from the one or more masking layers 140 can be removed by an additional cleaning step, such as rinsing with deionized water. The unmasked portions of the one or more first layers 120 form a plurality of openings 142. Step (iv) is to form a microstructure 160 within at least a portion of the plurality of openings 142, the microstructure 160 being in physical and electrical contact with the first semiconductor layer 120. Step (v) is to form one or more active layers 162 that at least partially cover the microstructure 160. The one or more active layers 162 may be deposited on only a portion of the microstructure 160. Step (vi) is to form a second semiconductor layer 164 that at least partially cover the microstructure 160 and / or one or more active layers 162. Step (vii) is to form both anode and cathode electrical contacts 180a and 180b on the epitaxial surface side 102 of the substrate 100. To form both anode and cathode electrical contacts 180a and b, electrode contact material 180 can be deposited in an empty opening 142 (i.e., an opening 142 without microstructure 160), in a filled opening 142 (i.e., an opening 142 with microstructure 160), or on a region extending over several openings 142, both filled and empty. This makes it possible to form an electrical connection between the LED array precursor 10 and the electrical contacts in the LED array from only one side of the LED array precursor 10.This has the advantage of reducing the number of processing steps when integrating the LED array precursor 10 into the LED array. Furthermore, the light-emitting region is not covered by electrical contacts, leaving a larger area available for light emission and for positioning other optical elements on the light-emitting surface. The light-emitting side is opposite to the epitaxial surface side of the LED array precursor 10. In addition, by positioning the anode and cathode electrical contacts 180a and 180b on the epitaxial surface side 102, both electrical contacts can be mechanically stabilized after contact with the backplane 20, for example, using a filler material.

[0038] In some embodiments, step (vii) is a substep, namely, (vii.i) A substep of depositing one or more additional masking layers 140a on the epitaxial surface side 102, (vii.ii) A substep of patterning a further masking layer 140a by selectively removing multiple portions from the further masking layer 140a (those skilled in the art may select any suitable lithography method known in the art for this purpose) to produce a further opening 142a, wherein at least a portion of the further opening 142a has a microstructure (160) formed under step (iv), (vii.iii) A substep of depositing electrode contact material 180 on a patterned masking layer 140a, (vii.iv) Optionally, a substep of removing at least a portion of the excess electrode contact material 180 and / or masking layer 140a, It holds.

[0039] One or more additional masking layers 140a may cover a combination of previously deposited structures located underneath, such as the first layer 120, the masking layer 140, the microstructure 160, the active layer 162, and / or the second semiconductor layer 164. The masking layer 140a may partially, asymmetrically, or completely cover the underlying structures.

[0040] The microstructure 160 may itself be covered by other layers, such as a masking layer 140, an active layer 162, or a second semiconductor layer. Any excess material from the further masking layer 140a can be removed by an additional cleaning step, such as rinsing with deionized water.

[0041] The electrode contact material 180 may differ for the formation of the cathode metal contact 180a and the anode metal contact 180b. Examples of materials for the electrode metal contact 180 are Ti / Au, WTiAu, and Al for the cathode contact material 180a, and AlNi / Au and ITO (indium tin oxide) for the anode electrode contact material 180b. The same or different materials may be used for the formation of the cathode metal contact 180a and the anode metal contact 180b. Any electrode material known in the art can be used as the electrode metal contact 180. The electrode metal contact material 180 may be deposited by techniques such as thermal deposition or electron beam deposition.

[0042] The above substeps of the embodiment may be repeated for the formation of the anode and cathode metal contacts 180a, b, respectively. The above substeps of the embodiment may be repeated several times to generate several patterns of openings 142, 142a, and electrode contact material 180 may be used within the LED array precursor 10. Examples of such patterns are described in reference to Figures 8a–8f.

[0043] The advantage of positioning both the anode and cathode metal contacts 180a and 180b on an electronically insulated LED structure having a microstructure 160 and an active layer 162 is that, depending on the integrated circuit, each LED structure or group of LEDs can be individually addressed, thereby allowing for separate control of light emission from individual LEDs. Furthermore, by making contact with the LED only from the epitaxial surface side 102, a shorter electrical connection path can be achieved.

[0044] The substrate 100 can be made from a material selected from the group consisting of SiC, Al2O3 (sapphire), Si, GaN, GaN-on-Si, GaN-on-sapphire, SiO2, graphene, and GaO. Preferably, the materials of the first and second semiconductor layers (120b, 164), the microstructure 160, and the active layer 162 are group III nitrides. Preferably, the buffer layer 120a is selected from the group consisting of SiC, sapphire, Si, GaN, GaN-on-Si, GaN-on-sapphire, GaN, AlN, InN, and ternary and quaternary compounds thereof.

[0045] The microstructure 160 can be a pyramidal structure, an elongated pyramidal structure, an elongated truncated pyramidal structure, a platelet, a nanowire, a nanowire with a pyramidal apex, an etched structure, or a combination thereof. Since the microscale and nanoscale microstructures 160 can be selectively grown within the apertures 142, 142a, they are advantageous building blocks for LED structures. This avoids the need for additional etching steps, keeping the overall number of processing steps low.

[0046] The active layer 162 may have one or more quantum structures (QS), such as quantum wells, quantum dots, quantum wires, or combinations thereof. The quantum structures may be GaN, AlN, InN, and / or ternary and quaternary compounds thereof. The quantum structures can function as light sources for polarized light emission, thereby eliminating the need for polarizing filters implemented between the emitter and the display in devices obtained using the LED array precursor.

[0047] The LED structure enables light emission in the visible range, i.e., 380-750 nm, and / or the UV range, i.e., 100-380 nm. By using a combination of the microstructure 160 and the active layer 162, light emission from the LED structure can be generated at several different dominant wavelengths. The dominant wavelength of the LED structure may differ for different LED structures within the LED array precursor 10. Preferably, the LED array precursor 10 exhibits LED structures in several different dominant wavelength regimes, such as red, green, blue, yellow, white, and UV.

[0048] In some embodiments, the method according to the first embodiment includes a further step of removing at least partially the substrate 100 from the LED array precursor 10, or partially removing the substrate 100 and the first layer 120. This removal improves the light emission of the single LED structure in the light extraction direction 400 when the LED array precursor 10 is connected to the associated secondary electrical contacts or electrical circuit to drive light emission.

[0049] In some embodiments, the method according to the first embodiment includes a further step of forming an electrical contact between at least a portion of the anode and cathode electrical contacts 180a,b of the LED array precursor 10 and the backplane 20 by chemically, physically, and / or mechanically bonding the electrical contact material 180 to the corresponding bonding pads 220 of the backplane 20, thereby bringing both the anode and cathode contacts 180a,b into electrical contact with the secondary electrical contacts of the backplane 20. Preferably, the electrical contact between the LED array precursor 10 and the backplane 20 is formed via metal bumps 240. Forming the electrical contact via metal bumps 240 has the advantage of making the height differences between the LED structures on the LED array precursor 10 uniform, thereby minimizing the strain in the resulting LED array.

[0050] In some embodiments, the method according to the first aspect includes a further step of filling the gap between the LED array precursor 10 and the backplane 20 with a filler material 300. The filler material 300 is used to redistribute thermomechanical stress caused by a mismatch in the coefficient of thermal expansion (CTE) between the different materials of the components of the LED array precursor 10 and the components of the backplane 20. Furthermore, the filler material 300 protects the components from moisture entering them. Depending on the application of the final product, the filler material 300 can be any suitable filler material, such as hydrogen silsesquioxane (HSQ). Other examples of filler materials.

[0051] In this embodiment, according to a second aspect, an LED array precursor 10 obtained according to the first aspect is provided.

[0052] Herein, according to a third aspect of the embodiment, an LED array precursor 10 is provided, and the LED array precursor 10 is One or more first layers 120, each having at least one first semiconductor layer 120b, and if present, one or more further first layers 120 being buffer layers 120a, An optional masking layer 140 that at least partially covers one or more first layers 120, and the masking layer 140 having a plurality of openings 142, A microstructure 160 on the first semiconductor layer 120b is provided within at least a portion of the opening 142 of the masking layer 140 during the manufacturing process, An active layer 162 that at least partially covers the microstructure 160, A second semiconductor layer 164 that at least partially covers the microstructure 160 and / or the active layer 162, These are anode and cathode electrical contacts 180a and b, both formed on the epitaxial surface side 102. It holds.

[0053] Herein, according to a fourth aspect of the embodiment, an LED array having an LED array precursor 10 according to the second or third aspect is provided.

[0054] According to a fifth aspect of the embodiment described herein, a display device, communication device, optoelectronic device, interconnection device, encryption device, lighting device, or illumination device is provided, having an LED array according to the fourth aspect and / or an LED array precursor 10 according to either the second or third aspect.

[0055] By utilizing the LED array according to the fourth embodiment and / or the LED array precursor 10 according to either the second or third embodiment, for example, the device exemplified above can be small in size, have high luminous intensity and low energy consumption, and may require fewer optical elements because the positioning and connection of the microstructure can compensate for various optical effects.

[0056] Figures 1a and 1b schematically show a cross-section of an LED array precursor 10, which is based on light emission from electronically insulated LEDs having a microstructure 160 and an active layer 162. The LED array precursor can be monolithic. Each LED in the LED array precursor may be grouped into different subarrays capable of emitting light at different dominant wavelengths. Other specific positioning and / or grouping of LEDs may be performed, as described in Figures 8a–8f.

[0057] As shown in Figures 1a and 1b, the LED array precursor is formed on a substrate 100. The substrate has an epitaxial surface side 102. Suitable materials for the substrate 100 include SiC, sapphire, Si, GaN, GaN·on·Si, GaN·on·sapphire, GaN·on·SiC, SiO2, and graphene, GaO. When used herein, any reference to a species by its constituent components includes all available stoichiometry. For example, AlGaN is Al, where x is not equal to 1 or 0. x Ga(1-x) This includes all alloys of N, etc. The preferred stoichiometry will vary depending on the function of the specific layer. The substrate 100 can be any known n-type substrate, a semi-insulating or insulating substrate, or any other suitable substrate known in the art. Preferably, the substrate 100 has a (0001) orientation.

[0058] A first layer 120 is formed on the epitaxial surface side 102 of the substrate 101. The first layer 120 is in direct physical contact with the substrate 100, and the layer having the first layer 120 is in direct physical contact with the layers stacked above and below it, where applicable. The first layer 120 may be continuous or discontinuous and / or may not completely cover the substrate 100. The first layer may be an epitaxial layer. The first layer 120 has at least one first semiconductor layer 120b. The first semiconductor layer 120b may have a group III nitride, such as GaN, AlN, InN, and their ternary and quaternary compounds. The group III nitride of the semiconductor layer 120b may be n-doped. n-doping may be achieved by using dopants such as Si, C, Ge, and their respective precursors. The dopant may be 10e 15 -10e 21 cm -3 Within the range, preferably 5e 18 cm -3 The first semiconductor layer 120b may have a thickness of 1 μm to 3 μm, more preferably 2 μm. Preferably, the first semiconductor layer 120b is (0001) oriented. The first layer 120 may have further additional semiconductor layers 120b.

[0059] Furthermore, the first layer 120 may have one or more buffer layers 120a laminated between the substrate 100 and the first semiconductor layer 120b or a further semiconductor layer 120b of the first layer 120. The one or more buffer layers 120a may be SiC, sapphire, Si, GaN, GaN-on-Si, GaN-on-sapphire, GaN, AlN, InN, and ternary and quaternary compounds thereof. The buffer layer 120a may have a thickness in the range of 2 nm to 3 μm, preferably 2 μm.

[0060] The first layer 120 is at least partially covered by a masking layer 140 on the side opposite to the substrate 100. The masking layer 140 may be continuous or discontinuous and / or may not completely cover the first layer 120. The masking layer 140 may be a lithographically patterned layer. The masking layer 140 may have a thickness in the range of 5 nm to 200 nm, preferably 50 nm. The material of the masking layer 140 is SiO2, SiN x It may have either , and / or Al2O3. The masking layer 140 can be electrically insulating. The masking layer 140 may be an amorphous layer. The masking layer 140 may be deposited ex-situ using standard deposition techniques known in the art, such as low-pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PECVD). Alternatively, the masking layer 140 may be deposited in a suitable reaction chamber, such as a CVD reactor. Where applicable, the masking layer 140 may be partially or completely removed after it has served its purpose in the manufacturing process.

[0061] The masking layer 140 has a plurality of apertures 142. The plurality of apertures 142 can be formed by selectively removing a portion of the masking layer 140. Removal of the masking layer 140 to form the plurality of apertures 142 can be performed by UV lithography and selective etching of a portion of the masking layer, for example, by plasma etching, wet etching, or reactive ion etching. Alternatively, the masking layer 140 may be deposited area-selectively by techniques such as laser CVD or photoCVD. The apertures 142 can vary in size. For example, the diameter of the apertures 142 can be from 50 nm to 30 μm, or from 1 μm to 3 μm. The preferred center-to-center distance between apertures 142 is from 1 μm to 10 μm. The apertures 142 can be circular in shape, or they can be primarily circular in shape, such as elliptical. The apertures can have a specific size depending on the pattern of the microstructure 160 grown therein. Other shapes of the aperture 142 may also be used to obtain other growth conditions for QS within the microstructure 160 and / or the active layer 162. The growth conditions and growth modes have a significant impact on properties such as homogeneity, luminescence efficiency, internal efficiency, and light extraction efficiency (LEE).

[0062] Within the opening 142, a directly deposited electrode metal contact 180 may be present, as shown in Figure 1a. The electrode metal contact can function as either a cathode metal contact 180a or an anode metal contact 180b. Examples of materials for the electrode metal contact 180 include Ti / Au, WTiAu, and Al for the cathode contact material 180a, and AlNi / Au and ITO (indium tin oxide) for the anode electrode contact material 180b. The same or different materials may be used for forming the cathode metal contact 180a and the anode metal contact 180b. Any electrode material known in the art can be used as the electrode metal contact 180. The electrode metal contact material 180 can be deposited by techniques such as thermal deposition or electron beam deposition.

[0063] A microstructure 160 is grown within at least a portion of the aperture 142 of the masking layer 140. The microstructure 160 can be grown by selective area growth (SAG). By using SAG for the fabrication of the microstructure 160 within the electrically insulated aperture 142, unlike traditional methods, no additional etching steps are required to define the microstructure. This is due to the favorable growth conditions for the growth of the microstructure 160 on the first layer 120 that is not covered by the masking layer 140. The microstructure can be an n-doped microstructure. n-doping can be achieved by using dopants such as Si, C, Ge, and their respective precursors. The dopant can be in the range of 10e 15 -10e 21 cm -3 and preferably 5e 18 cm -3 . The selection of a suitable type of microstructure is shown in FIGS. 6 and 7 and will be described later. The microstructure can be grown by metalorganic chemical vapor deposition (MOCVD), and particularly low-pressure horizontal hot-wall MOCVD can be used. Different types of microstructures 160 may be grown in different apertures 142 within the LED array precursor 10. Different sub-arrays may be associated with a particular type of microstructure 160 for emitting light at a particular dominant wavelength. Within a single aperture 142, several microstructures 160, such as several nanowires, may be grown. The microstructure 160 can have different growth times to obtain microstructures 160 that emit light of different dominant wavelengths.

[0064] The microstructure 160 may be at least partially covered by one or more optically active layers 162. For example, optically active layers 162 having one or more quantum structures (QS), such as quantum wells, quantum dots, quantum wires, or combinations thereof, are grown on the top of the microstructure 160. The optimal location of the QS within the active layer 162 depends on the microstructure 160 located below. In the case of a pyramidal microstructure 160, the QS may be located either on the facets of the pyramid or on the top of either a sharp or truncated pyramid. Also, locating the QS on the edges of the facets of the microstructure 160 may be advantageous, for example, if the microstructure 160 is a one-dimensional structure. The dominant confinement effect in the QS will reduce the negative effects of the quantum confined Stark effect (QCSE). The QCSE is described in detail in the publicly available literature. The QCSE in the QS may be further reduced by nonpolar or semipolar facets of the microstructure 160. This enhances the light extraction efficiency of the QS. The QS may be GaN, AlN, InN, and their ternary and quaternary compounds. The emission of the QS is typically strong and, due to the confinement of the QS, exhibits a narrow bandwidth, typically less than a few millielectron volts (meV). Furthermore, the approach of obtaining the QS on selected sites, sides, and / or facets of the microstructure 160 allows light with a highly controlled polarization direction to be emitted from the active layer 162. The microstructure 160 and the optically active elements 162 may be covered by different electroactive layers 162 depending on whether the microstructure 160 is used as an anode or a cathode. Furthermore, the active layer 162 may be adapted depending on the microstructure located underneath or on a specific subarray of the microstructure 160.

[0065] The second semiconductor layer 164 can at least partially cover the microstructure 160 and / or the active layer 162 covering the microstructure 160. The second semiconductor layer 164 may have a group III nitride such as GaN. The group III nitride of the second semiconductor layer 164 can be p-doped. p-doping can be achieved by using a dopant such as Mg and its precursors. The dopant is 10e 15 -10e 21 cm -3 , preferably 5e 18 cm -3 -5e 19 cm -3 The second semiconductor layer can be in the range of 1 nm to 3000 nm (3 μm), preferably with a thickness of 300 nm.

[0066] The second semiconductor layer 164 may be at least partially covered by an electrode metal contact 180. Electrical contacts for each LED or group of LEDs of the LED array precursor 10 are formed via the electrode metal contact 180 in order to individually address the light emission through the associated circuit. The electrode metal contact 180 thereby serves to connect the first layer 120 and / or the LEDs of the LED array precursor 10 to secondary electrical contacts of the backplane 20, when deposited directly in the opening 142 as described above. The secondary electrical contacts may be metal bumps 240. The electrode metal contact 180 may extend over the entire or a portion of the microstructure 160 that may be covered by the active layer 162 and / or the second semiconductor layer 164. The electrode metal contact 180 may extend over several microstructures 160 or a portion thereof that may be covered by the active layer 162 and / or the second semiconductor layer 164, thereby connecting electrical contacts on one or both electrode sides. The coverage of the electrode metal contact 180 does not have to be symmetrical on all sides of the microstructure 160. The electrode metal contact 180 may be overgrown on a portion of the microstructure 160 that can be covered by the active layer 162 and / or the second semiconductor layer 164, as shown in the microstructure on the left side of Figure 1a and the microstructure in the center of Figure 1b. Overgrown the electrode metal contact 180 reduces the risk of electrical leakage from the underlying layers. The cathode metal contact 180a may extend over a portion of the masking layer 140 to a surrounding n-type layer, such as one of the first layers 120, as shown in Figure 1b. Contact with the n-type layer may also be obtained in a separate opening 142 from the one having the microstructure to which it is to make contact. The anode metal contact 180b may contact only a p-type layer or an insulating layer, such as the second semiconductor layer 164.

[0067] The formation of anode and cathode contacts on the epitaxial surface side 102 of the substrate 100 of the LED array precursor 10 enables flip-chip integration of the LED array precursor 10. This means that the LED array precursor 10 can be directly attached to the secondary circuit of the backplane 20 by conductive metal bumps 240 without the need for any wire bonds. This is advantageous because it shortens the connection path compared to designs with electrical contacts on the opposite side of the epitaxial surface side 102. This results in lower electrical resistance and inductance compared to traditional wire-bonded LEDs. This improves the speed of the circuit, especially at high frequencies or high current densities. Furthermore, the absence of wire bonds in the flip-chip LED eliminates potential fault points, thereby increasing the reliability of the device. Wire bonds are prone to fracture or degradation over time, especially under thermal cycling conditions. In addition, the LED array precursor 10 has a smaller form factor because there are no electrical contacts on the opposite side of the epitaxial surface side 102. When forming an electrode metal contact 180 on a portion of the microstructure 160, the number of different elements and processing steps can be reduced.

[0068] The above-described embodiment may be based on a p-type first semiconductor layer 120b. In that case, the microstructure 160 can also be p-type, and the second semiconductor layer 164 can be n-type. The materials and doping levels described above can be used for n-type and p-type materials, respectively. The electronic contacts formed by the electrode metal contacts 180 are inversely related.

[0069] Figures 2a-2c schematically show the LED backplane 20. The backplane 20 has a backplane substrate 200, backplane electrode bonding pads 220, and metal bumps 240. Preferably, the backplane substrate 200 is made of Si. The substrate may be electrically insulating, or it may be covered with an additional electrically insulating layer, such as an insulator 260. The insulator 260 may be made of SiO2 or Si3N4. The backplane electrode bonding pads 220 supported on the backplane support 200 may be made of In, Cu, or Al. The electrode bonding pads may be cathode bonding pads 220a or anode bonding pads 220b. The electrode bonding pads 220 are in electrical contact with the metal bumps 240. The metal bumps 240 may be metal bumps connected to cathode 240a or anode 240b, respectively. The metal bumps 240 may be made of different materials for the anode and cathode. Preferably, the metal bumps 240 are made of Cu, In, or Au.

[0070] Various configurations exist for the secondary electrical contacts of the backplane 20. In Figure 2a, the backplane electrode bonding pad 220 may be connected to a single metal bump 240 or one or more metal bumps 240 of the same type. This allows for addressing one or more LED structures within the corresponding LED array precursor 10. Different metal bumps 240 on the backplane 20 are separated by gaps between them, thereby preventing them from electrically contacting each other. In the example in Figure 2b, each backplane electrode bonding pad 220 has a corresponding metal contact 240. The height of the metal bumps 240 can vary to compensate for different heights of the underlying structure on the LED array precursor 10 to which the backplane 20 is intended to be connected. The gaps between the metal bumps 240 are filled with an insulating layer 260. The insulator 260 may be made of SiO2 or Si3N4. As shown in Figure 2c, a single backplane electrode bonding pad 220 can also be connected to one or more metal contacts 240. The various features of the embodiments shown in Figures 2a-2c can be freely combined with each other and with any other embodiments disclosed herein.

[0071] Figure 3 schematically shows a cross-section of an LED array precursor 10 having different electrode metal contacts 180 for the cathode metal contact 180a and the anode metal contact 180b. Their formation requires the deposition of one or more additional masking layers 140a. The additional masking layers can at least partially cover either the microstructure 160 and / or the layer covering it. The additional masking layers may be of the same material and thickness as the masking layer 140. By removing a portion of the additional masking layer 140a, an opening 142a is created. The size of the opening 142a may differ for different LED structures to be contacted. The opening 142a can also cover a specific facet or side of the microstructure 160 located beneath it. Multiple additional masking layers 140a, each exhibiting a different pattern, may be applied to deposit one or more different types of electrode metal contacts 180. Optionally, at least a portion of the excess electrode metal contact material 180 may be selectively removed. To improve the light extraction characteristics of the LED structure, a further masking layer 140a may be deposited after the electrode metal contact 180 is formed.

[0072] The determination of whether the microstructure 160, which may be covered by the active layer 162 and / or the second semiconductor layer 164, functions as an anode or a cathode depends on the position of the electrode metal contact 180. If the electrode metal contact 180 is at least partially connected to an n-doped portion in the LED array precursor, the electrode metal contact 180 functions as a cathode metal contact. If the electrode metal contact 180 is at least partially connected to a p-doped portion in the LED array precursor, the electrode metal contact 180 functions as an anode metal contact 180b. The electrode metal contact may also extend over insulating portions of the LED array precursor, such as a masking layer 140 and a further masking layer 140a. The electrode metal contact 180 may extend over more than one LED, thereby allowing several LEDs to be grouped into an associated circuit and made addressable as a group. Where applicable, the masking layer and further masking layers 140, 140a may be partially or completely removed, or not removed, after they have served their purpose in the manufacture.

[0073] Figure 4 schematically shows a cross-section of the LED array precursor 10 in electrical contact with the backplane 20. This is achieved by chemically, physically, and / or mechanically bonding at least a portion of the electrical metal contacts 180 of the LED array precursor 10 to the corresponding bonding pads 220 of the backplane 20 via metal contacts 240. This establishes electrical contact between the primary electrical contacts of the LED array precursor 10, i.e., the cathode contact 180a and anode contact 180b, and the opposing secondary electrical contacts of the backplane 20, which allows the LED structure to drive light emission via the associated circuit. Sharp connection points between the LED structure and the metal contacts 240 of the backplane 20 are advantageous because they reduce connection problems in hybridization. Therefore, microstructures 160 that enable such connections are preferred.

[0074] Figure 4 also shows an embodiment in which the substrate 100 of the LED array precursor 10 is removed from the first layer 120. This is necessary for any opaque material of the substrate 100. This facilitates light emission from multiple electrically insulated LED structures, each having a microstructure 160 and an active layer 162, in direction 400. Optionally, only a portion of the substrate 100 may be removed. This may be done selectively for areas where LED structures selected for light emission are located. Furthermore, the buffer layer 120a may be removed at least partially. A new additional layer may be bonded to the first layer 120 to provide a surface with improved light extraction characteristics. Such layers may have SiC, sapphire, Si, GaN, GaN-on-Si, GaN-on-sapphire, GaN, AlN, InN, and ternary and quaternary compounds thereof. The layer may be roughened. The substrate 100, and / or a portion of the first layer 120, may be removed before or after contact with the backplane.

[0075] Figure 5 schematically shows a cross-section of an LED array precursor 10 electrically in contact with a backplane 20, with a filler material 300 between the LED array precursor 10 and the backplane 20. The filler material 300 may be epoxy, adhesive, solder, or flux, or other materials known in the art, preferably electrically insulating, flexible, with a low coefficient of thermal expansion and no degassing. The filler material 300 may be hydrogen silsesquioxane (HSQ). The filler material 300 may be applied by capillary flow or molded. The filler material 300 may be applied before the substrate 100 of the LED array precursor is removed.

[0076] Figures 6a–6i schematically show cross-sections of various examples of microstructures 160 that can be used in the LED array precursor 10. Figures 6a–6d show triangular cross-sections, trapezoidal cross-sections with a lower base smaller than the upper base, trapezoidal cross-sections with a lower base larger than the upper base, and rectangular cross-sections, respectively. Figures 6e–6i show preferred combinations of the aforementioned cross-sections for more advanced structures. Figures 6e-6i show, respectively, a trapezoidal cross section as a base structure, where the lower base is larger than the upper base, connected to a rectangular cross section added on top of the upper base of the base structure; a rectangular cross section having a base structure, where the trapezoidal cross section has a trapezoidal cross section on top of the upper side of the base structure, and the lower base of the trapezoidal cross section is wider than the upper side of the rectangular base structure; a rectangular cross section as a base structure, where the upper side of the base structure has a triangular cross section; a rectangular cross section as a base structure, where the upper side of the base structure has a triangular cross section, and the base of the triangular cross section is wider than the upper side of the rectangular base structure; a trapezoidal cross section as a base structure, where the lower base is larger than the upper base, connected to a rectangular cross section as an intermediate structure added on top of the base structure; and a triangular cross section added on top of the intermediate structure. The height of the microstructure 160 can range from a few monolayers to a few microns. The angle α can range from 0° to 90°, preferably between 50° and 70°, and most preferably between 60° and 65°.

[0077] Figures 7a–7h schematically show top views of various examples of microstructures 160 that can be used in the LED array precursor 10. Figures 7a–7e show a circular base, a square base, a rectangular base, a regular hexagonal base, and an elongated hexagonal base, respectively. Figures 7f–7h show embodiments in which the base is larger than the top. Figure 7f shows a hexagonal base and a hexagonal top with a smaller diameter. Figure 7g shows an embodiment having a hexagonal base and a smaller circular top. Figure 7h shows an embodiment having an elongated hexagonal base and a smaller elongated hexagonal top.

[0078] A three-dimensional microstructure 160 can be obtained by combining any of the previously disclosed cross-sections with the above-described base and / or base-top combinations. Preferred examples of the microstructure 160 are pyramidal structures, symmetrical pyramidal structures, elongated pyramidal structures, truncated pyramidal structures, platelets, nanowires, nanowires having pyramidal tops, or combinations thereof. These various three-dimensional microstructures can be obtained by SAG, through etching of the grown structure, or by combinations thereof. Examples of preferred microstructures 160 are described in SE537434C2.

[0079] Figures 8a–8f show a top view of the LED array precursor 10 and various embodiments of how the openings 142 having the LED structure are spaced across the LED array precursor 10. They can be packed in various regular patterns similar to those for close packing of circles, such as square packing or hexagonal packing. In Figures 8a, 8d, and 8e, the distribution of the openings 142 is based on a rectangular packing pattern. Figures 8b and 8c illustrate a hexagonal packing pattern. Other patterns may include wavy or curved rows, as shown in Figure 8f. The overall pattern of the LED array precursor 10 may be a combination of several patterns, which do not necessarily have to be continuous across the entire LED array precursor 10.

[0080] Independent of the pattern of apertures 142 having LED structures on the precursor 10, the LED structures can be made contact in different arrays and sub-arrays by contacting a common electrode contact material 180. The grouping of individual LEDs into arrays can be based on various parameters of the LED structure, such as the dominant wavelength and / or polarization of the emitted light. Figures 8a and 8b show the grouping of multi-row and multi-column LED structures into arrays for configurations based on square packing and hexagonal packing, respectively. Since only an excerpt of the entire LED array precursor 10 is shown, the precursor may have several of the illustrated arrays.

[0081] Figure 8c shows a subarray created by grouping single-row LED structures with the underlying hexagonal-packed aperture 142. Figure 8c further shows contact between individual LED structures. Figure 8d illustrates the grouping of LED structures in subarrays of different sizes with respect to the underlying square-packed aperture 142. The grouping motif in Figure 8e shows that LED structures in a single row and / or column may not be in contact at all. Figure 8f shows the grouping of LED structures for wavy and bent patterns.

[0082] Different packaging and contact patterns can be used to compensate for optical aberrations that may occur when assembling LED arrays into a device. This reduces system complexity, which is advantageous for manufacturing smaller and lighter devices. In particular, in applications with curved light extraction or projection surfaces, positioning with wavy, bent, or other distorted patterns can be advantageous.

[0083] When used herein, the expressions “can be obtained” and “in some embodiments” are typically used to indicate that the described features may be combined with any other embodiments disclosed herein.

[0084] When the terms “to have” or “to possess” are used, they are to be interpreted as non-restrictive, that is, as meaning “to consist of at least ~”.

[0085] The embodiments described herein are not limited to those described above. Various substitutions, modifications, and equivalents may be used. Accordingly, the embodiments described above should not be construed as limiting the scope of this disclosure as defined by the appended claims.

Claims

1. A method for forming a light-emitting diode (LED) array precursor (10), (i) A step of preparing the substrate (100), (ii) A step of forming one or more first layers (120) on the epitaxial surface side (102) of the substrate (100), wherein the one or more first layers (120) have at least a first semiconductor layer (120b), and if present, one or more further first layers (120) further have a buffer layer (120a) laminated between the substrate (100) and the first semiconductor layer (120b), (iii) A step of selectively masking one or more first layers (120) by depositing one or more masking layers (140) on them, wherein the unmasked portions of the one or more first layers (120) form a plurality of openings (142), (iv) A step of forming a microstructure (160) within at least a portion of the plurality of openings (142), wherein the microstructure (160) is in physical contact with the first semiconductor layer (120b), (v) A step of forming one or more active layers (162) that at least partially cover the microstructure (160), (vi) A step of forming a second semiconductor layer (164) that at least partially covers the microstructure (160) and / or the one or more active layers (162), (vii) A step of forming both an anode and a cathode electrical contact (180a, b) on the epitaxial surface side (102) of the substrate (100), A method of having.

2. The step (vii) of forming both anode and cathode electrical contacts (180a, b) on the epitaxial surface side (102) of the substrate (100) is as follows: (vii.i) Deposit one or more additional masking layers (140a) on the epitaxial surface side (102), (vii.iii) Pattern the further masking layer (140a) by selectively removing multiple portions of the further masking layer (140a) to create a further opening (142a), where at least a portion of the further opening (142a) has a microstructure (160) formed under step (iv). (vii.iii) Deposit the electrode contact material (180) onto the patterned masking layer (140a), (vii.iv) Optionally, remove at least a portion of the excess electrode contact material (180) and / or masking layer (140a). The method according to claim 1, wherein the method is as follows:

3. The method according to claim 1 or 2, wherein the microstructure (160) is one or more of the following: a pyramidal structure, a symmetrical pyramidal structure, an elongated pyramidal structure, a truncated pyramidal structure, a platelet, a nanowire, a nanowire having a pyramidal apex, an etched structure, or any combination thereof.

4. The method according to any one of claims 1 to 3, wherein the active layer (162) has one or more quantum structures such as a quantum well, a quantum dot, a quantum wire, or a combination thereof.

5. The method according to claim 4, wherein the quantum structure comprises GaN, AlN, InN, and / or ternary and quaternary compounds thereof.

6. The method according to any one of claims 1 to 5, further comprising the step of removing at least partially the substrate (100) from the LED array precursor (10) or partially removing the substrate (100) and the first layer (120).

7. The method according to any one of claims 1 to 6, further comprising the step of chemically, physically, and / or mechanically bonding the electrical contact material (180) to the corresponding bonding pad (220) of the backplane (20), thereby bringing both the anode and cathode electrical contacts (180a, b) into electrical contact with the secondary electrical contacts of the backplane (20), thereby forming an electrical contact between at least a portion of the anode and cathode electrical contacts (180a, b) of the LED array precursor (10) and the backplane (20).

8. The method according to claim 7, wherein the electrical contact between the LED array precursor (10) and the backplane (20) is formed via a metal bump (240).

9. The method according to claim 7 or 8, further comprising the step of filling the gap between the LED array precursor (10) and the backplane (20) with a filler material (300).

10. An LED array precursor (10) obtained by the method according to any one of claims 1 to 9.

11. (i) One or more first layers (120), having at least a first semiconductor layer (120b), and if present, one or more further first layers (120) being buffer layers (120a), (ii) Optionally, a masking layer (140) that at least partially covers one or more of the first layers (120), the masking layer (140) having a plurality of openings (142), (iii) A microstructure (160) located on the first semiconductor layer (120b) within at least a portion of the opening (142) of the masking layer (140) and in physical contact with the first semiconductor layer (120b), (iv) One or more active layers (162) that at least partially cover the microstructure (160), (v) A second semiconductor layer (164) that at least partially covers the microstructure (160) and / or the active layer (162), (vi) Anode and cathode electrical contacts (180a, b), both of which are provided on the epitaxial surface side (102), An LED array precursor (10) having the following features.

12. A substrate (100) having (i), (ii), (iii), (iv), (v), and (vi) on the epitaxial surface side, The LED array precursor (10) according to claim 11, having the following features.

13. The LED array precursor (10) according to claim 11 or 12, wherein both the anode and cathode electrical contacts (180a, b) of (vii) on the epitaxial surface (102) are formed within at least a portion of a further opening (142a) formed within a further masking layer (140a), and at least a portion of the further opening (142a) has the microstructure (160) of (iv).

14. An LED array having an LED array precursor (10) according to any one of claims 11 to 13, wherein at least a portion of both the anode and cathode electrical contacts (180a, b) is in electrical contact with a secondary electrical contact of a backplane (20).

15. A display device, communication device, optoelectronic device, interconnection device, encryption device, lighting device, or illumination device having the LED array described in claim 14 or the LED array precursor (10) described in any one of claims 10 to 13.

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