Transmit (TX) Receive (RX) Phased Array System

Abstract

A millimeter-wave (mmW) communication system arranged on a millimeter-wave integrated circuit (MMW-IC) includes a phase shifter selectively connected to a receiving path by a first electromagnetic (EM) element and selectively connected to a transmitting path by a second EM element; a first EM element configured to receive a transmit signal and a received signal from a low-noise amplifier (LNA); and a second EM element configured to receive a phase-shifted transmit signal or a phase-shifted received signal from the phase shifter, wherein the second EM element is configured to selectively provide the phase-shifted transmit signal to a power amplifier on the mmW-IC and the phase-shifted received signal to a received signal processing circuit located away from the mmW-IC.

Description

Technical Field

[0001]

[0001] This disclosure generally relates to electronic devices, and more particularly, to phase shifters of transceivers.

Background Art

[0002]

[0002] Wireless communication devices and technologies are becoming increasingly popular as communication devices operating at millimeter wave (mmW) and sub-terahertz (subTHz) frequencies. Wireless communication devices generally transmit and / or receive communication signals. In a radio frequency (RF) transceiver, the communication signal is typically amplified by a transmission section, transmitted, and the received communication signal is amplified and processed by a reception section. Transceivers for communication in 5G and 6G applications may communicate using millimeter wave (mmW) frequency signals and / or subTHz frequencies, and may use what is called a zero intermediate frequency (ZIF) architecture or a low IF architecture.

[0003]

[0003] Transceivers used in 5G communication systems may use what is called beamforming to increase system capacity. Beamforming generally uses individual transmit and receive elements where a phase shifter changes the phase of a signal. Typically, many such elements and phase shifters are implemented in such a system. Typically, each TX / RX element uses two phase shifters, one for transmission and one for reception.

[0004]

[0004] A typical system architecture may implement four phase shifters for two adjacent TX / RX elements. Each phase shifter may include a hybrid quadrature phase generator (HQG) and a coupling circuit, and as a result, may occupy a large area on the circuit.

[0005]

[0005] Therefore, in such a system, it is desirable to minimize the number of phase shifters. [Overview of the project]

[0006]

[0006] The various implementations of the systems, methods, and devices within the appended claims each have several aspects, and none of them alone bring about the desirable attributes described herein. Without limiting the scope of the appended claims, several notable features are described herein.

[0007]

[0007] Details of one or more implementations of the subject matter described herein are shown in the accompanying drawings and the following description. Other features, embodiments, and advantages will become apparent from the description, drawings, and claims. Note that the relative dimensions in the following figures may not be drawn to exact scale.

[0008]

[0008] One aspect of the present disclosure provides a millimeter-wave (mmW) communication system arranged on a millimeter-wave integrated circuit (MMW-IC), comprising: a phase shifter selectively connected to a receiving path by a first electromagnetic (EM) element and selectively connected to a transmitting path by a second EM element; a first EM element configured to receive a transmit signal and to receive a received signal from a low-noise amplifier (LNA); and a second EM element configured to receive a phase-shifted transmit signal or a phase-shifted receive signal from the phase shifter, wherein the second EM element is configured to selectively provide the phase-shifted transmit signal to a power amplifier on the mmW-IC and the phase-shifted receive signal to a received signal processing circuit located away from the mmW-IC.

[0009]

[0009] Another aspect of the present disclosure provides a method for phase-shifting a signal, comprising: selectively applying a transmit signal or a receive signal to a shared phase shifter; phase-shifting the transmit signal or the receive signal; and selectively applying the phase-shifted transmit signal to a power amplifier or selectively applying the phase-shifted receive signal to a phased array output.

[0010]

[0010] Another aspect of the present disclosure provides a device for signal phase shifting, comprising means for selectively applying a transmit signal or a receive signal to a shared phase shifter; means for phase shifting the transmit signal or the receive signal; and means for selectively applying the phase-shifted transmit signal to a power amplifier or selectively applying the phase-shifted receive signal to a phased array output.

[0011]

[0011] Another aspect of the present disclosure provides a phased array element comprising a receiving circuit, a transmitting circuit, a first electromagnetic (EM) element coupled to the receiving circuit, a second EM element coupled to the transmitting circuit, and a phase shifter coupled between the first EM element and the second EM element, wherein the phase shifter is configured to be shared by the receiving circuit and the transmitting circuit. [Brief explanation of the drawing]

[0012]

[0012] In the figures, unless otherwise indicated, the same reference numeral refers to the same part throughout the various figures. With respect to reference numerals that have a character code designation, such as "102a" or "102b", the character code designation can be used to distinguish between two similar parts or elements present in the same figure. If a reference numeral is intended to encompass all parts that have the same reference numeral in all figures, the character code designation for the reference numeral may be omitted. [Figure 1]

[0013] This diagram shows a wireless device communicating with a wireless communication system. [Figure 2A]

[0014] Block diagram showing a wireless device in which exemplary techniques of this disclosure may be implemented. [Figure 2B]

[0015] Block diagram showing a wireless device in which exemplary techniques of this disclosure may be implemented. [Figure 2C]

[0016] Block diagram showing a wireless device in which exemplary techniques of this disclosure may be implemented. [Figure 3]

[0017] This is a block diagram of the two transmit (TX) and receive (RX) elements in a phased array system. [Figure 4]

[0018] Figures 4A and 4B are schematic diagrams of the tricoil embodiment shown in Figure 3. [Figure 5]

[0019] Figures 5A and 5B are schematic diagrams of the tricoil embodiment shown in Figure 3. [Figure 6]

[0020] This is a flowchart illustrating an example of how a method for processing signals works. [Figure 7]

[0021] This is a functional block diagram of a device for processing signals. [Modes for carrying out the invention]

[0013]

[0022] The term “exemplary” is used herein to mean “serving as an example, case, or illustration.” No embodiment described herein as “exemplary” should be construed as necessarily preferable or advantageous to any other embodiment.

[0014]

[0023] According to an exemplary embodiment, the TX / RX radio architecture has a single phase shifter that can be shared between the transmitting and receiving elements, thus reducing the circuit area.

[0015]

[0024] According to an exemplary embodiment, the TX / RX radio architecture has a unidirectionally implemented phase shifter, and the transmit and receive signals are selectively routed through the phase shifter.

[0016]

[0025] According to an exemplary embodiment, the TX / RX wireless architecture uses one or more tricoil electromagnetic (EM) structures to combine signals including switching that provides impedance matching and reduces the load on the transmit and receive elements.

[0017]

[0026] According to an exemplary embodiment, the TX / RX wireless architecture can be single-ended in receive mode after the phase shifter.

[0018]

[0027] FIG. 1 is a diagram illustrating a wireless device 110 communicating with a wireless communication system 120. The wireless communication system 120 can be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, a Fifth Generation New Radio (5G NR) system, or some other wireless system. The CDMA system can implement Wideband CDMA (WCDMA), CDMA 1X, Evolution-Data Optimized (EVDO), Time Division-Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity, FIG. 1 shows the wireless communication system 120 including two base stations 130 and 132 and one system controller 140. In general, a wireless communication system can include any number of base stations and any set of network entities.

[0019]

[0028] Wireless device 110 may also be referred to as a user equipment (UE), mobile station, terminal, access terminal, subscriber unit, station, etc. Wireless device 110 can be a mobile phone, smartphone, tablet, wireless modem, personal digital assistant (PDA), handheld device, laptop computer, smartbook, netbook, tablet, cordless phone, medical device, automobile, a device configured to connect to one or more other devices (e.g., via the Internet of Things), a wireless local loop (WLL) station, a Bluetooth device, etc. Wireless device 110 can communicate with wireless communication system 120. Wireless device 110 can also receive signals from a broadcast station (e.g., broadcast station 134) and / or communicate with a satellite (e.g., satellite 150 in one or more global navigation satellite systems (GNSS), or a satellite capable of receiving signals from wireless device 110). Wireless device 110 can support one or more wireless technologies for wireless communication, such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11, 802.15, 5G, Sub6 5G, 6G, UWB, etc.

[0020]

[0029] Wireless device 110 can support carrier aggregation, for example, as described in one or more LTE or 5G standards. In some embodiments, for example, a single data stream is transmitted over multiple carriers using carrier aggregation, rather than using separate carriers for each data stream. Wireless device 110 can be capable of operating in various communication bands over a wide range of frequencies, including, for example, the communication bands used by LTE, WiFi, 5G, or other communication bands. Wireless device 110 can also be capable of communicating directly with other wireless devices without communicating via a network.

[0021]

[0030] Generally, carrier aggregation (CA) can be classified into two types: in-band CA and inter-band CA. In-band CA refers to operation on multiple carriers within the same bandwidth. Inter-band CA refers to operation on multiple carriers in different bandwidths.

[0022]

[0031] Figure 2A is a block diagram showing a wireless device 200 in which exemplary techniques of the present disclosure may be implemented. The wireless device 200 may be, for example, an embodiment of the wireless device 110 shown in Figure 1.

[0023]

[0032] Figure 2A shows one embodiment of a transceiver 220 having a transmitter 230 and a receiver 250. Generally, signal adjustment in the transmitter 230 and receiver 250 can be performed in one or more stages, such as amplifiers, filters, upconverters, and downconverters. These circuit blocks can also be arranged in a manner different from the configuration shown in Figure 2A. Furthermore, other circuit blocks not shown in Figure 2A can also be used to adjust signals in the transmitter 230 and receiver 250. Unless otherwise stated, any signals in Figure 2A or any other figures in the drawings can be either single-ended or differential. Some circuit blocks in Figure 2A can also be omitted.

[0024]

[0033] In the embodiment shown in Figure 2A, the wireless device 200 generally comprises a transceiver 220 and a data processor 210. The data processor 210 may include a processor 296 operably coupled to a memory 298. The memory 298 may be configured to store data and program code, as generally indicated using reference numeral 299, and may typically include analog and / or digital processing components. The processor 296 and the memory 298 may cooperate to control, set, program, or, in some cases, all or partly control some or all of the operation of the embodiments of the TX LO leakage calibration circuit described herein.

[0025]

[0034] The transceiver 220 includes a transmitter 230 and a receiver 250 that support bidirectional communication. Generally, the wireless device 200 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or part of the transceiver 220 can be mounted on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc.

[0026]

[0035] A transmitter or receiver can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is frequency-converted between radio frequency (RF) and baseband in multiple stages; for example, in the case of a receiver, the RF is frequency-converted to intermediate frequency (IF) in one stage, and then the IF is frequency-converted to baseband in another stage. In a direct conversion architecture, the signal is frequency-converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or may have different requirements. In the embodiment shown in Figure 2A, the transmitter 230 and receiver 250 are implemented using a direct conversion architecture.

[0027]

[0036] In the transmission path, the data processor 210 processes the data to be transmitted and provides the transmitter 230 with a common-phase (I) analog output signal and a quadrature-phase (Q) analog output signal. In an exemplary embodiment, the data processor 210 includes digital-to-analog converters (DACs) 214a and 214b for converting the digital signals generated by the data processor 210 into I analog output signals and Q analog output signals, such as I output current and Q output current, for further processing. In another embodiment, the DACs 214a and 214b are contained within the transceiver 220, and the data processor 210 provides the data (for example, relating to I and Q) digitally to the transceiver 220.

[0028]

[0037] Within transmitter 230, baseband (e.g., low-pass) filters 232a and 232b filter the I analog transmit signal and the Q analog transmit signal, respectively, to remove undesirable imagery caused by previous digital-to-analog conversion. Amplifiers (Amp) 234a and 234b amplify the signals from baseband filters 232a and 232b, respectively, supplying the I and Q baseband signals. An upconverter 240, having upconversion mixers 241a and 241b, uses the I TX LO and Q TX LO signals from the transmit (TX) local oscillator (LO) 290 to upconvert the I and Q baseband signals, providing the upconverted signals. Filter 242 filters the upconverted signals to remove undesirable imagery caused by frequency upconversion, as well as noise within the receive frequency band. A power amplifier (PA) 244 amplifies the signal from filter 242 to obtain the desired output power level, providing the transmit RF signal. The transmitted RF signal may be routed through a duplexer or switch 246 and transmitted via antenna 248. While the embodiments discussed herein utilize I and Q signals, those skilled in the art will understand that transceiver components may also be configured to utilize polar modulation.

[0029]

[0038] In the receiving path, antenna 248 receives the communication signal and provides the received RF signal. The received RF signal may be routed through a duplexer or switch 246 and provided to a low-noise amplifier (LNA) 252. The duplexer 246 is designed to operate with specific RX-TX duplexer frequency isolation so that the RX signal is isolated from the TX signal. To obtain the desired RF input signal, the received RF signal is amplified by the LNA 252 and filtered by filter 254.

[0030]

[0039] Downconversion mixers 261a and 261b within the downconverter 260 mix the output of filter 254 with the I RX LO signal and Q RX LO signal (i.e., LO_I and LO_Q) from the receiving (RX) LO signal generator 280 to generate the I baseband signal and Q baseband signal. The I baseband signal and Q baseband signal are amplified by amplifiers 262a and 262b and further filtered by low-pass filters 264a and 264b to obtain the I analog input signal and Q analog input signal, which are provided to the data processor 210. In the illustrated exemplary embodiment, the data processor 210 includes analog-to-digital converters (ADCs) 216a and 216b for converting the analog input signal into a digital signal that will be further processed by the data processor 210. In some embodiments, the ADCs 216a and 216b are contained within the transceiver 220 and provide the data to the data processor 210 digitally.

[0031]

[0040] In Figure 2A, the TX LO signal generator 290 generates the I TX LO signal and the Q TX LO signal used for frequency upconversion, while the RX LO signal generator 280 generates the I RX LO signal and the Q RX LO signal used for frequency downconversion. Each LO signal is a periodic signal with a specific fundamental frequency. The phase-locked loop (PLL) 292 receives timing information from the data processor 210 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the LO signal generator 290. Similarly, the PLL 282 receives timing information from the data processor 210 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the LO signal generator 280.

[0032]

[0041] The wireless device 200 may support carrier aggregation (CA) and may (i) receive multiple downlink signals transmitted by one or more cells on multiple downlink carriers at different frequencies, and / or (ii) transmit multiple uplink signals on multiple uplink carriers to one or more cells. However, those skilled in the art will understand that the embodiments described herein may be implemented in systems, devices and / or architectures that do not support carrier aggregation.

[0033]

[0042] Specific components of the transceiver 220 are shown in Figure 2A with respect to their function, and the configuration shown in this figure may or may not represent the physical device configuration in a particular implementation. For example, as mentioned above, the transceiver 220 can be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. In some embodiments, the transceiver 220 is implemented on a substrate or board, such as a printed circuit board (PCB) having various modules, chips, and / or components. For example, the power amplifier 244, filter 242, and duplexer 246 may be implemented in separate modules or as individual components, while the remaining components shown in the transceiver 220 may be implemented within a single transceiver chip.

[0034]

[0043] The power amplifier 244 may include one or more stages, including a driver stage, a power amplifier stage, or other components, which can be configured to amplify communication signals, for example, on one or more frequencies, within one or more frequency bands, and at one or more power levels. Depending on various factors, the power amplifier 244 may be configured to operate using one or more driver stages, one or more power amplifier stages, and one or more impedance matching networks, and may be configured to provide good linearity, efficiency, or a combination of good linearity and efficiency.

[0035]

[0044] In exemplary embodiments of the superheterodyne architecture, PA244 and LNA252 (and in some examples, filter 242 and filter 254) may be implemented separately from other components in the transmitter 230 and receiver 250, for example, on a millimeter-wave integrated circuit. An exemplary superheterodyne architecture is shown in Figure 2B.

[0036]

[0045] Figure 2B is a block diagram showing a wireless device in which exemplary techniques of the present disclosure may be implemented. Certain components of the wireless device 200a in Figure 2B, which may be indicated by, for example, the same reference numeral, can be configured in the same way as components in the wireless device 200 shown in Figure 2A, and the descriptions of items numbered identically in Figure 2B will not be repeated.

[0037]

[0046] Wireless device 200a is an embodiment of a heterodyne (or superheterodyne) architecture in which an upconverter 240 and a downconverter 260 are configured to process communication signals between the baseband and the intermediate frequency (IF). The IF signal may be a low IF (LIF) signal or a zero (or near-zero) IF (ZIF) signal. For example, the upconverter 240 may be configured to provide an IF signal to the upconverter 275. In an exemplary embodiment, the upconverter 275 may include an upconversion mixer 276. An summing function 278, which may be part of the upconverter 240, combines the I and Q outputs of the upconverter 240 to provide a non-orthogonal signal to the mixer 276. This non-orthogonal phase signal may be single-ended or differential. The mixer 276 is configured to receive the IF signal from the upconverter 240 and the TX RF LO signal from the TX RF LO signal generator 277, and to provide the upconverted RF signal to the phase shift circuit 281. Although PLL 292 is shown in Figure 2B as being shared by signal generators 290 and 277, a corresponding PLL could also be implemented for each signal generator. In the exemplary embodiment, the phase shift circuit configuration 281 may be part of or located on a millimeter-wave integrated circuit (mmW-IC).

[0038]

[0047] In exemplary embodiments, the components within the phase shift circuit 281 may include one or more adjustable or variable phased array elements that receive one or more control signals from the data processor 210 via connection 294 and operate the adjustable or variable phased array elements based on the received control signals.

[0039]

[0048] In an exemplary embodiment, the phase shift circuit 281 includes a phase shifter 283 and phased array elements 287. For ease of explanation, three phase shifters 283 and three phased array elements 287 are shown, but the phase shift circuit 281 may include more or fewer phase shifters 283 and phased array elements 287. For example, one or two arrays of four or five antennas and corresponding phase shifters / phased array elements may be implemented.

[0040]

[0049] Each phase shifter 283 may be configured to receive an RF transmit signal from the upconverter 275, change its phase by a certain amount, and provide the RF signal to its respective phased array element 287. Each phased array element 287 may include a transmit circuit and / or receive circuit, including one or more filters, amplifiers, driver amplifiers, and power amplifiers. In some embodiments, the phase shifters 283 may be incorporated within each phased array element 287.

[0041]

[0050] The output of the phase shift circuit configuration 281 is supplied to the antenna array 248. In an exemplary embodiment, the antenna array 248 typically includes a number of antennas corresponding to the number of phase shifters 283 and phased array elements 287, such that, for example, each antenna element is coupled to its respective phased array element 287. In an exemplary embodiment, the phase shift circuit configuration 281 and the antenna array 248 are referred to as a phased array.

[0042]

[0051] In the receiving direction, the output of the phase shift circuit 281 is provided to the downconverter 285. In an exemplary embodiment, the downconverter 285 may include a downconversion mixer 286. In an exemplary embodiment, the mixer 286 downconverts the received RF signal provided by the phase shift circuit 281 to an IF signal according to the RX RF LO signal provided by the RX RF LO signal generator 279. The I / Q generation function 291 in the downconverter 260 receives the IF signal from the mixer 286 and generates I and Q signals for the downconverter 260 to downconvert the IF signal to baseband as described above. The PLL 282 is shown in Figure 2B as being shared by the signal generators 280 and 279, but corresponding PLLs for each signal generator can also be implemented.

[0043]

[0052] In some embodiments, the upconverter 275, downconverter 285, and phase shift circuit 281 are mounted on a common IC. In some embodiments, the adder function 278 and I / Q generation function 291 are mounted separately from mixers 276 and 286, while the mixers 276, 286 and phase shift circuit 281 are mounted on a common IC (for example, the adder function 278 and I / Q generation function 291 are mounted in a separate IC coupled to the IC containing mixers 276, 286). In some embodiments, the LO signal generators 277 and 279 are included in a common IC. In some embodiments where the phase shift circuit configuration is mounted on a common IC comprising 276, 286, 277, 278, 279, and / or 291, the common IC and antenna array 248 are included in a module that can be coupled to other components of the transceiver 220 via connectors. In some embodiments, the phase shift circuit configuration 281, for example, the chip on which the phase shift circuit configuration 281 is mounted, is coupled to the antenna array 248 by an interconnect, or both are mounted on a substrate. For example, the components of the antenna array 248 may be mounted on a substrate and coupled to an integrated circuit that implements the phase shift circuit configuration 281 via a flexible printed circuit board, or the integrated circuit may be mounted on the opposite side of the substrate.

[0044]

[0053] In some embodiments, both the architecture shown in Figure 2A and the architecture shown in Figure 2B are implemented within the same device. For example, wireless device 110 or wireless device 200 may be configured to communicate with signals having frequencies below approximately 20 GHz using the architecture shown in Figure 2A, and to communicate with signals having frequencies above approximately 20 GHz using the architecture shown in Figure 2B. In devices implementing both architectures, one or more components of Figures 2A and 2B that are numbered identically may be shared between the two architectures. For example, both signals down-converted directly from RF to baseband and signals down-converted from RF to baseband via an IF stage may be filtered by the same baseband filter 264. In other embodiments, a first version of filter 264 is included in the part of the device implementing the architecture of Figure 2A, and a second version of filter 264 is included in the part of the device implementing the architecture of Figure 2B. While some exemplary frequencies are described herein, other implementations are possible. For example, signals having frequencies higher than approximately 20 GHz (e.g., having mmW frequencies) may be transmitted and / or received using a direct conversion architecture. In such embodiments, for example, a phased array may be implemented in the direct conversion architecture.

[0045]

[0054] Figure 2C is a block diagram showing a wireless device in which exemplary techniques of the present disclosure may be implemented. Certain components of the wireless device 200b in Figure 2C, for example, which may be indicated by the same reference numeral, may be configured similarly to components in the wireless device 200 shown in Figure 2A and / or the wireless device 200a shown in Figure 2B, and the descriptions of items numbered identically in Figure 2C will not be repeated.

[0046]

[0055] The wireless device 200b in Figure 2C incorporates the phase shift circuit 281 (Figure 2B) into a direct conversion architecture, so that the mmW transmit signal is upconverted and downconverted between baseband and RF without using intermediate frequency (IF) signal conversion. For example, the LO signal in the architecture of Figure 2C may have a signal at a frequency of several tens of GHz.

[0047]

[0056] In some embodiments, the upconverter 240, downconverter 260, and phase shift circuit 281 are mounted on a common IC. In some embodiments, the LO signal generators 280, 290 are included within the common IC. In some embodiments, the common IC and antenna array 248 are included in a module that can be coupled to other components of the transceiver 220 via connectors. In some embodiments, the phase shift circuit configuration 281, for example, the chip on which the phase shift circuit configuration 281 is mounted, is coupled to the antenna array 248 by an interconnect, or both are mounted on a substrate. For example, the components of the antenna array 248 may be mounted on a substrate and coupled to an integrated circuit that implements the phase shift circuit configuration 281 via a flexible printed circuit board, or the integrated circuit may be mounted on the opposite side of the substrate.

[0048]

[0057] Figure 3 is a block diagram 300 of two transmit (TX) and receive (RX) elements in a phased array system, which may, for example, be included in a phase-shift circuit 281. The elements in Figure 300 may be arranged on a millimeter-wave integrated circuit (mmW-IC). A first element 310, which may be an example of a phased array element 287, may include an electromagnetic (EM) element 312 configured to couple the TX and RX paths of the first element 310 to an antenna or antenna port 311. In an exemplary embodiment, the EM element 312 may include a first inductive element 313, a second inductive element 314, and a third inductive element 315. When the EM element 312 is implemented as a transformer (or as a magnetic circuit called a tricoil), the first inductive element 313 may be the primary side (or primary coil), the second inductive element 314 may be the secondary side (or secondary coil), and the third inductive element 315 may be the tertiary coil. In exemplary embodiments, the terms primary, secondary, and tertiary are not intended to indicate signal direction, as the transmitted signal may traverse the EM element 312 in a direction opposite to that of the received signal.

[0049]

[0058] In exemplary embodiments, the first element 310 may also comprise a power amplifier (PA) 318, a driver amplifier (DA) 319, and an EM element 328. In some embodiments, three or more stages of transmit signal amplification may be implemented. In exemplary embodiments, the EM element 328 may comprise a first inductive element 332, a second inductive element 331, and a third inductive element 329. When the EM element 328 is implemented as a transformer (or as a magnetic circuit called a tricoil), the first inductive element 332 may be the primary side (or primary coil), the second inductive element 331 may be the secondary side (or secondary coil), and the third inductive element 329 may be the tertiary coil. In exemplary embodiments, the third inductive element 329 may comprise switches 333 and 335 located on either side of and near the center tap of the third inductive element 329. In exemplary embodiments, the center tap may be connected to a bias voltage Vbias.

[0050]

[0059] In exemplary embodiments, the first element 310 may also comprise an RX circuit including a first-stage low-noise amplifier (LNA) 316 and a second-stage LNA 317, but different numbers of LNA stages may be implemented. The output of the second-stage LNA 317 may be provided to the EM element 321. In exemplary embodiments, the EM element 321 may comprise a first inductive element 322, a second inductive element 323, and a third inductive element 324. When the EM element 321 is implemented as a transformer (or as a magnetic circuit called a tricoil), the first inductive element 322 may be the primary side (or primary coil), the second inductive element 323 may be the secondary side (or secondary coil), and the third inductive element 324 may be the tertiary coil. In exemplary embodiments, the terms primary, secondary, and tertiary are not intended to indicate signal direction, as a transmitted signal may traverse the EM element 321 such that the first inductive element 322 may be considered a primary coil and the third inductive element 324 a secondary coil. However, a received signal may traverse the EM element 321 such that the second inductive element 323 may be considered a primary coil and the third inductive element 324 a secondary coil. In exemplary embodiments, the side of the second inductive element 323 opposite to the second stage LNA 317 may be connected to the system voltage VDD. In exemplary embodiments, the first inductive element 322 may include switches 325 and 327 located on either side of and near the center tap of the first inductive element 322. In exemplary embodiments, the center tap may be connected to the system voltage VDD.

[0051]

[0060] In an exemplary embodiment, the first element 310 includes a phase shifter 320 coupled between EM elements 321 and 328. While the phase shifter 320 is shown comprising a hybrid quadrature generator (HQG) 340 and variable gain amplifiers (VGAs) 334 and 336, other implementations of the phase shifter may be used. For example, a phase shifter having a polyphase filter and active or passive VGAs may be implemented. In an exemplary embodiment, the HQG 340 may be configured to generate in-phase (I) and quadrature (Q) signals separated by 90 degrees. For example, the VGA 334 may be configured to operate with the in-phase signal, and the VGA 336 may be configured to operate with the quadrature signal. In an exemplary embodiment, a vector modulator driver (VMDR) 326 may be coupled to the EM element 321 and configured to operate with the transmit signal, for example, by providing a differential transmit signal across the inductive element 322.

[0052]

[0061] In an exemplary embodiment, the output of VGA 334 is provided on both sides of inductor element 332, and the output of VGA 336 is provided on both sides of inductor element 332 of EM element 328. In an exemplary embodiment, switch 337 may be connected between one end of inductor element 331 and ground, and switch 338 may be connected between the other end of inductor element 331 and ground. Switch 338 may be controlled by the control signal Rx_en, and switch 337 may be controlled by the control signal Rx_enb, such that when switch 337 is conducting, switch 338 is non-conducting, and when switch 337 is conducting, switch 338 is non-conducting. Complementary control signals Rx_en and Rx_enb may be provided by a data processor (210, Figure 2C) or by another controller.

[0053]

[0062] A second element 350, which may be another example of the phased array element 287, may comprise a TX path of the second element 350 and an electromagnetic (EM) element 352 configured to couple the TX path to an antenna or antenna port 351. In exemplary embodiments, the EM element 352 may comprise a first inductive element 353, a second inductive element 354, and a third inductive element 355. If the EM element 352 is implemented as a transformer (or as a magnetic circuit called a tricoil), the first inductive element 353 may be the primary side (or primary coil), the second inductive element 354 may be the secondary side (or secondary coil), and the third inductive element 355 may be the tertiary coil. In exemplary embodiments, the terms primary, secondary, and tertiary are not intended to indicate signal direction, as the transmitted signal may traverse the EM element 352 in the opposite direction to the received signal.

[0054]

[0063] In exemplary embodiments, the second element 350 may also comprise a power amplifier (PA) 358, a driver amplifier 359, and an EM element 368. In some embodiments, three or more stages of transmit signal amplification may be implemented. In exemplary embodiments, the EM element 368 may comprise a first inductive element 372, a second inductive element 371, and a third inductive element 369. When the EM element 368 is implemented as a transformer (or as a magnetic circuit called a tricoil), the first inductive element 372 may be the primary side (or primary coil), the second inductive element 371 may be the secondary side (or secondary coil), and the third inductive element 399 may be the tertiary coil. In exemplary embodiments, the third inductive element 369 may comprise switches 373 and 375 located on either side of and near the center tap of the third inductive element 369. In exemplary embodiments, the center tap may be connected to a bias voltage Vbias.

[0055]

[0064] In exemplary embodiments, the second element 350 may also comprise an RX circuit including a first-stage low-noise amplifier (LNA) 356 and a second-stage LNA 357, although different numbers of LNA stages may be implemented. The output of the second-stage LNA 357 may be provided to the EM element 361. In exemplary embodiments, the EM element 361 may comprise a first inductive element 362, a second inductive element 363, and a third inductive element 364. When the EM element 361 is implemented as a transformer (or as a magnetic circuit called a tricoil), the first inductive element 362 may be the primary side (or primary coil), the second inductive element 363 may be the secondary side (or secondary coil), and the third inductive element 364 may be the tertiary coil. In exemplary embodiments, the terms primary, secondary, and tertiary are not intended to indicate signal direction, as a transmitted signal may traverse the EM element 361 such that the first inductive element 362 may be considered a primary coil and the inductive element 364 a secondary coil. However, a received signal may traverse the EM element 361 such that the inductive element 363 may be considered a primary coil and the inductive element 364 a secondary coil. In exemplary embodiments, the side of the second inductive element 363 opposite to the second stage LNA 357 may be connected to the system voltage VDD. In exemplary embodiments, the first inductive element 362 may include switches 365 and 367 located on either side of and near the center tap of the first inductive element 362. In exemplary embodiments, the center tap may be connected to the system voltage VDD.

[0056]

[0065] In an exemplary embodiment, the second element 350 includes a phase shifter 370 coupled between EM elements 361 and 368. While the phase shifter 370 is shown comprising a hybrid quadrature generator (HQG) 380 and variable gain amplifiers (VGAs) 374 and 376, other implementations of the phase shifter may be used. For example, a phase shifter having a polyphase filter and active or passive VGAs may be implemented. In an exemplary embodiment, the HQG 380 may be configured to generate in-phase (I) and quadrature (Q) signals separated by 90 degrees. For example, VGA 374 may be configured to operate with the in-phase signal, and VGA 376 may be configured to operate with the quadrature signal. In an exemplary embodiment, a vector modulator driver (VMDR) 366 may be coupled to EM element 361 and configured to operate with the transmit signal, for example, by providing a differential transmit signal across the inductive element 362.

[0057]

[0066] In an exemplary embodiment, the output of VGA 374 is provided on both sides of inductor element 372, and the output of VGA 376 is provided on both sides of inductor element 372 of EM element 368. In an exemplary embodiment, switch 377 may be connected between one end of inductor element 371 and ground, and switch 378 may be connected between the other end of inductor element 371 and ground. Switch 378 may be controlled by the control signal Rx_en, and switch 377 may be controlled by the control signal Rx_enb, such that when switch 377 is conducting, switch 378 is non-conducting, and when switch 377 is conducting, switch 378 is non-conducting. Complementary control signals Rx_en and Rx_enb may be provided by a data processor (210, Figure 2C) or by another controller.

[0058]

[0067] In exemplary embodiments, the transmit (TX) signal may be provided to VMDRs 326 and 366 via connections 341a and 341b. In the illustrated example, the TX signal is provided over a connection shared by elements 310 and 350, but in other examples, each of elements 310 and 350 may be coupled to the same or separate transmit signal via their respective connections. In exemplary embodiments, the TX signal may be a differential signal, but in other embodiments, it is a single-ended TX signal. Connection 341 may be coupled to upconverter 240 or 275. In exemplary embodiments, the transmit path within element 310 may be indicated using arrow 344, and in exemplary embodiments, the transmit path 344 includes VMDR 326, EM element 321, HQG 340, VGAs 334 and 336, EM element 328, driver amplifier 319, PA 318, and EM element 312. In an exemplary embodiment, the transmission path within element 350 may be indicated using arrow 384, in which the transmission path 384 includes VMDR 366, EM element 361, HQG 380, VGA 374 and 376, EM element 368, driver amplifier 359, PA 358, and EM element 352.

[0059]

[0068] In exemplary embodiments, the received signal may be provided to downstream processing elements via connection 342, for example, via a phased array output. In exemplary embodiments, the RX signal may be a differential signal or a single-ended signal. In exemplary embodiments, the received signal may be a single-ended signal. In the illustrated example, the RX signal is provided on a connection shared by elements 310 and 350, but in other examples, each of elements 310 and 350 may provide a transmit signal via its respective connection. Connection 342 may be coupled to a downconverter 260 or 285. In exemplary embodiments, the receive path within element 310 may be indicated using arrow 345, and in exemplary embodiments, the receive path 345 comprises EM element 312, LNA 316, second stage LNA 317, EM element 321, HQG 340, VGA 334 and 336, EM element 328, and connection 342. In exemplary embodiments, the receiving path within element 350 may be indicated using arrow 385, in which the receiving path 385 comprises EM element 352, LNA 356, second stage LNA 357, EM element 361, HQG 380, VGA 374 and 376, EM element 368, and connection 342. In exemplary embodiments, the transmitting path 344 and the receiving path 345 follow the same path (in the same direction) through the phase shifter 320, and the transmitting path 384 and the receiving path 385 follow the same path (in the same direction) through the phase shifter 370.

[0060]

[0069] Figures 4A and 4B are schematic diagrams of exemplary embodiments of the tricoil embodiment of Figure 3. In Figure 4A, the tricoil 400 may be an example of the EM element 321 or EM element 361 of Figure 3. In the exemplary embodiment, the tricoil 400 may comprise a first winding 402 coupled to the source of the transmitted signal (e.g., via VMDR 326 or 366), a second winding 403 coupled to an LNA (e.g., a second stage LNA 317 or 357), and a third winding 404 coupled to a phase shifter input (e.g., a phase shifter 320 or 370). In exemplary embodiments, the first winding 402 may correspond to a first inductive element 322 or 362 (Figure 3), the second winding 403 may correspond to a second inductive element 323 or 363 (Figure 3), and the third winding 404 may correspond to a third inductive element 324 or 364 (Figure 3).

[0061]

[0070] In an exemplary embodiment, the tricoil 400 also includes switches 412 and 414 located in the first winding 402. In the exemplary embodiment, switches 412 and 414 may correspond to switches 325 / 365 and 327 / 367 in Figure 3. Node 415 between switches 412 and 414 may be connected to the system voltage VDD. In the exemplary embodiment, the first winding 402, the second winding 403, and the third winding 404 are shown as monocoils having a substantially rectangular shape, however, the first winding 402, the second winding 403, and the third winding 404 can be manufactured using different numbers of turns and may have different shapes, such as square, hexagonal, octagonal, or other shapes.

[0062]

[0071] In exemplary embodiments, switches 412 and 414 may be P-type complementary metal-oxide-semiconductor (PMOS) switches, while in other embodiments, switches 412 and 414 may be N-type MOS (NMOS) switches or switches fabricated using other manufacturing techniques. In exemplary embodiments, switches 412 and 414 may be controlled by control signals from the data processor 210 or another controller. In exemplary embodiments, switches 412 and 414 may be configured to selectively change the impedance of the first winding 402 when in transmit mode or receive mode. For example, in receive mode, switches 412 and 414 may be open so that a high impedance is presented to the second stage LNA 317 (or 357) and HQG 340 (or 380). In transmit mode, switches 412 and 414 may be closed so that the transmit signal is transferred from the first winding 402 to the third winding 404.

[0063]

[0072] In exemplary embodiments, the placement of switches 412 and 414 in the first winding 402 near node 415, which has the system voltage VDD, may add little to no parasitic losses to differential mode signals. Placing switches 412 and 414 near node 415 (for example, near the center tap of the first winding 402 rather than the outer terminals of the first winding 402 connected to VMDR 326 or 366) reduces or avoids any differential parasitic capacitance from switches 412 and 414 loading VMDR 326 in differential mode.

[0064]

[0073] In exemplary embodiments, VMDRs 326 and 366 operate at a sufficiently low current so that switches 412 and 414 have a moderate resistance of, for example, 1 to 2 ohms, without causing a reduction in voltage headroom that could adversely affect signal quality.

[0065]

[0074] In an exemplary embodiment, when switches 412 and 414 are located near node 415 and are in a non-conducting state, the parasitic components of the switches resonate through the inductance of the first winding 402, which helps to maintain a relatively high off-impedance for switches 412 and 414.

[0066]

[0075] In an exemplary embodiment, the second stage LNA 317 has a very high off-impedance, which reduces or minimizes the load on the second stage LNA 317 presented to the transmitting circuit in the first element 310.

[0067]

[0076] In an exemplary embodiment, in RX mode, switches 412 and 414 are in a non-conductive state, thus allowing the received signal to easily pass from the second winding 403 to the third winding 404.

[0068]

[0077] In an exemplary embodiment, in TX mode, LNA 316 and the second stage LNA 317 are off, and switches 412 and 414 are in a conductive state to facilitate the transmission of the transmit signal from the first winding 402 to the third winding 404.

[0069]

[0078] Figures 5A and 5B are schematic diagrams of exemplary embodiments of the tricoil embodiment of Figure 3. In Figure 5A, the tricoil 500 may be an example of the EM element 328 or EM element 368 of Figure 3. In the exemplary embodiment, the tricoil 500 may comprise a first winding 502 coupled to the phase shifter output (e.g., phase shifter 320 or 370), a second winding 503 coupled to the receiving network (e.g., connection 342 and other downstream circuits), and a third winding 504 coupled to the PA (e.g., via DA 319 or 359, e.g., PA 318 or 358). In exemplary embodiments, the first winding 502 may correspond to a first inductor element 332 or 372 (Figure 3), the second winding 503 may correspond to a second inductor element 331 or 371 (Figure 3), and the third winding 504 may correspond to a third inductor element 329 or 369 (Figure 3).

[0070]

[0079] In an exemplary embodiment, the tricoil 500 also comprises switches 512 and 514 located on the third winding 504 and switches 522 and 524 located on the second winding 503. In the exemplary embodiment, switches 512 and 514 may correspond to switches 333 / 373 and 335 / 375 in Figure 3, and switches 522 and 524 may correspond to switches 337 / 377 and 338 / 378. A node 515 between switches 512 and 514 may be connected to a bias voltage Vbias. In the exemplary embodiment, the first winding 502, the second winding 503, and the third winding 504 are shown as monocoils having a substantially rectangular shape, but the first winding 502, the second winding 503, and the third winding 504 can be manufactured using different numbers of turns and may have different shapes, such as square, hexagonal, octagonal, or other shapes.

[0071]

[0080] In exemplary embodiments, switches 512 and 514 may be P-type complementary metal-oxide-semiconductor (PMOS) switches, but in other embodiments, switches 512 and 514 may be N-type MOS (NMOS) switches or switches manufactured using other manufacturing techniques. Similarly, switches 522 and 524 may be P-type complementary metal-oxide-semiconductor (PMOS) switches, but in other embodiments, switches 522 and 524 may be N-type MOS (NMOS) switches or switches manufactured using other manufacturing techniques. In exemplary embodiments, switches 512, 514, 522, and 524 may be controlled by control signals from the data processor 210 or another controller to selectively change the impedance of the second winding 503 and the third winding 504.

[0072]

[0081] In exemplary embodiments, the positions of switches 512 and 514 in the third winding 504, and switches 522 and 524 in the second winding 331, may add little or no parasitic loss or load to the differential mode signal, as described above. In exemplary embodiments, switch 522 is located near the lowest differential mode voltage swing point and does not add capacitive parasitic loss to the second winding 503. Optimally, switch 524 may be significantly smaller (more than 1 / 5 the size) than switch 522 to maintain the desired isolation between the first winding 502 and the second winding 503 in transmit mode, while presenting minimal load to the second winding 503.

[0073]

[0082] In an exemplary embodiment, there is no DC current on the gate of the driver amplifier 319 (Figure 3), and as a result, the NMOS switches implemented as switches 512 and 514 each operate as level-shift switches. For example, in TX mode, switches 512 and 514 have drain-source voltages that are the same as the gate-source voltage of the driver amplifier 319 (Figure 3). Therefore, switches 512 and 514 are turned on using the gate voltage of VDD plus the gate-source voltage of the driver amplifier 319 (Figure 3).

[0074]

[0083] In an exemplary embodiment, in RX mode, switches 512 and 514 are in a non-conducting state, switch 524 is in a non-conducting state, and switch 522 is in a conductive state, thus allowing the received signal to easily pass from the first winding 502 to the second winding 503. Switches 522 and 524 are controlled complementaryly by complementary control signals Rx_en and Rx_enb.

[0075]

[0084] In an exemplary embodiment, in TX mode, LNA 316 (or 356) and the second stage LNA 317 (or 357) are off, switches 512 and 514 are conducting, switch 524 is conducting, and switch 522 is not conducting. Switches 522 and 524 are controlled complementaryly by complementary control signals Rx_en and Rx_enb.

[0076]

[0085] Figure 6 is a flowchart 600 illustrating an example of the operation of a method for processing signals. The blocks in method 600 can be executed in the order shown or in a different order, and in some embodiments they can be executed at least partially in parallel.

[0077]

[0086] In block 602, a transmit signal (e.g., mmW) or a receive signal (e.g., mmW) is selectively applied to the phase shifter. For example, EM element 321, which may be configured as a tricoil, may be configured to apply a transmit signal from VMDR 326 to HQG 340, or EM element 321 may be configured to selectively apply a receive signal from a second stage LNA 317 to HQG 340.

[0078]

[0087] In block 604, the transmitted or received signal is phase-shifted by a shared phase shifter. For example, the transmitted or received signal may be phase-shifted by HQG 340 and variable gain amplifiers (VGAs) 334 and 336.

[0079]

[0088] In block 606, the phase-shifted transmit signal is selectively applied to the power amplifier, or the phase-shifted receive signal is selectively applied to the phased array output. For example, in transmit mode, the transmit signal may be applied to the driver amplifier 319 by an EM element 328 which may be configured as a tricoil, or the receive signal may be selectively applied to connection 342 by an EM element 328 for further processing.

[0080]

[0089] Figure 7 is a functional block diagram of the device 700 for processing signals. The device 1700 includes means 702 for selectively applying a transmitted or received signal to means for phase-shifting. In a particular embodiment, means 702 for selectively applying a transmitted or received signal to means for phase-shifting may be configured to perform one or more of the functions described in the operation block 602 of method 600 (Figure 6). In an exemplary embodiment, means 702 for selectively applying a transmitted or received signal to means for phase-shifting may include an EM element 321 which can be configured as a tricoil.

[0081]

[0090] The apparatus 700 may also include a shared means 704 for phase-shifting a transmitted or received signal. In a particular embodiment, the shared means 704 for phase-shifting a transmitted or received signal may be configured to perform one or more of the functions described in the operation block 604 of Method 600 (Figure 6). In an exemplary embodiment, the shared means 704 for phase-shifting a transmitted or received signal may comprise an HQG 340 and variable gain amplifiers (VGAs) 334 and 336.

[0082]

[0091] The apparatus 700 may also include means 706 for selectively applying a transmit signal to a power amplifier or selectively applying a receive signal to a phased array output. In certain embodiments, means 706 for selectively applying a transmit signal to a power amplifier or selectively applying a receive signal to a phased array output may be configured to perform one or more of the functions described in the operation block 606 of method 600 (Figure 6). In exemplary embodiments, means 706 for selectively applying a transmit signal to a power amplifier or selectively applying a receive signal to a phased array output may include an EM element 312 which can be configured as a tricoil.

[0083]

[0092] Implementation examples are described in the following numbered clauses.

[0093] 1. A millimeter-wave (mmW) communication system arranged on a millimeter-wave integrated circuit (MMW-IC), comprising: a phase shifter selectively connected to a receiving path by a first electromagnetic (EM) element and selectively connected to a transmitting path by a second EM element; a first EM element configured to receive a transmitted signal and to receive a received signal from a low-noise amplifier (LNA); and a second EM element configured to receive a phase-shifted transmitted signal or a phase-shifted received signal from the phase shifter, wherein the second EM element is configured to selectively provide the phase-shifted transmitted signal to a power amplifier on the mmW-IC and the phase-shifted received signal to a received signal processing circuit located away from the mmW-IC.

[0094] 2. The communication system according to Clause 1, wherein the first EM element comprises a first winding, a second winding, and a third winding, and the first winding comprises a switch configured to change the impedance of the first winding.

[0095] 3. The communication system according to Clause 1 or 2, wherein the second EM element comprises a first winding, a second winding, and a third winding, the second winding comprising a switch configured to change the impedance of the second winding, and the third winding comprising a switch configured to change the impedance of the third winding.

[0096] 4. In receiving mode, the switch of the first winding is configured to be in a non-conductive state in order to present high impedance to the second and third windings, as described in Clause 2.

[0097] 5. The communication system according to Clause 2, wherein in transmission mode, the switch of the first winding is configured to be conductive so that the transmission signal is transferred from the first winding to the third winding.

[0098] 6. The communication system according to any one of clauses 2, 4, or 5, wherein the switch in the first winding is located near the center tap of the first winding to minimize parasitic losses to differential mode signals.

[0099] 7. The communication system described in Clause 3, wherein in receiving mode, the first switch in the second winding is selectively conductive, the second switch in the second winding is selectively non-conductive, and the switch in the third winding is non-conductive, allowing the received signal to pass from the first winding to the second winding.

[0100] 8. The communication system described in Clause 3, wherein in transmission mode, the first switch in the second winding is selectively conductive, the second switch in the second winding is selectively non-conductive, and the switch in the third winding is conductive, allowing the transmission signal to pass from the first winding to the third winding.

[0101] 9. The communication system according to any one of clauses 3, 7, or 8, wherein the switch in the third winding is located near the center tap of the third winding to minimize parasitic losses to differential mode signals.

[0102] 10. A method for phase-shifting a signal, comprising: selectively applying a transmitted signal or a received signal to a shared phase shifter; phase-shifting the transmitted signal or the received signal; selectively applying the phase-shifted transmitted signal to a power amplifier, or selectively applying the phase-shifted received signal to a phased array output. Methods that include...

[0103] 11. The method according to Clause 10, which includes selectively applying a transmitted or received signal to a shared phase shifter, and impedance matching.

[0104] 12. The method according to any one of the clauses 10 to 11, wherein selectively applying a received signal to a shared phase shifter includes selectively setting a switch in the first winding of the first EM element to a non-conducting state so that the received signal passes from the second winding in the first EM element to the third winding in the first EM element.

[0105] 13. The method according to any one of the clauses 10 to 12, wherein selectively applying a transmit signal to a shared phase shifter includes selectively setting a switch in the first winding of the first EM element to a conductive state so that the transmit signal passes from the first winding in the first EM element to the third winding in the first EM element.

[0106] 14. The method according to clause 12, wherein the switch in the first winding of the first EM element is located near the center tap of the first winding to minimize parasitic losses to the differential signal.

[0107] 15. The method according to Clause 10, wherein selectively applying a phase-shifted received signal to a phased array output includes selectively setting a complementary switch in the second winding of a second EM element to a conduction state and a deconduction state, and selectively setting a switch in the third winding of the second EM element to a deconduction state, such that the phase-shifted received signal passes from the first winding in the second EM element to the second winding of the second EM element.

[0108] 16. The method according to Clause 15, wherein selectively applying a phase-shifted transmit signal to a power amplifier includes selectively setting a complementary switch in the second winding of the second EM element to a conducted and deconducted state, and selectively setting a switch in the third winding of the second EM element to a conducted state, such that the phase-shifted transmit signal passes from the first winding of the second EM element to the third winding of the second EM element.

[0109] 17. The method according to any one of the clauses 15 to 16, wherein the switch in the third winding of the second EM element is located near the center tap of the third winding to minimize parasitic losses to the differential signal.

[0110] 18. A device for signal phase shifting, comprising: means for selectively applying a transmitted signal or a received signal to a shared phase shifter; means for phase shifting a transmitted signal or a received signal; and means for selectively applying a phase-shifted transmitted signal to a power amplifier or selectively applying a phase-shifted received signal to a phased array output.

[0111] 19. The device described in Clause 18, wherein means for selectively applying a transmitted or received signal to a shared phase shifter include means for impedance matching.

[0112] 20. The device according to any one of the clauses 18 to 19, wherein the means for selectively applying a received signal to a shared phase shifter includes means for selectively setting a switch in the first winding of the first EM element to a non-conducting state so that the received signal passes from the second winding in the first EM element to the third winding in the first EM element.

[0113] 21. The device according to any one of the clauses 18 to 20, wherein the means for selectively applying a transmit signal to a shared phase shifter includes means for selectively setting a switch in the first winding of the first EM element to a conductive state so that the transmit signal passes from the first winding in the first EM element to the third winding in the first EM element.

[0114] 22. The device described in Clause 20, wherein the switch in the first winding of the first EM element is located near the center tap of the first winding to minimize parasitic losses to the differential signal.

[0115] 23. The device according to Clause 18, wherein means for selectively applying a phase-shifted received signal to a phased array output include means for selectively setting a complementary switch in the second winding of a second EM element to a conducted and deconducted state so that the phase-shifted received signal passes from the first winding in the second EM element to the second winding of the second EM element, and means for selectively setting a switch in the third winding of the second EM element to a deconducted state.

[0116] 24. The device according to Clause 18, for selectively applying a phase-shifted transmit signal to a power amplifier, comprising means for selectively setting a complementary switch in a second winding of a second EM element to a conducted and deconducted state such that the phase-shifted transmit signal passes from a first winding in the second EM element to a third winding of the second EM element, and means for selectively setting a switch in a third winding of the second EM element to a conducted state.

[0117] 25. The device described in any of clauses 23 to 24, wherein the switch in the third winding of the second EM element is located near the center tap of the third winding to minimize parasitic losses to the differential signal.

[0118] 26. A phased array element comprising a receiving circuit, a transmitting circuit, a first electromagnetic (EM) element coupled to the receiving circuit, a second EM element coupled to the transmitting circuit, and a phase shifter coupled between the first EM element and the second EM element, wherein the phase shifter is configured to be shared by the receiving circuit and the transmitting circuit.

[0119] 27. The phased array element as described in Clause 26, wherein the transmitted signal and the received signal follow the same path through the phase shifter.

[0120] 28. A phased array element as described in any of clauses 26 to 27, wherein the first EM element includes a first tricoil and the second EM element includes a second tricoil.

[0121] 29. The phased array element as described in Clause 28, wherein the first EM element is differentially coupled to a hybrid quadrature generator or a multiphase filter, the hybrid quadrature generator or multiphase filter is configured to provide quadrature signals to each variable gain amplifier, and each variable gain amplifier is differentially coupled to a second EM element.

[0122] 30. The phased array element described in Clause 29, wherein the second EM element is configured to provide a single-ended received signal.

[0084]

[0123] The circuit architectures described herein can be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architectures described herein can also be fabricated using a variety of IC process techniques, such as complementary metal oxide semiconductors (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), and silicon-on-insulators (SOI).

[0085]

[0124] Devices implementing the circuits described herein may be standalone devices or part of a larger device. The devices may include (i) standalone ICs, (ii) one or more sets of ICs which may include memory ICs for storing data and / or instructions, (iii) RFICs such as RF receivers (RFRs) or RF transmitters / receivers (RTRs), (iv) ASICs such as mobile station modems (MSMs), (v) modules which may be embedded in other devices, (vi) receivers, mobile phones, wireless devices, handsets, or mobile units, (vii) and the like.

[0086]

[0125] Although the selected embodiments have been illustrated and described in detail, it will be understood that various substitutions and modifications can be made in those embodiments without departing from the spirit and scope of the invention as defined by the following claims.

Claims

1. A millimeter-wave (mmW) communication system arranged on a millimeter-wave integrated circuit (MMW-IC), A phase shifter selectively connected to the receiving path by a first electromagnetic (EM) element and selectively connected to the transmitting path by a second EM element, The first EM element is configured to receive a transmitted signal and to receive a received signal from a low-noise amplifier (LNA), The second EM element is configured to receive a phase-shifted transmitted signal or a phase-shifted received signal from the phase shifter, A millimeter-wave communication system in which the second EM element is configured to selectively provide the phase-shifted transmit signal to a power amplifier on the mmW-IC and the phase-shifted receive signal to a receive signal processing circuit located away from the mmW-IC.

2. The communication system according to claim 1, wherein the first EM element comprises a first winding, a second winding, and a third winding, and the first winding comprises a switch configured to change the impedance of the first winding.

3. The communication system according to claim 1, wherein the second EM element comprises a first winding, a second winding, and a third winding, the second winding includes a switch configured to change the impedance of the second winding, and the third winding includes a switch configured to change the impedance of the third winding.

4. The communication system according to claim 2, wherein in receiving mode, the switch of the first winding is configured to be in a non-conductive state in order to present high impedance to the second winding and the third winding.

5. The communication system according to claim 2, wherein in transmission mode, the switch of the first winding is configured to be conductive so that a transmission signal is transferred from the first winding to the third winding.

6. The communication system according to claim 2, wherein the switch in the first winding is located near the center tap of the first winding in order to minimize parasitic losses to differential mode signals.

7. The communication system according to claim 3, wherein in receiving mode, the first switch in the second winding is selectively conductive, the second switch in the second winding is selectively non-conductive, and the switch in the third winding is non-conductive, allowing the received signal to pass from the first winding to the second winding.

8. The communication system according to claim 3, wherein in transmission mode, the first switch in the second winding is selectively conductive, the second switch in the second winding is selectively non-conductive, and the switch in the third winding is conductive, allowing the transmission signal to pass from the first winding to the third winding.

9. The communication system according to claim 3, wherein the switch in the third winding is located near the center tap of the third winding to minimize parasitic losses to differential mode signals.

10. A method for phase-shifting a signal, Selectively applying the transmitted signal or received signal to a shared phase shifter, The transmission signal or the reception signal is phase-shifted, The phase-shifted transmitted signal is selectively applied to a power amplifier, or the phase-shifted received signal is selectively applied to a phased array output. Methods that include...

11. The method according to claim 10, wherein selectively applying the transmitted signal or the received signal to a shared phase shifter includes impedance matching.

12. The method according to claim 10, wherein selectively applying the received signal to the shared phase shifter includes selectively setting a switch in the first winding of the first EM element to a non-conductive state such that the received signal passes from the second winding in the first EM element to the third winding in the first EM element.

13. The method according to claim 12, wherein selectively applying the transmission signal to the shared phase shifter includes selectively setting a switch in the first winding of the first EM element to a conductive state such that the transmission signal passes from the first winding in the first EM element to the third winding in the first EM element.

14. The method according to claim 12, wherein the switch in the first winding of the first EM element is located near the center tap of the first winding to minimize parasitic losses to the differential signal.

15. The method according to claim 10, wherein selectively applying the phase-shifted received signal to the phased array output includes selectively setting a complementary switch in the second winding of the second EM element to a conductive and non-conductive state, and selectively setting a switch in the third winding of the second EM element to a non-conductive state, such that the phase-shifted received signal passes from the first winding in the second EM element to the second winding of the second EM element.

16. The method according to claim 15, wherein selectively applying the phase-shifted transmit signal to the power amplifier includes selectively setting the complementary switch in the second winding of the second EM element to a conductive state and a non-conductive state, and selectively setting the switch in the third winding of the second EM element to a conductive state, such that the phase-shifted transmit signal passes from the first winding in the second EM element to the third winding of the second EM element.

17. The method according to claim 15, wherein the switch in the third winding of the second EM element is located near the center tap of the third winding to minimize parasitic losses to the differential signal.

18. A device for signal phase shifting, Means for selectively applying a transmitted signal or a received signal to a shared phase shifter, Means for phase-shifting the transmitted signal or the received signal, Means for selectively applying the phase-shifted transmitted signal to a power amplifier, or for selectively applying the phase-shifted received signal to a phased array output, A device equipped with the following features.

19. The device according to claim 18, wherein the means for selectively applying the transmitted signal or the received signal to a shared phase shifter includes means for impedance matching.

20. The device according to claim 18, wherein the means for selectively applying the received signal to the shared phase shifter includes means for selectively setting a switch in the first winding of the first EM element to a non-conductive state so that the received signal passes from the second winding in the first EM element to the third winding in the first EM element.

21. The device according to claim 18, wherein the means for selectively applying the transmission signal to the shared phase shifter includes means for selectively setting a switch in the first winding of the first EM element to a conductive state such that the transmission signal passes from the first winding in the first EM element to the third winding in the first EM element.

22. The device according to claim 20, wherein the switch in the first winding of the first EM element is located near the center tap of the first winding to minimize parasitic losses to the differential signal.

23. The device according to claim 18, wherein the means for selectively applying the phase-shifted received signal to the phased array output includes means for selectively setting a complementary switch in the second winding of the second EM element to a conductive and non-conductive state so that the phase-shifted received signal passes from the first winding in the second EM element to the second winding of the second EM element, and means for selectively setting a switch in the third winding of the second EM element to a non-conductive state.

24. The device according to claim 18, wherein the means for selectively applying the phase-shifted transmit signal to the power amplifier includes means for selectively setting a complementary switch in the second winding of the second EM element to a conductive and non-conductive state so that the phase-shifted transmit signal passes from the first winding in the second EM element to the third winding of the second EM element, and means for selectively setting a switch in the third winding of the second EM element to a conductive state.

25. The device according to claim 23, wherein the switch in the third winding of the second EM element is located near the center tap of the third winding to minimize parasitic losses to the differential signal.

26. Phased array elements, Receiving circuit and Transmitter circuit and A first electromagnetic (EM) element coupled to the receiving circuit, A second EM element coupled to the aforementioned transmitting circuit, The system comprises a phase shifter coupled between the first EM element and the second EM element, The phased array element is configured such that the phase shifter is shared by the receiving circuit and the transmitting circuit.

27. The phased array element according to claim 26, wherein the phased array element is configured such that the transmitted signal and the received signal follow the same path through the phase shifter.

28. The phased array element according to claim 26, wherein the first EM element includes a first tricoil, and the second EM element includes a second tricoil.

29. The phased array element according to claim 28, wherein the first EM element is differentially coupled to a hybrid quadrature generator or a multiphase filter, the hybrid quadrature generator or multiphase filter is configured to provide quadrature signals to each variable gain amplifier, and each variable gain amplifier is differentially coupled to the second EM element.

30. The phased array element according to claim 29, wherein the second EM element is configured to provide a single-ended received signal.

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