Interleaved digital trigger compensation

Abstract

The test measurement apparatus has an array of data pipes, each data pipe in the array having an input that is coupled to the output of an interleaved analog-to-digital converter (ADC), a hysteresis processor coupled to this input that receives the current pipe data value, and a pipeline trigger comparator. The hysteresis processor is coupled to another hysteresis processor in the data pipe array to receive the previous data value and the direction of the previous data. The hysteresis processor is configured to compare the current pipe data value with the previous data value and to determine whether the magnitude of the difference between the current pipe data value and the previous data value exceeds a hysteresis value. The method is also described.

Description

Technical Field

[0001] The present disclosure relates to test and measurement devices such as oscilloscopes, and particularly to a trigger system and method for precise trigger processing in test and measurement devices.

Background Art

[0002] Most modern oscilloscopes have replaced analog triggers with digital triggers, which are rapidly becoming the industry standard. Any trigger, in either analog or digital form, is used to determine which portion of the signal input to the test and measurement device by the oscilloscope is captured for analysis. First, the oscilloscope stores the data received at its input in a temporary buffer. The data stored in the buffer is overwritten when the received data exceeds the buffer size. Due to a trigger event, the device stores the data from the temporary buffer as a sampled waveform for analysis elsewhere in the device. The sampled waveform may include data that was stored in the temporary buffer before the trigger event occurred, and the user can evaluate the device under test (DUT) before, during, and after the trigger event.

[0003] High-performance oscilloscopes use a series or array of interleaved analog-to-digital converters (ADCs) for each input channel to achieve effective sample rates higher than possible with a single ADC. As the number of interleaved ADCs increases, the received data width becomes too large to distribute to a single physical location, making it increasingly difficult to transfer all the data to a centralized trigger processor. For example, some conventional high-bandwidth devices use demultiplexers to deinterleave the interleaved ADCs. These multiplexers are typically integrated into field-programmable gate arrays (FPGAs) or ASICs (application-specific integrated circuits) that support digital triggering, ADC data storage, and other digital processing functions. As data sampling rates and resolutions improve, these demultiplexers face substantial limitations on the number of data pipes they can process and store. Furthermore, there are practical limitations on the amount of output each demultiplexer can send to a centralized location to perform triggering functions. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] U.S. Patent Application Publication No. 2013 / 0060527 [Patent Document 2] Japanese Patent Publication No. 2009-503456 [Patent Document 3] Japanese Patent Publication No. 2017-026603 [Overview of the project] [Problems that the invention aims to solve]

[0005] For these reasons, some oscilloscopes are beginning to incorporate digital triggers into the data pipeline of each ADC. However, digital triggers in each data pipeline will trigger undersampled data because each ADC only touches a portion of the input data. Frequencies above the Nyquist frequency of each pipe are aliased. Triggering on aliased data works for certain types of data, but it is not accurate for very high-bit-rate single pulses or high-frequency radio frequency (RF) applications.

[0006] The embodiments aim to overcome these and other limitations of current technology. [Means for solving the problem]

[0007] Embodiments of this disclosure include an array of multiple individual digital trigger processors within a data pipe that transmits hysteresis and directional information from adjacent pipes within a ring communication network structure. The hysteresis and directional information improves the performance of digital triggers by allowing each trigger processor in the pipe to accurately trigger only the events that are actually triggered, reducing the number of false triggers that may occur due to noise. On the other hand, unlike conventional methods, each individual digital trigger processor recognizes only a portion of the input signal because the input data acquisition method is interleaved. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a block diagram of a test and measurement apparatus including an interleaved digital trigger error correction circuit according to an embodiment of the present disclosure. [Figure 2] Figure 2 is a block diagram showing a first architecture having multiple ADCs according to an embodiment of the present disclosure, where each of the multiple ADCs has a digital pipe trigger circuit and receives information from another digital pipe trigger circuit. [Figure 3]Figure 3 is a block diagram showing a second architecture having multiple ADCs according to an embodiment of the present disclosure, where each of the multiple ADCs has a digital pipe trigger circuit and receives information from another digital pipe trigger circuit. [Figure 4] Figure 4 is a block diagram showing a pipe trigger processor with hysteresis and direction processing capabilities according to an embodiment of the present disclosure. [Figure 5] Figure 5 is a block diagram based on an embodiment of the present disclosure illustrating how multiple data input pipes from multiple ADCs share hysteresis and direction information for advanced triggering. [Figure 6] Figure 6 is a block diagram showing an example of the logic circuit structure of the hysteresis / direction processing block shown in Figures 4 and 5, based on embodiments of the present disclosure. [Modes for carrying out the invention]

[0009] Figure 1 is an example block diagram of a test measurement apparatus 100 having an interleaved digital trigger compensation circuit, based on some embodiments of the present disclosure. The test measurement apparatus 100 has one or more ports 102, which may be some kind of electrical or optical signal transmission medium. Ports 102 may include receivers (receiving circuits), transmitters (transmitting circuits), and transceivers. Each port 102 is a channel of the test measurement apparatus 100. In some embodiments, the test measurement apparatus 100 includes eight, sixteen, or more independent ports. The test measurement apparatus 100 can be coupled to a device under test (DUT) 101 through one or more ports 102. A DUT 101 with multiple outputs can have each output connected to the test measurement apparatus 100 through multiple independent ports 102.

[0010] These input signals received at port 102 are sent to a plurality of interleaved analog-to-digital converters (ADCs) 104. The interleaved ADCs 104 convert the analog signals received through one or more ports 102 into digital data representing the input signals. Interleaved ADCs mean that each ADC in the interleaved ADCs 104 processes only a portion of the data from input port 102. The ADCs 104 are available in the test measurement device 100 and have a sampling rate sufficient to sample the input signals with sufficient resolution; they may be 8-bit, 12-bit, or higher resolution ADCs. The output data from the interleaved ADCs 104 are re-combined by a de-interleaver 110 to generate a full-bandwidth signal received by the test measurement device 100.

[0011] In some embodiments, each ADC of the interleaved ADC 104 is also individually coupled to its corresponding pipe trigger processor 106, so that there is one pipe trigger processor for each ADC of the interleaved ADC 104. Embodiments of this disclosure also include communication between adjacent pipe trigger processors 106. Specifically, information regarding the hysteresis level and the direction of data travel from the input (up or down) is transmitted in a ring to a group of pipe trigger processors 106 using an array of hysteresis and direction processing blocks 108, as described in detail below. The output from the group of pipe trigger processors 106 is a trigger signal, which the acquisition processor 112 can use to determine which information from the DUT to store in the acquisition memory 114 as input waveforms for measurement and testing of the DUT.

[0012] The acquisition memory 114 may be relatively large and is designed to quickly store large amounts of received data. The acquisition memory 114 may be implemented as volatile memory or as solid-state memory, such as a solid-state disk drive.

[0013] The test measurement device 100 also includes one or more main processors 120 configured to execute instructions from the main memory 121, which can perform any method or associated steps indicated by these instructions.

[0014] The user input unit 130 is coupled to one or more processors 120 and may have a keyboard, mouse, touchscreen, or other optional operating device that the user can use to interactively operate the GUI on the output display 132. In some embodiments, the user input unit 130 may be connected to or controlled by a remote interface 134, so that the user can control the operation of the test measurement device 100 from a remote location physically separated from the test measurement device. The display 132 may be a digital screen such as an LCD or other monitor for displaying waveforms, measurements, and other data to the user. In some embodiments, the output display 132 is also located far away from the test measurement device 100.

[0015] One or more measurement units 140 are shown as part of the test measurement apparatus 100. These measurement units 140 perform the primary function of measuring the parameters and other characteristics of the signal from the DUT 101 that the test measurement apparatus 100 measures. Typical measurements include measuring the voltage, current, and power of the input signal in the time domain, and measuring the characteristics of the input signal in the frequency domain. The measurement units 140 typically provide any measurements that the test measurement apparatus would perform.

[0016] The components of the test measurement device 100 are depicted as being integrated within the test measurement device 100. However, those skilled in the art will understand that any of these components may exist outside of the test measurement device 100 and can be connected to the test measurement device 100 by any conventional method (e.g., wired or wireless communication media or mechanisms). For example, in some embodiments, the display 132 may be located remotely from the test measurement device 100, or data and images from the output of the test measurement device may be available on other devices through a cloud or other communication network 150.

[0017] FIG. 2 is a block diagram showing a first front-end trigger architecture 200 having a plurality of ADCs 210 according to an embodiment of the present disclosure. At this time, each ADC includes a digital pipe trigger 220 that receives information from another digital pipe trigger within the architecture. The front-end trigger architecture 200 of FIG. 2 generally describes the hardware and processes located between the input port 102 and the acquisition processor 112 of FIG. 1, but in some embodiments, additional components may be included.

[0018] In the front-end trigger architecture 200, the input port 202 is connected to a track-and-hold circuit 204, which temporarily stores the input signal until it is sampled by the ADC 210. Similar to the system described with reference to FIG. 1, these ADCs 210 are interleaved, and each ADC samples only a portion of the input received at the input port 202.

[0019] The sample outputs of each ADC 210 are sent to the pipe trigger circuit 220, which functions to determine whether the input portion sampled by the connected ADC exceeds the trigger threshold. As described above, for alias data exceeding the Nyquist frequency, it is difficult to detect some triggers. According to an embodiment of the present disclosure, as shown in FIG. 2, by transmitting information regarding adjacent data pipes in a ring (circular) manner from one pipe to another, even difficult triggers can be accurately detected. In a specific embodiment, the transmitted information includes hysteresis information and direction information, which will be described in detail below.

[0020] In the conventional method, individual trigger blocks were physically arranged in various devices and distributed to a centrally processed trigger circuit. In contrast, in this ring circuit configuration as shown in FIG. 2, a large amount of data distribution is saved. By using the ring circuit configuration, an embodiment of the present disclosure provides sufficient data for each pipe trigger circuit to accurately detect trigger events.

[0021] In FIG. 2, four demultiplexers 240 are shown, each having two pipe trigger circuits 220 and memory storage 230 for storing sample and trigger data. The demultiplexer 240 performs at least a part of the deinterleaving function described with reference to FIG. 1. Also, in a high-performance device, a demultiplexer such as the demultiplexer 240 is often physically arranged in various devices. By using the front-end trigger architecture 200 of FIG. 2, it is not necessary to distribute a large amount of data to a trigger circuit that makes a determination in a centrally processed manner. Instead, the embodiment eliminates the data bottleneck faced by the centrally processed trigger by distributing a minimum amount of data and enabling the pipe trigger circuits to operate dispersedly.

[0022] Figure 3 shows the front-end trigger architecture 300, which is similar to the front-end trigger architecture 200 in Figure 2, but differs in that the front-end trigger architecture 300 has two demultiplexers 350, each containing four pipe trigger circuits 320. Similar to the pipe trigger circuit 220 in Figure 2, each pipe trigger circuit 320 is powered by a single ADC 310. The ring-shaped circuit configuration, which transmits small amounts of data between adjacent pipes, is similar to the front-end trigger architecture 200, but differs in the number of data connections outside the demultiplexer 350. In other words, the communication of the ring-shaped circuit configuration between the four pipe trigger circuits 320 within the demultiplexer 350 "DEMUX A" is all internally connected within the DEMUX A device. Therefore, in the front-end trigger architecture 300, the ring-shaped circuit configuration that sends data from one pipe to another has only two ring-shaped connections outside of the DEMUX 350. The first external ring-shaped connection sends information from the DEMUX A pipe (highest level) to the DEMUX B pipe (lowest level). Similarly, the second external ring-shaped connection sends information from the DEMUX B pipe (highest level) to the DEMUX A pipe (lowest level). In comparison, the front-end trigger architecture 200 in Figure 2 has four external data connections within its ring-shaped architecture, which are connections between DEMUX A, DEMUX B, DEMUX C, and DEMUX D, respectively. As mentioned above, even with multiple external connections, the data carried by the ring-shaped circuit configuration is very small, and the ring-shaped circuit configuration saves data distribution of important data between demultiplexers, even when each pipe is physically located in various devices.

[0023] When implemented in hardware, each demultiplexer 350 may have up to 10 separate pipes based on 10 different ADCs 310, and therefore may have up to 10 separate pipe trigger circuits.

[0024] Figure 4 is a block diagram showing the main components of a pipe trigger processor 400 with hysteresis and directional processing functions according to an embodiment of the present disclosure. The pipe trigger processor 400 in Figure 4 may be an example of the pipe trigger processor 106 described with reference to Figure 1.

[0025] ADC 410 is one of the interleaved ADCs and generates a current (single) data sample, which is passed to the hysteresis / direction block processor 420 and edge detector 430. The hysteresis / direction block processor 420 receives two additional inputs: the direction of the previous pipe and the sample of the previous pipe. The direction of the previous pipe is a 1-bit data, where 0 indicates a negative direction and 1 indicates a positive direction, although other encodings and bit depths may be used. The hysteresis / direction block processor 420 generates two outputs (the direction of the next pipe and the sample of the next pipe) and sends them to the next hysteresis / direction block processor 420 in the ring. A detailed explanation of how each hysteresis / direction block processor 420 responds to the three inputs and generates two outputs is described below with reference to Figures 5 and 6.

[0026] The edge detector 430 has a comparator that compares the current pipe sample received directly from the ADC 410 with a previous pipe sample received from the previous hysteresis / direction block processor 420 in the ring with one or more trigger thresholds. Based on the comparison result, the edge detector 430 generates a trigger signal, which can be used as a trigger event.

[0027] Figure 5 is a block diagram of a ring structure 500. The ring structure 500 shares hysteresis and previous sample information with adjacent data pipes within the ring structure. Roughly speaking, the ring structure 500 represents three independent data pipes 550 in a system containing a total of "N" data pipes. In the ring structure 500, each data pipe 550 in the system has roughly the same components as all other data pipes connected in the ring structure. In other words, there is no master pipe or master controller that can access all the data in all the pipes. Instead, hysteresis and trigger processing are distributed among all the data pipes 550 connected in the ring structure 500.

[0028] Each data pipe 550 includes a trigger filter 560, a hysteresis / direction block processor 570 (details shown in Figure 5) as described with reference to Figure 4, and digital threshold comparators 580 and 582 for detecting trigger events. One difference in the data pipe 550 in Figure 5 is the presence of two digital threshold comparators 580 and 582, unlike the single threshold comparator described with reference to the edge detector 430. Embodiments of this disclosure function equally effectively with any number of threshold comparators, such as the trigger logic and sequence processing block 598, which can be in complex combinations.

[0029] During operation, each data pipe 550 exhibits similar behavior to one another. For example, each trigger filter 560 of each data pipe 550 receives a data sample from another ADC (not shown). After filtering the sample in 560, the sample is passed to the hysteresis / direction block processor 570, which also receives inputs of the previous pipe's direction and previous pipe's sample from adjacent data pipes 550. For example, the hysteresis / direction block processor 570 of pipe 1 receives the previous pipe's direction and previous pipe's sample from pipe 2. Similarly, the hysteresis / direction block processor 570 of pipe 1 sends its previous pipe's direction and previous pipe's sample to pipe N, which then sends its previous pipe's direction and previous pipe's sample to pipe N-1.

[0030] Furthermore, the current and previous samples are compared by digital threshold comparators 580 and 582, as described with reference to edge detector 430 (Figure 4). Note in Figure 5 that the outputs of digital threshold comparators 580 and 582 are coupled to OR gates 590 and 592, respectively. In this way, the trigger logic and sequence processing block 598 receives a signal when either threshold comparator reaches its threshold. Also, since each pipe performs a separate threshold comparison with digital threshold comparators 580 and 582, the trigger logic and sequence processing block 598 is alerted at the exact cycle in which the threshold is reached.

[0031] Embodiments of this disclosure utilize the hysteresis / direction block processor 570 in each block 550 to perform specific processing, thereby enabling highly accurate digital threshold comparators 580 and 582 and eliminating the source of errors caused by conventional trigger circuits. Due to the distributed nature of the ring structure 500, each data pipe 550 can independently perform data comparison and generate signals to the trigger logic and sequence processing block 598 when a trigger threshold is reached, eliminating the need to distribute large amounts of data to a centralized processing location. Furthermore, the hysteresis / direction block processor 570 plays a crucial role in ensuring that the digital threshold comparators 580 and 582 operate based on actual data, virtually eliminating trigger processing for noise or false data.

[0032] In particular, the hysteresis / direction block processor 570 performs hysteresis functionality by implementing the following set of rules based on the magnitude and direction of the comparison between the current pipe sample from the trigger filter and the previous sample from the adjacent data pipe. This comparison is referred to as the "comparison" in the rules above, and is as follows: If the direction of the comparison is opposite to the direction of the previous pipe, and if the magnitude of the comparison is greater than the provided hysteresis value, the current pipe sample from the trigger filter is used as the "next pipe sample" output of the hysteresis / direction block processor 570. Otherwise, the "previous pipe sample" received from the adjacent data pipe is transmitted as the "next pipe sample" output of the hysteresis / direction block processor 570.

[0033] This rule reduces the likelihood that noise will interfere with the comparison of trigger processing. In other words, by ensuring that the difference from the previous sample exceeds the hysteresis value, it effectively ignores small disturbances caused by spurious noise at the ADC or elsewhere, thereby improving the accuracy of trigger detection by preventing trigger processing from being performed on erroneous results caused by such noise.

[0034] Figure 6 is a block diagram showing an example of the logic circuit structure of the hysteresis / directional block processor 600, which may be an embodiment of the hysteresis / directional block processor described with reference to Figures 4 and 5, or a similar embodiment.

[0035] The hysteresis / direction block processor 600 in Figure 6 has three inputs, which are the same as the inputs described above. Specifically, a) the "pipe sample" received from the ADC (Figure 4) or trigger filter (Figure 5), plus b) the "previous pipe sample" and c) the "previous pipe direction," both of which are received from the hysteresis / direction block processor in the previous pipe within the ring (Figure 5). As described above, the pipe sample and the previous pipe sample are sampled input data, while the previous pipe direction is encoded data indicating the direction in which the input sample is moving relative to the previous sample. In some embodiments, the encoded data may be a single bit indicating the direction.

[0036] Furthermore, as mentioned above, the hysteresis / direction block processor 600 generates two outputs: "next pipe sample" and "next pipe direction." These two outputs are functions of the three inputs, as shown in Figure 6 and described below. To clarify, note that the "next pipe sample" and "next pipe direction" of the hysteresis / direction block processor 600 become the "previous pipe sample" and "previous pipe direction" when the hysteresis / direction block processor 600 sends this data to the next hysteresis / direction block processor 600 at the end of the current cycle.

[0037] In operation, the subtractor 602 subtracts a pipe sample from a previous pipe sample to generate both the subtraction output value and its sign. The sign bit is provided to the inverter 604, while the output value generates its magnitude through the absolute value process 606. This magnitude is compared to a hysteresis value in process 608. The hysteresis value may be user-controllable or it may be preset based on a specific signal being measured or a specific measurement by a measuring device. Generally, the hysteresis value should be set higher than the internal noise value. The output of the comparison process 608 generates the "direction of the next pipe" via combinational logic circuits 610, 612, 614, and 616. This is one of the outputs of the hysteresis / direction block processor 600. This newly obtained "direction of the next pipe" is then combined with the "direction of the previous pipe" in the XOR gate 618. This "direction of the previous pipe" is input to the hysteresis / direction block processor 600.

[0038] Of course, the hysteresis / direction block processor 600 in Figure 6 is just one of many ways in which information about adjacent data pipes is considered in a particular data pipe. For example, in another embodiment, a slight modification to the hysteresis / direction block processor 600 is possible to compare subsequent data values ​​in adjacent data pipes in the ring, rather than previous data values. Also, although Figure 6 shows a combinational logic circuit, embodiments of this disclosure can utilize various methods to implement the described functions, such as ASICs, FPGAs, digital signal processors, or specially programmed general-purpose processors.

[0039] By using information from previous samples and directions, a group of data pipes according to embodiments of this disclosure can precisely control which data is stored in each pipe in each cycle, such as storing new data if the newly sampled data exceeds the hysteresis value, and the previous value if it does not. One advantage of this system is the automatic removal of noise in the input and the high reliability that when a trigger processing unit in each data pipe triggers, the trigger occurs at a timing very close to the actual time when the input signal reached the threshold. Thus, embodiments according to this disclosure improve the accuracy of triggers in high-performance measuring devices.

[0040] Embodiments of this disclosure uniquely enhance the accuracy of trigger functionality by precisely controlling when to update data values ​​in a particular data pipe based on a comparison of the current data value from an ADC or filter with the previous data value from an adjacent pipe. If the comparison result is less than a hysteresis value, the current data pipe adopts the value from the previous pipe, thereby preventing noise from adversely affecting the trigger determination process. Other advantages for the trigger system are also provided.

[0041] Embodiments of the disclosed technology can operate on a specially programmed general-purpose computer, including specially created hardware, firmware, digital signal processors, or processors that operate according to programmed instructions. The terms “controller” or “processor” in this application mean microprocessors, microcomputers, ASICs, and dedicated hardware controllers, etc. Embodiments of the disclosed technology can be implemented by one or more computers (including monitoring modules) or other devices, using computer-readable data such as program modules and computer-executable instructions. Generally, program modules include routines, programs, objects, components, data structures, etc., which, when executed by a processor in a computer or other device, perform specific tasks or implement specific abstract data type expressions. Computer-executable instructions may be stored on computer-readable storage media such as hard disks, optical disks, removable storage media, solid-state memory, and RAM. As will be understood by those skilled in the art, the functions of the program modules may be combined or distributed as needed in various embodiments. Furthermore, these functions can be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits or field-programmable gate arrays (FPGAs). One or more aspects of the disclosed technology can be more effectively implemented using specific data structures, such data structures are considered to be within the scope of computer-executable instructions and computer-usable data described herein.

[0042] The disclosed embodiments may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored in one or more computer-readable media that can be read and executed by one or more processors. Such instructions may be referred to as computer program products. The computer-readable media described herein means any medium accessible by a computing device. For example, but not limited to, computer-readable media may include computer storage media and communication media.

[0043] Computer storage media means any medium that can be used to store computer-readable information. Examples of computer storage media include, but are not limited to, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory and other memory technologies, compact disc read-only memory (CD-ROM), DVD (Digital Video Disc) and other optical disc storage devices, magnetic cassettes, magnetic tapes, magnetic disk storage devices and other magnetic storage devices, and any other volatile or non-volatile removable or non-removable media implemented by any technology. Computer storage media exclude signals themselves and temporary forms of signal transmission.

[0044] A communication medium means any medium that can be used to transmit computer-readable information. Examples of communication mediums, though not limited to them, include coaxial cables, fiber optic cables, air, or any other medium suitable for transmitting electrical, optical, radio frequency (RF), infrared, sound, or other types of signals.

[0045] In addition, the description of this application refers to certain features. It should be understood that the disclosures herein include all possible combinations of these particular features. Where a particular feature is disclosed in relation to a particular aspect or example, that feature may, to the extent possible, also be used in relation to other aspects and examples.

[0046] Furthermore, when this application refers to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, as long as the circumstances do not rule out such possibilities.

[0047] For the sake of explanation, specific embodiments of the disclosed technology have been illustrated and described, but it should be understood that various modifications are possible without deviating from the gist and scope of the present invention. Examples

[0048] The aforementioned versions of the subject matter of this disclosure have many effects that have been described or will be apparent to those skilled in the art. Nevertheless, not all of these effects or features are required in all versions of the disclosed apparatus, system, or method.

[0049] Example 1 is a test and measurement device, Data pipe array and, Pipeline trigger comparator and Equipped with, Each of the above data pipes in the above data pipe array is, The input section is coupled to the output section of an interleaved analog-to-digital converter (ADC), A hysteresis processor coupled to the input unit to receive the current pipe data value, and further coupled to another hysteresis processor in the array of data pipes to receive the previous data value and the previous data direction. It has, The hysteresis processor described above is configured to compare the current pipe data value with the previous data value and determine whether the magnitude of the difference between the current pipe data value and the previous data value exceeds the hysteresis value.

[0050] Example 2 is a test measurement apparatus based on Example 1, wherein the pipeline trigger comparator is configured to compare the current pipe data value and the previous data value with a trigger threshold.

[0051] Example 3 is a test measurement apparatus based on any of the above-described embodiments, wherein the output of the pipeline trigger comparator of each data pipe in the array of data pipes is coupled to an OR gate, and the OR gate is further coupled to a trigger processor.

[0052] Example 4 is a test measurement apparatus based on any of the above-described embodiments, wherein the hysteresis processors in the array of data pipes are connected to each other in a ring-shaped circuit structure.

[0053] Example 5 is a test measurement apparatus based on any of the above-described embodiments, wherein the hysteresis processor is configured to transmit the previous data value received from the first neighboring hysteresis processor to the second neighboring hysteresis processor when the magnitude of the difference between the current pipe data value and the previous data value is smaller than the hysteresis value.

[0054] Example 6 is a test measurement apparatus based on any of the above-described embodiments, wherein the hysteresis processor is configured to transmit the current pipe data value to a second neighboring hysteresis processor if the difference between the current pipe data value and the previous data value is greater than the hysteresis value, provided that the direction of the previous data is opposite to the direction of the output of the difference between the current pipe data value and the previous data value.

[0055] Example 7 is a test and measurement device based on any of the above-described examples, wherein the hysteresis value is selected by the user of the test and measurement device.

[0056] Example 8 is a test and measurement apparatus based on any of the above-described embodiments, wherein the hysteresis value is greater than the internal noise value of the test and measurement apparatus.

[0057] Example 9 is a test measurement apparatus based on any of the above-described embodiments, wherein the pipeline trigger comparator is configured to compare the current pipe data value with a first trigger threshold and a second trigger threshold.

[0058] Example 10 is a method in a test measurement apparatus, wherein in each of the data pipe arrangements, The process involves receiving the current pipe data value from the input section coupled to the output section of an interleaved analog-to-digital converter (ADC), and The process involves comparing the current pipe data value with the previous data value received from an adjacent data pipe in the array of data pipes, and generating the direction and magnitude of the comparison result. The process involves comparing the magnitude of the result with the hysteresis value, Based on the comparison result of the above hysteresis values, the current pipe data value or the previous data value is transmitted as the next data value to the adjacent data pipe in the above data pipe array. The process of performing trigger comparison and It is equipped with.

[0059] Example 11 is a method based on Example 10, wherein the process for performing trigger comparison includes a process for comparing the current pipe data value and the previous data value with a trigger threshold.

[0060] Example 12 is a method based on any of the above-described examples, further comprising a process to indicate a trigger event relating to the data pipe array when any of the trigger comparisons in the data pipe array generates a positive trigger result.

[0061] Example 13 is a method based on any of the above-described examples, wherein each of the data pipes in the data pipe array is connected to one another in a ring-shaped circuit structure.

[0062] Example 14 is a method based on any of the above-described examples, further comprising the process of transmitting the previous data value to a second adjacent data pipe when the magnitude of the result is smaller than the hysteresis value.

[0063] Example 15 is a method based on Example 14, further comprising the process of transmitting the current pipe data value to a second adjacent data pipe only if the magnitude of the above result is greater than the above hysteresis value and the direction indicated by the previous data received from the adjacent data pipe does not match the direction of the above result.

[0064] Example 16 is a method based on any of the above-described examples, further comprising the process of receiving the hysteresis value from the user of the test measuring device.

[0065] Example 17 is a method based on any of the above-described examples, wherein the hysteresis value is greater than the internal noise value of the test measuring device.

[0066] Example 18 is a method based on any of the above-described examples, wherein the trigger comparison process includes a process of comparing a first trigger threshold with a second trigger threshold.

[0067] In addition, the description of this application refers to certain features. It should be understood that the disclosures herein include all possible combinations of these particular features. Where a particular feature is disclosed in relation to a particular aspect or example, that feature may, to the extent possible, also be used in relation to other aspects and examples.

[0068] Furthermore, when this application refers to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, as long as the circumstances do not rule out such possibilities.

[0069] For the sake of explanation, specific embodiments of the present invention have been illustrated and described, but it should be understood that various modifications are possible without deviating from the gist and scope of the present invention. Therefore, the present invention should not be limited to anything other than the appended claims.

Claims

1. A test and measurement device, Data pipe array and Pipeline trigger comparator and Equipped with, Each of the above data pipes in the above data pipe array is, The input section is coupled to the output section of an interleaved analog-to-digital converter (ADC), A hysteresis processor coupled to the input unit to receive the current pipe data value, and further coupled to another hysteresis processor in the array of data pipes to receive the previous data value and the previous data direction. It has, A test measurement device configured such that the hysteresis processor compares the current pipe data value with the previous data value to determine whether the magnitude of the difference between the current pipe data value and the previous data value exceeds the hysteresis value.

2. A test measurement device according to claim 1, wherein the pipeline trigger comparator is configured to compare the current pipeline data value and the previous data value with a trigger threshold.

3. A test and measurement apparatus according to claim 1, wherein the output of the pipeline trigger comparator of each of the data pipes in the above array of data pipes is coupled to an OR gate, and the OR gate is further coupled to a trigger processor.

4. A test and measurement apparatus according to claim 1, wherein the hysteresis processors in the array of data pipes are connected to one another in a ring-shaped circuit structure.

5. A test and measurement apparatus according to claim 1, wherein the hysteresis processor is configured to transmit the previous data value received from the first adjacent hysteresis processor to the second adjacent hysteresis processor when the magnitude of the difference between the current pipe data value and the previous data value is smaller than the hysteresis value.

6. A test measurement apparatus according to claim 1, wherein the hysteresis processor is configured to transmit the current pipe data value to a second adjacent hysteresis processor if the difference between the current pipe data value and the previous data value is greater than the hysteresis value, provided that the direction of the previous data is opposite to the direction of the output of the difference between the current pipe data value and the previous data value.

7. The above hysteresis value is selected by the user of the test and measurement device according to claim 1.

8. A test and measurement device according to claim 1, wherein the above hysteresis value is greater than the internal noise value of the test and measurement device.

9. A test and measurement apparatus according to claim 1, wherein the pipeline trigger comparator is configured to compare the current pipe data value with a first trigger threshold and a second trigger threshold.

10. A method in a test measurement apparatus, wherein in each of the data pipe arrangements, The process involves receiving the current pipe data value from the input section coupled to the output section of an interleaved analog-to-digital converter (ADC), and The process involves comparing the current pipe data value with the previous data value received from an adjacent data pipe in the array of data pipes, and generating the direction and magnitude of the comparison result. The process involves comparing the magnitude of the result with the hysteresis value, Based on the comparison result of the above hysteresis values, the process involves transmitting the current pipe data value or the previous data value as the next data value to the adjacent data pipe in the above data pipe array, The process of performing trigger comparison and A method in a test and measurement apparatus equipped with the following.

11. A method according to claim 10, wherein the process for performing trigger comparison includes a process for comparing the current pipe data value and the previous data value with a trigger threshold.

12. The method according to claim 10, further comprising a process to indicate a trigger event relating to the array of data pipes when any of the trigger comparisons in the array of data pipes generates a positive trigger result.

13. A method according to claim 10, wherein each of the data pipes in the data pipe array is connected to one another in a ring-shaped circuit structure.

14. The method according to claim 10, further comprising the process of transmitting the previous data value to a second adjacent data pipe when the magnitude of the above result is smaller than the above hysteresis value.

15. The method according to claim 14, further comprising the process of transmitting the current pipe data value to a second adjacent data pipe only if the magnitude of the above result is greater than the above hysteresis value and the direction indicated by the previous data received from the adjacent data pipe does not coincide with the direction of the above result.

16. The method according to claim 10, further comprising a process for receiving the hysteresis value from the user of the above-mentioned test measuring device.

17. The method according to claim 10, wherein the hysteresis value is greater than the internal noise value of the test measuring device.

18. The method according to claim 10, wherein the trigger comparison process includes a process of comparing a first trigger threshold with a second trigger threshold.

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