Quantum compilation service

Abstract

A system and method for implementing a quantum circuit compilation-as-a-service are disclosed. In some embodiments, the quantum circuit compilation service is configured to compile quantum circuits for multiple third-party customers, and the compilation service supports compiling quantum circuits to run on multiple different quantum processing units utilizing various different quantum computing technologies. In some embodiments, the quantum computing service generates a customized compilation job plan for each quantum circuit to be compiled. The compilation job plan may refer to modularized compilation paths stored in the quantum circuit compilation service repository. The modularized paths may be mixed and adapted as needed to enable the compilation of a wide variety of quantum circuits to run using various different quantum computing technologies.

Description

[Technical Field]

[0001] Quantum computing uses the laws of quantum physics to process information. Quantum physics is a theory that describes the behavior of reality at a fundamental level. Currently, quantum physics is the only physical theory that can consistently predict the behavior of microscopic quantum objects such as photons, molecules, atoms, and electrons. [Background technology]

[0002] A quantum computer is a device that uses quantum physics to enable the writing, storage, processing, and retrieval of information encoded in quantum states, such as the states of quantum objects. A quantum object is a physical object that behaves according to the laws of quantum physics. The state of a physical object is a description of the object at a given time.

[0003] In quantum physics, the state of a two-level quantum system, or simply the state of a qubit, is a list of two complex numbers whose squares sum to 1. Each of these two numbers is called an amplitude, or pseudoprobability, and their absolute squares are the probability that the measurement of the qubit will result in either zero or one. The fundamental and semi-intuitive difference between a probability bit (e.g., a classical zero or one bit) and a qubit is that a probability bit represents a lack of information about the two-level classical system, while a qubit contains the greatest information about the two-level quantum system.

[0004] Quantum computers are based on such quantum bits (qubits) and can experience the phenomena of "superposition" and "quantum entanglement." Superposition allows a quantum system to be in multiple states simultaneously. For example, while classical computers are based on bits that are either zero or one, qubits can be both zero and one at the same time, with different probabilities assigned to zero and one. Quantum entanglement is a strong correlation between quantum systems, where quantum systems are entangled even when they are far apart.

[0005] A quantum algorithm involves a reversible transform that acts on a qubit in a desired, controlled manner, followed by a measurement on one or more qubits. For example, if the system has two qubits, the transform can modify four numbers; with three qubits, this would be eight numbers. Thus, a quantum algorithm acts on an exponentially large list of numbers, determined by the number of qubits. To implement a transform, it can be decomposed, for example, into smaller operations that act on a single qubit or a pair of qubits. Such smaller operations may be called quantum gates, and special arrangements of quantum gates implement quantum circuits.

[0006] There are different types of qubits that can be used in quantum computers, each with different advantages and disadvantages. For example, some quantum computers may include qubits constructed from superconductors, trapped ions, semiconductors, photonics, etc. Each may experience different levels of interference, error, and decoherence. Also, some may be more useful for generating certain types of quantum circuits or quantum algorithms, while others may be more useful for generating other types of quantum circuits or quantum algorithms. Cost, runtime, error rate, availability, etc., can also differ between quantum computing technologies. [Brief explanation of the drawing]

[0007] [Figure 1] This figure illustrates a service provider network, in several embodiments, that enables customers to compile and / or execute quantum circuits using multiple quantum computing technologies. [Figure 2] This diagram illustrates additional components that may be included in a quantum circuit compilation service for a service provider network, according to several embodiments. [Figure 3] This figure illustrates exemplary modularized compilation paths that may be included in a modularized compilation path repository for a quantum circuit compilation service, according to several embodiments. [Figure 4] This diagram illustrates exemplary quantum circuit compilation job plans that can be generated by a quantum circuit compilation service in several embodiments, and illustrates a workflow for orchestrating the execution of a quantum circuit compilation job plan to compile a quantum circuit at least partially. [Figure 5] This diagram illustrates an exemplary quantum circuit compilation process in which, according to several embodiments, a client-side compiler outsources one or more compilation passes to be performed by a quantum circuit compilation service. [Figure 6] This figure illustrates an exemplary quantum circuit compilation process in which, according to several embodiments, a quantum compilation service provides a client-side compiler with a containerized computing object containing a quantum compilation job plan and modularized compilation path instructions for executing a set of modularized compilation paths shown in the quantum compilation job plan. [Figure 7] This diagram illustrates an exemplary quantum circuit compilation process in which, according to several embodiments, a quantum compilation service performs quantum circuit compilation on behalf of a quantum computing service, the customer submits the quantum circuit to be executed to the quantum computing service, the quantum computing service compiles the quantum circuit in cooperation with the quantum circuit compilation service, and the quantum computing service executes the quantum circuit using the compiled artifacts returned from the quantum circuit compilation service. [Figure 8]This diagram illustrates an exemplary quantum circuit compilation process, in several embodiments, in which a customer delegates quantum compilation to a quantum circuit compilation service, the quantum circuit compilation service partially compiles the quantum circuit, the quantum circuit compilation service returns the partially compiled quantum circuit to a client-side compiler, the client-side compiler performs one or more additional compilation passes, the client-side compiler then returns the further partially compiled quantum circuit to the quantum circuit compilation service, the quantum circuit compilation service completes the compilation, and a quantum computing service executes the quantum circuit using the compiled artifacts generated by the quantum circuit compilation service. [Figure 9] This figure illustrates an exemplary quantum circuit compilation process, which is called "verbatim" quantum circuit compilation, according to several embodiments. [Figure 10A] This diagram illustrates an inline compilation process in which the compilation of a quantum task is performed inline with the execution of the quantum task, according to several embodiments. [Figure 10B] This figure illustrates a separated quantum circuit compilation process, which may be performed by a quantum circuit compilation service, in which compilation is performed in a manner separated from quantum circuit execution, according to several embodiments. [Figure 11] This figure illustrates an example of a web-based implementation of a user interface for a quantum circuit compilation service, according to several embodiments. [Figure 12A] This figure illustrates an example of the generation of a physical qubit connectivity graph, corresponding physical qubits, and edge lists for a given quantum hardware device, according to several embodiments. [Figure 12B] This figure illustrates an example of a logic quantum circuit and the generation of corresponding logic qubits, gates, and gate dependency lists according to several embodiments. [Figure 13]FIG. illustrating an exemplary modular compilation path module that can generate a mapping of a logical quantum circuit to a quantum hardware device, for example, using a SAT solver, according to some embodiments. [Figure 14] FIG. illustrating another exemplary modular compilation path module that can generate a mapping of a logical quantum circuit to a quantum hardware device, for example, using a reinforcement learning-based machine learning model, according to some embodiments. [Figure 15] FIG. illustrating an additional exemplary modular compilation path module that can generate a mapping of a logical quantum circuit to a quantum hardware device, for example, using an SMT solver, according to some embodiments. [Figure 16] FIG. illustrating an edge computing device of a quantum computing service physically located at a quantum hardware provider location, according to some embodiments. [Figure 17] FIG. illustrating an exemplary edge computing device connected to a quantum computing service, according to some embodiments. [Figure 18] FIG. illustrating an exemplary interaction between a quantum computing service and an edge computing device of the quantum computing service, according to some embodiments. [Figure 19] FIG. flowchart illustrating an exemplary process for compiling a quantum circuit on behalf of a customer using a cloud-based quantum circuit compilation service, according to some embodiments. [Figure 20] Block diagram illustrating an exemplary classical computing device that can be used in at least some embodiments.

[0008] Embodiments are described herein as examples of several embodiments and illustrative drawings, but those skilled in the art will recognize that embodiments are not limited to those described or drawn. It should be understood that the drawings and their detailed description are not intended to limit embodiments to any particular form disclosed, but rather to encompass all modifications, equivalents, and substitutes included in the spirit and scope defined by the appended claims. Headings used herein are for structural purposes only and are not intended to limit the scope of the description or claims. As used throughout this application, the word “may” is used in an allowable sense (i.e., having the potential to) rather than an essential sense (i.e., having the potential to). Similarly, the words “include,” “including,” and “includes” mean including, but not limited to. Where used in the claims, the term “or” is used as an inclusive OR, not an exclusive OR. For example, the phrase "at least one of x, y, or z" means any one of x, y, and z, as well as any combination thereof. [Modes for carrying out the invention]

[0009] This disclosure relates to a method and apparatus for performing a quantum circuit compilation-as-a-service. Quantum circuits (and / or other quantum algorithms) are often constructed using logic qubits and logic operators. However, these logic qubits and logic operators need to be mapped and scheduled to the real-world physical components of a quantum processing unit in order to execute the quantum circuit using quantum hardware. Furthermore, due to the limited number of physical qubits in most quantum hardware devices, efficient mapping and scheduling are required to enable quantum circuits to be executed on real-world quantum processing units. In addition, it is necessary for the quantum circuit mapping to "fit" within the available qubits of the physical quantum hardware device, and various quantum circuit mappings that "fit" within the available qubits of the physical quantum hardware device may exhibit varying levels of error due to noise, crosstalk, etc. Therefore, compilation may consider not only how to "fit" and "schedule" the logic qubits and logic operators within the limited physical capacity of the quantum hardware device, but also how various mappings and schedulings may affect the error rate of the quantum circuit execution. In other words, quantum circuit compilation involves generating hardware-specific executable files (compiled artifacts, such as compiled binaries for generating pulse sequences used to implement quantum circuits on quantum hardware devices) based on a provided abstract quantum algorithm or logic quantum circuit. In some embodiments, the compiled artifacts may then be executed on a physical quantum computing device and / or a simulator that simulates a quantum computing device.

[0010] In some embodiments, the compilation result may be evaluated based on, to some extent, the amount of quantum gates used in the compilation and / or the resulting circuit depth. For example, using fewer quantum gates (in particular, SWAP gates) reduces the complexity of the compiled quantum circuit's execution and also reduces the chance of errors occurring during the execution of the compiled quantum circuit. Similarly, reducing circuit depth also reduces complexity and errors. In some embodiments, circuit depth may be understood as the number of gates executed for a given physical qubit. For example, if five gates are executed for a physical qubit, the quantum circuit (with respect to that qubit) may be said to have a circuit depth of 5. In some embodiments, SWAP gates may be used to swap logical states between physical qubits to allow gates to be executed between qubits that do not have direct physical connectivity. However, it is desirable to minimize SWAP gates in a compiled quantum circuit because swap gates increase circuit depth and gate count, which can introduce opportunities for errors.

[0011] In some embodiments, compilation may include two higher-level phases: a first compilation phase that generates optimized qubit assignments and mappings specific to a particular quantum processing unit configured to execute quantum circuits; and a second compilation phase that generates pulse sequences used to implement logical qubits and logic gates on the physical qubits of the particular quantum processing unit. In addition, the first compilation phase may involve at least three higher-level steps: (1) nativeization, (2) qubit assignment and gate mapping, and (3) optimization. In some embodiments, the optimization step may be performed throughout the compilation process, such as between nativeization passes, or between qubit assignment and / or gate mapping passes, or as another optimization step following qubit assignment and gate mapping.

[0012] In some embodiments, the compiled quantum circuit may first be formatted in an intermediate representation that represents the elements of the quantum circuit (e.g., qubits and gates) using logic operators that are not specific to any one quantum hardware device or type of quantum hardware device. This may allow a customer to write a single quantum circuit and then run that single quantum circuit on various different quantum hardware devices, for example, which may be provided by various quantum hardware providers and which may use various quantum computing techniques. To compile such a quantum circuit represented in the intermediate representation, the logic elements are first converted into native operators that are native to the particular type of quantum hardware to be used to run the quantum circuit. Then, qubit assignment and mapping determine how to assign the logic qubits of the nativeized quantum circuit to the physical qubits of the quantum processing unit to be used to run the quantum circuit, using the nativeized quantum circuit. Mapping also involves determining which gates will be executed between which physical qubits and in what order so that the mapped gates achieve the logic of the nativeized quantum circuit. In some embodiments, various optimization solvers, such as SAT solvers and SMT solvers, may be used to determine the optimized mapping.

[0013] In some embodiments, nativeization may involve decomposing a higher-level abstract quantum gate (or other logical operator) into a set of native gates that, when performed in a specific order, achieve the logical result of the higher-level abstract quantum gate. In some embodiments, a customer of the quantum compilation service may submit custom gate decompositions that the customer wishes to be used in compiling quantum circuits on their behalf. The quantum circuit compilation service may also include its own library of gate decompositions used to nativeize quantum circuits. In some embodiments, the gate decomposition library of the quantum circuit compilation service may be extended using custom gate decompositions submitted by the customer.

[0014] In some embodiments, a customer may request that the quantum circuit compilation service determine a compilation job plan, for example, a list of compilation paths to be performed, and the quantum circuit compilation service returns to the customer a software container containing the quantum circuit job plan and modularized compilation path instructions (e.g., executable code) for performing the compilation paths indicated in the compilation job plan. Alternatively, in some embodiments, the quantum circuit compilation service may determine a compilation job plan and orchestrate its execution using computing resources of a service provider network. For example, the service provider network may include computing resources that can be efficiently scaled up to perform mapping optimization using high-performance solvers, such as a SAT solver or an SMT solver. Also, in some embodiments, the performance of the compilation paths may be shared between the client-side compiler and the quantum compilation service. For example, a client-side compiler may perform its own compilation process but lack the resources to perform a high-performance solver, and therefore may delegate the mapping optimization compilation path to the quantum compilation service to perform it using, for example, a SAT solver, an SMT solver, etc. As yet another example, a customer may delegate compilation to a quantum circuit compilation service, but may reserve one or more compilation passes performed by the customer's client-side compiler. In such a case, the quantum compilation service may pass the partially compiled quantum circuit to the customer's client-side compiler (e.g., in an intermediate representation), and then receive an updated version of the partially compiled quantum circuit containing the results from one or more compilation passes performed by the customer's client-side compiler.The quantum compilation service may perform one or more additional compilation passes to complete the compilation, return the compiled quantum circuit to the customer, and / or pass the compiled quantum circuit to a quantum computing service configured to orchestrate the execution of the compiled quantum circuit for the customer using the quantum hardware provider's QPU and / or the quantum computing service's QPU.

[0015] In some embodiments, an optimized compilation pass may be performed throughout the compilation process. An optimized compilation pass may reduce the gate count, for example, by identifying gates that can be replaced and therefore removed, or by reducing swapped gates, for example, by determining an optimized gate scheduling that better utilizes the qubit connectivity of the quantum hardware. Optimization may also rearrange qubit allocation and / or gate scheduling to reduce circuit depth, crosstalk, idle errors, etc. As another example, optimization may merge single-qubit gates, such as a series of consecutive single-qubit gates.

[0016] In some embodiments, a second phase of the compilation process uses the compiled quantum circuit resulting from the first phase to generate compiled artifacts for implementing pulses. For example, the quantum processing unit may include a field-programmable gate array (FPGA) or other processor that acts as an interface for the QPU's equipment, which emits pulses that quantum-entangle qubits and gates on a physical quantum hardware device. The FPGA may execute compiled artifacts, such as compiled binaries, to cause the QPU's equipment to emit pulses of a determined pulse sequence. In some embodiments, the customer may submit custom pulse sequences to be used to implement specific gates, and these custom pulse sequences may be used when generating compiled artifacts for implementing pulses, such as compiled binaries executed using an FPGA or ASIC that controls the equipment of the quantum hardware device. In some embodiments, the quantum compilation service may perform further optimizations when generating pulse sequences. For example, efficiency may be gained by changing the ordering of pulses.

[0017] In some embodiments, a customer of a quantum compilation service may desire "verbatim" compilation and / or execution of quantum circuits. For example, to conduct reproducible experiments, a customer may desire that compilation be performed without variability from one run to the next. To provide "verbatim" compilation, a customer may provide their own quantum compilation job plan, which will be executed using the resources of the "verbatim" quantum compilation service, as laid out in a quantum compilation job plan provided by the customer. Alternatively, a customer may submit a set of quantum circuits and indicate that "verbatim" compilation should be performed by the quantum compilation service. In such a case, the quantum compilation service may determine a quantum compilation job plan for the first instance of the set of verbatim quantum circuits and cache the determined compilation job plan which will be used "verbatimally" to compile the remaining instances of the set of verbatim quantum circuits. Also in some embodiments, a customer may perform compilation using a client-side compiler to generate compiled artifacts to be used for "verbatim" execution. In some embodiments, the client-side compiler may outsource one or more passes to the quantum circuit compilation service, as described above.

[0018] In some embodiments, a quantum circuit compilation service may provide a centralized and standardized compilation process that enables customers to learn how to compile quantum circuits to run on various types of quantum hardware devices, while avoiding the need for customers to learn the details of the diverse compilation procedures used by various different quantum hardware providers. For example, a customer may use the quantum compilation service to compile quantum circuits to run on various different quantum hardware provider QPUs. As described in more detail below, the use of modularized compilation paths may enable the quantum compilation service to be configured to compile various types of quantum circuits to be compiled for various types of quantum hardware devices. The modularity of modularized compilation paths also enables efficient use of resources, for example, by scaling up computing resources to perform high-performance optimizations, while not requiring the allocation of such large amounts of computing resources when implementing other less computationally intensive modularized compilation paths.

[0019] In some embodiments, the quantum compilation service may also decouple the compilation of quantum circuits from their execution. For example, the quantum compilation service may compile quantum circuits outside of the workflow for executing them on the QPU. This may enable pre-compilation. For instance, if a quantum algorithm includes various quantum circuits, the quantum compilation service may pre-compile the various quantum circuits before execution. This may enable more efficient use of the access time window on the QPU. For example, instead of waiting for subsequent quantum circuits in a quantum algorithm to be called and then compiling those subsequent quantum circuits, the quantum circuits may be compiled in advance, and the resulting compiled artifacts can be run when each quantum circuit is called without waiting for compilation. This may contribute to more efficient use of the limited access time window for QPU use.

[0020] In some embodiments, the quantum compilation service may further utilize machine learning to select modularized compilation paths included in the compilation job plan and / or determine the ordering for executing the modularized compilation paths.

[0021] In some embodiments, the quantum compilation service may be further connected to a quantum hardware information service that collects information from the quantum hardware provider, such as qubit connectivity graphs and calibration information. This collected information can be used to compile quantum circuits for execution on each quantum hardware provider. Connecting to the quantum hardware information service may also avoid the need for the customer to provide such information when requesting that a given quantum circuit be compiled by the quantum circuit compilation service.

[0022] In some embodiments, the mapping process involves enabling a logic quantum circuit to be executed on a given quantum hardware device according to the physical qubit connectivity graph (also referred to as the qubit interaction graph) of the quantum hardware device. Such a process may be referred to herein as quantum circuit mapping. In some embodiments, the logic computations that may be required to execute the logic quantum circuit may utilize more physical qubits than are available on a given quantum hardware device, and / or the logic computations may not be guided to a given configuration of physical qubits and connected edges (also referred to as the physical qubit connectivity graph). For example, the logic computations may assign a gate to be performed between two physical qubits on a quantum hardware device that are not physically connected via edges. In such cases, a “SWAP operation” (e.g., a SWAP gate) may be used to logically exchange quantum states between the two respective physical qubits, enabling the circumvention of some physical limitations of the given quantum hardware device.

[0023] A SWAP operation (e.g., a SWAP gate) can extend the ability of a given quantum hardware device to perform a logic operation by allowing a specific qubit state to be logically remapped, but such a SWAP operation can increase the duration required to execute a given logic quantum circuit. For example, a SWAP gate may include three CNOT gates that add time to the total execution time of the logic quantum circuit. Furthermore, the three CNOT gates may introduce additional errors and / or noise (e.g., crosstalk), and thus introduce additional difficulty in error correction of the quantum circuit. Therefore, it is beneficial to minimize the number of SWAP operations (e.g., SWAP gates) implemented in a given quantum circuit mapping.

[0024] Solving a given quantum circuit mapping problem (e.g., mapping a given logic quantum circuit to a given qubit layout of a quantum hardware device and generating an assignment that can be performed using the quantum hardware device) and optimizing it (e.g., minimizing the number of SWAP gates) can be considered an NP-hard (also called NP-complete) optimization problem.

[0025] Exemplary quantum computing service Quantum computers are difficult and costly to build and operate. Furthermore, there is a diverse range of quantum computing technologies under development, and there is no clear trend indicating which of these technologies will gain prominence. Therefore, potential users of quantum computers may hesitate to invest in building or acquiring a particular type of quantum computer, as other quantum computing technologies may outperform the selected quantum computing technology they could invest in. Additionally, successfully using quantum computers to solve practical problems may require considerable trial and error and / or significant specialized knowledge.

[0026] As an alternative to building and maintaining quantum computers, potential users of quantum computers may instead prefer to rely on quantum computing services to provide access to quantum computers. In some embodiments, quantum computing services such as those described herein may enable potential users of quantum computers to access quantum computers based on multiple different quantum computing technologies and / or paradigms without the costs and resources required to build or manage such quantum computers. In some embodiments, quantum computing services such as those described herein may provide a variety of services that simplify the experience of using quantum computers so that potential users of quantum computers who lack deep experience or knowledge of quantum mechanics can nevertheless use quantum computing services to solve problems.

[0027] Furthermore, in some embodiments, quantum computing services, such as those described herein, may be used to complement other services provided by the service provider network. For example, a quantum computing service may interact with classical computing services to execute hybrid algorithms. In some embodiments, a quantum computing service may enable a classical computer to be accelerated by sending a particular task to a quantum computer for execution, and then using the results of the execution of the quantum computing object on the quantum computer to perform additional classical computations. For example, a quantum computing service may enable the acceleration of a virtual machine implemented on classical hardware, similar to how a graphics processing unit (GPU) can accelerate graphical computations that would otherwise be performed on a central processing unit (CPU). A quantum computing service may also interact with other services provided by the service provider network, such as the compilation service described above.

[0028] In some embodiments, a quantum computing service may provide potential quantum computer users with access to quantum computers using a variety of quantum computing techniques, such as quantum annealers, ion trap machines, superconducting machines, Rydberg atomic arrays, and photonic devices. In some embodiments, a quantum computing service may provide customers with access to at least three broad categories of quantum computers, including quantum annealers, circuit-based quantum computers, and analog or continuous-variable quantum computers. As used herein, these three broad categories may be referred to as quantum computing paradigms.

[0029] In some embodiments, a quantum computing service may be configured to provide a simulation service that uses classical hardware-based computing instances to simulate the execution of quantum circuits on a quantum computer. In some embodiments, a quantum computing service may be configured to perform general simulations and / or simulations that specifically simulate the execution of quantum circuits on a particular type of quantum computer of a particular type of quantum computing technology or paradigm. In some embodiments, the simulation may be entirely managed by the quantum computing service on behalf of the customer of the quantum computing service. For example, the quantum computing service may ensure sufficient computing power on a virtualized computing service of a service provider network to perform simulations without the customer being involved in the details of managing the simulator's resources.

[0030] In some embodiments, the quantum computing service may include a dedicated console that provides customers with access to multiple quantum computing technologies. Furthermore, the quantum computing service may provide a quantum algorithm development kit that enables customers with varying levels of expertise in quantum circuit design to design and execute quantum circuits. In some embodiments, the console of the quantum computing service may include various application programming interfaces (APIs), such as: ● Simulator Configuration (Create / Delete / Update / Get / List) - Create, read, update, and delete (CRUD) operations on simulator configuration objects. ●(Start / Cancel / Description) Simulator - Used to control each user-defined simulator instance. ●(List / Description) Quantum Processor Unit (QPU) - Extracts information from quantum computer hardware. ●(Create / Cancel / List / Description) Jobs - Used to manage the lifecycle of quantum jobs. ● (Assignment / Update / List) Quality of Service (QoS) Assurance - Used to manage QoS assurance for quantum jobs and / or quantum tasks. ●(Create / Cancel / List / Description) Task - Used to manage the lifecycle of individual quantum tasks / quantum objects.

[0031] In some embodiments, the quantum algorithm development kit may include a graphical user interface, API, or other interface to enable customers of quantum computing services to define quantum objects such as quantum tasks, quantum algorithms, or quantum circuits using the quantum algorithm development kit. In some embodiments, the quantum algorithm development kit may include interface options that enable customers to share quantum objects with other customers of quantum computing services. For example, the quantum algorithm development kit may include a marketplace that enables customers to share or sell specific quantum objects with other customers. In some embodiments, the quantum algorithm development kit may include interface elements that enable customers to select QoS to apply to quantum jobs or quantum tasks defined via the quantum algorithm development kit. Also, in some embodiments, the quantum algorithm development kit (or other SDK) may enable customers to define parameters for compilation and / or build compilation job plans.

[0032] In some embodiments, a quantum computing service may include a public application programming interface (API) that accepts quantum objects submitted by customers of the quantum computing service. In some embodiments, the quantum computing service may accept instructions for QoS assurance used for one or more quantum jobs or quantum tasks, such as executing quantum objects received via the public API, either through the public API or another API. In addition, the quantum computing service may include a non-public backend API transport. The backend API transport may enable the transport of quantum circuits from a centralized location implementing the quantum computing service, such as one or more data centers in a service provider network, to edge computing devices at a specific quantum hardware provider location where the quantum circuits are to be executed. In some embodiments, quantum objects or quantum tasks may be executed using the internal QPU of the quantum computing service without using a backend API transport to transport quantum jobs or quantum tasks to an external quantum hardware provider location.

[0033] In some embodiments, the results of executing quantum circuits on a quantum computer at a quantum hardware provider location may be provided to an edge computing device at the quantum hardware provider location. The edge computing device may automatically transport the results to a secure storage service on the service provider network, and customers can access the results using the storage service on the service provider network or via the console of the quantum computing service. Similarly, the results of executing quantum circuits via an internal QPU may be accessed via the console of the quantum computing service.

[0034] In some embodiments, results stored in a secure storage service can be seamlessly used by other services integrated into the service provider network, such as machine learning services, database services, object-based storage services, block storage services, and data presentation services (which reformat the results into a more usable configuration). For example, in some embodiments, a machine learning service may be used to optimize a quantum algorithm or quantum circuit. For example, a machine learning service may, via a quantum computing service, allow various versions of a quantum algorithm or quantum circuit to be run on a quantum computer. The machine learning service may also provide access to the results of running the quantum algorithm or quantum circuit. In some embodiments, a machine learning service may allow the quantum algorithm or quantum circuit to be run on quantum computers based on various different quantum computing technologies. Based on the results, the machine learning service may determine one or more optimizations to improve the quantum algorithm or quantum circuit.

[0035] In some embodiments, a quantum computing service may support creating snapshots of the results of executing quantum circuits. For example, a quantum computing service may store snapshots of intermediate results of a hybrid algorithm, or more generally, snapshots of any results generated by executing a quantum circuit on a quantum computer. In some embodiments, an edge computing device at a hardware provider location may temporarily store the results and create snapshot copies of the results stored on the edge computing device. The edge computing device may further ensure that the snapshot copies are stored in an object-based data storage service on the service provider network. In some embodiments, snapshots may not be taken, based on customer preference.

[0036] Furthermore, in connection with the description herein, it can be understood that quantum hardware, such as quantum hardware devices, may be used to implement quantum computers and / or various components of a quantum computer (e.g., quantum processing units / cores (QPUs), routing spaces, magic state distillation factories, and other components used to perform logical quantum computation). For example, a given quantum hardware device may be analogous to the "building blocks" of a quantum computer, such as a grid of qubits (e.g., a one-dimensional grid, a two-dimensional grid, etc.) that can be initialized in various ways to form various components of a quantum computer, such as a topological quantum code. The quantum hardware device may be further configured so that single-qubit gates, multi-qubit gates, and / or other operations of quantum circuits can be performed between the qubits of the quantum hardware device (according to a given physical qubit connectivity graph of the quantum hardware device detailing which physical qubits are connected to each other physical qubits via edges). Those skilled in the art should also understand that, depending on factors such as the type of qubit technology used and the type of gates performed between the qubits, quantum hardware devices may also include various control devices (e.g., function generators, devices for controlling temperature, magnetism, and / or other environmental factors related to the local environment of the qubit grid) that can be used to maintain and / or transform various properties of the qubits and / or other physical components of a given quantum computer. Furthermore, those skilled in the art should understand that a qubit may refer to both a logical bit (e.g., 1 or 0 with a certain probability) and one or more physical components used to construct a given qubit. For example, a superconducting qubit (e.g., a transmon) may be constructed using at least a superconducting material and a non-superconducting material located between sections of the superconducting material.In relation to this understanding, it should also be understood that quantum hardware can therefore be used to implement physical qubits, which can be combined in various ways to implement one or more logical qubits, so that logical quantum operations can be performed using the physical elements of the quantum hardware, in the manner described above.

[0037] Exemplary services and interactions in a service provider network Figure 1 illustrates, in several embodiments, a service provider network that enables customers to compile and / or execute quantum circuits using multiple quantum computing technologies.

[0038] In some embodiments, the service provider network 100 may include a variety of services, such as quantum computing services 102, compilation services 134, and optimization problem services 144, in addition to one or more other services related to quantum compilation and quantum computation. In some embodiments, the service provider network 100 may include data centers, routers, networking devices, etc., such as a cloud computing provider network. In some embodiments, customers 104, 106, and 108, and / or additional customers of the service provider network 100 and / or quantum computing services 102, may connect to the service provider network 100 in a variety of ways, such as via a logically isolated connection over a public network, via a dedicated private physical connection inaccessible to the public, or via a public internet connection.

[0039] In some embodiments, the service provider network 100 may include a compilation service 134. The compilation service 134 may take in an input logic quantum circuit and orchestrate one or more compilation paths (e.g., compilation mapping of the logic quantum circuit to a given quantum hardware device structure, compilation of gate nativeization, conversion of the quantum circuit to a quantum circuit specific to the design / language / architecture / technology of a given quantum hardware provider) which can be used to execute the circuit using a given quantum hardware device of a given quantum hardware provider via the quantum computing service 102. Customers of the service provider network 100 (e.g., customers 104, 106, 108, etc.) may interact with the compilation service 134 to submit compilation requests, according to some embodiments. The compilation service 134 may also, for example, in some situations based on the customer's preference, return the compiled quantum circuit to the customer instead of providing the compiled quantum circuit directly to the quantum computing service 102 for execution.

[0040] In some embodiments, a modularized path of the compilation service may perform various steps in the compilation process. For example, the mapping module 136 may be used to encode the quantum circuit mapping as an optimization problem, such as a SAT solver problem. According to some embodiments, inputs and information related to the quantum circuit mapping generated via the compilation service 134 may be received and stored using logic quantum circuit information and physical qubit connectivity information. Such inputs may be submitted via the user interface 140 (see the description of interface 1100 shown in Figure 11 in this specification). For example, the logic quantum circuit cache 1352 (as shown in Figure 13) may be configured to store logic quantum circuits of one or more customers of the compilation service 134, and the logic qubit list 1354 and gate list 1356 may be configured to store lists of logic qubits and gates corresponding to each logic quantum circuit (see also the description of Figure 12B in this specification). According to some embodiments, in order to encode a quantum circuit mapping problem as a SAT solver problem, a gate dependency list may be generated as part of the encoding process based on a given logic quantum circuit stored in the logic quantum circuit cache 1352. Such gate dependency generation may be stored in a gate dependency generation 1358 according to some embodiments. In another example, a physical qubit connectivity graph cache 1362 may be configured to store physical qubit connectivity graphs (e.g., physical qubit connectivity graph 1200 shown in Figure 12A) of one or more quantum hardware devices of a quantum hardware provider (e.g., quantum hardware providers 124, 126, 128, 130), and / or physical qubit connectivity graphs provided by customers of the compilation service 134. Physical qubit lists 1364 and edge lists 1366 may be configured to store lists of physical qubits and edges corresponding to their respective physical qubit connectivity graphs.In some embodiments, in order to encode a quantum circuit mapping problem as a SAT solver problem, a list of physical qubits and edges may be generated as part of the encoding process based on a given physical qubit connectivity graph stored in a physical qubit connectivity graph cache 1362.

[0041] In some embodiments, the compilation service 134 is configured to use the information in the logic quantum circuit information 1350 and the physical qubit connectivity information 1360, and a layout transition-based sequential coding scheme defined via the SAT coding definition 1370, to generate a CNF equation representing a given quantum circuit mapping problem. According to some embodiments, the SAT coding definition 1370 may include one or more conditions, constraints, and / or other definitions used to code the quantum circuit mapping problem as a SAT solver problem, such as a gate scheduling condition 1372, a qubit mapping condition 1374, a SWAP operand selection condition 1376, and / or other conditions 1378.

[0042] The encoded SAT solver problem can then be provided by the compilation service 134 to the optimization problem service (e.g., optimization problem service 142, optimization problem service 144, etc.) so that the encoded SAT solver problem can be executed using a SAT solver (e.g., a SAT solver invoked by modularized path 1302). In some embodiments, the optimization problem service may be configured to implement SAT solving instances in addition to instances of other optimization problem solving techniques (e.g., SMT solving, heuristic solving methods, etc.).

[0043] The compilation service 134 may also orchestrate and / or harmonize the execution of an encoded SAT solver problem. For example, the compilation service 134 may use an optimization problem service to request specific computing resources, time allocations, etc., to enable the execution of an encoded SAT solver problem. In some embodiments, the compilation service 134 may communicate with an optimization problem service 144 in the service provider network 100 to harmonize the execution of a given encoded SAT solver problem using a SAT solving instance of the SAT solver 146. In some embodiments, the compilation service 134 may be configured to communicate with one or more other optimization problem services accessible via the service provider network 100, such as an optimization problem service 142, which may be located on a premises outside the service provider network 100. In such embodiments, the compilation service 134 may communicate with the optimization problem service 142 via an edge computing device physically located on the premises of the optimization problem service 142, so that the service provider network 100 can be extended. In some embodiments where multiple encoded SAT solver problems are submitted for execution using SAT solving techniques, the compilation service 134 may be further configured to harmonize the execution of the problems using multiple optimization problem services in order to make the execution more efficient.

[0044] While the above example is specific to SAT resolution, it should be noted that in some embodiments, the modularized paths 136-138 of the compilation service 134 may utilize other mapping paradigms, such as using reinforcement learning-based trained models as shown in Figure 14, SMT resolution as shown in Figure 15, or various other mapping processes.

[0045] The compilation service 134 may also include one or more additional modules (e.g., other compilation modules 1338, 1438, 1538, etc.). For example, a transformation module may be configured to transform non-Clifford operations of a logic quantum circuit into a set of Clifford operations and / or to perform one or more other intermediate transformations related to the target quantum hardware provider. In another example, several 2-qubit gates of a logic quantum circuit may be decomposed into a set of native gates, and a gate nativeization module may be configured to perform such decomposition. In yet another example, in some embodiments where the quantum hardware provider of quantum hardware providers 124-130 relates to a Rydberg atomic array, according to some embodiments, other compilation modules (e.g., 1338, 1438, 1538, etc.) may include a module configured to compile and / or encode a mapping problem for determining the atomic computation positions in the Rydberg atomic array.

[0046] The service provider network 100 also includes quantum computing services 102. In some embodiments, quantum computing services 102 may include a quantum computing simulator using a quality of service (QoS) and out-of-band prioritization module 110, a quantum algorithm development kit 116, a transformation module 114, and classical hardware 120. Quantum computing services 102 also connect to quantum hardware providers 124, 126, 128, and 130. In some embodiments, quantum hardware providers 124, 126, 128, and 130 may provide access to run quantum objects on quantum computers operating on various different types of quantum computing techniques or paradigms, such as those based on quantum annealing, ion traps, superconducting materials, photons, etc.

[0047] As will be discussed in more detail in Figure 16, in some embodiments, the service provider network 100 may be extended to include one or more edge computing devices physically located at quantum hardware provider locations, such as at the facilities of quantum hardware providers 124, 126, 128, and 130. Physically locating the edge computing devices of the service provider network 100 on-premises at the quantum hardware provider facilities (e.g., colocating them) can extend the data security and encryption of the service provider network 100 to the facilities of quantum hardware providers 124, 126, 128, and 130, and thus ensure the security of customer data. Furthermore, physically locating the edge computing devices of the service provider network 100 on-premises at the quantum hardware provider facilities can reduce latency between the computing instances of the service provider network and the quantum computers located at the quantum hardware provider facilities. Therefore, some applications, such as hybrid algorithms that are sensitive to network latency, can be implemented by the quantum computing service 102, whereas other systems that do not have the classical computing power to colocate at the hardware provider locations may have too high a latency to efficiently implement such hybrid algorithms.

[0048] In some embodiments, the quantum computing service 102 includes one or more backend API transport modules 112. In some embodiments, the backend API transport module 110 may be primarily implemented on edge computing devices of the quantum computing service located at the quantum hardware provider location (such as edge computing devices 1604a, 1604b, 1604c, and 1604d shown in Figure 16). Also in some embodiments, at least a portion of the backend API transport functionality may be implemented on one or more computing devices of the service provider network implementing the quantum computing service (such as computing devices in data centers 1606a, 1606b, and 1606c illustrated in Figure 16). In some embodiments, different quantum hardware providers may require different backend API transport modules, which may add further variability to the execution duration of quantum tasks. Some quantum hardware providers may accept quantum tasks over the network via APIs such that the provider network does not need to locate edge computing devices at the quantum hardware provider's facilities to submit quantum tasks. In some embodiments, some quantum hardware providers may follow a first-in, first-out (FIFO) execution model for quantum tasks submitted to them for execution. Other quantum hardware providers may follow a batch execution model. To address these execution duration variability and further address execution duration variability due to various quantum task characteristics (e.g., number of shots, quantum circuit size, number of gates, switching time between quantum circuits, etc.), a priority access control plane may order quantum tasks submitted to the backend API transport for various quantum hardware providers in a prioritized order so as to comply with quality of service (QoS) guarantees and other scheduling rules.

[0049] The quantum computing service 102 is also configured to convert a given quantum computing object into a selected quantum circuit format for a specific quantum computing technology used by a selected quantum hardware provider or internal QPU, where the selected quantum circuit format for a specific quantum computing technology is one of several quantum circuit formats for several different quantum computing technologies supported by the quantum computing service. To convert a quantum computing object into a selected quantum circuit format, one or more computing devices implementing the quantum computing service are configured to identify the portion of the quantum computing object in which the quantum object corresponds to quantum operators in an intermediate representation submitted by the customer, replace the quantum operators in the intermediate representation with quantum operators in the quantum circuit format of the specific quantum computing technology, and perform one or more optimizations to reduce the total number of quantum operators in the converted quantum circuit, which is the converted version of the received quantum computing object. In addition, the quantum computing service 102 may be configured to provide the converted quantum circuit for execution in a quantum hardware provider or internal QPU using the specific quantum computing technology, receive the results of the execution of the converted quantum circuit from the quantum hardware provider or internal QPU, and provide notification to the customer of the quantum computing service that the quantum computing object has been executed.

[0050] The quantum circuits transformed by the transformation module 114 may be provided to the backend API transport module 112 for transport to the quantum computer at each quantum hardware provider location. In some embodiments, the backend API transport 112 may be a private API accessible by edge computing devices in the service provider network 100 but not publicly available. In some embodiments, a quality of service (QoS) and out-of-band prioritization module 110 may manage which quantum tasks are submitted to the backend API transport and in what order. In some embodiments, edge computing devices in quantum hardware providers 124, 126, 128, and 130 may periodically ping the quantum computer service-side interface to the backend API transport 112 to determine if there are any quantum circuits (or batches of quantum circuits) waiting to be transported to the edge computing device. If so, the edge computing device may make an API call to the backend API transport 112 so that the quantum circuits are transported over a private connection to the edge computing device and scheduled for execution on the quantum computer. Furthermore, the edge computing device may be configured to have a quantum machine image that enables the edge computing device to cooperate with the scheduling application of the quantum hardware provider on which the edge computing device is located, in order to schedule time slots for executing quantum circuits on the quantum computer of the quantum hardware provider via the backend API transport 112.

[0051] In some embodiments, the results of executing a quantum circuit on a quantum computer at a quantum hardware provider location may be returned to an edge computing device at the quantum hardware provider location. The edge computing device and / or quantum computing service 102 may ensure that the results are stored in a data storage system of the service provider network 100. In some embodiments, a results storage / notification module 118 may synchronize the storage of results and notify a customer, such as customer 104, that the results are ready from the execution of the customer's quantum object, such as a quantum task, quantum algorithm, or quantum circuit. In some embodiments, the results storage / notification module 118 may allocate storage space in the data storage service to the customer to store the customer's results. The results storage / notification module 118 may also specify access restrictions for viewing the customer's results according to the customer's preferences.

[0052] In some embodiments, a quantum computing simulator using classical hardware 120 of a quantum computing service 102 may be used to simulate quantum algorithms or quantum circuits using classical hardware. For example, one or more virtual machines of a virtual computing service may be instantiated to handle quantum algorithm or quantum circuit simulation jobs. In some embodiments, the quantum computing simulator using classical hardware 120 may have complete control over the computing instances that perform the quantum circuit simulation. For example, in some embodiments, a customer may submit the quantum circuit to be simulated, and the quantum computing simulator using classical hardware 120 may determine the resources needed to perform the simulation job, such as allocating resources and configuring resources. In some embodiments, the quantum computing simulator using classical hardware 120 may include one or more "warm" simulators that are pre-configured simulators ready to perform simulation jobs without the delays typically associated with allocating resources and configuring resources to run the simulation.

[0053] In some embodiments, the quantum computing service 102 includes a quantum hardware provider recommendation / selection module 122. In some embodiments, the quantum hardware recommendation / selection module 122 may make recommendations to the customer of the quantum computing service regarding what type of quantum computer or which quantum hardware provider to use to execute the quantum object submitted by the customer. In addition, or otherwise, the quantum hardware provider recommendation / selection module 122 may receive a customer selection of the type of quantum computer and / or quantum hardware provider to use to execute the customer's quantum object, such as a quantum task, quantum algorithm, quantum circuit, etc., submitted by the customer or otherwise defined in the customer input. In some embodiments, the recommendations may include estimated costs, error rates, runtime, etc., associated with executing the quantum computing object on each quantum computer, either a quantum hardware provider or an internal QPU.

[0054] In some embodiments, the recommendations provided by the quantum hardware provider recommendation / selection module 122 may be based on one or more characteristics of a quantum object submitted by the customer, and one or more characteristics of quantum hardware providers supported by the quantum computing service 102, such as one or more of quantum hardware providers 124, 126, 128, or 130.

[0055] In some embodiments, the quantum hardware provider recommendation / selection module may make recommendations based on known data about previously executed quantum objects similar to the quantum object submitted by the customer. For example, the quantum computing service 102 may store a certain amount of metadata about executed quantum objects and use such metadata to make recommendations. In some embodiments, the recommendation may include an estimated cost for performing the quantum computing task by each of the first and second quantum hardware providers. In some embodiments, the recommendation may include an estimated error rate for each of the first and second quantum hardware providers with respect to performing the quantum computing task. In some embodiments, the recommendation may include an estimated time length for performing the quantum computing task for each of the first and second quantum hardware providers. In some embodiments, the recommendation may include various other types of information related to one or more quantum hardware providers or any combination thereof.

[0056] In some embodiments, a quantum computing simulator using classical hardware 120 may enable a customer to simulate one or more specific quantum computing technology environments. For example, a customer may simulate quantum circuits in an annealing quantum computing environment and an ion trap quantum computing environment to determine the simulated error rate. The customer may then use this information to select a quantum hardware provider to use to run their quantum circuits.

[0057] Quantum Compilation as a Service The following figures (Figures 2-10B) provide illustrative embodiments of how the compilation service 134 may be used to compile quantum circuits on behalf of customers for execution using various types of quantum hardware devices, according to several embodiments.

[0058] Figure 2 illustrates additional components that may be included in a quantum circuit compilation service of a service provider network, such as a quantum circuit compilation service 134 of the service provider network 100, in several embodiments.

[0059] In some embodiments, a quantum compilation service such as compilation service 134 may include path selection 202, a modularized compilation path repository 204, computing resource provisioning 206, a gate decomposition library 208, compilation path execution orchestration 210, a pulse sequence library 212, compiled artifact storage 214, verbatim compilation orchestration 216, a user interface 140, a quantum computing service interface 218, and other service interfaces 220 for orchestration.

[0060] In some embodiments, the modularized compile path repository 204 may include various compile path modules for performing various steps of compilation, such as qubit assignment, gate mapping, optimization, and pulse sequence generation. The compile path selection module 202 may select a set of available modularized compile paths to be included in a quantum compilation job. For example, one of the given qubit assignment path modules may be selected along with one or more optimization path modules. A given mapping module may be selected from a set of supported mapping compile path modules, such as a SAT solver-based mapping module (as shown in Figure 13), a machine learning-based mapping module (as shown in Figure 14), or an SMT solver-based mapping module (as shown in Figure 15). In some embodiments, the compile path selection 202 may be performed according to customer preferences submitted via the user interface 140. In some embodiments, a machine learning model may be used by the compile path selection module 202 to select compile paths to be included in a quantum compilation job for a given quantum circuit, and / or to determine the order or sequence of the selected compile paths. Furthermore, in some embodiments, multiple passes from different sets of sets may be selected to be included in the quantum compilation job plan. For example, multiple optimization passes may be performed sequentially and / or between each of the remaining other passes. Also, in some embodiments, passes may not be selected from each kind of set. For example, a customer may provide a partially compiled quantum circuit, where qubit assignment has already been performed, and may ask the quantum circuit compilation service to perform gate mapping using a more powerful solver, such as a SAT solver or an SMT solver. In such a scenario, the quantum compilation job plan may omit the qubit assignment pass and / or apply optimization passes to the initially provided qubit assignment to determine an improved qubit assignment.The quantum circuit job plan may then include paths for performing gate mapping, such as modularized paths that invoke higher-performance solvers, like SAT solvers or SMT solvers.

[0061] Computation resource provisioning 206 may provision (and scale up or down) the computing resources required to execute each compilation path using quantum compilation modules from the modularized compilation path repository 204. For example, virtual computing resources may be allocated from virtualized computing services of the service provider network 100 to execute the compilation instructions contained in each of the modularized compilation path modules. In some embodiments, compilation path execution orchestration module 210 may provide performance for workflow management tasks such as loading instructions for executing a given modularized quantum compilation path onto provisioned computing resources, providing input representations of quantum circuits to be compiled into the modularized quantum compilation path, and / or harmonizing the storage or transfer of resulting versions of quantum circuits after they have been at least partially compiled by the modularized quantum compilation path. For example, compilation path execution orchestration module 210 may route a partially compiled quantum circuit to the next modularized compilation path implemented on another provisioned computing resource. Furthermore, as described below, in some embodiments, a partially compiled quantum circuit may be routed to a client-side compiler, which performs one or more compilation passes and then returns a further compiled version of the quantum circuit to the compilation service 134 for further compilation.

[0062] In some embodiments, an intermediate or final compiled version of the quantum circuit to be compiled may be stored in the compiled artifact storage 214. In some embodiments, the compiled artifact representing the compiled quantum circuit may be provided to the customer, for example, via the user interface 140, for execution on the customer's quantum computer or a third-party quantum computer. In some embodiments, the compiled artifact may be provided as a compiled circuit representation, which represents a compiled version of the quantum circuit specifically compiled for execution on a given QPU. In some embodiments, the compiled artifact may also be compiled into a pulse sequence to be used to implement the quantum circuit on a given QPU. In addition, in some embodiments, the compiled artifact may include a compiled pulse sequence compiled into a compiled binary that runs on a processor of an associated quantum hardware device, such as an FPGA or ASIC.

[0063] In some embodiments, compiled artifacts may be provided to a quantum computing service, such as quantum computing service 102, for execution via the quantum computing service's QPU or via the QPU of a third-party quantum hardware provider (QHP) associated with the quantum computing service. For example, compiled artifacts may be provided to quantum computing service 102 using the quantum computing service interface 218. In some embodiments, computing resource provisioning 206 may use other service interfaces 220 for orchestration to secure the computing resources necessary to implement a given modularized compilation pass. Compilation pass execution orchestration 210 may also cooperate with other services to implement a particular aspect of the modularized compilation pass. For example, other service interfaces 220 for orchestration may be used to call solver 146 or solver 148 of optimization problem service 144, for example, as part of implementing a mapping compilation pass.

[0064] In some embodiments, the customer may also submit custom paths, custom gate decompositions, and / or custom pulse sequences to be used when compiling the customer's quantum circuits. These custom objects may be stored in a gate decomposition library 208, a pulse sequence library 212, and / or a modularized compilation path repository 204, and may augment the respective gate decompositions, pulse sequences, and modularized paths stored in the respective libraries and repositories.

[0065] In some embodiments, verbatim compilation orchestration may cache quantum circuit compilation job plans so that subsequent quantum circuits that call the same verbatim compilation are compiled according to a consistent job plan. This can reduce compilation variability, for example, for customers conducting experiments.

[0066] Figure 3 illustrates exemplary modularized compilation paths that may be included in a modularized compilation path repository for a quantum circuit compilation service, according to several embodiments.

[0067] In some embodiments, a modularized compilation path repository may include multiple modularized compilation path modules that can be selected for various steps in the compilation process. For example, different modularized compilation paths may be mixed and adapted to form a quantum compilation job plan that is customized to the needs of a given compilation job (e.g., a quantum circuit to be compiled). For example, a modularized compilation path repository 204 may include multiple qubit allocation modules 302, such as modules 304A to 304N; multiple gate scheduling modules 306, such as modules 308A to 308N; multiple optimization modules 310, such as optimization modules 312A to 312N; multiple pulse sequence generation modules 314, such as modules 316A to 316N; and one or more other compilation modules 318, which may include modules 320A to 320N.

[0068] In some embodiments, each set of different types of optimization modules (e.g., qubit allocation module 302, gate scheduling module 306, optimization module 310, pulse sequence generation module 314, other compilation modules 318, etc.) may include a diverse number of optimization path modules, the applicability of each path varying based on quantum hardware technology, the state of the partially compiled quantum circuit (before each path is executed), etc. In some embodiments, a particular path among the paths may be selected from each set of optimization modules based on the state of a given quantum circuit being compiled.

[0069] In some embodiments, past compilation experience can be used to select which paths to use and in what order to arrange the selected paths. For example, a machine learning model can be used to perform path selection, and the machine learning model can provide recommendations for paths to include in the compilation job plan.

[0070] In some embodiments, the customer may specify one or more paths to be used, such as a SAT solver mapping optimization path or an SMT solver mapping optimization path. In some embodiments, the paths may be selected based on constraints. For example, the quantum circuit compilation service and / or the customer may specify a time limit for performing the compilation job, or the amount of resources to be allocated for performing the compilation job. In such situations, the compilation paths may be selected to comply with such constraints.

[0071] Figure 4 illustrates exemplary quantum circuit compilation job plans that may be generated by a quantum circuit compilation service in several embodiments, and illustrates a workflow for orchestrating the execution of the quantum circuit compilation job plan to compile a quantum circuit at least partially.

[0072] For example, to compile a given quantum circuit, the quantum circuit compilation service 134 may generate a compilation job plan 402. The compilation job plan may include a compilation path list 404. For example, the compilation path list 404 may be generated by the compilation path selection module 202 of the quantum circuit compilation service 134. The compilation job plan 402 may also include software modules for executing the selected compilation paths included in the compilation path list 404. For example, the compilation job plan 402 may include a modularized compilation path 406. In some embodiments, the modularized compilation path 406 may be retrieved from the modularized compilation path repository 204 of the quantum circuit compilation service 134.

[0073] In some embodiments, the compile-path execution orchestration module 210 of the quantum circuit compilation service 134 may orchestrate the execution of the compile job plan 402 together with the compute resource provisioning module 206 of the quantum circuit compilation service 134. For example, the resource provisioning module 206 may reserve the necessary computing resources to execute paths 304C, 308E, 312B, 316A, etc., as shown in 450 of Figure 4, and the compile-path execution orchestration module 210 may use the resources reserved by the compute resource provisioning module 206 to harmonize the execution of consecutive paths, as shown in 450. In some embodiments, each modularized compile-path 406 may be configured as a machine image used to boot the computing resources reserved by the compute resource provisioning module 206. The machine image may contain the code necessary to execute each specialized compile-path.

[0074] It should be noted that compilation orchestration via provisioned computing resources 450 is provided for the sake of clarity. However, in some embodiments, more or fewer paths may be used and may be arranged in various configurations.

[0075] Figure 5 illustrates an exemplary quantum circuit compilation process in several embodiments, where a client-side compiler outsources one or more compilation passes performed by a quantum circuit compilation service.

[0076] In some embodiments, a quantum circuit compilation service, such as a quantum circuit compilation service 134, may further include a compiler meta-optimization module 516 that intelligently performs path selection. For example, the model used for path selection may be tuned via path parameter tuning 518. In some embodiments, the module used for path selection may be a machine learning model that undergoes machine learning training to determine the tuning parameters that are adjusted via path parameter tuning 518.

[0077] In addition, in some embodiments, the quantum computing service interface 218 may receive feedback from the quantum computing service 102 via the compilation service interface 520. The feedback may also be used by the path parameter tuning 518 to adjust the path. For example, feedback related to error rate, noise, calibration, etc., may be used to adjust the parameters used in a given path and / or to adjust the path selection. Also, in some embodiments, the quantum computing service interface 218 may provide compiled artifacts to the quantum computing service 102 via the compilation service interface 520. For example, the quantum circuit compilation service 134 may provide the quantum computing service 102 with compiled quantum circuits that will be executed using the quantum computing service 102 or a QPU managed by the quantum hardware provider associated with the quantum computing service 102.

[0078] In some embodiments, the compilation of the quantum circuit may be partially performed using a client-side compiler, which performs some compilation passes and outsources the other compilation passes to a quantum circuit compilation service 134.

[0079] For example, customer 1(104)'s client-side compiler 502 may execute client-side compiler passes 504-506, and then outsource compiler passes 508-510 to a quantum compilation service 134. The quantum circuit being compiled through compiler pass 506 may be passed to the quantum compilation service 134 in an intermediate representation 534. Furthermore, after the quantum compilation service 134 executes the outsourced compiler pass 510, the further compiled version may be passed back to the client-side compiler 502 in an intermediate representation 534. The client-side compiler 502 may then execute additional compilation passes 512-514.

[0080] In some embodiments, a customer, such as customer 1(104), may provide the quantum circuit 522 to be compiled to a client-side compiler 502. The customer may then receive the compiled artifact 524 back and submit the compiled artifact 526 to the quantum computing service 102 for execution, such as "verbatim" execution. Customer 1(104) may also receive the execution result 528 back from the quantum computing service 102. For example, the quantum computing service 102 may execute the compiled artifact 526 on a local QPU (such as the local QPU 1626 shown in Figure 16) or orchestrate the execution of the compiled artifact on a QPU of an associated quantum hardware provider (such as the QHP 1602 shown in Figure 16).

[0081] As another example, customer 2 (106) may provide a quantum circuit 530 to be executed to the quantum computing service 102, and the quantum computing service 102 may delegate the compilation of the quantum circuit 530 to be executed to the quantum compilation service 134. The quantum computing service 102 may provide the quantum circuit to be compiled (e.g., 530) to the quantum compilation service 134 via the compilation service interface 520 and receive the compiled artifact back. The quantum computing service 102 may then execute the compiled artifact on, for example, a local QPU (such as the local QPU 1626 shown in Figure 16), or orchestrate the execution of the compiled artifact on the QPU of an associated quantum hardware provider (such as the QHP 1602 shown in Figure 16). The quantum computing service 102 may then return the execution result 532.

[0082] As yet another example, customer 3(108) may submit the quantum circuit 534 to be compiled to the quantum computing service 102 (or directly to the quantum compilation service 134) and receive the compiled artifact 536 back. Customer 3(108) may then submit the compiled artifact as a verbatim job to the quantum computing service 102, or execute the compiled artifact on a third-party QPU or QPU managed by customer 3(108).

[0083] Figure 6 illustrates an exemplary quantum circuit compilation process in which, according to several embodiments, a quantum compilation service provides a client-side compiler with a containerized computing object containing a quantum compilation job plan and modularized compilation path instructions for executing a set of modularized compilation paths shown in the quantum compilation job plan.

[0084] For example, the client-side compiler 602 may submit the quantum circuit 604 to be compiled to the quantum circuit compilation service 134. The quantum circuit compilation service 134 may determine a compilation job plan, such as the compilation job plan 402 shown in Figure 4. However, in some embodiments, instead of executing the compilation job plan itself, the quantum circuit compilation service 134 may provide the client-side compiler 602 with software objects 606, such as a container containing a compilation path list and instructions for executing modularized compilation paths referenced in the compilation path list. The client-side compiler 602 may then perform the compilation using the provided compilation job plan. In some embodiments, the client-side compiler may replace paths in the provided compilation job plan with the customer's own paths, or use other provided modularized compilation paths included in the job plan for other paths among the paths.

[0085] In some embodiments, a customer associated with a client-side compiler 602 may manage the execution of the compiled artifacts compiled via a client-side router 602, or may submit the compiled artifacts to a quantum computing service 102 (608), which manages the execution of the compiled artifacts. In addition, a customer associated with a client-side compiler 602 may submit the compiled artifacts as "verbatim" jobs in 610, which ensure that sequentially executed jobs are compiled in the same way. This can reduce variability, such as when a job is used as part of conducting an experiment. The execution results 612 (either 608, 610, or both) of the execution of the compiled artifacts may be provided to be returned to the customer.

[0086] Figure 7 illustrates an exemplary quantum circuit compilation process in several embodiments, where a quantum compilation service performs quantum circuit compilation on behalf of a quantum computing service, the customer submits the quantum circuit to be executed to the quantum computing service, the quantum computing service compiles the quantum circuit in cooperation with the quantum circuit compilation service, and the quantum computing service executes the quantum circuit using the compiled artifacts returned from the quantum circuit compilation service.

[0087] In some embodiments, a customer, such as customer 702, may submit a quantum circuit 704 to be executed to the quantum computing service 102. The quantum computing service 102 may perform one or more tasks with respect to the quantum circuit 704 to be executed, such as (optionally) recommending a quantum hardware provider to be used to execute the quantum circuit, and / or converting the quantum circuit into a representation that includes gates used by the selected quantum hardware provider (QHP). The quantum computing service 102 may also submit the quantum circuit 704 (in its original form or after conversion to a QHP-specific form) to the quantum compilation service 134 via the compilation service interface 520. For example, the quantum circuit representation 706 is submitted to the quantum compilation service 134, and a compiled artifact 708 is returned. The quantum computing service 102 may, for example, harmonize the execution of the compiled artifact 708 on a quantum processing unit (QPU) of the selected quantum hardware provider (QHP) and return the execution result 710 to customer 702.

[0088] Figure 8 illustrates an exemplary quantum circuit compilation process in several embodiments, in which the customer delegates quantum compilation to a quantum circuit compilation service, the quantum circuit compilation service partially compiles the quantum circuit, the quantum circuit compilation service returns the partially compiled quantum circuit to a client-side compiler, the client-side compiler performs one or more additional compilation passes, the client-side compiler then returns the further partially compiled quantum circuit to the quantum circuit compilation service, the quantum circuit compilation service completes the compilation, and the quantum computing service executes the quantum circuit using the compiled artifacts generated by the quantum circuit compilation service.

[0089] In some embodiments, the client-side compiler 802 may submit the quantum circuit 804 to be compiled to the quantum compilation service 134. The quantum compilation service 134 may perform a subset of the compilation passes and return a partially compiled version of the quantum circuit to the client-side compiler 802 (in 806). The partially compiled version of the quantum circuit may be formatted in an intermediate representation supported by the client-side compiler 802. The client-side compiler 802 may perform one or more additional compilation passes and return a further partially compiled version of the quantum circuit to the quantum computing service 134 (in 808). The quantum compilation service 134 may perform one or more additional passes, or may omit performing additional passes if the quantum circuit returned from the client-side compiler 802 is fully compiled. The quantum compilation service 134 may then provide the compiled artifact 810 to the quantum computing service 102 via the compilation service interface 520. The quantum computing service 102 can, for example, synchronize the execution of the compiled artifact 810 on the QPU of a selected QHP and return the execution result 812 to the customer 802.

[0090] Figure 9 illustrates an exemplary quantum circuit compilation process, which is called "verbatim" quantum circuit compilation, in several embodiments.

[0091] In some embodiments, customers of quantum compilation services and / or quantum computing services may submit multiple jobs that the customer wishes to be compiled in the same way, for example, “verbatim.” For example, verbatim compilation can reduce variability that may result from different compilation paths or different parameter selections within the compilation path. In some situations, the customer may request “verbatim” compilation to reduce variability in the compilation process, such as when used in controlled experiments, in order to obtain more reproducible results.

[0092] A first job marked as verbatim, such as quantum circuit 904, can be processed in the quantum compilation service 134, for example, by having the compilation path selection module 202 perform the path selection. The job plan for the verbatim circuit 904 is stored in a cache, such as cache 910, and can also be transferred to the compilation orchestration 912 to generate compiled artifacts for job 904. Subsequent jobs, such as quantum circuits 906 and 908, marked for verbatim compilation by referring to job 904, can be compiled using the same cached job plan stored in cache 912. The compiled artifacts for each verbatim job can be provided to the quantum computing service 102 via the compilation service interface 520. The quantum computing service 102 can, for example, harmonize the execution of the compiled artifacts for jobs 904, 906, and 908 on the QPU of a selected QHP and return the execution results 914 to the customer 902.

[0093] Figure 10A illustrates an inline compilation process in which the compilation of a quantum task is performed inline with the execution of the quantum task, according to several embodiments.

[0094] In some embodiments, compilation may be performed inline with execution, as shown in Figure 10A, and classical computing operations are performed as part of the compilation between successive iterations of quantum execution.

[0095] Figure 10B illustrates a separate quantum circuit compilation process, which may be performed by a quantum circuit compilation service in which compilation is performed in a manner separate from quantum circuit execution, according to several embodiments.

[0096] In contrast to what is shown in Figure 10A, in some embodiments, compilation may be performed in advance in a manner that is separate from execution. For example, as shown in Figure 10B, compilation may be performed in advance for multiple jobs, and the jobs may be executed sequentially on the quantum computer using the pre-compiled artifacts. This allows for better utilization of the limited access window for accessing the QPU compared to inline compilation as shown in Figure 10A.

[0097] Figure 11 illustrates an example of a web-based implementation of a user interface for a quantum circuit compilation service, according to several embodiments.

[0098] In some embodiments, interface 1100 may be implemented as a web-based graphical user interface, and customers of the service provider network 100 may upload and / or provide various information to the compilation service 134 regarding requests for quantum circuit compilation tasks that the customer wishes to complete.

[0099] In some embodiments, interface 1100 includes a box 1102 that asks the customer what types of inputs they can provide for the requested quantum compilation task. For example, in some embodiments, where the quantum compilation task is a mapping task involving optimizations such as SAT, SMT, etc., for the compilation service 134 to prepare the quantum circuit mapping problem, the compilation service 134 may need to receive and / or generate at least: a gate dependency list (see Figure 12B), a list of physical qubits contained in the target quantum hardware device, and how each of the physical qubits is connected via edges (see Figure 12A). In some embodiments, the customer may also provide an instruction on the number of SWAP gates that the customer wants the solver to attempt to use at resolution. The customer may click on various options in fields 1102, 1104, and 1106 to provide such inputs directly and / or other inputs (e.g., logic quantum circuit information and / or physical qubit connectivity information) that the compilation service 134 may use to generate the above inputs for the quantum circuit mapping problem.

[0100] In some embodiments, the customer may also provide information about constraints applied as part of performing the compilation, such as convergence criteria, confidence thresholds, acceptable amount of time to be used for compilation, allocated costs for performing the compilation, and the number of iterations for which the solver will seek an optimized mapping.

[0101] In field 1102, the customer may click on various options, such as “Upload gate dependency list,” in which case a gate dependency list corresponding to the order in which the gates of a given logic quantum circuit will be executed (which may be ordered by logic qubits) may be uploaded. An example of a gate dependency list is shown in Figure 12B herein. The uploaded gate dependency list may, according to some embodiments, then be stored in gate dependency generator 1358 or 1558 (as some examples). Alternatively, the customer may decide to click “Browse saved quantum circuits,” in which case the current request shown in interface 1100 may be performed using logic quantum circuits stored in logic quantum circuit cache 1352 or 1552 (as some examples). Another option is for the customer to click “Upload new quantum circuit,” in which case the customer may upload a logic quantum circuit, such as logic quantum circuit 1220 (shown in Figure 12B). The uploaded logic quantum circuits are then, according to some embodiments, stored in (as some examples) logic quantum circuit caches 1352 or 1552 and can be used by a compilation service to generate a gate dependency list.

[0102] Alternatively, a customer of the compilation service 134 may also be a customer of the quantum computing service 102, and therefore may click field 1104 to import a project from the quantum computing service 102. For example, a customer may have a quantum algorithm project stored in the quantum computing service 102 (a given quantum algorithm includes one or more quantum circuits representing intermediate logic calculations of the overall quantum algorithm) and may request that the quantum circuit mapping be resolved for use with the compilation service 134.

[0103] In field 1106, the customer may click on various options, such as “Upload physical qubit connectivity graph.” An example of a physical qubit connectivity graph is shown in Figure 12A herein. The uploaded physical qubit connectivity graph may, according to some embodiments, then be stored in the physical qubit connectivity graph cache 1362 or 1562 (as some examples). If, as introduced above, the customer of the compilation service 134 is also a customer of the quantum computing service 102, the customer may click “Select quantum hardware provider” and select a quantum hardware provider accessible via the service provider network 100 (e.g., quantum hardware providers 124, 126, 128, 130, etc.). If the customer selects such an option, the compilation service 134 may, according to some embodiments, communicate with the quantum computing service 102 to obtain information associated with the selected quantum hardware provider (e.g., the layout of a particular quantum hardware device, the physical qubit connectivity graph of a particular quantum hardware device, a list of physical qubits and edges of a particular quantum hardware device, etc.). Similarly, if the customer selects "Choose Qubit Technology - I'll handle the rest myself!", the compilation service 134 may communicate with the quantum hardware provider recommendation 122 of the quantum computing service 102 to recommend one or more quantum hardware providers to the customer, and once the customer selects one of the recommended quantum hardware providers, the quantum computing service 102 may then provide the compilation service 134 with physical qubit connectivity information related to the quantum hardware device of the recommended quantum hardware provider.

[0104] In some embodiments, specific combinations of inputs to fields 1102, 1104, and 1106 may be interdependent, and therefore, specific subfields of fields 1102, 1104, and / or 1106 may or may not be provided at the customer's discretion. For example, if the customer selects field 1104 to import a project from quantum computing service 102, the customer may also not be able to select an option in field 1102. In a second example, if the customer selects field 1104 to import a project from quantum computing service 102, the information imported from quantum computing service 102 with respect to a particular project may already contain information about the target quantum hardware provider, and therefore, the compilation service 134 may already have enough information to perform a given quantum circuit mapping request resulting from the selection of imported project information in field 1104, and thus the customer may not be provided with an option in field 1106.

[0105] In field 1108, the customer may indicate whether a full compilation or a partial compilation will be performed. The customer may also specify which path will be performed by the compilation service 134. In some embodiments, the customer may further specify whether the compilation service returns the compiled artifact to the customer, to the customer's client-side compiler, or to a quantum computing service such as the quantum computing service 102, which uses the compiled artifact to run a quantum circuit.

[0106] In some embodiments, in field 1110, the customer may specify whether verbatim compilation will be used to compile each quantum circuit. Also, in fields 1112, 1114, and 1116, the customer may import custom compilation paths, custom gate decompositions, and / or custom pulse sequences to be used when compiling one or more quantum circuits on behalf of the customer.

[0107] After completing the combination of fields 1102, 1104, 1106, 1108, 1110, 1112, 1114, and / or 1116, the customer may use the submit button 1110 to initiate their request to the compilation service 134.

[0108] In some embodiments, interface 1100 may be implemented as a graphical user interface. However, according to some embodiments, interface 1100 may also be implemented as various types of programs (e.g., application programming interfaces (APIs)) or command-line interfaces to support the methods and systems described herein.

[0109] Furthermore, interface 1100 may be a customer-facing interface (e.g., user interface 140) to which customers of compilation service 134 can submit inputs to be used in a given quantum circuit mapping problem, such as the inputs shown in Figure 1. Alternatively, customers of quantum computing service 102 (e.g., customers 104, 106, 108, etc.) may request that the quantum algorithms they provide to quantum computing service 102 be executed using quantum hardware devices of a given quantum hardware provider (e.g., quantum hardware providers 124, 126, 128, 130, etc.). As part of fulfilling such a request, the quantum algorithm may be divided into one or more logic quantum circuits representing intermediate logic computations used within the overall quantum algorithm. These logic quantum circuits may then be provided to compilation service 134 by quantum computing service 102 to generate quantum circuit mappings of the logic quantum circuits to quantum hardware devices of a given quantum hardware provider. In such embodiments, interface 1100 may be an interface (e.g., an API) between the quantum computing service 102 and / or the compilation service 134, rather than a customer-facing interface.

[0110] Figure 12A illustrates an example of the generation of a physical qubit connectivity graph, corresponding physical qubits, and edge lists for a given quantum hardware device, according to several embodiments.

[0111] In some embodiments, the description of the physical qubit arrangement and their respective connectivity to each other for a given quantum hardware device may be analogous to the physical qubit connectivity graph 1200. Those skilled in the art should understand that the physical qubit connectivity graph 1200 is used herein as an example, and that physical qubit connectivity graphs for other quantum hardware devices (e.g., quantum hardware devices provided by quantum hardware providers 124, 126, 128, 130, etc.) may include more or fewer physical qubits than the four physical qubits shown in the physical qubit connectivity graph 1200, and / or may be connected via edges arranged in configurations other than those shown in the physical qubit connectivity graph 1200.

[0112] In some embodiments, the physical qubit connectivity graph 1200 illustrates four physical qubits (e.g., physical qubits 1201, 1202, 1203, and 1204), where physical qubits 1201 and 1202 are physically connected via edge e1, physical qubits 1202 and 1203 are physically connected via edge e2, and physical qubits 1202 and 1204 are physically connected via edge e3. The physical qubit connectivity graph 1200 can be used to complete a list of physical qubits (e.g., physical qubit list: {q 301 ,q 302 ,q 303 ,q 304 It is possible to generate both a list of edges that physically connect each physical qubit (for example, edge list: ({e1, e2, e3})) and a list of edges that physically connect each physical qubit among the physical qubits.

[0113] In some embodiments, it can be implicitly understood via the physical qubit connectivity graph 1200 that the following two-qubit gates can be implemented according to the physical layout of a given quantum hardware device represented by the physical qubit connectivity graph 1200: the two-qubit gate between physical qubits 1201 and 1202, the two-qubit gate between physical qubits 1202 and 1203, and the two-qubit gate between physical qubits 1202 and 1204. Similarly, the following two two-qubit gates may not need to be implemented (directly) according to the physical layout represented by the physical qubit connectivity graph 1200: the two-qubit gate between physical qubits 1201 and 1204, and the two-qubit gate between physical qubits 1203 and 1204. If a given logical quantum circuit requires that a two-qubit gate between physical qubits 1201 and 1204, or between physical qubits 1203 and 1204, be implemented, the states of two given physical qubits among qubits 1201, 1202, 1203, and 1204 can be logically changed to implement the gate using SWAP gates or other indirect methods.

[0114] In some embodiments, the above description of the physical qubit connectivity graph can be generalized as follows: A given physical qubit connectivity graph can include P physical qubits and K connected edges e for i, j ∈ (0, P] and i ≠ j. ij Then, such information regarding physical qubit connectivity can be initialized to: an ordered list of edges E = {d1,..., d k ,..., d K}, where each d k corresponds to an edge in a given physical qubit connectivity graph that includes P physical qubits and K edges that connect each of the physical qubits among the physical qubits.

Number

[0115] Figure 12B illustrates an example of a logic quantum circuit and the generation of corresponding logic qubits, gates, and gate dependency lists according to several embodiments.

[0116] In some embodiments, a quantum logic circuit submitted by a customer of the service provider network 100 may be analogous to the quantum logic circuit 1220. Those skilled in the art should understand that the quantum logic circuit 1220 is used herein as an example, and that quantum logic circuits corresponding to other quantum logic computations may include more or fewer logic qubits than the four logic qubits shown in the quantum logic circuit 1220, and / or additional and / or other single or multi-qubit gates other than the six 2-qubit gates shown in the quantum logic circuit 1220.

[0117] In some embodiments, the logic quantum circuit 1220 details six 2-qubit gates that will be performed between each of the four logic qubits shown to complete a given quantum computation. Using the logic quantum circuit 1220, a list of logic qubits (e.g., logic qubit list: {A, B, C, D}) and a list of gates that will be performed between each of the logic qubits (e.g., gate list: {g0, g1, g2, g3, g4, g5}) can be generated. A gate dependency list may also be generated, in which case, according to the logic quantum circuit 1220, gate g0 must be performed on logic qubit A before gate g3 is performed on logic qubit A, gate g3 must be performed on logic qubit A before gate g5 is performed on logic qubit A, and so on.

[0118] In some embodiments, the above description of a logic quantum circuit can be generalized as follows: A given logic quantum circuit to be used in quantum circuit mapping is a circuit with V logic qubits and n 2-qubit gates G={g0,...g}. i ,...,g n-1 It can be represented using an ordered list of}. Such information related to the description of a logic quantum circuit can then be initialized as follows: g in G i For a larger gate operand, g i .op max It can be expressed as, and a smaller gate operand is, g i .op max They can be represented as such, and then they are initialized into an array. i .op max and g i .op max Both of these can be fixed for i∈[0,n). Furthermore, the gate dependency list for generalized logic quantum circuits is:

number

number

number

[0119] Figure 13 illustrates an exemplary modularized compilation path module, which, in several embodiments, can generate mappings of logic quantum circuits to quantum hardware devices, for example, using a SAT solver.

[0120] In some embodiments, the modularized path N138 shown in Figure 1 may be a mapping path 1302 using a SAT solver as shown in Figure 13. The mapping path 1302 may be used to encode the quantum circuit mapping as an optimization problem, such as a SAT solver problem. According to some embodiments, logic quantum circuit information 1350 and physical qubit connectivity information 1360 may be used to receive and store inputs and information related to the quantum circuit mapping generated via the compilation service 134. Such inputs may be submitted via a user interface 140 (see the description of interface 1100 in this specification). For example, a logic quantum circuit cache 1352 may be configured to store logic quantum circuits (e.g., logic quantum circuits 1220) of one or more customers of the compilation service 134, and a logic qubit list 1354 and a gate list 1356 may be configured to store lists of logic qubits and gates corresponding to each logic quantum circuit (see also the description of Figure 12B in this specification). According to some embodiments, in order to encode a quantum circuit mapping problem as a SAT solver problem, a gate dependency list may be generated as part of the encoding process based on a given logic quantum circuit stored in the logic quantum circuit cache 1352. Such gate dependency generation may be stored in a gate dependency generation 1358 according to some embodiments. In another example, a physical qubit connectivity graph cache 1362 may be configured to store physical qubit connectivity graphs (e.g., physical qubit connectivity graph 1200) of one or more quantum hardware devices of a quantum hardware provider (e.g., quantum hardware providers 124, 126, 128, 130), and / or physical qubit connectivity graphs provided by customers of the compilation service 134. Physical qubit lists 1364 and edge lists 1366 may be configured to store lists of physical qubits and edges corresponding to their respective physical qubit connectivity graphs.In some embodiments, in order to encode a quantum circuit mapping problem as a SAT solver problem, a list of physical qubits and edges may be generated as part of the encoding process based on a given physical qubit connectivity graph stored in a physical qubit connectivity graph cache 1362.

[0121] In some embodiments, the compilation service 134 is configured to use the information in the logic quantum circuit information 1350 and the physical qubit connectivity information 1360, and a layout transition-based sequential coding scheme defined via the SAT coding definition 1370, to generate a CNF equation representing a given quantum circuit mapping problem. According to some embodiments, the SAT coding definition 1370 may include one or more conditions, constraints, and / or other definitions used to code the quantum circuit mapping problem as a SAT solver problem, such as a gate scheduling condition 1372, a qubit mapping condition 1374, a SWAP operand selection condition 1376, and / or other conditions 1378.

[0122] The encoded SAT solver problem can then be provided by the compilation service 134 to optimization problem services (e.g., optimization problem service 142, optimization problem service 144, etc.) so that the encoded SAT solver problem can be executed using a SAT solver (e.g., SAT solver 146). In some embodiments, the optimization problem services may be configured to implement SAT solving instances in addition to instances of other optimization problem solving techniques (e.g., SMT solving, heuristic solving methods, etc.).

[0123] The compilation service 134 may also orchestrate and / or harmonize the execution of an encoded SAT solver problem. For example, the compilation service 134 may use an optimization problem service to request specific computing resources, time allocations, etc., to enable the execution of an encoded SAT solver problem. In some embodiments, the compilation service 134 may communicate with an optimization problem service 144 in the service provider network 100 to harmonize the execution of a given encoded SAT solver problem using a SAT solving instance of the SAT solver 146. In some embodiments, the compilation service 134 may be configured to communicate with one or more other optimization problem services accessible via the service provider network 100, such as an optimization problem service 142, which may be located on a premises outside the service provider network 100. In such embodiments, the compilation service 134 may communicate with the optimization problem service 142 via an edge computing device physically located on the premises of the optimization problem service 142, so that the service provider network 100 can be extended. In some embodiments where multiple encoded SAT solver problems are submitted for execution using SAT solving techniques, the compilation service 134 may be further configured to harmonize the execution of the problems using multiple optimization problem services in order to make the execution more efficient.

[0124] The compilation service 134 may also include one or more additional modules (e.g., other compilation modules 1338). For example, a transformation module 1380 may be configured to transform non-Clifford operations of a logic quantum circuit into a set of Clifford operations and / or to perform one or more other intermediate transformations related to the target quantum hardware provider. In another example, several 2-qubit gates of a logic quantum circuit may be decomposed into a set of native gates, and a gate nativeization module 1382 may be configured to handle such decomposition. In yet another example, in some embodiments where the quantum hardware provider of quantum hardware providers 124-130 relates to a Rydberg atomic array, according to some embodiments, the other compilation module 1338 may include a module configured to compile and / or encode a mapping problem for determining atomic computation positions in the Rydberg atomic array.

[0125] Figure 14 illustrates another exemplary modularized compile-path module, which, in several embodiments, can generate mappings of logic quantum circuits to quantum hardware devices, for example, using a reinforcement learning-based machine learning model.

[0126] In some embodiments, the modularized path M136 may be a reinforcement learning-based mapping module 1402 used to compile instructions including quantum circuit mappings, so that logic quantum circuits can be executed using quantum hardware devices via the compiled instructions. Those skilled in the art should understand that Figure 14 is intended to be a visual representation of computational instances and / or program instructions that, when executed, cause one or more processors to implement the methods and apparatus described herein, and that there may be additional configurations of Figure 14 that perform such implementations and are intended to be included herein. Furthermore, Figure 14 describes, according to some embodiments, components of an RL-based quantum circuit router 1450 that may be located within the modularized path M136 to which the components map.

[0127] Those skilled in the art of machine learning techniques should understand that, using the following terms and definitions, reinforcement learning training models can be described within the context of solving the quantum circuit mapping problem herein and within the context of generally understood machine learning techniques. Generally, a reinforcement learning training model describes “actions” selected by an “agent,” where an action modifies the agent’s “environment” to “play” the quantum circuit mapping “game.” Within the context of quantum circuit mapping and the methods and techniques described herein, an agent may be described as a “player” of a quantum circuit mapping game, assisted by a neural network (e.g., policy network 1454) that determines a plurality of possible actions that modify the current state of the quantum circuit mapping problem. The agent may then select an action from the plurality of actions, and in some embodiments, the policy network may be further assisted via an MCTS algorithm that uses “inference” to determine a predicted outcome based on the selection of each of the actions. In addition, an action may be described herein as the scheduling of one or more SWAP gates. Furthermore, the “environment” in the context of quantum circuit mapping can, according to some embodiments, be described through the current (e.g., initial, intermediate, final, etc.) states of the quantum circuit mapping problem, where the initial state of the quantum circuit mapping problem can be described as a state in which not all quantum gates of the logic quantum circuit are yet scheduled for execution, the intermediate state of the quantum circuit mapping problem can be described as a state in which some additional quantum gates are scheduled with respect to the initial state, and the final state of the quantum circuit mapping problem can be described as a state in which all quantum gates of the logic quantum circuit are scheduled for execution.

[0128] As shown in Figure 14, the RL-based quantum circuit router 1450 may include computational resources configured to implement a neural network (e.g., policy network 1454) which can be assisted via a Monte Carlo tree search (MCTS) algorithm (Monte Carlo tree search (MCTS) 1452) according to some embodiments. In some embodiments, MCTS 1452 may use the “tree search” method to identify the predicted outcomes of various actions determined via the policy network 1454 and / or determine the loss associated with selecting those various actions.

[0129] In some embodiments, the policy network 1454 may be configured to connect the current state of the environment (e.g., a given quantum circuit mapping problem) to actions that the policy network may decide and / or select. Examples of guidelines that may be used to guide the training and / or action selection of the policy network 1454 may include: For example, a reinforcement learning model may select an action based at least in part on deciding that a particular action among several actions updates the current state of the environment so that an additional quantum gate of a given logic quantum circuit can be scheduled for execution. In another example, a reinforcement learning model may select an action based at least in part on the gate dependency of a given logic quantum circuit (e.g., a second quantum gate depends on the output of a first quantum gate). Those skilled in the art should understand that the RL model training guidelines are intended to be illustrative guidelines that may be defined for an RL-based quantum circuit router, and that additional and / or different guidelines may also be used to assist the direction of an RL-based quantum circuit router according to different mapping scenarios.

[0130] In some embodiments, agent 1456 may include a value network (e.g., value network 1458) configured to determine quantum circuit routing rewards (e.g., reward distribution, reward weights, loss values, etc.) which can be used by policy network 1454 to provide recommendations for a given action among several to choose from. Examples of guidelines that can be used to guide the reward distribution determined via value network 1458 may include: For example, an agent in a reinforcement learning training model may be rewarded proportionally higher for selecting an action that results in one or more quantum gates of a given logic quantum circuit being scheduled than for selecting a different action that does not result in one or more quantum gates being scheduled. In another example, an agent in a reinforcement learning training model may be rewarded proportionally higher for successfully scheduling all quantum gates of a given logic quantum circuit than for failing to schedule all quantum gates of a given logic quantum circuit (which can be abbreviated as "losing the game" and / or "losing"). In yet another example, an agent in a reinforcement learning training model may be rewarded proportionally higher for successfully scheduling all quantum gates of a given logic quantum circuit with fewer scheduled SWAP gates than for successfully scheduling all quantum gates of a given logic quantum circuit with a larger number of scheduled SWAP gates, as this uses a more efficient path to solve a given quantum circuit mapping problem. Those skilled in the art should understand that such RL reward guidelines are intended to be illustrative guidelines that may be defined for RL-based quantum circuit routers, and that additional and / or different guidelines may be used to assist in action recommendations determined via the RL model according to different mapping scenarios.

[0131] The modularized path M136 may include various memory caches to provide the RL-based quantum circuit router 1450 with access to frequently used information. Such memory caches may, according to some embodiments, be configured as computational resources for the quantum compilation service 134. As shown in Figure 14, the RL-based quantum circuit router experience generation 1462 may include a logic quantum circuit cache 1464, a physical qubit connectivity graph cache 1466, a qubit allocation cache 1468, an experience replay buffer 1470, a sampled past experience cache, and compiled instructions 1474. In some embodiments, the logic quantum circuit cache may be used to store various logic quantum circuits that may be in the mapping process for the RL-based quantum circuit router 1450. In some embodiments, the logic quantum circuit cache may store logic quantum circuits submitted by customers of the service provider network 100, and / or logic quantum circuits used to train a given RL-based quantum circuit routing instance 1450 (e.g., a "training game").

[0132] In some embodiments, a physical qubit connectivity graph cache 1466 may be used to store various physical qubit connectivity graphs corresponding to quantum hardware devices such as the quantum hardware devices of quantum hardware providers 124, 126, 128, and 130. The physical qubit connectivity graph cache 1466 may store information related to the quantum hardware device and / or information on how to request such information (e.g., via the quantum computing service 102). Furthermore, the physical qubit connectivity graph cache 1466 may store physical qubit connectivity graphs (e.g., physical qubit connectivity graph 1220), ordered lists of physical qubits, how physical qubits are connected to each other via edges, and / or any equivalent information describing the connectivity of physical qubits on a given quantum hardware device.

[0133] In some embodiments, the qubit allocation cache 1468 may be used to store various qubit allocation schemes that can be used during the resolution of a corresponding quantum circuit mapping problem. In some embodiments, a customer may submit a given qubit allocation scheme when submitting a given quantum circuit mapping request to the quantum compilation service 134, and the qubit allocation scheme may be stored in the qubit allocation cache 1468. In other embodiments, the quantum compilation service 134 may generate a qubit allocation scheme using information about a given logic quantum circuit stored in the logic quantum circuit cache 1464 and information about the connectivity of a given quantum hardware device stored in the physical qubit connectivity graph cache 1466, and store the qubit allocation scheme in the qubit allocation cache 1468.

[0134] In some embodiments, the experience replay buffer 1470 can be used to store various states of the environment within a given quantum circuit mapping problem. For example, if an agent of the RL-based quantum circuit router 1450 has selected a given number of actions, the experience replay buffer 1470 can store information relating to how the state of the environment was updated following each selection of the selected actions. In another example, the experience replay buffer 1470 can store quantum circuit mapping decision scenarios completed by the RL-based quantum circuit router 1450 so that the experience replay buffer 1470 grows over time.

[0135] In some embodiments, a sampled past experience cache 1472 may be used to store various quantum circuit mapping problems previously solved and / or attempted by the RL-based quantum circuit router 1450. For example, an agent of the RL-based quantum circuit router 1450 may search the sampled past experience cache 1472 to determine whether a particular scenario and / or similar scenario between the current quantum circuit mapping problems has already been solved in a previously attempted quantum circuit mapping problem.

[0136] In some embodiments, the compiled instruction 1474 can be used to store the results in various ongoing or previously completed quantum circuit mapping problems. For example, the quantum compilation service 134 may be configured to compile an instruction containing quantum circuit mapping results for executing a logic quantum circuit using a given quantum hardware device, and the compiled instruction 1474 can be used to retrieve the quantum circuit mapping results in order to compile an instruction that can then be provided to the quantum computing service 102.

[0137] In some embodiments, the RL-based quantum circuit router experience generator 1462 may store additional information related to simple quantum circuit mapping scenarios that can be used to train and / or improve a reinforcement learning training model. In addition, or alternatively, such a “training game” may include an ordered list of training scenarios to be used to train and / or improve a reinforcement learning training model, assuming that program instructions are executed such that an instance of the RL-based quantum circuit router 1450 is installed on an additional server (either inside or outside the service provider network 100). In some embodiments, such a training game may be used to train the RL-based quantum circuit router 1450 via a reinforcement learning training model. In other embodiments, the trained reinforcement learning model may include an agent 1456 and a policy network 1454, the policy network 1454 having undergone some level of pre-training via the reinforcement learning training model. In some embodiments where computing resources may be limited, it may be advantageous to apply the trained reinforcement learning model to a given quantum circuit mapping problem of a customer of the service provider network 100.

[0138] In some embodiments, the quantum compilation service 134 may also leverage multiple RL-based quantum circuit routing computation instances (e.g., RL-based quantum circuit routers 1450) to run multiple quantum circuit mapping problems simultaneously, thereby accelerating the process of generating quantum circuit mappings and / or enabling the quantum compilation service to simultaneously manage quantum circuit mapping problems for multiple customers of the service provider network. In some embodiments, various instances of the RL-based quantum circuit router 1450 may be specifically trained for a particular set and / or subset of qubit techniques. For example, a first RL-based quantum circuit routing instance 1450 may be trained using training scenarios related to annealing-based quantum hardware devices and may be configured to generate compiled instructions for executing logic quantum circuits using the quantum hardware devices of quantum hardware provider 124. In another example, a second RL-based quantum circuit routing instance 1450 may be trained using other training scenarios related to superconductivity-based quantum hardware devices and may be configured to generate compiled instructions for executing logic quantum circuits using the quantum hardware devices of quantum hardware provider 128.

[0139] Figure 15 illustrates additional exemplary modularized compilation path modules, which, in several embodiments, can generate mappings of logic quantum circuits to quantum hardware devices using, for example, an SMT solver.

[0140] In some embodiments, the modularized path L may be a mapping path 1502 using an SMT solver as shown in Figure 15. The mapping path 1502 may be used to encode the quantum circuit mapping as an optimization problem, such as an SMT solver problem. According to some embodiments, inputs and information related to the quantum circuit mapping generated via the compilation service 134 may be received and stored using logic quantum circuit information 1550 and physical qubit connectivity information 1560. Such inputs may be submitted in a manner similar to that described with respect to the SAT solver compilation path module described above with respect to Figure 13, and may include a logic quantum circuit cache 1552, a logic qubit list 1554, a gate list 1556, and a gate dependency generator 1558. These inputs may also include a physical qubit connectivity graph cache 1562, a physical qubit list 1564, and an edge list 1566.

[0141] In some embodiments, the compilation service 134 is configured to generate an SMT optimization problem using the information in the logic quantum circuit information 1550 and the physical qubit connectivity information 1560. For example, the problem may be constructed using an SMT coding definition 1570 which includes gate scheduling conditions 1572, qubit mapping conditions 1574, and symbolic bit matrix representations of the circuit elements of the Clifford circuit design problem 1576.

[0142] The encoded SMT solver problem can then be provided by the compilation service 134 to optimization problem services (e.g., optimization problem service 142, optimization problem service 144, etc.) so that the encoded SMT solver problem can be executed using an SMT solver (e.g., SMT solver 146). In some embodiments, the optimization problem services may be configured to implement SMT solving instances in addition to instances of other optimization problem solving techniques (e.g., SAT solving, heuristic solving methods, etc.).

[0143] The compilation service 134 may also orchestrate and / or harmonize the execution of an encoded SMT solver problem. For example, the compilation service 134 may use an optimization problem service to request specific computing resources, time allocations, etc., to enable the execution of an encoded SMT solver problem. In some embodiments, the compilation service 134 may communicate with an optimization problem service 144 in the service provider network 100 to harmonize the execution of a given encoded SMT solver problem using an SMT-solved instance of the SMT solver 146. In some embodiments, the compilation service 134 may be configured to communicate with one or more other optimization problem services accessible via the service provider network 100, such as an optimization problem service 142, which may be located on a premises outside the service provider network 100. In such embodiments, the compilation service 134 may communicate with the optimization problem service 142 via an edge computing device physically located on the premises of the optimization problem service 142, so that the service provider network 100 can be extended. In some embodiments where multiple encoded SMT solver problems are submitted for execution using SMT solving techniques, the compilation service 134 may be further configured to harmonize the execution of the problems using multiple optimization problem services in order to make the execution more efficient.

[0144] The compilation service 134 may also include one or more additional modules (e.g., other compilation modules 1538). For example, a transformation module 1580 may be configured to transform non-Clifford operations of a logic quantum circuit into a set of Clifford operations and / or to perform one or more other intermediate transformations related to the target quantum hardware provider. In another example, several 2-qubit gates of a logic quantum circuit may be decomposed into a set of native gates, and a gate nativeization module 1582 may be configured to handle such decomposition. In yet another example, in some embodiments where the quantum hardware provider of quantum hardware providers 124-130 relates to a Rydberg atomic array, according to some embodiments, the other compilation module 1538 may include a module configured to compile and / or encode a mapping problem for determining atomic computation positions in the Rydberg atomic array.

[0145] Figure 16 illustrates edge computing devices for quantum computing services that are physically located at quantum hardware provider locations, according to several embodiments.

[0146] In some embodiments, the service provider network 100, as illustrated in Figure 1, may include one or more data centers connected to each other via private or public network connections. Edge computing devices located at quantum hardware provider locations may also be connected to the service provider network via private or public network connections. For example, the service provider network 100 illustrated in Figure 16 includes data centers 1606a, 1606b, and 1606c connected to each other via private physical network links of the service provider network 100. In some embodiments, customers of the service provider network may also be connected via private physical network links not available to the public for carrying network traffic, such as physical connections at router colocation facilities. For example, customer 1610 is connected to a router associated with data center 1606c via a direct connection 1624. Similarly, edge computing devices located at quantum hardware provider locations may be connected to the service provider network via private physical network links not available for carrying public network traffic.

[0147] For example, an edge computing device 1604a located at quantum hardware provider location 1602a is connected to a router in data center 1606a via direct connection 1618. Similarly, an edge computing device 1604b at quantum hardware provider location 1602b is connected to a router in data center 1606b via direct connection 1620. Also, an edge computing device 1604c at quantum hardware provider 1602c is connected to a router in data center 1606c via direct connection 1622.

[0148] Furthermore, in some embodiments, edge computing devices in a service provider network located at a quantum hardware provider location may be connected to the service provider network via logically isolated network connections, such as via the internet or another public network. For example, edge computing device 1604d at quantum hardware provider location 1602d is connected to data center 1606c via a logically isolated network connection through network 1616. Similarly, in some embodiments, customers such as customer 1614 may be connected to the service provider network 100 via a public network 1612.

[0149] In some embodiments, a similar configuration may exist between the compilation service 134 and the optimization problem service 142. For example, the compilation service 134 may be connected to the optimization problem service 142 by using a logically isolated network connection over a public network, or by using a dedicated physical non-public network link. In some embodiments, another edge computing device may be located within the premises of the optimization problem service 142 so that the compilation service 134 can be connected to the optimization problem service 142 via an edge computing device.

[0150] In some embodiments, quantum computing services such as quantum computing service 102 and / or quantum circuit compilation services such as compilation service 134 may be implemented using one or more computing devices in any of the data centers 1606a, 1606b, 1606c, etc. In some embodiments, a network connection 1612 and / or a direct connection 1624 may be used to pass a partially compiled quantum circuit in an intermediate representation between the client-side compiler and the quantum circuit compilation service such as compilation service 134. Furthermore, quantum computing service 102 may provide customers such as customer 1614 or customer 1610 with access to a quantum computer in any of the quantum hardware provider locations 1602a, 1602b, 1602c, 1602d, etc. For example, a customer may not be limited to using a quantum hardware provider in their local region. Instead, a customer may be allocated a computing instance instantiated on a local edge computing device located at a selected quantum hardware provider location, so that their location does not limit their access to quantum computers based on various types of quantum computing technologies.

[0151] In some embodiments, one or more of the data centers 1606 may also include local quantum hardware devices such as local QPUs 1626. One or more of the data centers 1606 may also include local optimization problem services such as optimization problem services 144, and one or more computing devices in the data centers 1606 are configured to implement various optimization solution techniques such as SAT solutions and SMT solutions (e.g., solver 146, solver 148, etc.).

[0152] Exemplary edge computing devices located at quantum hardware provider locations Figure 17 illustrates exemplary edge computing devices connected to quantum computing services in several embodiments.

[0153] The service provider network 100 and quantum computing service 102 may be similar to the service provider network and quantum computing service described herein, as shown in Figure 1. The edge computing device 1752 may be similar to any of the edge computing devices described earlier, such as in Figure 1 or 16. The edge computing device 1752 may be connected to the service provider network 100 via a network connection 1700, which may be a logically isolated network connection via a public network, a dedicated physical non-public network link, or other suitable network connection.

[0154] The edge computing device 1752 may include a network manager 1758, a storage manager 1760, and a virtual machine control plane 1756.

[0155] In some embodiments, a backend application programming interface (API) transport of an edge computing device, such as the backend API transport 1754 of the edge computing device 1752, may ping a quantum computing service to determine if there are one or more quantum tasks (e.g., compiled quantum circuits) waiting to be transported to the edge computing device. The edge computing device may further use a non-public backend API transport, such as the backend API transport 1754, to transport the compiled quantum circuits to the edge computing device 1752.

[0156] In addition, for each customer, the backend API transport of the edge computing device for quantum computing services, such as the backend API transport 1754 of the edge computing device 1752, may be instantiated to manage scheduling and results for a given compiled quantum circuit pulled from the backend API to the edge computing device. For example, virtual machine 1770 may function as an interface to a quantum hardware provider for a given customer (e.g., customer 1) of the service provider network. The edge computing device may be directly connected to a local non-public network at the quantum hardware provider location and may work in conjunction with the quantum hardware provider's scheduling component to schedule availability (e.g., usage slots) on the quantum computer of the quantum hardware provider.

[0157] In some embodiments, the virtual machine 1770 may be booted with a specific machine image that supports coordination with the scheduling component of the quantum hardware provider, and different quantum hardware providers require different scheduling interfaces.

[0158] In some embodiments, the virtual machine 1770 may be booted with a quantum circuit queuing component 1772, a quantum circuit scheduling component 1776, a component for managing local storage buckets on the edge computing device for temporarily storing results such as a temporary bucket 1774, and a results manager 1778. In some embodiments, the quantum circuit scheduling component 1776 may order the compiled quantum circuits in the quantum circuit queuing component in the order in which those quantum circuits are received, and the received order enforces quality of service (QoS) assurance by ordering quantum tasks in the quantum task queue of the quantum computing service based on priorities determined using the QoS assurance.

[0159] In some embodiments, edge computing devices, such as edge computing device 1752, may support multi-tenancy (e.g., providing services to multiple customers of a service provider network 100). Also in some embodiments, edge computing device 1752 may also instantiate virtual machines that perform classical computing tasks, such as the classical computing portion of a hybrid algorithm. For example, virtual machine 1770 may be further configured to perform the classical computing portion of a hybrid algorithm.

[0160] In some embodiments, a quantum circuit compilation service, such as compilation service 134, may perform isolated compilation, as considered in Figure 10B. In such embodiments, the execution of the quantum portion of the hybrid algorithm may need to be delayed while waiting for inline compilation to be performed. For example, in contrast to inline compilation as shown in Figure 10A, compilation is performed inline before each quantum task, while in isolated compilation, the compilation work may be performed in advance on a quantum processing unit, such as one provided by a quantum hardware provider, to minimize delay when executing quantum tasks during an allocated availability window.

[0161] In some embodiments, the backend API transport of an edge computing device located at a quantum hardware provider location may be linked to a backend API transport interface 112 of a computing device at a remote location where one or more computing devices implementing quantum computing services are located.

[0162] It should be noted that the edge computing device 1752 may be physically located (e.g., co-located) within the quantum hardware provider premises 1750, such as in the building of the quantum hardware provider facility.

[0163] In some embodiments, components of the virtual machine 1770 may be contained within a backend API transport 1754, and the backend API transport 1754 may execute the relevant components within the backend API transport without having to instantiate a separate VM 1770.

[0164] Figure 18 illustrates exemplary interactions between a quantum computing service and an edge computing device for that quantum computing service, in several embodiments.

[0165] The backend API transport 1754 of the edge computing device 1752 may submit pings 1802, 1804, 1806, etc. to the quantum computing service 102 to determine whether there are any quantum tasks (e.g., compiled quantum circuits) to be transported to the edge computing device 1752. In 1808, the quantum computing service 102 may indicate to the edge computing device 1752 that there are any compiled quantum circuits (e.g., logic quantum circuits, such as logic quantum circuits, that are mapped to a given quantum hardware device of a given quantum hardware provider and converted to a format acceptable by the quantum hardware provider) that are ready to be transported to the edge computing device 1752.

[0166] In some embodiments, the compiled quantum circuit may represent a logic quantum circuit smoothed to a native gate representation, or it may be in an intermediate representation that will be further compiled by a quantum hardware provider. Also in some embodiments, the compiled quantum circuit may be compiled by a quantum compilation service into a pulse-level compiled artifact that can be executed, for example, via the FPGA of a quantum processing unit (QPU) for execution on a QPU.

[0167] In response to an instruction that there is a compiled quantum circuit ready for transport, the backend API transport 1754 may cause the virtual machine control plane 1756 to instantiate the virtual machine 1770 to function as the customer interface to the quantum hardware provider. In 1810, VM 1770 may call the backend API transport 1754 requesting a compiled quantum circuit (e.g., a quantum task or a batch of quantum tasks). In response, in 1812, the backend API transport 1754 may cause the compiled quantum circuit (e.g., a quantum task or a batch of quantum tasks) to be transported to the queue 1772 of VM 1770. In some embodiments, instead of the polling protocol ping, the edge computing device 1752 may use various other techniques to determine whether there is a quantum computing circuit (e.g., a quantum task or a batch of quantum tasks) ready to be transported to the edge computing device 1752. Also in some embodiments, a given quantum hardware provider may include two or more quantum computers and / or quantum computers of a certain type. In such embodiments, the backend API transport and / or VM interface to the quantum hardware provider may route quantum circuits to be executed in the quantum hardware provider to an assigned quantum computer in the quantum hardware provider.

[0168] In some embodiments, quantum tasks may arrive in queue 1772 along with their associated access tokens, and the quantum tasks may be ordered in queue 1772 based on their respective access tokens or the timestamps contained within each access token.

[0169] Exemplary process performed by a cloud-based quantum circuit compilation service In block 1900, a cloud-based quantum circuit compilation service receives quantum circuits to be compiled. These quantum circuits may be received from a given customer among multiple customers of the cloud-based quantum computing service. In some embodiments, the quantum circuits received from a given customer may be received via a user interface accessed by that customer. Also in some embodiments, the quantum circuits may be received from a given customer's client-side compiler, for example, in the format of a partially compiled quantum circuit. For example, a customer may perform various quantum circuit compilation paths using their client-side compiler, but may outsource other compilation paths to the quantum circuit compilation service. For example, a gate mapping path, which can be improved by using an optimization solver, may be outsourced to the quantum circuit compilation service. For instance, a client-side compiler may lack sufficient computing resources or licensing privileges to solve complex optimization problems, such as NP-hard problems. However, the quantum circuit compilation service may be able to scale provisioned computing resources as needed to solve such NP-hard problems. The quantum circuit compilation service may also have access to optimization problem services, such as the cloud-based optimization problem service 144 or a third-party optimization problem service 142. Therefore, quantum circuit compilation services can provide superior computing power and access to solvers that client-side compilers do not have access to.

[0170] In some embodiments, the quantum compilation service may be configured to compile each quantum circuit that will be executed on each of several different quantum hardware devices based on different quantum computing technologies. For example, the quantum circuit to be compiled received in 1900 may be a quantum circuit that is compiled for execution on various different quantum hardware devices using various different quantum computing technologies.

[0171] In block 1902, the cloud-based quantum circuit compilation service determines the set of compilation paths to be performed to compile (or partially compile) the received quantum circuit. In some embodiments, rules may be defined by the customer or administrator and used to select and order the compilation paths to be performed based on the characteristics of the quantum circuit to be compiled and / or based on the customer's preferences. In some embodiments, a machine learning model may be trained and used to select and order the compilation paths to be performed for each quantum circuit based on the characteristics of the quantum circuit. In some embodiments, the selected compilation paths may be chosen from a set of available compilation paths stored in a modularized compilation path repository, such as a modularized compilation path repository 204. In some embodiments, the customer may submit their own custom compilation paths that are added to the modularized compilation path repository (at least temporarily) and made available for use when compiling quantum circuits for the customer. In some embodiments, the customer may also submit custom gate decomposition definitions and / or custom pulse sequences that will be used when compiling quantum circuits for the customer.

[0172] In block 1904, the quantum circuit compilation service selects the first (or next) modularized compilation path to be performed.

[0173] In block 1906, the quantum circuit compilation service retrieves instructions from a modularized compilation path repository to execute a selected compilation path. For example, as shown in Figure 4, the compilation job plan 402 may include a compilation path list 404. The first (or next) compilation path to be executed may be determined based on the compilation path list 404. The quantum circuit compilation service may then retrieve instructions from a modularized compilation path 406 to execute a compilation path, which may contain instructions or pointers to retrieve instructions from the modularized compilation path repository. For example, a path may be a mapping path using a SAT solver, and instructions for the modularized path may include instructions to orchestrate an optimization problem using the SAT solver service to perform the mapping. The instructions may also indicate the computing resources required to execute the modularized compilation path.

[0174] In block 1908, the quantum circuit compilation service automatically orchestrates the provisioning of the computing resources required to execute the compilation pass. For example, virtual machines may be instantiated to provide the computing resources necessary to execute the compilation pass.

[0175] In block 1910, the quantum circuit compilation service uses provisioned computing resources and retrieved instructions to ensure that a compilation pass is executed. As considered herein, the result of a compilation pass may be a partially compiled quantum circuit that can be returned to the customer for compilation. Alternatively, the result of a compilation pass may be used as input to a subsequent compilation pass. In some embodiments, the result of one or more compilation passes may be compiled artifacts configured to be provided to the QHP for further compilation and / or execution. In some embodiments, the quantum circuit compilation service may perform compilation down to the pulse sequence level, and the compiled artifacts may be compiled binaries for implementing the pulse sequence.

[0176] In block 1912, the quantum circuit compilation service determines, based on the compilation job plan, whether there are any additional compilation passes to be performed by the quantum circuit compilation service. If there are compilation passes that have not yet been performed, the process returns to block 1904 and is repeated for the next compilation pass to be performed. If, in block 1912, based on the compilation job plan, it is determined that there are no additional compilation passes to be performed, the quantum circuit compilation service provides a compiled artifact representing the compiled version of the quantum circuit. The compiled artifact may be provided to the customer for further client-side compilation. The compiled artifact may also be provided to the customer in a format for execution on the customer's QPU. In addition, the compiled artifact may be provided to the provider network's quantum computing service to harmonize the execution of the compiled artifact using the QPU of a remote quantum hardware provider or using the QPU within the service provider network.

[0177] Exemplary Computer Systems Figure 20 is a block diagram illustrating an exemplary computing device that may be used in at least some embodiments.

[0178] Figure 20 illustrates such a general-purpose computing device 2000 that may be used in any of the embodiments described herein. In the illustrated embodiment, the computing device 2000 includes one or more processors 2010 coupled to system memory 2020 (which may include both non-volatile and volatile memory modules) via an input / output (I / O) interface 2030. The computing device 2000 further includes a network interface 2040 coupled to the I / O interface 2030.

[0179] In various embodiments, the computing device 2000 may be a uniprocessor system including one processor 2010, or a multiprocessor system including several (e.g., two, four, eight, or another preferred number) processors 2010. A processor 2010 may be any preferred processor capable of executing instructions. For example, in various embodiments, a processor 2010 may be a processor implementing one of a variety of instruction set architectures (ISAs), such as x86, PowerPC, SPARC, or MIPS ISA, or any other preferred ISA. In a multiprocessor system, each of the processors 2010 may, though not required, generally implement the same ISA. In some implementations, a graphics processing unit (GPU) may be used instead of, or in addition to, conventional processors. In some embodiments, a processor 2010 may include a field-programmable gate array (FPGA) that acts as an interface to a QPU, the FPGA executing a compiled artifact to cause the QPU's equipment to emit pulses according to the pulse sequence indicated in the compiled artifact.

[0180] The system memory 2020 may be configured to store instructions and data accessible by the processor 2010. In at least some embodiments, the system memory 2020 may include both a volatile portion and a non-volatile portion, while in other embodiments, only volatile memory may be used. In various embodiments, the volatile portion of the system memory 2020 may be implemented using any suitable memory technology, such as static random-access memory (SRAM), synchronous dynamic RAM, or any other type of memory. For the non-volatile portion of the system memory (which may include, for example, one or more NVDIMMs), in some embodiments, a flash memory device including a NAND flash device may be used. In at least some embodiments, the non-volatile portion of the system memory may include a power source, such as a supercapacitor or other energy storage device (e.g., a battery). In various embodiments, at least one of the following may be used for the non-volatile portion of the system memory: memristor-type resistive random-access memory (ReRAM), three-dimensional NAND technology, ferroelectric RAM, magnetoresistive RAM (MRAM), or various types of phase-change memory (PCM). In the illustrated embodiments, it is shown that program instructions and data implementing one or more desired functions, such as those methods, techniques, and data described above, are stored in system memory 2020 as code 2025 and data 2026.

[0181] In some embodiments, the I / O interface 2030 may be configured to harmonize I / O traffic between the processor 2010, the system memory 2020, the network interface 2040, or any peripheral devices within the device, including other peripheral devices such as various types of persistent and / or volatile storage devices. In some embodiments, the I / O interface 2030 may perform any necessary protocols, timing, or other data conversions to convert data signals from one component (e.g., the system memory 2020) into a format suitable for use by another component (e.g., the processor 2010). In some embodiments, the I / O interface 2030 may include support for devices mounted through various types of peripheral buses, such as variations of the Peripheral Component Interconnect (PCI) bus standard or the Universal Serial Bus (USB) standard. In some embodiments, the functionality of the I / O interface 2030 may be divided into two or more separate components, such as a northbridge and a southbridge. Furthermore, in some embodiments, some or all of the functionality of the I / O interface 2030, such as the interface to the system memory 2020, may be directly incorporated into the processor 2010.

[0182] The network interface 2040 may be configured to enable data exchange between the computing device 2000 and other devices 2060 attached to one or more networks 2050, such as other computer systems or devices illustrated in Figures 1 to 19. In various embodiments, the network interface 2040 may support communication over any suitable wired or wireless general data network, such as an Ethernet network. In addition, the network interface 2040 may support communication over telecommunications / telephone networks, such as analog voice networks or digital fiber optic networks, over storage area networks, such as Fibre Channel SANs, or over any other suitable type of network and / or protocol.

[0183] In some embodiments, system memory 2020 may represent an embodiment of a computer-accessible medium configured to store at least a subset of program instructions and data used to implement the methods and apparatus considered in the context of Figures 1 to 19. However, in other embodiments, program instructions and / or data may be received, transmitted, or stored on different types of computer-readable media. Generally speaking, the computer-accessible medium may include non-temporary storage media or memory media such as magnetic or optical media (e.g., disks or DVDs / CDs) coupled to the computing device 2000 via the I / O interface 2030. The non-temporary computer-accessible storage medium may also include any volatile or non-volatile media such as RAM (e.g., SDRAM, DDR SDRAM, RDRAM, SRAM, etc.), ROM, etc., which may be included in some embodiments of the computing device 2000 as system memory 2020 or another type of memory. In some embodiments, multiple non-temporary computer-readable storage media may collectively store program instructions that implement at least one subset of the methods and techniques described above when executed on or across one or more processors. Computer-accessible media may further include transmission media or signals, such as electrical signals, electromagnetic signals, or digital signals, transmitted over communication media, such as networks and / or wireless links, which may be implemented via network interface 2040. Some or all of multiple computing devices, such as those illustrated in Figure 20, may be used to implement the functionality described in various embodiments; for example, software components running on a variety of different devices and servers may work together to provide functionality. In some embodiments, some of the described functionality may be implemented using storage devices, network devices, or dedicated computer systems, in addition to, or instead of, using a general-purpose computer system.As used herein, the term “computing device” refers to, but is not limited to, at least all of these types of devices.

[0184] Embodiments of this disclosure may be described in consideration of the following provisions. Clause 1. A system, A service provider network comprising one or more computing devices configured to implement a quantum compilation service, wherein one or more computing devices implement the quantum compilation service, A compiled quantum circuit, where the quantum circuit is represented in an intermediate representation, and the quantum circuit receives, The quantum compilation service determines, based on a given quantum processing unit used to execute the quantum circuit, a set of compilation paths to be performed for at least a portion of the compilation process for compiling the received quantum circuit, and the quantum compilation service supports compiling quantum circuits against quantum processing units implemented using multiple quantum computing technologies. For each compilation path in the set of compilation paths, Accessing a modularized compilation path repository and retrieving instructions to execute each compilation path, Provisioning the computing resources required to execute each compilation path, and Using provisioned computing resources, execute instructions to implement each compilation path, It is configured to provide compiled artifacts that represent compiled versions of quantum circuits, A compilation service is a system configured to perform compilation as a compilation-as-a-service resource for multiple customers of a service provider network. Clause 2. The set of compilation paths is the system described in Clause 1, which includes the full set of compilation paths for compiling the received quantum circuit. Clause 3. One or more computing devices, The system described in Clause 1 or 2, further configured to provide compiled artifacts representing compiled versions of quantum circuits to quantum computing services on a service provider network, the quantum computing services being configured to run the compiled versions of quantum circuits on a quantum hardware provider quantum processing unit (QPU) or on a quantum processing unit on the service provider network. Clause 4. The set of compilation paths performed by the quantum compilation service includes the first part of the full set of compilation paths for compiling the received quantum circuit, and one or more computing devices The service provider network provides customers with a partially compiled version of the quantum circuit, represented in an intermediate representation. It is further configured to receive a more partially compiled version of the quantum circuit, represented in an intermediate representation, and the customer has a second set of one or more compilation passes to compile the received quantum circuit. The compiled artifact, representing a compiled version of a quantum circuit, is generated using a further partially compiled version of the quantum circuit, represented in an intermediate representation received from a customer of the service provider network, as described in Clause 1. Clause 5. One or more computing devices, The system described in Clause 4, configured to perform one or more of the remaining compilation passes of a set of compilation passes by using a further partially compiled version of the quantum circuit, represented in an intermediate representation, as input to one or more of the remaining compilation passes. Article 6. The system further comprises one or more additional computing devices configured to implement quantum computing services, and to implement quantum computing services, the one or more additional computing devices are Quantum computing services receive quantum circuits for execution, The compilation service compiles the quantum circuit into a compiled artifact for execution on a specific quantum processing unit (QPU). A system as described in any one of clauses 1 to 5, configured to orchestrate the execution of quantum circuits on a QPU using compiled binaries. Clause 7. A compiled artifact representing a compiled version of a quantum circuit is a pulse-level compiled binary containing instructions that cause the quantum circuit to execute in pulses directed to a quantum hardware device when executed by a field-programmed gate array or processor, as described in any one of Clauses 1 to 6 of the System. Clause 8. One or more computing devices, A system as described in any one of Clauses 1-7, configured to receive one or more custom pulse sequences used to implement one or more gates of the compiled quantum circuit, and whose pulse-level compiled binary includes one or more of the custom pulse sequences. Clause 9. A compiled artifact representing a compiled version of a quantum circuit is a native gate-level representation of the quantum circuit, including native gates that are native to a given quantum processing unit used to execute the quantum circuit, as described in any one of Clauses 1 through 8. Article 10. The quantum circuit to be compiled is received with a first request indicating that verbatim compilation should be performed. One or more computing devices, Store the compiled artifacts that represent the compiled version of the quantum circuit, The system described in Clause 1, configured to, in response to one or more subsequent requests for compiling a quantum circuit using verbatim compilation, provide a stored compiled artifact in the same format and containing the same content as that provided for the first request. Article 11. We receive information about quantum processing units from quantum hardware providers. The system according to any one of the clauses 1 to 10, further comprising one or more computing devices configured to implement a quantum device information service configured to provide received information to a quantum compilation service for use when compiling quantum circuits to be executed on a quantum processing unit of a quantum hardware provider. Article 12. Method, In the quantum compilation service, receiving the quantum circuit to be compiled and The quantum compilation service provisions computing resources to execute multiple compilation passes for compiling the received quantum circuit, The quantum compilation service orchestrates the performance of each compilation path using provisioned computing resources, This includes providing compiled artifacts that represent compiled versions of quantum circuits, A compilation service is configured to perform compilation of quantum circuits received from multiple customers as a compile-as-a-service resource. Clause 13. Multiple compilation paths include modularized compilation paths selected from the modularized compilation path repository of the quantum compilation service, as described in Clause 12. Clause 14. The modularized compilation path repository for the quantum compilation service is: Multiple qubit assignment and gate mapping compilation paths, The method described in Clause 13, including multiple pulse-level compilation paths. Clause 15. Multiple qubit assignment and gate mapping compilation paths are available. SAT resolution-based gate scheduling and mapping compilation path, SMT resolution-based gate scheduling and mapping compilation paths, or The method according to Clause 14, comprising two or more of the following: a reinforcement learning model-based gate scheduling and mapping compilation path. Article 16. The method according to Clause 15, further comprising scaling up or down the amount of computing resources provisioned to perform a given qubit gate mapping compilation pass by a quantum compilation service, the amount of computing resources being scaled so that the gate mapping compilation pass is completed within or at a cost less than a threshold amount of time required to perform a quick gate mapping compilation pass. Article 17. The quantum compilation service further includes determining a set of compilation paths to be performed for at least a portion of the compilation process for compiling the received quantum circuit. Orchestrating the performance of each compilation path is Accessing a modularized compilation path repository and retrieving instructions for each compilation path, The method described in any one of the clauses 12 to 16, including using provisioned computing resources to execute instructions for each compilation path. Article 18. Receiving custom compilation paths from customers of the quantum compilation service, The method described in any one of clauses 13 to 17, further including adding a custom compilation path to a modularized compilation path repository for use when compiling customer quantum circuits. Article 19. One or more non-temporary computer-readable storage media storing program instructions, wherein when the program instructions are executed on or across one or more processors, they are stored on one or more processors. The provisioned computing resources are used to compile the received quantum circuit through multiple compilation passes. The provisioned computing resources are used to orchestrate the performance of each compilation path. Implement a quantum compilation service configured to provide compiled artifacts that represent compiled versions of quantum circuits. A compilation service is one or more non-temporary computer-readable storage media configured to perform compilation for multiple customers as a compilation resource-as-a-service. Clause 20. When a program instruction is executed on or across one or more processors, it shall be executed on one or more processors. A first request is received indicating that verbatim compilation should be performed on the quantum circuit. The compiled artifact, which represents the compiled version of the quantum circuit, is stored. One or more non-temporary computer-readable storage media as described in Clause 19, which provide stored compiled artifacts for one or more subsequent received requests to compile quantum circuits using verbatim compilation.

[0185] conclusion Various embodiments may further include receiving, transmitting, or storing instructions and / or data implemented in accordance with the foregoing description on a computer-accessible medium. Generally speaking, computer-accessible mediums may include storage or memory media such as magnetic or optical media (e.g., disks or DVD / CD-ROMs), volatile or non-volatile media such as RAM (e.g., SDRAM, DDR, RDRAM, SRAM, etc.) and ROM, and transmission media or signals such as electrical signals, electromagnetic signals, or digital signals transmitted over communication media such as networks and / or wireless links.

[0186] The various methods illustrated in the figures and described herein represent exemplary embodiments of the method. The method may be implemented in software, hardware, or a combination thereof. The order of the method may be changed, and various elements may be added, rearranged, combined, omitted, or modified.

[0187] As will be apparent to those skilled in the art, various modifications and changes can be made that have advantages of the present disclosure. It is intended to encompass all such modifications and changes, and therefore the above description is intended to be considered illustrative rather than restrictive.

Claims

1. It is a system, A service provider network comprising one or more computing devices configured to implement a quantum compilation service, wherein, in order to implement the quantum compilation service, the one or more computing devices The quantum circuit to be compiled is received, The performance of a set of compilation passes performed for at least a portion of the compilation process for compiling the received quantum circuit is orchestrated. It is configured to provide a compiled artifact representing a compiled version of the quantum circuit, The compilation service is a system configured to perform compilation as a compile-as-a-service resource for multiple customers of the service provider network.

2. To orchestrate the performance of the set of compilation paths, one or more computing devices The quantum compilation service determines, based on a given quantum processing unit used to execute the quantum circuit, a set of compilation paths to be performed for at least a portion of the compilation process for compiling the received quantum circuit, wherein the quantum compilation service supports compiling the quantum circuit to a quantum processing unit implemented using multiple quantum computing technologies. For each compilation path in the aforementioned set of compilation paths, Accessing a modularized compilation path repository and retrieving instructions to execute each compilation path, Provisioning the computing resources required to execute each of the aforementioned compilation paths, and The system according to claim 1, further configured to use the provisioned computing resources to execute the instructions for implementing each of the compilation paths.

3. The one or more computing devices are The system according to claim 1 or 2, further configured to provide the compiled artifact representing the compiled version of the quantum circuit to the quantum computing service of the service provider network, wherein the quantum computing service is configured to run the compiled version of the quantum circuit on a quantum hardware provider quantum processing unit (QPU) or on a quantum processing unit of the service provider network.

4. The set of compilation paths performed by the quantum compilation service includes a first portion of the full set of compilation paths for compiling the received quantum circuit, and the one or more computing devices The service provider network provides customers with a partially compiled version of the quantum circuit, represented in an intermediate representation. The system is further configured to receive a more partially compiled version of the quantum circuit represented in the aforementioned intermediate representation, wherein the customer has the system perform a second set of one or more compilation passes to compile the received quantum circuit. The system according to any one of claims 1 to 3, wherein the compiled artifact representing the compiled version of the quantum circuit is generated using the further partially compiled version of the quantum circuit represented in the intermediate representation, received from the customer of the service provider network.

5. The one or more computing devices are The system according to claim 4, wherein one or more remaining compilation passes of the set of compilation passes are configured to be carried out using the further partially compiled versions of the quantum circuit, represented in the intermediate representation, as inputs to the one or more remaining compilation passes.

6. The system further comprises one or more additional computing devices configured to implement quantum computing services, and to implement the quantum computing services, the one or more additional computing devices The aforementioned quantum computing service receives the quantum circuit for execution, The compilation service is instructed to compile the quantum circuit into a compiled artifact for execution on a specific quantum processing unit (QPU). The system according to any one of claims 1 to 5, configured to orchestrate the execution of the quantum circuit on the QPU using a compiled binary.

7. The system according to any one of claims 1 to 6, wherein the compiled artifact representing the compiled version of the quantum circuit is a pulse-level compiled binary containing instructions that cause the quantum circuit to execute in pulses directed to a quantum hardware device when executed by a field programming gate array or processor.

8. The system according to any one of claims 1 to 7, wherein the compiled artifact representing the compiled version of the quantum circuit is a native gate-level representation of the quantum circuit, including native gates that are native to a given quantum processing unit used to execute the quantum circuit.

9. The quantum circuit to be compiled is received with a first requirement indicating that verbatim compilation should be performed. The one or more computing devices are The compiled artifact representing the compiled version of the quantum circuit is stored. The system according to claim 1, configured to, in response to one or more subsequent requests to compile the quantum circuit using the verbatim compilation, provide the stored compiled artifact in the same format and containing the same content as that provided for the first request.

10. It is a method, In the quantum compilation service, receiving the quantum circuit to be compiled and The quantum compilation service provision computing resources to execute multiple compilation passes for compiling the received quantum circuit, The quantum compilation service orchestrates the performance of each compilation path using the provisioned computing resources, This includes providing a compiled artifact representing a compiled version of the quantum circuit, The compilation service is configured to perform compilation of quantum circuits received from multiple customers as a compile-as-a-service resource.

11. The method according to claim 10, wherein the plurality of compilation paths include modularized compilation paths selected from the modularized compilation path repository of the quantum compilation service.

12. The modularized compilation path repository of the quantum compilation service is Multiple qubit assignment and gate mapping compilation paths, The method according to claim 11, comprising a plurality of pulse-level compilation paths.

13. The aforementioned multiple qubit allocation and gate mapping compilation paths are: SAT resolution-based gate scheduling and mapping compilation path, SMT resolution-based gate scheduling and mapping compilation path, or The method according to claim 12, comprising two or more of the following: a reinforcement learning model-based gate scheduling and a mapping compilation path.

14. The method according to claim 13, further comprising scaling up or down the amount of computing resources provisioned to perform a given qubit gate mapping compilation pass by the quantum compilation service, wherein the amount of computing resources is scaled such that the gate mapping compilation pass is completed within a threshold amount of time or at a cost less than the threshold amount required to perform a qubit gate mapping compilation pass.

15. The quantum compilation service further includes determining a set of compilation paths to be performed for at least a portion of the compilation process for compiling the received quantum circuit. Orchestrating the performance of each of the aforementioned compilation paths is Accessing a modularized compilation path repository and retrieving instructions for executing each of the aforementioned compilation paths, The method according to any one of claims 10 to 14, comprising using the provisioned computing resources to execute the instructions for implementing each of the compilation paths.

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