Chip package with glass interposer

Abstract

The chip package has a package substrate, including a top surface. The first chip module and the second chip module are mounted on the top surface of the package substrate. The first interposer is positioned between the package substrate and the first and second chip modules and includes a glass interposer. The first interposer couples the first and second chip modules to the package substrate. An interconnection bridge is positioned within the cavity of the glass interposer. The interconnection bridge includes a circuit that connects the circuit of the first chip module to the circuit of the second chip module.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims priority to U.S. Provisional Patent Application No. 63 / 463,259, filed on May 1, 2023, the entire disclosure of which is incorporated herein by reference.

[0002] (Field of the Invention) Examples of the present disclosure generally relate to chip packages, and more particularly to chip packages having integrated circuit (IC) dies disposed on a glass interposer.

Background Art

[0003] In particular, electronic devices such as tablets, computers, copiers, digital cameras, smartphones, control systems, and automated teller machines often use electronic components that utilize chip packages for improved functionality and increased component density. Conventional chip packaging methods often utilize a package substrate, often together with a through - silicon - via (TSV) interposer, to enable multiple integrated circuit (IC) dies to be mounted on a single package substrate. The IC die may include memory, logic, or other IC devices.

[0004] Wafer-level multi-chip packaging technology has been developed to integrate multiple dies side-by-side on a silicon interposer to achieve better interconnection density and performance. Individual chips are bonded via microbumps on the silicon interposer to form a chip-on-wafer (CoW). The CoW is then thinned so that through-silicon vias are exposed. This is followed by C4 bump formation and singulation. Bonding to a package substrate completes the CoWoS (Chip on Wafer on Substrate) package. However, wafer-based packaging for large chip modules has limited scalability due to reticle limitations.

[0005] Therefore, an improved chip package that can be expanded to accommodate larger chip modules is needed. [Overview of the project] [Means for solving the problem]

[0006] A chip package is provided having a first chip module and a second chip module mounted above the upper surface of a package substrate. A first interposer is positioned between the package substrate and the first and second chip modules and includes a glass interposer. The first interposer couples the first and second chip modules to the package substrate. An interconnection bridge is positioned within the cavity of the glass interposer. The interconnection bridge includes circuits that connect the circuits of the first chip module to the circuits of the second chip module. In one example, the first interposer includes an interconnection routing structure positioned above the upper surface of the glass interposer and below the first and second chip modules. The interconnection routing structure may include one or more redistribution layers having circuits that connect the circuits of the interconnection bridge to the circuits of the first and second chip modules. The one or more redistribution layers also include circuits that connect the circuits of the first and second chip modules to the circuits of the package substrate.

[0007] Another example provides a method for manufacturing a chip package. The method includes mounting an interconnection bridge in the cavity of a first interposer having a glass interposer. At least one integrated circuit die is mounted on a second interposer to form a first integrated circuit chip module. For example, the first chip module may include a first circuit die and a second circuit die mounted on the second interposer. Similarly, at least one integrated circuit die is mounted on a third interposer to form a second integrated circuit chip module. For example, the second chip module may include a third circuit die and a fourth circuit die mounted on the second interposer. The first and second chip modules are mounted on the first interposer. The interconnection bridge circuit connects the circuit of the first chip module to the circuit of the second chip module. The first and second chip modules, as well as the first interposer, are mounted on a package substrate.

[0008] More detailed explanations of the features listed above are provided in a manner that allows for a thorough understanding of the characteristics, by referring to exemplary implementations, some of which are shown in the attached drawings. However, it should be noted that the attached drawings only show typical exemplary implementations and should therefore not be considered limiting in scope. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic cross-sectional view of a chip package having a glass interposer and interconnecting bridges located within the interposer. [Figure 2] This is a schematic sub-diagram of a part of the chip package shown in Figure 1, which illustrates the interposer in detail. [Figure 3] This is a flowchart of a method for manufacturing a chip package having a glass interposer and an interconnection bridge that connects a first chip module to a second chip module. [Modes for carrying out the invention]

[0010] For ease of understanding, the same reference numerals are used to indicate identical elements common to the drawings, where possible. Elements of one embodiment are intended to be usefully incorporated into other embodiments.

[0011] This specification describes an improved chip package and a method for manufacturing the same. This improved chip package utilizes a glass interposer, taking advantage of the shape of a glass panel for chip packaging. Two chip modules, each containing multiple dies, are mounted on the glass interposer. The glass interposer is then mounted on a package substrate. The two chip modules are coupled via an interconnect bridge located within the glass interposer. In some embodiments, a photonic connector is mounted on the glass interposer.

[0012] Referring now to Figure 1, Figure 1 is a schematic cross-sectional view of a chip package 100 having a first chip module 102 and a second chip module 104, a first interposer 150, and a package substrate 108. The first chip module 102 and the second chip module 104 are arranged laterally on the upper surface 172 of the first interposer 150. In one embodiment, the first interposer 150 includes a glass interposer 405. The first interposer 150 is positioned above the package substrate 108. In one embodiment, the glass interposer 405 may be manufactured from a glass panel. The glass interposer 405 may have a thickness in the range of 200 μm to 1500 μm, for example, 300 μm to 400 μm or 800 μm to 1200 μm.

[0013] In the example shown in Figure 1, the first chip module 102 includes a first IC die 201, a second IC die 202, and a third IC die 203 arranged laterally on the second interposer 208. The second chip module 104 includes a fourth IC die 204 and a fifth IC die 205 arranged laterally on the third interposer 209. In this example, the first IC die 201 and the fourth IC die 204 may be core dies (e.g., logic or processor dies such as a Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), or other digital signal processing chip). The second IC die 202, the third IC die 203, and the fifth IC die 205 may be memory devices such as High Bandwidth Memory (HBM). However, IC dies 201-205 are intended to be any suitable combination of logic and memory devices, such as field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), memory devices such as high-bandwidth memory (HBM), optical devices, processors, or other IC logic or memory structures. One or more of the IC dies 206 may optionally include optical devices such as photodetectors, lasers, or light sources.

[0014] The second interposer 208 and the third interposer 209 may be a silicon interposer, an organic interposer, a ceramic interposer, a glass interposer, or a stack of suitable materials on which interconnect routing can be arranged. The bottom surfaces of the second interposer 208 and the third interposer 209 face the top surface 172 of the first interposer 150.

[0015] Figure 1 shows five IC dies 201-205, but the total number of IC dies to be placed on the second interposer 208 and the third interposer 209 may range from two to a number that can fit within the chip modules 102 and 104. Furthermore, one or more dies may be directly laminated on one or more of the IC dies 201-205. A filler material 168 may be placed between the IC dies 201-205 and the second interposer 208 and the third interposer 209 to provide structural integrity to the chip modules 102 and 104.

[0016] Each of the IC dies 201-205 includes internal functional circuits 221-225 coupled to contact pads (not shown) exposed on the bottom surface of the IC dies 201-205 by internal routing 231-235. The contact pads exposed on the bottom surface of the IC dies 201-205 are coupled to internal routing 252, 256 of the internal circuits 238 of their respective interposers 208, 209 by interconnects 262, such as solder microbumps. The internal routing 252 provides communication between the IC dies 201-205, for example, between the first IC die 201 and the second IC die 202, or between the fourth IC die 204 and the fifth IC die 205. Internal routing 256 provides communication between IC dies 201-205 and the first interposer 150, for example, between the first IC die 201 and the first interposer 150, or between the fourth IC die 204 and the first interposer 150. Interconnection 262 provides mechanical and electrical connections between IC dies 201-205 and the second interposer 208 and the third interposer 209. Filling material 169 may be placed between chip modules 102, 104 and the first interposer 150 to provide structural integrity.

[0017] The bottom surfaces of the second interposer 208 and the third interposer 209 face and overlap the top surface 172 of the first interposer 150. An interconnection 240, which may be, for example, a controlled collapse chip connection (C4 ball), connects a portion of the internal routing 256 of the second interposer 208 and the third interposer 209 to a circuit 236 formed through the first interposer 150. The interconnection 240 provides mechanical and electrical connections between the second interposer 208 and the third interposer 209 and the first interposer 150. In one embodiment, the circuit 236 of the first interposer 150 includes one or more redistribution layers 270 of the first interposer 150 and a circuit passing through the glass interposer 405. In one example, two redistribution layers 270 are formed on the top surface 407 of the glass interposer 405. The redistribution layer 270 may be used to extend the pitch of the interconnects 240.

[0018] In one embodiment, a portion of the internal routing 256 of the second interposer 208 and the third interposer 209 is connected to an interconnect bridge 180 located within the first interposer 150. The interconnect bridge 180 provides communication between the first chip module 102 and the second chip module 104. In one example, the interconnect bridge 180 is an embedded multi-die interconnect bridge (EMIB) with high-density routing. In another example, the interconnect bridge 180 is a silicon-based integrated circuit die with internal high-density solid-state routing to provide communication between the first chip module 102 and the second chip module 104. In some examples, the interconnect bridge 180, configured as a silicon-based integrated circuit die, has only solid-state routing and no active circuit elements such as transistors.

[0019] The bottom surface 409 of the first interposer 150 faces and overlaps with the top surface 124 of the package substrate 108. An interconnect 110, which may be, for example, a control collapse chip connection (C4 ball), connects a portion of the circuit 236 of the first interposer 150 to a circuit 136 formed through the package substrate 108. The interconnect 110 provides mechanical and electrical connections between the package substrate 108 and the first interposer 150.

[0020] Some of the circuits 136 formed within the package substrate 108 are terminated at contact pads (not shown) exposed on the bottom surface 126 of the package substrate 108, facing away from the first interposer 150. Solder balls 116 (e.g., Ball Grid Array (BGA)) are placed on the contact pads exposed on the bottom surface 126 of the package substrate 108. The solder balls 116 are used to bond the chip package 100 to the printed circuit board 118 (shown by dashed lines) to form an electronic device.

[0021] In one embodiment, the chip package 100 includes a photonic connector 310 mounted on a first interposer 150. The photonic connector 310 includes an optical fiber cable 312 for connecting to an optical device. The bottom surface of the photonic connector 310 faces and overlaps with the top surface 172 of the first interposer 150. An interconnect 240 couples the circuit of the photonic connector 310 to a circuit 236 formed through the first interposer 150. The interconnect 240 provides mechanical and electrical connections between the photonic connector 310 and the first interposer 150. In one embodiment, an electric integrated circuit (EIC) 315 located within the first interposer 150 provides communication between a second chip module 104 and the photonic connector 310. The EIC 315 may function as an electrical-to-optical converter. In some embodiments, a common package cable 313 is mounted on the first interposer 150.

[0022] In one embodiment, the first interposer 150 and chip modules 102, 104 may be manufactured individually and then assembled together to form a chip package 100. Figure 2 shows an enlarged partial view of an exemplary embodiment of the first interposer 150. The first interposer 150 includes a glass interposer 405 provided with a plurality of vias 410. In some examples, the vias 410 are formed through the glass interposer 405, which may have a thickness of about 300 μm to about 400 μm. Pads 412 are formed on the top and bottom surfaces of the glass interposer 405. An interconnect bridge 180 is located in a cavity 415 formed within the glass interposer 405. In one example, the interconnect bridge 180 is an embedded multi-die interconnect bridge (EMIB) with high-density routing. The interconnect bridge 180 may be attached to the glass interposer 405 using any suitable mechanism such as a die mounting tape 183.

[0023] The interconnect routing structure is formed on the exposed surface of the glass interposer 405. In this example, the interconnect routing structure is embodied as one or more redistribution layers such as the first redistribution layer 421 and the second redistribution layer 431. Each of the redistribution layers 421, 431 may include three or more patterned metal layers disposed between dielectric layers. In one example, the metal layer is plated copper and the dielectric layer is an oxide. The patterned metal layers are used to form pads 423, 433 and lines that are interconnected by vias to form an electrical routing circuit through the redistribution layers 421, 431. The electrical routing circuit through the redistribution layers 421, 431 is utilized to connect the functional circuit 236 of the first interposer 150 to the internal routing 256 of the first chip module 102 and the second chip module 104. For example, one pad 433 of the routing circuit of the second redistribution layer 431 terminates at the solder interconnect 240, and the routing circuit of the second redistribution layer 431 connects the pad 433 to the pad 423 of the first redistribution layer 421. Next, the routing circuit of the first redistribution layer 421 connects the pad 423 to the pad 412 of the glass interposer 405. The redistribution layers 421, 431 connect the internal routing 256 of the first chip module 102 and the second chip module 104 to the functional circuit of the interconnect bridge 180. In this way, the redistribution layers 421, 431 may be formed directly on the exposed upper surface of the glass interposer 405 without intervening solder connections. The solder interconnect 240 is plated on the pad 433 of the second redistribution layer 431 or formed in some other way.

[0024] FIG. 3 is a flowchart of a method 500 for manufacturing a chip package having a glass interposer and an interconnect bridge that couples a first chip module and a second chip module. The method 500 may be utilized to manufacture the chip package 100 described above or other similar chip packages.

[0025] Method 500 begins with operation 502 where an interconnect bridge 180 is implemented within cavity 415 of a first interposer 150. In this example, the first interposer 150 includes a glass interposer 405. The interconnect bridge 180 is an embedded multi-die interconnect bridge (EMIB) having high-density routing. In this example, the interconnect bridge 180 is disposed within a cavity formed within the glass interposer 405. The glass interposer 405 may have a thickness of from about 300 μm to about 400 μm and a plurality of vias 410 formed therethrough. In some embodiments, an interconnect routing structure is formed on an exposed surface of the glass interposer 405 and connected to the vias 410. In this example, the interconnect routing structure is embodied as one or more redistribution layers such as two redistribution layers 421, 431, etc. In some embodiments, the glass interposer 405 may have a thickness of from about 800 μm to 1,200 μm. In the case of these thicker glass interposers, a plurality of pillar vias are formed to a desired depth within the glass interposer 405 instead of passing through the glass interposer 405.

[0026] In operation 504, a first integrated circuit (IC) die 201 and a second IC die 202 are implemented on a second interposer 208 via an interconnect 262 to form a first chip module 102. In operation 504, a fill material 168 may also be disposed on the second interposer 208 to fill an inter-die gap laterally defined between the IC dies 201, 202. In some embodiments, three or more dies (e.g., a third IC die 203) may be implemented on the second interposer 208.

[0027] In operation 506, the fourth IC die 204 and the fifth IC die 205 are mounted on the second interposer 208 via the interconnect 262 to form the second chip module 104. In operation 506, filler material 168 may also be placed on the third interposer 209 to fill the laterally defined inter-die gap between the IC dies 204 and 205. In some embodiments, three or more dies may be mounted on the third interposer 209. Operations 504 and 506 are intended to be performed before operations 502.

[0028] In operation 508, the first chip module 102 and the second chip module 104 are mounted on the first interposer 150. In operation 508, a solder interconnect 240 electrically and mechanically connects the first chip module 102 and the second chip module 104 to the first interposer 150. In this example, the first chip module 102 and the second chip module 104 are mounted on the interconnect routing structure of the first interposer 150, for example, mounted above two redistribution layers 421, 431. The first chip module 102 and the second chip module 104 are electrically connected to the circuit of the interconnect bridge 180. The interconnect bridge 180 provides communication between the first chip module 102 and the second chip module 104. In embodiments in which the glass interposer 405 includes pillar vias instead of glass through vias, a grinding process may be performed on the glass interposer 405 to expose the pillar vias for connection to the package substrate 108.

[0029] In operation 510, the first chip module 102, the second chip module 104, and the first interposer 150 are mounted on the package substrate 108. In operation 510, the interconnect 110 electrically and mechanically couples the first chip module 102, the second chip module 104, and the first interposer 150 to the package substrate 108. In one embodiment, solder balls 116 are placed on the bottom surface 126 of the package substrate 108 to form the chip package 100. The solder balls 116 may be used to electrically and mechanically couple the chip package 100 to the printed circuit board 118.

[0030] In operation 512, the photonic connector 310 is optionally mounted on the top surface of the first interposer 150. In operation 512, the electrical integrated circuit 315 is placed within the glass interposer 405 of the first interposer 150. The electrical integrated circuit 315 connects the photonic connector 310 to the second chip module 104. The photonic connector 310 may include an optical fiber cable 312 for connection to an optical device. Note that operation 512 may be performed before operation 508 or 510.

[0031] An improved chip package and a method for manufacturing the same are described, providing a chip package including a first glass interposer. In this regard, the glass interposer may be manufactured from a glass panel, which advantageously provides an expandable solution for large reticle modules based on the shape of the glass panel (e.g., a rectangle including a square). The chip package described above advantageously allows for the inclusion of a photonic connector in the chip package and the embedding of an electrical integrated circuit die in the glass interposer.

[0032] The above applies to specific examples, but other and further examples may be devised without departing from the basic scope, which is determined by the following "Claims".

Claims

1. A package substrate having an upper surface, A first chip module mounted on the upper surface of the package substrate, A second chip module mounted on the upper surface of the aforementioned package substrate, A first interposer disposed between the package substrate and the first chip module and the second chip module, the first interposer including a glass interposer, which connects the first chip module and the second chip module to the package substrate, The interconnection bridge is located within the cavity of the glass interposer and includes a circuit that connects the circuit of the first chip module to the circuit of the second chip module. Chip package.

2. The first interposer includes an interconnection routing structure located on the upper surface of the glass interposer and below the first chip module and the second chip module. A chip package according to claim 1.

3. The interconnection routing structure comprises one or more redistribution layers having circuits that connect the circuits of the interconnection bridge to the circuits of the first chip module and the second chip module. The chip package according to claim 2.

4. The interconnection routing structure comprises one or more redistribution layers having circuits that connect the circuits of the first chip module and the second chip module to the circuits of the package substrate. The chip package according to claim 2.

5. The first interposer includes a photonic connector mounted on its upper surface, A chip package according to claim 1.

6. The first interposer comprises an electrical integrated circuit, The aforementioned electrical integrated circuit provides communication between the second chip module and the photonic connector. The chip package according to claim 5.

7. The aforementioned photonic connector includes an optical fiber cable. The chip package according to claim 5.

8. The first chip module comprises a first die mounted on a second interposer, The aforementioned second chip module comprises a second die mounted on a third interposer. A chip package according to claim 1.

9. The first chip module comprises a third die mounted on the second interposer, The second chip module comprises a fourth die mounted on the third interposer. The chip package according to claim 8.

10. The aforementioned interconnection bridge includes high-density routing, A chip package according to claim 1.

11. A package substrate having an upper surface, A first chip module mounted on the upper surface of the package substrate, A second chip module mounted on the upper surface of the aforementioned package substrate, A first interposer disposed between the package substrate and the first chip module and the second chip module, the first interposer including a glass interposer, which connects the first chip module and the second chip module to the package substrate, A photonic connector mounted on the upper surface of the first interposer, An electrical integrated circuit disposed within the first interposer, comprising an electrical integrated circuit that provides communication between the second chip module and the photonic connector, Chip package.

12. The glass interposer includes an interconnection bridge located within it, The interconnection bridge has a circuit that connects the circuit of the first chip module to the circuit of the second chip module. The chip package according to claim 11.

13. The first interposer includes a redistribution layer located on the upper surface of the glass interposer, below the first chip module and the second chip module. The redistribution layer includes a circuit that connects the interconnection bridge circuit to the circuits of the first chip module and the second chip module. A chip package according to claim 12.

14. A method for manufacturing a chip package, Implementing an interconnection bridge within the cavity of a first interposer having a glass interposer, The first integrated circuit (IC) die and the second integrated circuit (IC) die are mounted on a second interposer to form a first chip module, The third integrated circuit (IC) die and the fourth integrated circuit (IC) die are mounted on the third interposer to form a second chip module, The first chip module and the second chip module are mounted on the first interposer, Using the interconnection bridge circuit, the circuit of the first chip module is connected to the circuit of the second chip module, This includes mounting the first chip module, the second chip module, and the first interposer onto a package substrate. method.

15. This includes implementing a photonic connector on the first interposer. The method according to claim 14.

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